83940D

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Low Skew, 1-to-18 LVPECL-TO-LVCMOS / LVTTL Fanout Buffer 83940D DATASHEET 83940D REVISION B 3/25/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 83940D is a low skew, 1-to-18 LVPECL-to-LVC- MOS/LVTTL Fanout Buffer. The 83940D has two select- able clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_ CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The 83940D is characterized at full 3.3V and 2.5V or mixed3.3V core, 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 83940D ideal for those clock distribution applications demanding well defi ned performance and repeatability. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

• 18 LVCMOS/LVTTL outputs
• Selectable LVCMOS_CLK or LVPECL clock inputs
• PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
• LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part to part skew: 750ps (maximum)
• Additive phase jitter, RMS: < 0.03ps (typical)
• Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output supply modes
• 0°C to 70°C ambient operating temperature
• Lead-Free package available 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Pacakge Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 V DD Q10 Q11 GND GND GND LVCMOS_CLK CLK_SEL PCLK nPCLK V DD VDDO VDDO Q12 Q13 Q14 GND Q15 Q16 Q17 GND V DDO ICS83940D

2 REVISION B 3/25/15

TABLE 1. PIN DESCRIPTIONS 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS_CLK Input Pulldown Clock input. LVCMOS / LVTTL interface levels.

4 CLK_SEL Input Pulldown

LOW. LVCMOS / LVTTL interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Inverting differential LVPECL clock input. DD/2 default when left fl oating. 7, 21 V DD Power Core supply pins. 8, 16, 29 V DDO Power Output supply pins. Output Clock outputs. LVCMOS / LVTTL interface levels. Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS

0 Selected De-selected

1 De-selected Selected

NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.

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LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 3.6V Inputs, V I -0.3V to V DD + 0.3V Outputs, V O -0.3V to V DDO + 0.3V Input Current, I IN ±20mA Storage Temperature, T STG -40°C to 125°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER 83940D DATA SHEET

4 REVISION B 3/25/15

TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2.4 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V VPP Peak-to-Peak Input Voltage PCLK, nPCLK 500 1000 mV VCMR Input Common Mode Voltage; NOTE 1, 2 PCLK, nPCLK V DD - 1.4 V DD - 0.6 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -20mA 2.4 V VOL Output Low Voltage I OL = 20mA 0.5 V IDD Core Supply Current 25 mA NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 f ≤ 150MHz 1.6 3.0 ns LVCMOS_CLK; NOTE 2, 5 f ≤ 150MHz 1.8 3.0 ns tpLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 f > 150MHz 1.6 3.3 ns LVCMOS_CLK; NOTE 2, 5 f > 150MHz 1.8 3.2 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 150 ps LVCMOS_CLK 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f ≤ 150MHz 1.4 ns LVCMOS_CLK f ≤ 150MHz 1.2 ns tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f > 150MHz 1.7 ns LVCMOS_CLK f > 150MHz 1.4 ns tsk(pp) Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 850 ps LVCMOS_CLK 750 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 7 0.03 ps t R / tF Output Rise/Fall Time 0.5 to 2.4V 0.3 1.1 ns odc Output Duty Cycle f < 134MHz 45 50 55 % 134MHz ≤ f ≤ 250MHz 40 50 60 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 6: Defi ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 7: Driving only one input clock.

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LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0° TO 70° TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2.4 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V VPP Peak-to-Peak Input Voltage PCLK, nPCLK 300 1000 mV VCMR Input Common Mode Voltage; NOTE 1, 2 PCLK, nPCLK V DD - 1.4 V DD - 0.6 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -20mA 1.8 V VOL Output Low Voltage I OL = 20mA 0.5 V IDD Core Supply Current 25 mA NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH. Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 f ≤ 150MHz 1.7 3.2 ns LVCMOS_CLK; NOTE 2, 5 f ≤ 150MHz 1.7 3.0 ns tpLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 f > 150MHz 1.6 3.4 ns LVCMOS_CLK; NOTE 2, 5 f > 150MHz 1.8 3.3 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 150 ps LVCMOS_CLK 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f ≤ 150MHz 1.5 ns LVCMOS_CLK f ≤ 150MHz 1.3 ns tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f > 150MHz 1.8 ns LVCMOS_CLK f > 150MHz 1.5 ns tsk(pp) Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 850 ps LVCMOS_CLK 750 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 7 0.03 ps t R / tF Output Rise/Fall Time 0.5 to 1.8V 0.3 1.2 ns odc Output Duty Cycle f < 134MHz 45 50 55 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 6: Defi ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 7: Driving only one input clock.

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER 83940D DATA SHEET

6 REVISION B 3/25/15

TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V VPP Peak-to-Peak Input Voltage PCLK, nPCLK 300 1000 mV VCMR Input Common Mode Voltage; NOTE 1, 2 PCLK, nPCLK V DD - 1.4 V DD - 0.6 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -12mA 1.8 V VOL Output Low Voltage I OL = 12mA 0.5 V IDD Core Supply Current 25 mA NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH. TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 200 MHz tpLH Propagation Delay; PCLK, nPCLK; NOTE 1, 5 f ≤ 150MHz 1.2 3.8 ns LVCMOS_CLK; NOTE 2, 5 f ≤ 150MHz 1.5 3.2 ns tpLH Propagation Delay; PCLK, nPCLK; NOTE 1, 5 f > 150MHz 1.5 3.7 ns LVCMOS_CLK; NOTE 2, 5 f > 150MHz 2 3.6 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 200 ps LVCMOS_CLK 200 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f ≤ 150MHz 2.6 ns LVCMOS_CLK f ≤ 150MHz 1.7 ns tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f > 150MHz 2.2 ns LVCMOS_CLK f > 150MHz 1.7 ns tsk(pp) Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 1.2 ns LVCMOS_CLK 1.0 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 7 0.03 ps t R / tF Output Rise/Fall Time 0.5 to 1.8V 0.3 1.2 ns odc Output Duty Cycle f < 134MHz 45 55 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 6: Defi ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 7 Driving only one input clock.

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LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER Input/Output Additive Phase Jitter at 155.52MHz = 0.03ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M The spectral purity in a band at a specifi c offset from the fun- damental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fun- damental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the As with most timing specifi cations, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor of the device. This is illustrated above. The 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER 83940D DATA SHEET

8 REVISION B 3/25/15

PARAMETER MEASUREMENT INFORMATION 2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART-TO-PART SKEW OUTPUT SKEW

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LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER PROPAGATION DELAY 3.3V OUTPUT RISE/FALL TIME 2.5V OUTPUT RISE/FALL TIME

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER 83940D DATA SHEET

10 REVISION B 3/25/15

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

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LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface ex- amples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confi rm the driver termination requirements. FIGURE 2A. PCLK/nPCLK I NPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 2B. PCLK/nPCLK I NPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER FIGURE 2C. PCLK/nPCLK I NPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 2F. PCLK/nPCLK I NPUT DRIVEN BY A 3.3V LVDS DRIVER PCLK/nPCLK 2.5V Zo = 60 Ohm SSTL HiPerClockS PCLK nPCLK 120 3.3V 120 Zo = 60 Ohm 120 120 2.5V FIGURE 2E. PCLK/nPCLK I NPUT DRIVEN BY AN SSTL DRIVER HiPerClockS PCLK nPCLK PCLK/nPCLK 3.3V 3.3V Zo = 50 Ohm CML 3.3V Zo = 50 Ohm 3.3V HiPerClockS PCLK nPCLK 125 Input Zo = 50 Ohm 125 LVPECL 3.3V 3.3V Zo = 50 Ohm 100 Zo = 50 Ohm 3.3V 3.3V LVDS HiPerClockS PCLK nPCLK Zo = 50 Ohm 3.3V PCLK/nPCLK 3.3V 100 - 200 3.3V 3.3V HiPerClockS PCLK nPCLK 125 PCLK/nPCLK 125 Zo = 50 Ohm Zo = 50 Ohm 100 - 200 3.3V LVPECL FIGURE 2D. PCLK/nPCLK I NPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE

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TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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TABLE 7. PACKAGE DIMENSIONS

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TABLE 8. ORDERING INFORMATION

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LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page Description of Change Date A T5A T5B T5C 3.3V AC Characteristics table -  tsk(pp) Test Conditions, replaced “<” with “ ≤ “; corrected Units to “ns” from “ps”.  odc - corrected Test Conditions to read “134MHz ≤ f ≤ 250MHz”, from “f ≤ 250MHz”. 3.3V/2.5V AC Characteristics table - tsk(pp) Test Conditions, replaced “<” with “ ≤ “; corrected Units to read “ns” from “ps”. 2.5V AC Characteristics table - tsk(pp) Test Conditions, replaced “<” with “ ≤ “; corrected Units to “ns” from “ps”. 10/11/02 AT 2 Pin Characteristics table - changed ROUT 25Ω maximum to 28Ω maximum. Delete RPULLUP row. 3.3V Output Load AC Test Circuit diagram - corrected GND equation to read Added LVTTL to title. Updated format. 12/12/02 B T5A T5B T5C Pin Description Table - added Pullup and Pulldown to Pin 6, nPCLK. Pin Characteristics Table - added R PULLUP row. Added tjit row. Added tjit row. Added tjit row. Added Additive Phase Jitter section. Updated Single Ended Signal Driving Differential Input diagram. Added LVPECL Clock Interface section. 10/9/03 B T5A - T5C 4 - 6 Added “Lead-Free” bullet to Features section. Added NOTE 7. Updated LVPECL Clock Input Interface section. Ordering Information table - added “Lead-Free” part number. 6/15/04 B T8 14 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/9/10 Updated data sheet format. 3/25/15

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