83940-01

83940-01 Datasheet

Document overview

• Manufacturer or author: rdvorak
• PDF pages: 15

Technical content

Low Skew, 1-to-18 LVPECL-TO-LVCMOS / LVTTL Fanout Buffer 83940-01 DATASHEET 83940-01 REVISION A NOVEMBER 4, 2014 1 ©2014 Integrated Device Technology, Inc. GENERAL DESCRIPTION The ICS83940-01 is a low skew, 1-to-18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer. The ICS83940-01 has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML or SSTL input levels. The single ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 Ω series or parallel terminated transmis- sion lines. The effective fanout can be increased from 18 to 36 by utilizing the ability of the outputs to drive two series terminated lines. The ICS83940-01 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operat- ing supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83940-01 ideal for those clock distribution applications demanding well defined performance and repeatability. BLOCK DIAGRAM P IN ASSIGNMENT 32-Lead LQFP Y Pacakge 7mm x 7mm x 1.4mm package body Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 V DDO Q10 Q11 GND GND GND LVCMOS_CLK CLK_SEL PCLK nPCLK V DD VDDO VDDO Q12 Q13 Q14 GND Q15 Q16 Q17 GND V DDO ICS83940-01

FEATURES

• Eighteen LVCMOS/LVTTL outputs, 23Ω typical output impedance
• Selectable LVCMOS_CLK or LVPECL clock inputs
• LVCMOS_CLK supports the following input types: LVCMOS or LVTTL
• PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
• Maximum output frequency: 250MHz
• Output skew: 85ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in lead-free RoHS compliant package Q0:Q17 CLK_SEL PCLKnPCLK LVCMOS_CLK

2 REVISION A 11/4/14

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS

0 Selected De-selected

1 De-selected Selected

NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”. 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS_CLK Input Pulldown Clock input. LVCMOS / LVTTL interface levels.

4 CLK_SEL Input Pulldown

LOW. LVCMOS / LVTTL interface levels. 5 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 6 nPCLK Input Inverting differential LVPECL clock input. DD/2 default when left fl oating. 7V DD Power Power supply pin. 8, 16, 21, 29 V DDO Power Output supply pins. Output Clock outputs. LVCMOS / LVTTL interface levels. Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

3 LOW SKEW, 1-TO-18

LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 3.6V Inputs, V I -0.3V to V DD + 0.3V Outputs, V O -0.3V to V DDO + 0.3V Input Current, I IN ±20mA Storage Temperature, T STG -40°C to 125°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0° TO 70° TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2.4 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V VPP Peak-to-Peak Input Voltage PCLK, nPCLK 500 1000 mV VCMR Input Common Mode Voltage; NOTE 1, 2 PCLK, nPCLK V DD - 1.4 V DD - 0.6 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -20mA 2.4 V VOL Output Low Voltage I OL = 20mA 0.5 V IDD Power Supply Current 25 mA NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2.4 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V VPP Peak-to-Peak Input Voltage PCLK, nPCLK 300 1000 mV VCMR Input Common Mode Voltage; NOTE 1, 2 PCLK, nPCLK V DD - 1.4 V DD - 0.6 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -20mA 1.8 V VOL Output Low Voltage I OL = 20mA 0.5 V IDD Power Supply Current 25 mA NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH.

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER 83940-01 DATA SHEET

4 REVISION A 11/4/14

TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 f 150MHz 1.6 3.0 ns LVCMOS_CLK; NOTE 2, 5 f 150MHz 1.8 3.0 ns tpLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 f > 150MHz 1.6 3.3 ns LVCMOS_CLK; NOTE 2, 5 f > 150MHz 1.8 3.2 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 85 ps LVCMOS_CLK 85 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f 150MHz 1.4 ns LVCMOS_CLK f 150MHz 1.2 ns tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f > 150MHz 1.7 ns LVCMOS_CLK f > 150MHz 1.4 ns tsk(pp) Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 850 ps LVCMOS_CLK 750 ps tR, tF Output Rise/Fall Time 20% to 80% 400 800 ps odc Output Duty Cycle f 150MHz 45 55 % 150MHz < f 250MHz 40 60 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 6: Defi ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage LVCMOS_CLK 2 V DD V VIL Input Low Voltage LVCMOS_CLK 0.8 V VPP Peak-to-Peak Input Voltage PCLK, nPCLK 300 1000 mV VCMR Input Common Mode Voltage; NOTE 1, 2 PCLK, nPCLK V DD - 1.4 V DD - 0.6 V IIN Input Current ±200 µA VOH Output High Voltage I OH = -12mA 1.8 V VOL Output Low Voltage I OL = 12mA 0.5 V IDD Power Supply Current 25 mA NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH.

5 LOW SKEW, 1-TO-18

LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 f 150MHz 1.7 3.2 ns LVCMOS_CLK; NOTE 2, 5 f 150MHz 1.7 3.0 ns tpLH Propagation Delay PCLK, nPCLK; NOTE 1, 5 f > 150MHz 1.6 3.4 ns LVCMOS_CLK; NOTE 2, 5 f > 150MHz 1.8 3.3 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 150 ps LVCMOS_CLK 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f 150MHz 1.5 ns LVCMOS_CLK f 150MHz 1.3 ns tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f > 150MHz 1.8 ns LVCMOS_CLK f > 150MHz 1.5 ns tsk(pp) Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 850 ps LVCMOS_CLK 750 ps tR, tF Output Rise/Fall Time 20% to 80% 400 800 ps odc Output Duty Cycle f < 134MHz 45 55 % 134MHz f < 250MHz 40 60 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 6: Defi ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2.

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER 83940-01 DATA SHEET

6 REVISION A 11/4/14

TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0° TO 70° Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 200 MHz tpLH Propagation Delay; PCLK, nPCLK; NOTE 1, 5 f 150MHz 1.2 3.8 ns LVCMOS_CLK; NOTE 2, 5 f 150MHz 1.5 3.2 ns tpLH Propagation Delay; PCLK, nPCLK; NOTE 1, 5 f > 150MHz 1.5 3.7 ns LVCMOS_CLK; NOTE 2, 5 f > 150MHz 2 3.6 ns tsk(o) Output Skew; NOTE 3, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 150 ps LVCMOS_CLK 150 ps tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f 150MHz 2.6 ns LVCMOS_CLK f 150MHz 1.7 ns tsk(pp) Part-to-Part Skew; NOTE 6 PCLK, nPCLK f > 150MHz 2.2 ns LVCMOS_CLK f > 150MHz 1.7 ns tsk(pp) Part-to-Part Skew; NOTE 4, 5 PCLK, nPCLK Measured on rising edge @VDDO/2 1.2 ns LVCMOS_CLK 1.0 ns tR, tF Output Rise/Fall Time 20% to 80% 400 800 ps odc Output Duty Cycle f < 134MHz 45 55 % 134MHz f 200MHz 40 60 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 6: Defi ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2.

7 LOW SKEW, 1-TO-18

LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART-TO-PART SKEW OUTPUT SKEW

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER 83940-01 DATA SHEET

8 REVISION A 11/4/14

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

9 LOW SKEW, 1-TO-18

LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 1kΩ resistor can be tied from the CLK input to ground. protection. A 1kΩ resistor can be used. that there is no trace attached.

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER 83940-01 DATA SHEET

10 REVISION A 11/4/14

LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and oth- er differential signals. Both V SWING and V OH must meet the VPP and V CMR input requirements. Figures 2A to 2E show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confi rm the driver termination requirements. FIGURE 2A. PCLK/nPCLK I NPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 2B. PCLK/nPCLK I NPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER FIGURE 2C. PCLK/nPCLK I NPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 2F. PCLK/nPCLK I NPUT DRIVEN BY A 3.3V LVDS DRIVER PCLK/nPCLK 2.5V Zo = 60 Ohm SSTL HiPerClockS PCLK nPCLK 120 3.3V 120 Zo = 60 Ohm 120 120 2.5V FIGURE 2E. PCLK/nPCLK I NPUT DRIVEN BY AN SSTL DRIVER HiPerClockS PCLK nPCLK PCLK/nPCLK 3.3V 3.3V Zo = 50 Ohm CML 3.3V Zo = 50 Ohm 3.3V HiPerClockS PCLK nPCLK 125 Input Zo = 50 Ohm 125 LVPECL 3.3V 3.3V Zo = 50 Ohm 100 Zo = 50 Ohm 3.3V 3.3V LVDS HiPerClockS PCLK nPCLK Zo = 50 Ohm 3.3V PCLK/nPCLK 3.3V 100 - 200 3.3V 3.3V HiPerClockS PCLK nPCLK 125 PCLK/nPCLK 125 Zo = 50 Ohm Zo = 50 Ohm 100 - 200 3.3V LVPECL FIGURE 2D. PCLK/nPCLK I NPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE

11 LOW SKEW, 1-TO-18

TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

12 REVISION A 11/4/14

TABLE 7. PACKAGE DIMENSIONS

13 LOW SKEW, 1-TO-18

TABLE 8. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS complaint.

LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER 83940-01 DATA SHEET

14 REVISION A 11/4/14

Rev Table Page Description of Change Date A T8 Added Lead-Free bullet. Added Recommendations for Unused Input and Output Pins. Updated LVPECL Clock Input Interface section. Added Lead-Free part number, marking and note. 11/18/05 AT 8 1 3 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/4/10 A T 13 Removed Leaded devices Updated Datasheet format 11/4/14

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