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Technical content
Features
- Eighteen LVCMOS/LVTTL output
- Selectable crystal oscillator interface or LVCMOS_CLK
- Maximum output frequency: 200MHz
- Crystal input frequency range: 10MHz to 40MHz
- RMS phase jitter using a 25MHz crystal (1kHz – 1MHz): 0.449ps (typical) @ 3.3V/3.3V
- Output skew: 75ps (maximum) @ 3.3V/3.3V
- Operating supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package OSC 0 Q0:Q17 Pulldown Pulldown CLK_SEL LVCMOS_CLK XTAL_IN XTAL_OUT 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 V DDO Q10 Q11 GND GND GND LVCMOS_CLK CLK_SEL XTAL_IN XTAL_OUT V DD VDDO GND VDDO Q0Q17 Q16 Q14 Q15 GND Q13 Q12 VDDO Pin Assignment 83918
32 Lead LQFP
7mm x 7mm x 1.4mm package body Y Package Top View Block Diagram 83918 Data Sheet Low Skew, 1:18 Crystal-to-LVCMOS/LVTTL Fanout Buffer
83918 Data Sheet
Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2, 12, 17, 25 GND Power Power supply ground. 3 LVCMOS_CLK Input Pulldown Single-ended clock i nput. LVCMOS/LVTTL interface levels. selects crystal inputs. LVCMOS/LVTTL interface levels. 7V DD Power Positive supply pin. 8, 16, 21, 29 V DDO Power Output supply pins. Output Single-ended clock outputs. LV CMOS/LVTTL interface levels.
3©2016 Integrated Device Technology, Inc Revision B March 17, 2016 NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C Table 3C. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 53.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 24 mA IDDO Output Supply Current No Load 27 mA Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 24 mA IDDO Output Supply Current No Load 26 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 24 mA IDDO Output Supply Current No Load 29 mA
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 4. Crystal Characteristics
5©2016 Integrated Device Technology, Inc Revision B March 17, 2016 Table 5A. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at fOUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units fOUT Output Frequency 200 MHz tpLH Propagation Delay, Low to High; NOTE 1 1.85 3.0 ns tjit(Ø) RMS Phase Jitter, (Random); NOTE 2 25MHz, Integration Range: 1kHz to 1MHz 0.449 ps tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz to 20MHz 0.145 ps tsk(o) Output Skew; NOTE 3, 6 75 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 300 700 ps odc Output Duty Cycle ƒ OUT 150MHz 45 55 %
6©2016 Integrated Device Technology, Inc Revision B March 17, 2016 Table 5B. AC Characteristics, VDD = 3.3V±5%,VDDO = 2.5V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at f OUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5C. AC Characteristics, VDD = 3.3V±5%,VDDO = 1.8V±0.2V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at f OUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 200 MHz tpLH Propagation Delay, Low to High; NOTE 1 23 n s tjit(Ø) RMS Phase Jitter, (Random); NOTE 2 25MHz, Integration Range: 1kHz to 1MHz 0.465 ps tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz to 20MHz 0.161 ps tsk(o) Output Skew; NOTE 3, 6 75 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 1n s tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 300 700 ps odc Output Duty Cycle ƒ OUT 150MHz 45 55 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 200 MHz tpLH Propagation Delay, Low to High; NOTE 1 1.65 4.3 ns tjit(Ø) RMS Phase Jitter, (Random); NOTE 2 25MHz, Integration Range: 1kHz to 1MHz 0.595 ps tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz to 20MHz 0.228 ps tsk(o) Output Skew; NOTE 3, 6 75 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 1n s tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps odc Output Duty Cycle ƒ OUT 150MHz 40 60 %
7©2016 Integrated Device Technology, Inc Revision B March 17, 2016 Table 5D. AC Characteristics, VDD = VDDO = 2.5V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at f OUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5E. AC Characteristics, VDD = 2.5V±5%,VDDO = 1.8V±0.2V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at f OUT unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Refer to the Phase Noise Plot following this section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 200 MHz tpLH Propagation Delay, Low to High; NOTE 1 23 n s tjit(Ø) RMS Phase Jitter, (Random); NOTE 2 25MHz, Integration Range: 1kHz to 1MHz 0.478 ps tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz to 20MHz 0.157 ps tsk(o) Output Skew; NOTE 3, 6 75 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 1n s tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 300 700 ps odc Output Duty Cycle ƒ OUT 150MHz 45 55 % Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 200 MHz tpLH Propagation Delay, Low to High; NOTE 1 1.75 3.85 ns tjit(Ø) RMS Phase Jitter, (Random); NOTE 2 25MHz, Integration Range: 1kHz to 1MHz 0.591 ps tjit Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 155.52MHz, Integration Range: 12kHz to 20MHz 0.175 ps tsk(o) Output Skew; NOTE 3, 6 75 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 1.15 ns tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 800 ps odc Output Duty Cycle ƒ OUT 150MHz 45 55 %
8©2016 Integrated Device Technology, Inc Revision B March 17, 2016 Typical Phase Noise at 25MHz Crystal (3.3V core/3.3V output) Noise Power dBc Hz Offset Frequency (Hz)
9©2016 Integrated Device Technology, Inc Revision B March 17, 2016 Additive Phase Jitter (2.5V output) The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator". Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.161ps (typical) SSB Phase Noise dBc/Hz Offset from Carr ier Frequency (Hz)
10©2016 Integrated Device Technology, Inc Revision B March 17, 2016 Parameter Measurement Information 3.3 Core/3.3V Output Load AC Test Circuit 3.3V Core/1.8V Output Load AC Test Circuit 2.5V/1.8V Output Load AC Test Circuit 3.3V Core/2.5V Output Load AC Test Circuit 2.5V/2.5V Output Load AC Test Circuit RMS Phase Jitter SCOPE Qx GND 1.65V±5% -1.65V±5% VDD, VDDO VDD VDDO SCOPE Qx GND 2.4V±5% -0.9V±0.1V 0.9V±0.1V VDD VDDO SCOPE Qx GND 1.6V±0.025V -0.9V±0.1V 0.9V±0.1V VDD VDDO SCOPE Qx GND 2.05V±5% -1.25V±5% 1.25V±5% VDD VDDO SCOPE Qx GND 1.25V±5% -1.25V±5% VDD, VDDO
11©2016 Integrated Device Technology, Inc Revision B March 17, 2016 Parameter Measurement Information, continued Output Skew Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period Part-to-Part Skew Propagation Delay Qx Qy tsk(b) VCCO VCCO 20% 80% 80% 20% tR tF Q0:Q17 Q0:Q17 Qx Qy tsk(pp) VDDO VDDO Part 1 Part 2 t PD VDD VDDO 2Q0:Q17 LVCMOS_CLK
can be slightly adjusted for different board layouts. Figure 1. Crystal Input Interface performance is guaranteed by using a quartz crystal.
13©2016 Integrated Device Technology, Inc Revision B March 17, 2016 Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. LVCMOS_CLK Input For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the LVCMOS_CLK to ground. LVCMOS Control Pin The control pin has an internal pulldown; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached.
This section provides information on power dissipation and junction temperature for the 83918. Equations and example calculations are also provided. DD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 53.5°C/W per Table 6 below. Table 6. Thermal Resistance JA for 32 Lead LQFP, Forced Convection
Table 7. JA vs. Air Flow Table for a 32 Lead LQFP
Table 8. Package Dimensions for 32 Lead LQFP
17©2016 Integrated Device Technology, Inc Revision B March 17, 2016
Ordering Information
Table 9. Ordering Information
18©2016 Integrated Device Technology, Inc Revision B March 17, 2016 Rev Table Page Description of Change Date B T5A, T5B, T5D, T5E T5D 5 - 7 AC Characteristic Tables - added Test Conditions to Output Duty Cycle. 2.5 AC Characteristics Table - changed Part-to-Part skew from 1.1ns max to 1.0 ns max. 8/17/10 Updated data sheet format. 3/25/15 Updated header and footer. 3/17/16
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