83908I-02 Datasheet

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  • Manufacturer or author: rdvorak
  • PDF pages: 16

Technical content

Low Skew, 1-to-8 Crystal-to-LVCMOS Fanout Buffer 83908I-02 Data Sheet ©2016 Integrated Device Technology, Inc Revision A March 17, 20161 GENERAL DESCRIPTION The 83908I-02 is a low skew, high performance 1-to-8 Crystal Oscillator//Crystal-to-LVCMOS fanout buffer from IDT. The 83908I-02 has selectable single-ended clock or two crystal-oscillator inputs. There is an output enable to disable the outputs by placing them into a high-impedance state. Guaranteed output and part-to-part skew characteristics make the 83908I-02 ideal for those applications demanding well defi ned performance and repeatability.

FEATURES

  • Eight LVCMOS/LVTTL outputs , 19 Ω typical output impedance @ V DD = V DDO = 3.3V
  • Two Crystal oscillator input pairs One LVCMOS/LVTTL clock input
  • Crystal input frequency range: 10MHz - 40MHz
  • Output frequency: 200MHz (typical)
  • Output Skew: 70ps (maximum) @ V DD = V DDO = 3.3V
  • Part-to-part skew: 700ps (maximum) @ V DD = V DDO = 3.3V
  • RMS phase jitter @ 25MHz output using a 25MHz crystal (12kHz - 10MHz): 0.39ps (typical) @ V DD = V DDO = 3.3V Offset Noise Power Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V
  • -40 °C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package OSC OSC 0 0 0 1 1 0 1 1

8 LVCMOS Outputs

CLK_SEL0 CLK CLK_SEL1 XTAL_IN0 XTAL_OUT0 XTAL_IN1 XTAL_OUT1 BLOCK DIAGRAM PIN ASSIGNMENT 83908I-02 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.925mm body package G Package Top View VDD XTAL_IN0 XTAL_OUT0 VDDO GND V DDO CLK_SEL0 CLK GND XTAL_IN1 XTAL_OUT1 V DDO GND V DDO CLK_SEL1 OE

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS XTAL_OUT0 Input Crystal oscillator interface. XTAL_IN0 is the input. Q4, Q5, Q6, Q7 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 7, 18, 24 GND Power Power supply ground. CLK_SEL1 Input Pulldown Clock select inputs. See Table 3, Input Reference Function Table. LVCMOS / LVTTL interface levels. 12 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 13 OE Input Pullup Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. XTAL_IN1 Input Crystal oscillator interface. XTAL_IN1 is the input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 3. INPUT REFERENCE FUNCTION TABLE

©2016 Integrated Device Technology, Inc Revision A March 17, 20163 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θ JA 87.8°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current No Load & XTALx selected 30 mA No Load & CLK selected 1 mA I DDO Output Supply Current No Load & CLK selected 1 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current No Load & XTALx selected 30 mA No Load & CLK selected 1 mA I DDO Output Supply Current No Load & CLK selected 1 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 1.6 1.8 2.0 V I DD Power Supply Current No Load & XTALx selected 30 mA No Load & CLK selected 1 mA I DDO Output Supply Current No Load & CLK selected 1 mA

/2. See Parameter Measurement section, “Load Test Circuit” diagrams. TABLE 5. CRYSTAL CHARACTERISTICS

©2016 Integrated Device Technology, Inc Revision A March 17, 20165 TABLE 6A. AC CHARACTERISTICS, V DD = V DDO TABLE 6B. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Fre- quency w/external XTAL 10 40 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.4 2.0 2.6 ns tsk(o) Output Skew; NOTE 2 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 4 25MHz XTAL, (12kHz-10MHz) 0.39 ps t R / t F Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle w/external XTAL ƒ ≤ 38.88MHz 45 55 % w/external CLK ƒ ≤ 133MHz 47 53 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Fre- quency w/external XTAL 10 40 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.5 2.1 2.7 ns tsk(o) Output Skew; NOTE 2 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 4 25MHz XTAL, (12kHz-10MHz) 0.42 ps t R / t F Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle w/external XTAL ƒ ≤ 38.88MHz 45 55 % w/external CLK ƒ ≤ 133MHz 47 53 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

©2016 Integrated Device Technology, Inc Revision A March 17, 20166 TABLE 6D. AC CHARACTERISTICS, V DD = V DDO TABLE 6C. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Fre- quency w/external XTAL 10 40 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.6 2.4 3.2 ns tsk(o) Output Skew; NOTE 2 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 4 25MHz XTAL, (12kHz-10MHz) 0.43 ps t R / t F Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle w/external XTAL ƒ ≤ 38.88MHz 45 55 % w/external CLK ƒ ≤ 133MHz 47 53 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Fre- quency w/external XTAL 10 40 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.7 2.4 3.1 ns tsk(o) Output Skew; NOTE 2 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 4 25MHz XTAL, (12kHz-10MHz) 0.44 ps t R / t F Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle w/external XTAL ƒ ≤ 38.88MHz 45 55 % w/external CLK ƒ ≤ 133MHz 47 53 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

©2016 Integrated Device Technology, Inc Revision A March 17, 20167 TABLE 6E. AC CHARACTERISTICS, V DD = 2.5V ± 5%, V DDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Fre- quency w/external XTAL 10 40 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.7 2.6 3.5 ns tsk(o) Output Skew; NOTE 2 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 4 25MHz XTAL, (12kHz-10MHz) 0.37 ps t R / t F Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle w/external XTAL ƒ ≤ 38.88MHz 45 55 % w/external CLK ƒ ≤ 133MHz 47 53 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

©2016 Integrated Device Technology, Inc Revision A March 17, 20168 25MHz RMS Phase Jitter (Random) 12kHz to 10MHz = 0.39ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz TYPICAL PHASE NOISE AT 25MHZ @ 3.3V/3.3V Raw Phase Noise Data

©2016 Integrated Device Technology, Inc Revision A March 17, 20169 PARAMETER MEASUREMENT INFORMATION 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER

©2016 Integrated Device Technology, Inc Revision A March 17, 201610 OUTPUT SKEW PART-TO-PART SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME PROPAGATION DELAY Qx Qy tsk(o) VDDO VDDO PARAMETER MEASUREMENT INFORMATION, CONTINUED

©2016 Integrated Device Technology, Inc Revision A March 17, 201612 INPUTS: CLK INPUT For applications not requiring the use of the clock input, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. C RYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT should be tied to ground. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground and from XTAL_OUT to ground. LVCMOS C ONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVCMOS OUTPUTS All unused LVCMOS output can be left fl oating. There should be no trace attached.

TABLE 7. θ

TABLE 9. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision A March 17, 201615 REVISION HISTORY SHEET Rev Table Page Description of Change Date Updated datasheet format. 3/27/15 Updated header and footer 3/17/16

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