83908-02 Final Data Sheet

Document overview

  • Manufacturer or author: epieczon
  • PDF pages: 16

Technical content

Features

  • Eight LVCMOS / LVTTL outputs, 19 typical output impedance at VDD = VDDO = 3.3V
  • Two crystal oscillator input pairs One LVCMOS / LVTTL clock input
  • Crystal input frequency range: 10MHz – 40MHz
  • Output frequency: 200MHz (maximum)
  • Output skew: 70ps (maximum) at VDD = VDDO = 3.3V
  • Part-to-part skew: 700ps (maximum) at VDD = VDDO = 3.3V
  • RMS phase jitter @ 25MHz output, using a 25MHz crystal, (12kHz – 10MHz): 0.39ps (typical) at V DD = VDDO = 3.3V
  • RMS phase noise at 25MHz Offset Noise Power
  • Power Supply Voltage Modes: Core / Output 3.3V / 3.3V 3.3V / 2.5V 3.3V / 1.8V 2.5V / 2.5V 2.5V / 1.8V
  • 0°C to 70°C ambient operating temperature
  • Lead-free (RoHS 6) packaging Block Diagram Pin Assignment 83908-02 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View OSC OSC 0 0 0 1 1 0 1 1

8 LVCMOS Outputs

CLK_SEL0 CLK CLK_SEL1 XTAL_IN0 XTAL_OUT0 XTAL_IN1 XTAL_OUT1 GND XTAL_IN1 XTAL_OUT1 VDDO GND VDDO CLK_SEL1 OE VDD XTAL_OUT0 VDDO GND VDD0 CLK FemtoClock® Crystal-to-LVDS 8-Output Clock Synthesizer 83908-02 Datasheet

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Input Reference Function Table 1V DD Power Power supply pin. XTAL_OUT0 Input Crystal oscillator interface. XTAL_IN0 is the input. 4, 10, 15, 21 V DDO Power Output supply pins. Q4, Q5, Q6, Q7 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 7, 18, 24 GND Power Power supply ground. CLK_SEL1 Input Pulldown Clock select inputs. See Table 3, Input Reference Function Table. LVCMOS/LVTTL interface levels. 12 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 13 OE Input Pullup Output enable. When LOW, outputs are in high-impedance state. When HIGH, outputs are active. LVCMOS/LVTTL interface levels. XTAL_IN1 Input Crystal oscillator interface. XTAL_IN1 is the input.

3©2016 Integrated Device Technology, Inc. Revision B, April 7, 2016 83908-02 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ±5%, TA = 0°C to 70°C Table 4B. Power Supply DC Characteristics, VDD = 3.3V ±5%, VDDO = 2.5V ±5%, TA = 0°C to 70°C Table 4C. Power Supply DC Characteristics, VDD = 3.3V ±5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 87.8C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current No Load & XTALx selected 30 mA No Load & CLK selected 1 mA IDDO Output Supply Current No Load & CLK selected 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current No Load & XTALx selected 30 mA No Load & CLK selected 1 mA IDDO Output Supply Current No Load & CLK selected 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current No Load & XTALx selected 30 mA No Load & CLK selected 1 mA IDDO Output Supply Current No Load & CLK selected 1 mA

4©2016 Integrated Device Technology, Inc. Revision B, April 7, 2016 83908-02 Datasheet Table 4D. Power Supply DC Characteristics, VDD = VDDO = 2.5V ±5%, TA = 0°C to 70°C Table 4E. Power Supply DC Characteristics, VDD = 2.5V ±5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C Table 4F. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, Load Test Circuit diagram. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current No Load & XTALx selected 20 mA No Load & CLK selected 1 mA IDDO Output Supply Current No Load & CLK selected 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current No Load & XTALx selected 20 mA No Load & CLK selected 1 mA IDDO Output Supply Current No Load & CLK selected 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V ±5% 2.2 V DD + 0.3 V VDD = 2.5V ±5% 1.6 V DD + 0.3 V VIL Input Low Voltage IIH Input High Current CLK, CLK_SEL[0:1] VDD = 3.3V or 2.5V ±5% 150 µA OE V DD = 3.3V or 2.5V ±5% 5 µA IIL Input Low Current CLK, CLK_SEL[0:1] VDD = 3.3V or 2.5V ±5% -5 µA OE V DD = 3.3V or 2.5V ±5% -150 µA VOH Output High Voltage; NOTE 1 VDDO = 3.3V ±5% 2.6 V VDDO = 2.5V ±5% 1.8 V VDDO = 1.8V ±0.2V 1.2 V VOL Output Low Voltage; NOTE 1 VDDO = 3.3V ±5% 0.6 V VDDO = 2.5V ±5% 0.5 V VDDO = 1.8V ±0.2V 0.4 V

Table 5. Crystal Characteristics has been reached under these conditions. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

6©2016 Integrated Device Technology, Inc. Revision B, April 7, 2016 83908-02 Datasheet Table 6B. AC Characteristics, VDD = 3.3V ±5%, VDDO = 2.5V ±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the V DD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Table 6C. AC Characteristics, VDD = 3.3V ±5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency w/ external XTAL 10 40 MHz w/ external CLK 200 MHz tpLH Propagation Delay, Low to High; NOTE 1 1.5 2.1 2.7 ns tsk(o) Output Skew; NOTE 2 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit() RMS Phase Jitter, Random; NOTE 4 25MHz, Integration Range: 12kHz – 10MHz 0.42 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle w/ external XTAL  38.88MHz 45 55 % w/ external CLK  133MHz 47 53 % tEN Output Enable Time; NOTE 5 10 ns tDIS Output Disable Time; NOTE 5 10 ns Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency w/ external XTAL 10 40 MHz w/ external CLK 200 MHz tpLH Propagation Delay, Low to High; NOTE 1 1.6 2.4 3.2 ns tsk(o) Output Skew; NOTE 2 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit() RMS Phase Jitter, Random; NOTE 4 25MHz, Integration Range: 12kHz – 10MHz 0.43 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle w/ external XTAL  38.88MHz 45 55 % w/ external CLK  133MHz 47 53 % tEN Output Enable Time; NOTE 5 10 ns tDIS Output Disable Time; NOTE 5 10 ns

7©2016 Integrated Device Technology, Inc. Revision B, April 7, 2016 83908-02 Datasheet Table 6D. AC Characteristics, VDD = VDDO = 2.5V ±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the V DD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Table 6E. AC Characteristics, VDD = 2.5V ±5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency w/ external XTAL 10 40 MHz w/ external CLK 200 MHz tpLH Propagation Delay, Low to High; NOTE 1 1.7 2.4 3.1 ns tsk(o) Output Skew; NOTE 2 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit() RMS Phase Jitter, Random; NOTE 4 25MHz, Integration Range: 12kHz – 10MHz 0.44 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle w/ external XTAL  38.88MHz 45 55 % w/ external CLK  133MHz 47 53 % tEN Output Enable Time; NOTE 5 10 ns tDIS Output Disable Time; NOTE 5 10 ns Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency w/ external XTAL 10 40 MHz w/ external CLK 200 MHz tpLH Propagation Delay, Low to High; NOTE 1 1.7 2.6 3.5 ns tsk(o) Output Skew; NOTE 2 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit() RMS Phase Jitter, Random; NOTE 4 25MHz, Integration Range: 12kHz – 10MHz 0.37 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle w/ external XTAL  38.88MHz 45 55 % w/ external CLK  133MHz 47 53 % tEN Output Enable Time; NOTE 5 10 ns tDIS Output Disable Time; NOTE 5 10 ns

8©2016 Integrated Device Technology, Inc. Revision B, April 7, 2016 83908-02 Datasheet Typical Phase Noise at 25MHz @3.3V/3.3V Noise Power (dBc/Hz) Offset Frequency (Hz) 25MHz RMS Phase Jitter Random) 12kHz to 10MHz = 0.39ps (typical) Raw Phase Noise Data

9©2016 Integrated Device Technology, Inc. Revision B, April 7, 2016 83908-02 Datasheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load Test Circuit 3.3V Core/1.8V LVCMOS Output Load Test Circuit 2.5V Core/1.8V LVCMOS Output Load Test Circuit 3.3V Core/2.5V LVCMOS Output Load Test Circuit 2.5V Core/2.5V LVCMOS Output Load Test Circuit RMS Phase Jitter SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO SCOPE Qx GND VDDO VDD 0.9V±0.1V -1.25V±5% 2.4V±0.065V SCOPE Qx GND VDDO VDD 0.9V±0.1V 1.6V±0.025V SCOPE Qx GND VDDO VDD 1.25V±5% -1.25V±5% 2.05V±5% SCOPE Qx GND VDD, 1.25V±5% -1.25V±5% VDDO Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power

10©2016 Integrated Device Technology, Inc. Revision B, April 7, 2016 83908-02 Datasheet Parameter Measurement Information, continued Output Skew Propagation Delay Output Duty Cycle/Pulse Width/Period Part-to-Part Skew Output Rise/Fall Time tsk(o) VDDO VDDO Qx Qy t PD VDD VDDO CLK Q[0:7] Q[0:7] tsk(pp) VDDO VDDO Part 1 Part 2 Qx Qy 20% 80% 80% 20% tR tF Q[0:7]

Table 7. JA vs. Air Flow Table for a 24-Lead TSSOP

14©2016 Integrated Device Technology, Inc. Revision B, April 7, 2016 83908-02 Datasheet

Ordering Information

Table 9. Ordering Information

15©2016 Integrated Device Technology, Inc. Revision B, April 7, 2016 83908-02 Datasheet Revision History Sheet Rev Table Page Description of Change Date B Deleted “ICS” prefix from part number throughout the datasheet. Updated datasheet header/footer. 4/7/16

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