83905I RENESAS | Alldatasheet
Document overview
- Manufacturer or author: epieczon
- PDF pages: 22
Technical content
Features
- Six LVCMOS / LVTTL outputs
- Outputs able to drive 12 series terminated lines
- Crystal Oscillator Interface
- Crystal input frequency range: 10MHz to 40MHz
- Output skew: 80ps (maximum)
- RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.26ps (typical), VDD = VDDO = 2.5V Offset Noise Power
- 5V tolerant enable inputs
- Synchronous output enables
- Operating power supply modes: Full 3.3V, 2.5V, 1.8V Mixed 3.3V core/2.5V output operating supply Mixed 3.3V core/1.8V output operating supply Mixed 2.5V core/1.8V output operating supply
- -40°C to 85°C ambient operating temperature
- Lead-free (RoHS 6) packaging Block Diagram XTAL_IN ENABLE1 BCLK5 VDDO BCLK4 GND BCLK3 VDDBCLK2 GND BCLK1 VDDO BCLK0 GND ENABLE2 XTAL_OUT 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View SYNCHRONIZE SYNCHRONIZE BCLK0 BCLK1 BCLK2 BCLK3 BCLK4 BCLK5 XTAL_IN XTAL_OUT ENABLE 1 ENABLE 2 83905I Datasheet Low Skew, 1:6 Crystal Interface to LVCMOS/ LVTTL Fanout Buffer
Table 1. Pin Descriptions Table 2. Pin Characteristics 1 XTAL_OUT Output Crystal oscillator inte rface. XTAL_OUT is the output. 2 ENABLE2 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3. 3 GND Power Power supply ground. 4 BCLK0 Output Clock output. LVCM OS/LVTTL interface levels. DDO Power Output supply pin. 6 BCLK1 Output Clock output. LVCM OS/LVTTL interface levels. 7 GND Power Power supply ground. 8 BCLK2 Output Clock output. LVCM OS/LVTTL interface levels. 10 BCLK3 Output Clock output. LVCM OS/LVTTL interface levels. 11 GND Power Power supply ground. 12 BCLK4 Output Clock output. LVCM OS/LVTTL interface levels. 13 V DDO Power Output supply pin. 14 BCLK5 Output Clock output. LVCM OS/LVTTL interface levels. 15 ENABLE1 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3. 16 XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input.
Table 3. Output Enable and Clock Enable Function Table Figure 1. Enable Timing Diagram
4©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO+ 0.5V Package Thermal Impedance, JA 16-Lead TSSOP package 89 C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current ENABLE [1:2] = 00 10 mA IDDO Output Supply Current ENABLE [1:2] = 00 5 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current ENABLE [1:2] = 00 8 mA IDDO Output Supply Current ENABLE [1:2] = 00 4 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current ENABLE [1:2] = 00 5 mA IDDO Output Supply Current ENABLE [1:2] = 00 3 mA
5©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet Table 4D. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C Table 4E. Power Supply DC Characteristics, 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C Table 4F. Power Supply DC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current ENABLE [1:2] = 00 10 mA IDDO Output Supply Current ENABLE [1:2] = 00 4 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current ENABLE [1:2] = 00 10 mA IDDO Output Supply Current ENABLE [1:2] = 00 3 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current ENABLE [1:2] = 00 8 mA IDDO Output Supply Current ENABLE [1:2] = 00 3 mA
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Table 5. Crystal Characteristics
7©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ fMAX using a crystal input unless noted otherwise. NOTE: Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Table 6B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ fMAX using a crystal input unless noted otherwise. NOTE: Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f MAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz odc Output Duty Cycle 48 52 % tsk(o) Output Skew; NOTE 2, 3 80 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 4 25MHz, Integration Range: 100Hz – 1MHz 0.13 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps tEN Output Enable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz odc Output Duty Cycle 47 53 % tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random); NOTE 4 25MHz, Integration Range: 100Hz – 1MHz 0.26 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps tEN Output Enable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles
8©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet Table 6C. AC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ fMAX using a crystal input unless noted otherwise. NOTE: Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Table 6D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ fMAX using a crystal input unless noted otherwise. NOTE: Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz odc Output Duty Cycle 47 53 % tsk(o) Output Skew; NOTE 2, 3 80 ps tjit(Ø) RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.27 ps tR / tF Output Rise/Fall Time 20% to 80% 200 900 ps tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz odc Output Duty Cycle 48 52 % tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.14 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles t DIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles
9©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet Table 6E. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ fMAX using a crystal input unless noted otherwise. NOTE: Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Table 6F. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ fMAX using a crystal input unless noted otherwise. NOTE: Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz odc Output Duty Cycle 48 52 % tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.18 ps tR / tF Output Rise/Fall Time 20% to 80% 200 900 ps tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f MAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz odc Output Duty Cycle 47 53 % tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.19 ps tR / tF Output Rise/Fall Time 20% to 80% 200 900 ps tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles t DIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles
10©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet Typical Phase Noise at 25MHz (2.5V Core/2.5V Output) Typical Phase Noise at 25MHz (2.5V Core/2.5V Output) Raw Phase Noise Data 25MHz RMS Phase Jitter (Random) 100Hz to 1MHz = 0.26ps (typical) Noise Power(dBc/Hz) Offset Frequency (Hz) Raw Phase Noise Data 25MHz RMS Phase Jitter (Random) 100Hz to 1MHz = 0.13ps (typical) Noise Power(dBc/Hz) Offset Frequency (Hz)
11©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 1.8V Core/1.8V LVCMOS Output Load AC Test Circuit 3.3V Core/1.8V LVCMOS Output Load AC Test Circuit 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 2.5V Core/1.8V LVCMOS Output Load AC Test Circuit SCOPE Qx GND VDD, -1.65V±5% 1.65V±5% VDDO SCOPE Qx GND VDD, -0.9V±0.1V 0.9V±0.1V VDDO SCOPE Qx GND VDD -0.9V±0.1V 2.4V±0.9V VDDO 0.9V±0.1V SCOPE Qx GND VDD, -1.25±5% 1.25V±5% VDDO SCOPE Qx GND VDD -1.25±5% 2.05V±5% VDDO 1.25V±5% SCOPE Qx GND VDD -0.9V±0.1V 1.6V±0.025% VDDO 0.9V±0.1V
12©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet Parameter Measurement Information, continued Output Skew Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period Qx Qy t sk(b) VDDO VDDO 20% 80% 80% 20% tR tF BCLK[0:5] BCLK[0:5]
guaranteed by using a quartz crystal. Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface
the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. Enhance Leadframe Base Package, Amkor Technology. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) protection. A 1k resistor can be used.
This section provides information on power dissipation and junction temperature for the 83905I. Equations and example calculations are also provided. The total power dissipation for the 83905I is the sum of the core power plus the analog power plus the power dissipated due to the load. DD = 3.3V + 5% = 3.465V, which gives worst case results.
- Power (core) MAX = VDD_MAX * (IDD + IDDO) = 3.465V *(10mA + 5mA) = 51.9mW
- Output Impedance R OUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 7)] = 30.4mA
- Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 7 * (30.4mA)2 = 6.5mW per output
- Total Power Dissipation on the ROUT Total Power (ROUT) = 6.5mW * 6 = 39mW Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDD)2 = 19pF * 25MHz * (3.465V)2 = 5.70mW per output Total Power (25MHz) = 5.70mW * 6 = 34.2mW Total Power Dissipation
- Total Power = Power (core)MAX + Total Power (ROUT) + Total Power (25MHz) = 51.98mW + 39mW + 34.2mW = 125.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 89°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.125W * 89°C/W = 96.1°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 7. Thermal Resistance JA for 16-Lead TSSOP , Forced Convection NOTE: Most modern PCB designs use milti-layered boards. The data in the second row pertains to most designs.
Table 8. JA vs. Air Flow Table for a 16-Lead TSSOP NOTE: Most modern PCB designs use milti-layered boards. The data in the second row pertains to most designs.
Table 9. Package Dimensions for 16-Lead TSSOP
19©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet
Ordering Information
Table 10. Ordering Information
20©2016 Integrated Device Technology, Inc. Revision C September 28, 2016 83905I Datasheet Revision History Sheet Rev Table Page Description of Change Date A 2 Added Enable Timing Diagram. 3/28/05 B T6A - T6F 5 - 7 Features Section - added RMS Phase Jitter bullet. AC Characteristics Tables - added RMS Phase Jitter specs. Corrected ambient operating temperature Added Phase Noise Plot. 4/8/05 B 11 Added Crystal Input Interface in Application Section. Added Schematic layout. 5/16/05 B number. Removed 2500 on tape and reel shipping information. Removed lead free note. 12/3/15 C Corrected Figure 1, Enable Timing Diagram. Applications Information Section: Deleted Crystal Input Interface application note, see Layout Guideline Added LVCMOS to XTAL Interface application note Added VFQFN EPAD Thermal Release Path application note Added Recommendations for Unused Input and Output Pins application note Updated Layout Guideline, adding crystal interface Added Power Considerations section. Updated datasheet header/footer and format. 9/28/16
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