83905AMLFT

83905 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: epieczon
• PDF pages: 22

Technical content

Features

• Six LVCMOS / LVTTL outputs
• Outputs able to drive 12 series terminated lines
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Output skew: 80ps (maximum)
• RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.26ps (typical), VDD = VDDO = 2.5V Offset Noise Power
• 5V tolerant enable inputs
• Synchronous output enables
• Operating power supply modes: Full 3.3V, 2.5V, 1.8V Mixed 3.3V core/2.5V output operating supply Mixed 3.3V core/1.8V output operating supply Mixed 2.5V core/1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Lead-free (RoHS 6) packaging Block Diagram 6 7 8 9 10 19 20 18 17 16 GND VDDO GND BCLK0 BCLK1 BCLK4 BCLK5 VDDO GND GND VDD BCLK2 GND GND BCLK3 ENABLE1 ENABLE2 XTAL_IN XTAL_OUT nc XTAL_IN ENABLE1 BCLK5 VDDO BCLK4 GND BCLK3 VDDBCLK2 GND BCLK1 VDDO BCLK0 GND ENABLE2 XTAL_OUT 83905 16-Lead SOIC, 150 Mil 3.9mm x 9.9mm x 1.38mm package body M Package Top View 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View 83905 20-Lead VFQFN 4mm x 4mm x 0.925mm package body K Package Top View SYNCHRONIZE SYNCHRONIZE BCLK0 BCLK1 BCLK2 BCLK3 BCLK4 BCLK5 XTAL_IN XTAL_OUT ENABLE 1 ENABLE 2 83905 Datasheet Low Skew, 1:6 Crystal-to-LVCMOS/ LVTTL Fanout Buffer

83905 Datasheet

Table 1. Pin Descriptions Table 2. Pin Characteristics Table 3. Clock Enable Function Table Figure 1. Enable Timing Diagram XTAL_OUT Output Crystal oscillator in terface. XTAL_OUT is the output. XTAL_IN Input Crystal oscillator in terface. XTAL_IN is the input. ENABLE1, ENABLE2 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3. BCLK3, BCLK4, BCLK5 Output Clock outputs. LVCMOS/LVTTL interface levels. GND Power Power supply ground. VDDO Power Output supply pin.

3©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO+ 0.5V Package Thermal Impedance, JA 16-Lead SOIC package 16-Lead TSSOP package 20-Lead VFQFN package 78.8C/W (0 mps) 100.3C/W (0 mps) 57.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current ENABLE [1:2] = 00 10 mA IDDO Output Supply Current ENABLE [1:2] = 00 5 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current ENABLE [1:2] = 00 8 mA IDDO Output Supply Current ENABLE [1:2] = 00 4 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current ENABLE [1:2] = 00 5 mA IDDO Output Supply Current ENABLE [1:2] = 00 3 mA

4©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Table 4D. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C Table 4E. Power Supply DC Characteristics, 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Table 4F. Power Supply DC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current ENABLE [1:2] = 00 10 mA IDDO Output Supply Current ENABLE [1:2] = 00 4 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current ENABLE [1:2] = 00 10 mA IDDO Output Supply Current ENABLE [1:2] = 00 3 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current ENABLE [1:2] = 00 8 mA IDDO Output Supply Current ENABLE [1:2] = 00 3 mA

NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Table 5. Crystal Characteristics

6©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Table 6B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  f MAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f MAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 4 25MHz, Integration Range: 100Hz – 1MHz 0.13 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle 48 52 % tEN Output Enable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random); NOTE 4 25MHz, Integration Range: 100Hz – 1MHz 0.26 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle 47 53 % tEN Output Enable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles

7©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Table 6C. AC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. Table 6D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  f MAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units f MAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit(Ø) RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.27 ps tR / tF Output Rise/Fall Time 20% to 80% 200 900 ps odc Output Duty Cycle 47 53 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.14 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle 48 52 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles

8©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Table 6E. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. Table 6F. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ  f MAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f MAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.18 ps tR / tF Output Rise/Fall Time 20% to 80% 200 900 ps odc Output Duty Cycle 48 52 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.19 ps tR / tF Output Rise/Fall Time 20% to 80% 200 900 ps odc Output Duty Cycle 47 53 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles

9©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Typical Phase Noise at 25MHz (2.5V Core/2.5V Output) Raw Phase Noise Data 25MHz RMS Phase Jitter (Random) 100Hz to 1MHz = 0.26ps (typical) Noise Power(dBc/Hz) Offset Frequency (Hz)

10©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 1.8V Core/1.8V LVCMOS Output Load AC Test Circuit 3.3V Core/1.8V LVCMOS Output Load AC Test Circuit 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 2.5V Core/1.8V LVCMOS Output Load AC Test Circuit SCOPE Qx GND VDD, -1.65V±5% 1.65V±5% VDDO SCOPE Qx GND VDD, -0.9V±0.1V 0.9V±0.1V VDDO SCOPE Qx GND VDD -0.9V±0.1V 2.4V±0.9V VDDO 0.9V±0.1V SCOPE Qx GND VDD, -1.25±5% 1.25V±5% VDDO SCOPE Qx GND VDD -1.25±5% 2.05V±5% VDDO 1.25V±5% SCOPE Qx GND VDD -0.9V±0.1V 1.6V±0.025% VDDO 0.9V±0.1V

11©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Parameter Measurement Information, continued Output Skew Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period Qx Qy t sk(b) VDDO VDDO 20% 80% 80% 20% tR tF BCLK[0:5] BCLK[0:5]

12©2016 Integrated Device Technology, Inc. Revision D September 27, 2016

Application Information

Figure 2 shows an example of 83905 crystal interface with a parallel resonant crystal. The frequency accuracy can be fine tuned by adjusting the C1 and C2 values. For a parallel crystal with loading capacitance CL = 18pF, to start with, we suggest C1 = 15pF and C2 = 15pF. These values may be slightly fine tuned further to optimize the frequency accuracy for different board layouts. Slightly increasing the C1 and C2 values will slightly reduce the frequency. Slightly decreasing the C1 and C2 values will slightly increase the frequency. For the oscillator circuit below, R1 can be used, but is not required. For new designs, it is recommended that R1 not be used. Figure 2. Crystal Input Interface guaranteed by using a quartz crystal. Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface

the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) protection. A 1k resistor can be used.

LVCMOS Termination Application Note. place all filter components on the device side of the board. used for reducing external noise from coupling into the devices. capacitance in the local area of all devices. Figure 5. Schematic of Recommended Layout

This section provides information on power dissipation and junction temperature for the 83905. Equations and example calculations are also provided. The total power dissipation for the 83905 is the sum of the core power plus the analog power plus the power dissipated due to the load. DD = 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core) MAX = VDD_MAX * (IDD + IDDO) = 3.465V *(10mA + 5mA) = 51.9mW
• Output Impedance R OUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 7)] = 30.4mA
• Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 7 * (30.4mA)2 = 6.5mW per output
• Total Power Dissipation on the ROUT Total Power (ROUT) = 6.5mW * 6 = 39mW Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDD)2 = 19pF * 25MHz * (3.465V)2 = 5.70mW per output Total Power (25MHz) = 5.70mW * 6 = 34.2mW Total Power Dissipation
• Total Power = Power (core)MAX + Total Power (ROUT) + Total Power (25MHz) = 51.98mW + 39mW + 34.2mW = 125.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj =  JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 100.3°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 7. Thermal Resistance JA for 16-Lead TSSOP, Forced Convection

16©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Table 8A. JA vs. Air Flow Table for a 16-Lead TSSOP Table 8B. JA vs. Air Flow Table for a 16-Lead SOIC Table 8C. JA vs. Air Flow Table for a 20-Lead VFQFN Transistor Count The transistor count for 83905: 339 JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 100.3°C/W 96.0°C/W 93.9°C/W JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 78.8°C/W 71.1°C/W 66.2°C/W JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 57.5°C/W 50.3°C/W 45.1°C/W

17©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 9A. Package Dimensions for 16-Lead TSSOP Reference Document: JEDEC Publication 95, MO-153 Package Outline - M Suffix for 16-Lead SOIC Table 9B. Package Dimensions for 16-Lead SOIC Reference Document: JEDEC Publication 95, MS-012 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 9.80 10.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27  0° 8° 150 il (N B d ) SOIC

Table 10. Package Dimensions outline drawing PSC-4170, rev03.

1. Dimensions and tolerances conform to ASME Y14.5M-1994
2. All dimensions are in millimeters. All angles are in degrees.
3. N is the total number of terminals.
4. All specifications co mply with JEDEC MO-220.

19©2016 Integrated Device Technology, Inc. Revision D September 27, 2016

Ordering Information

Table 11. Ordering Information

20©2016 Integrated Device Technology, Inc. Revision D September 27, 2016 Rev Table Page Description of Change Date A 2 Added Enable Timing Diagram. 3/28/05 BT 6 A - T 6 F 5 - 7 Features Section - added RMS Phase Jitter bullet. AC Characteristics Tables - added RMS Phase Jitter specs. Added Phase Noise Plot. 4/8/05 B 11 Added Crystal Input Interface in Application Section. Added Schematic layout. 5/16/05 B Absolute Maximum Ratings - corrected 20-Lead VFQFN package Thermal Impedance. Added Recommendations for Unused Input and Output Pins. Corrected Theta JA Air Flow Table for 20-Lead VFQFN. 10/2/06 B Added LVCMOS to XTAL Interface section. Added Thermal Release Path section. AC Characteristics Table - added lead-free marking for 20-Lead VFQFN package. 7/9/07 B T7B - T7C Absolute Maximum Ratings - updated TSSOP and VFQFN Thermal Impedance. Updated Thermal Release Path section. Updated TSSOP and VFQFN Thermal Impedance. Added note to VFQFN Package Outline. 1/24/08 B 15 Added Power Considerations section. Converted datasheet format. 7/20/09 B T10 19 Removed leaded order-able parts from Ordering Information table 11/14/12 C T6D T9A T11 1, 15 Deleted HiPerClockS references. Features, last bullet: updated packaging note. Mixed AC Characteristics Table - corrected typo, switched Output Rise/Fall Time spec with Output Duty Cycle spec. Replaced schematic. 16-Lead TSSOP Package Table - corrected dimension A1 Minimum = 0.05. Updated VFQFN package outline page. Ordering Information table - deleted Lead-free note, and quantity from Tape and Reel. 4/18/13 C 1 Pin Assignment: Corrected 20-Lead illustration cut-off text 2/27/14 C T6A - T6F T10 6 - 8 Pin Assignment, 20-Lead VFQFN: removed the Epad dimensions. Changed NOTE 1to XTAL_IN can be overdriven by a single-ended LVCMOS signal. Please refer to Application Information section. Deleted 3.3V Phase Noise Plot Deleted RMS Phase Jitter graph. Modified dimensions to reflect tightened tolerances. Updated contact information. 8/6/14 D 2 Figure 1 corrected. Updated datasheet header/footer. Deleted “ICS” prefix from part number throughout the datasheet 9/27/16

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