83905AMLFT

ICS83905_08 IDT | Alldatasheet

Document overview

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Technical content

Features

• Six LVCMOS / LVTTL outputs
• Outputs able to drive 12 series terminated lines
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Output skew: 80ps (maximum)
• RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.26ps (typical), VDD = VDDO = 2.5V Offset Noise Power
• 5V tolerant enable inputs
• Synchronous output enables
• Operating power supply modes: Full 3.3V, 2.5V, 1.8V Mixed 3.3V core/2.5V output operating supply Mixed 3.3V core/1.8V output operating supply Mixed 2.5V core/1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS 6 7 8 9 10 19 20 18 17 16 GND VDDO GND BCLK0 BCLK1 BCLK4 BCLK5 VDDO GND GND VDD BCLK2 GND GND BCLK3 ENABLE1 ENABLE2 XTAL_IN XTAL_OUT nc XTAL_IN ENABLE1 BCLK5 VDDO BCLK4 GND BCLK3 VDDBCLK2 GND BCLK1 VDDO BCLK0 GND ENABLE2 XTAL_OUT SYNCHRONIZE SYNCHRONIZE BCLK0 BCLK1 BCLK2 BCLK3 BCLK4 BCLK5 XTAL_IN XTAL_OUT ENABLE 1 ENABLE 2 ICS83905 16-Lead SOIC, 150 Mil 3.9mm x 9.9mm x 1.38mm package body M Package Top View 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View Pin Assignments Block Diagram ICS83905 20-Lead VFQFN 4mm x 4mm x 0.925mm package body K Package Top View

ICS83905AM REVISION B JULY 20, 2009 2 ©2009 Integrated Device Technology, Inc. Table 1. Pin Descriptions Table 2. Pin Characteristics Table 3. Clock Enable Function Table Figure 1. Enable Timing Diagram XTAL_OUT Output Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. ENABLE1, ENABLE2 Input Clock enable. LVCMOS /LVTTL interface levels. See Table 3. BCLK3, BCLK4, BCLK5 Output Clock outputs. LVCMOS /LVTTL interface levels. GND Power Power supply ground. VDDO Power Output supply pin.

00 L O W L O W

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 3 ©2009 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO+ 0.5V Package Thermal Impedance, θJA

16 Lead SOIC package

16 Lead TSSOP package

20 Lead VFQFN package

78.8°C/W (0 mps) 100.3°C/W (0 mps) 57.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current ENABLE [1:2] = 00 10 mA IDDO Output Supply Current ENABLE [1:2] = 00 5 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current ENABLE [1:2] = 00 8 mA IDDO Output Supply Current ENABLE [1:2] = 00 4 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current ENABLE [1:2] = 00 5 mA IDDO Output Supply Current ENABLE [1:2] = 00 3 mA

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 4 ©2009 Integrated Device Technology, Inc. Table 4D. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C Table 4E. Power Supply DC Characteristics, 3.3V ± 5%, VDDO = 1.8V ± 0.2V%, TA = 0°C to 70°C Table 4F. Power Supply DC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V%, TA = 0°C to 70°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current ENABLE [1:2] = 00 10 mA IDDO Output Supply Current ENABLE [1:2] = 00 4 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current ENABLE [1:2] = 00 10 mA IDDO Output Supply Current ENABLE [1:2] = 00 3 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current ENABLE [1:2] = 00 8 mA IDDO Output Supply Current ENABLE [1:2] = 00 3 mA

ICS83905AM REVISION B JULY 20, 2009 5 ©2009 Integrated Device Technology, Inc. NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Table 5. Crystal Characteristics

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 6 ©2009 Integrated Device Technology, Inc. Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%,TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Table 6B. AC Characteristics, VDD = VDDO = 2.5V ± 5%,TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 4 25MHz, Integration Range: 100Hz – 1MHz 0.13 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle 48 52 % tEN Output Enable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random); NOTE 4 25MHz, Integration Range: 100Hz – 1MHz 0.26 ps tR / tF Output Rise/Fall Time 20% to 80% 200 800 ps odc Output Duty Cycle 47 53 % tEN Output Enable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 5 ENABLE1 4 cycles ENABLE2 4 cycles

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 7 ©2009 Integrated Device Technology, Inc. Table 6C. AC Characteristics, VDD = VDDO = 1.8V ± 0.2V,TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. Table 6D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%,TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit(Ø) RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.27 ps tR / tF Output Rise/Fall Time 20% to 80% 200 900 ps odc Output Duty Cycle 47 53 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.14 ps tR / tF Output Rise/Fall Time 20% to 80% 48 52 ps odc Output Duty Cycle 200 800 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 8 ©2009 Integrated Device Technology, Inc. Table 6E. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V,TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. Table 6F. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.18 ps tR / tF Output Rise/Fall Time 20% to 80% 200 900 ps odc Output Duty Cycle 48 52 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 cycles Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source NOTE 1 DC 100 MHz tsk(o) Output Skew; NOTE 2, 3 80 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.19 ps tR / tF Output Rise/Fall Time 20% to 80% 200 900 ps odc Output Duty Cycle 47 53 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 9 ©2009 Integrated Device Technology, Inc. Typical Phase Noise at 25MHz (2.5V Core/2.5V Output) Typical Phase Noise at 25MHz (3.3VCore/3.3V Output) Raw Phase Noise Data 25MHz RMS Phase Jitter (Random) 100Hz to 1MHz = 0.26ps (typical) Noise Power dBc Hz Offset Frequency (Hz) Raw Phase Noise Data .25MHz RMS Phase Jitter (Random) 100Hz to 1MHz = 0.13ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 10 ©2009 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 1.8V Core/1.8V LVCMOS Output Load AC Test Circuit 3.31.8V Core/1.8V LVCMOS Output Load AC Test Circuit 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 2.5V Core/1.8V LVCMOS Output Load AC Test Circuit SCOPE QxLVCMOS GND VDD, -1.65V±5% 1.65V±5% VDDO SCOPE QxLVCMOS GND VDD, -0.9V±0.1V 0.9V±0.1V VDDO SCOPE Qx LVCMOS GND VDD -0.9V±0.1V 2.4V±0.9V VDDO 0.9V±0.1V SCOPE QxLVCMOS GND VDD, -1.25±5% 1.25V±5% VDDO SCOPE Qx LVCMOS GND VDD -1.25±5% 2.05V±5% VDDO 1.25V±5% SCOPE Qx LVCMOS GND VDD -0.9V±0.1V 1.6V±0.025% VDDO 0.9V±0.1V

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 11 ©2009 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Skew Output Rise/Fall Time RMS Phase Jitter Output Duty Cycle/Pulse Width/Period Qx Qy tsk(b) VCCO VCCO 20% 80% 80% 20% tR tF BCLK[0:5] Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power tPERIOD tPW tPERIOD odc = VDD x 100% tPW BCLK[0:5]

ICS83905AM REVISION B JULY 20, 2009 13 ©2009 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) resistance is not required but can be added for additional protection.

ICS83905AM REVISION B JULY 20, 2009 15 ©2009 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS83905. Equations and example calculations are also provided. following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. maximum recommended junction temperature for HiPerClockS devices is 125°C. a multi-layer board, the appropriate value is 100.3°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 16 ©2009 Integrated Device Technology, Inc. Reliability Information Table 8A. θJA vs. Air Flow Table for a 16 Lead TSSOP Table 8B. θJA vs. Air Flow Table for a 16 Lead SOIC Table 8C. θJA vs. Air Flow Table for a 20 Lead VFQFN Transistor Count The transistor count for ICS83905: 339 Pin compatible to MPC905 θJA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 100.3°C/W 96.0°C/W 93.9°C/W θJA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 78.8°C/W 71.1°C/W 66.2°C/W θJA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 57.5°C/W 50.3°C/W 45.1°C/W

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 17 ©2009 Integrated Device Technology, Inc. Package Outline and Package Dimensions Package Outline - G Suffix for 16 Lead TSSOP Table 9A. Package Dimensions for 16 Lead TSSOP Reference Document: JEDEC Publication 95, MO-153 Package Outline - M Suffix for 16 Lead SOIC Table 9B. Package Dimensions for 16 Lead SOIC Reference Document: JEDEC Publication 95, MS-012 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 9.80 10.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8°

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 18 ©2009 Integrated Device Technology, Inc. Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9C below. Table 9C. Package Dimensions Reference Document: JEDEC Publication 95, MO-220 To p View Index Area D Chamfer 4x 0.6 x 0.6 max OPTIONAL Anvil Singulation A 0. 08 C C Seating Plane E2 E2 L (N -1)x e (Re f.) (Ref.) N & N Even N e (Ref.) N & N Odd e (Ty p.) If N & N are Even (N -1)x e (Re f.) b Th er mal Base N OR JEDEC Variation: VGGD-1/-5 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 20 A 0.80 1.00 A1 00 . 0 5 A3 0.25 Ref. b 0.18 0.30 ND & NE 5 D & E 4.00 Basic D2 & E2 1.95 2.25 e 0.50 Basic L 0.35 0.75

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 19 ©2009 Integrated Device Technology, Inc.

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. for use in life support devices or critical medical instruments.

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER ICS83905AM REVISION B JULY 20, 2009 20 ©2009 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date A 2 Added Enable Timing Diagram. 3/28/05 BT 6 A - T 6 F 5 - 7 Features Section - added RMS Phase Jitter bullet. AC Characteristics Tables - added RMS Phase Jitter specs. Added Phase Noise Plot. 4/8/05 B 11 Added Crystal Input Interface in Application Section. Added Schematic layout. 5/16/05 B Absolute Maximum Ratings - corrected 20 lead VFQFN package Thermal Impedance. Added Recommendations for Unused Input and Output Pins. Corrected Theta JA Air Flow Table for 20 lead VFQFN. 10/2/06 B Added LVCMOS to XTAL Interface section. Added Thermal Release Path section. AC Characteristics Table - added lead-free marking for 20 lead VFQFN package. 7/9/07 B T7B - T7C Absolute Maximum Ratings - updated TSSOP and VFQFN Thermal Impedance. Updated Thermal Release Path section. Updated TSSOP and VFQFN Thermal Impedance. Added note to VFQFN Package Outline. 1/24/08 B 15 Added Power Considerations section. Converted datasheet format. 7/20/09

ICS83905 Data Sheet LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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