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Technical content
Features
- Six LVCMOS outputs
- Outputs able to drive 12 series terminated lines
- Crystal Oscillator Interface
- Crystal input frequency range: 10MHz to 40MHz
- Output skew: 95ps (maximum)
- RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.17ps (typical) Offset Noise Power
- Synchronous output enables
- Power supply modes: Full 1.8V, 1.5V, 1.2V Mixed 1.8V core/1.5V output operating supply Mixed 1.8V core/1.2V output operating supply Mixed 1.5V core/1.2V output operating supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package Block Diagram 20-pin, 4mm x 4mm VFQFN Package 83905-01 GND GND BCLK4 VDDO BCLK5 GND GND BCLK2 VDD BCLK3 6 7 89 1 0 20 19 18 17 16 ENABLE2 XTAL_OUT nc ENABLE1 XTAL_IN BCLK1 VDDO BCLK0 GND GND 1 15 83905-01 16-pin, 4.4mm x 5.0mm TSSOP Package BCLK4 VDDO BCLK5 ENABLE1 XTAL_IN VDD BCLK3 GND VDDO BCLK0 GND ENABLE2 XTAL_OUT BCLK2 GND BCLK1 SYNCHRONIZE SYNCHRONIZE BCLK0 BCLK1 BCLK2 BCLK3 BCLK4 BCLK5 XTAL_IN XTAL_OUT ENABLE 1 ENABLE 2
Table 1. Pin Descriptions Table 2. Pin Characteristics Table 3. Clock Enable Function Table Figure 1. Enable Timing Diagram XTAL_OUT Output Crystal oscillator interface. XTAL_IN Input Crystal oscillator interface. ENABLE1, ENABLE2 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3. BCLK3, BCLK4, BCLK5 Output Clock outputs. LVCMOS interface levels. GND Power Power supply ground. VDDO Power Output supply pin.
REVISION 1 05/01/15 3 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 1.8V ±0.2V, TA = 0°C to 70°C NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4B. Power Supply DC Characteristics, VDD = VDDO = 1.5V ±0.1V, TA = 0°C to 70°C NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.2V ±5%, TA = 0°C to 70°C NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Input, VI Crystal Oscillator Input 0V to V DD Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, TJ 125C Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 4 10 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 1.4 1.5 1.6 V VDDO Output Supply Voltage 1.4 1.5 1.6 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 3 7 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 1.14 1.2 1.26 V VDDO Output Supply Voltage 1.14 1.2 1.26 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 2 6 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 4 REVISION 1 05/01/15 NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4E. Power Supply DC Characteristics, VDD = 1.8V ±0.2V, VDDO = 1.2V ±5%, TA = 0°C to 70°C NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4F. Power Supply DC Characteristics, VDD = 1.5V ±0.1V, VDDO = 1.2V ±5%, TA = 0°C to 70°C NOTE 1: Measured with outputs unterminated, and XTAL_IN and XTAL_OUT floated. Table 4G. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.4 1.5 1.6 V IDD; NOTE 1 Power Supply Cu rrent ENABLE [1:2] = 00 4 10 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 1.6 1.8 2.0 V VDDO Output Supply Voltage 1.14 1.2 1.26 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 4 10 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 1.4 1.5 1.6 V VDDO Output Supply Voltage 1.14 1.2 1.26 V IDD; NOTE 1 Power Supply Current ENABLE [1:2] = 00 3 7 mA IDDO; NOTE 1 Output Supply Current ENABLE [1:2] = 00 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VDD = 1.8V ± 0.2V 1.2 V DD + 0.3 V VDD = 1.5V ± 0.1V 1.0 V DD + 0.3 V VDD = 1.2V ± 5% 0.8 V DD + 0.3 V VIL Input Low Voltage VDD = 1.8V ± 0.2V -0.3 0.4 V VDD = 1.5V ± 0.1V -0.3 0.3 V VOH Output High Voltage; NOTE 1 VDDO = 1.8V ± 0.2V 0.7 V VDDO = 1.5V ± 0.1V 0.7 V VDDO = 1.2V ± 5% 0.7 V VOL Output Low Voltage; NOTE 1 VDDO = 1.8V ± 0.2V 0.4 V VDDO = 1.5V ± 0.1V 0.4 V VDDO = 1.2V ± 5% 0.4 V
Table 5. Crystal Characteristics has been reached under these conditions. All parameters measured at ƒ 40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: See phase noise plot. NOTE 5: These parameters are guaranteed by design. Not tested in production.
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 6 REVISION 1 05/01/15 Table 6B. AC Characteristics, VDD = VDDO = 1.5V ±0.1V, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ 40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. Table 6C. AC Characteristics, VDD = VDDO = 1.2V ±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ 40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 11 0 0 M H z tsk(o) Output Skew; NOTE 2, 3 90 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.3 ps tR / tF Output Rise/Fall Time 20% to 80% 300 650 ps odc Output Duty Cycle 44 50 56 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 11 0 0 M H z tsk(o) Output Skew; NOTE 2, 3 90 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.7 ps tR / tF Output Rise/Fall Time 20% to 80% 350 800 ps odc Output Duty Cycle 44 50 56 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles
REVISION 1 05/01/15 7 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ 40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. Table 6E. AC Characteristics, VDD = 1.8V ±0.2V, VDDO = 1.2V ±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ 40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 11 0 0 M H z tsk(o) Output Skew; NOTE 2, 3 90 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.18 ps tR / tF Output Rise/Fall Time 20% to 80% 300 650 ps odc Output Duty Cycle 40 50 60 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 11 0 0 M H z tsk(o) Output Skew; NOTE 2, 3 95 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.2 ps tR / tF Output Rise/Fall Time 20% to 80% 350 800 ps odc Output Duty Cycle 42 50 58 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 8 REVISION 1 05/01/15 Table 6F. AC Characteristics, VDD = 1.5V ±0.1V, VDDO = 1.2V ±5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ 40MHz using a crystal input unless noted otherwise. Outputs terminated with 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven by an external source. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by design. Not tested in production. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 11 0 0 M H z tsk(o) Output Skew; NOTE 2, 3 90 ps tjit RMS Phase Jitter (Random) 25MHz, Integration Range: 100Hz – 1MHz 0.34 ps tR / tF Output Rise/Fall Time 20% to 80% 350 800 ps odc Output Duty Cycle 42 50 58 % tEN Output Enable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles tDIS Output Disable Time; NOTE 4 ENABLE1 4 cycles ENABLE2 4 cycles
REVISION 1 05/01/15 9 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Typical Phase Noise at 25MHz (1.8V Core, 1.8V Output) Noise Power (dBc/Hz) Offset Frequency (Hz)
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 10 REVISION 1 05/01/15 Parameter Measurement Information 1.8V Core/1.8V LVCMOS Output Load Test Circuit 1.2V Core/1.2V LVCMOS Output Load Test Circuit 1.8V Core/1.2V LVCMOS Output Load Test Circuit 1.5V Core/1.5V LVCMOS Output Load Test Circuit 1.8V Core/1.5V LVCMOS Output Load Test Circuit 1.5V Core/1.2V LVCMOS Output Load Test Circuit SCOPE Qx GND VDD, -0.9V±0.1V 0.9V±0.1V VDDO SCOPE Qx GND VDD, -0.6V±5% 0.6V±5% VDDO SCOPE Qx GND VDD -0.6V±5% 1.2V±0.2V VDDO 0.6V±5% SCOPE Qx GND VDD, -0.75V±0.05V 0.75V±0.05V VDDO SCOPE Qx GND VDD -0.75V±0.05V 1.05V±0.15V VDDO 0.75V±0.05V SCOPE Qx GND VDD -0.6V±5% 0.9V±0.07V VDDO 0.6V±5%
REVISION 1 05/01/15 11 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET Parameter Measurement Information, continued Output Skew Output Rise/Fall Time Output Enable/Disable RMS Phase Jitter Output Duty Cycle/Pulse Width/Period BCLKx BCLKy tsk(b) VDDO VDDO 20% 80% 80% 20% tR tF BCLK[0:5] VDD/2 V DD/2 VDDO/2 VOL VOH VDD tDIS tEN Output BCLKx (See Note) OEx (High-level enabling) tPERIOD tPW tPERIOD odc = VDDO x 100% tPW BCLK[0:5]
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 12 REVISION 1 05/01/15
Application Information
Recommendations for Unused Output Pins Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. Crystal Input Interface The 83905-01 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. Figure 2. Crystal Input Interface
This section provides information on power dissipation and junction temperature for the 83905-01. Equations and example calculations are also provided. DD = 1.8V + 0.2V = 2.0V, which gives worst case results.
- Total Power Dissipation on the ROUT Total Power (ROUT) = 3.8mW * 6 = 22.8mW Dynamic Power Dissipation at 100MHz Power (100MHz) = CPD * Frequency * (VDD)2 = 12pF * 100MHz * (2V)2 = 4.8mW per output Total Power (100MHz) = 4.8mW * 6 = 28.8mW Total Power Dissipation Total Power = Power (core)MAX + Total Power (ROUT) + Total Power (100MHz) = 20mW + 22.8mW + 28.8mW = 71.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 100.3°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 7. Thermal Resistance JA for 16-Lead TSSOP, Forced Convection
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 16 REVISION 1 05/01/15 Reliability Information Table 8A. JA vs. Air Flow Table for a 16-Lead TSSOP Table 8B. JA vs. Air Flow Table for a 20-Lead VFQFN Transistor Count The transistor count for 83905-01: 505 JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 100.3°C/W 96.0°C/W 93.9°C/W JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 57.5°C/W 50.3°C/W 45.1°C/W
REVISION 1 05/01/15 17 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 83905-01 DATA SHEET 16-Lead TSSOP Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Table 9A. Package Dimensions for 16-Lead TSSOP Reference Document: JEDEC Publication 95, MO-153 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0° 8° aaa 0.10
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 18 REVISION 1 05/01/15 20-Lead VFQFN Package Outline and Package Dimensions Package Outline - K Suffix for 20-Lead VFQFN Reference Document: JEDEC Publication 95, MO-220 NOTE: The drawing and dimension data originate from IDT package outline drawing PSC-4170, rev03. 1. Dimensions and tolerances conform to ASME Y14.5M-1994 2. All dimensions are in millimeter s. All angles are in degrees. 3. N is the total number of terminals. 4. All specifications comply with JEDEC MO-220. Table 9C. Package Dimensions for 20-Lead VFQFN All Dimensions in Millimeters Symbol Minimum Nom Maximum b 0.20 0.25 0.30 D 3.90 4.00 4.10 E 3.90 4.00 4.10 D2 1.95 2.10 2.25 E2 1.95 2.10 2.25 L 0.45 0.55 0.65 e 0.50 BSC N 20 A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 0.2 REF
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS FANOUT BUFFER 19 REVISION 1 05/01/15
Ordering Information
Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
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