83904AG-02LF | DigiCamel IC Datasheet

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83904-02 Datasheet

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Manufacturer or author: rdvorak
PDF pages: 16

Technical content

FEATURES

Four LVCMOS/LVTTL outputs, 19 Ω typical output impedance @ V DD = V DDO = 3.3V
Two Crystal oscillator input pairs One LVCMOS/LVTTL clock input
Crystal input frequencry range: 12MHz – 38.88MHz
Output frequency: 200MHz (maximum)
Output Skew: 40ps (maximum) @ V DD = V DDO = 3.3V RMS phase jitter @ 25MHz output, using a 25MHz crystal (100Hz – 1MHz): 0.16ps (typical) @ V DD = V DDO = 3.3V RMS phase noise at 25MHz: Offset Noise Power Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V
0 °C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package GENERAL DESCRIPTION The 83904-02 is a low skew, high performance 1-to-4 Crystal-to- LVCMOS Fanout Buffer. The 83904-02 has selectable single-ended clock or two crystal-oscillator inputs. There is an output enable to disable the outputs by placing them into a high-impedance state. Guaranteed output and part-to-part skew characteristics make the 83904-02 ideal for those applications demand- ing well deﬁ ned performance and repeatability. BLOCK DIAGRAM OE CLK_SEL0 CLK_SEL1 CLK OSC OSC 0 0 0 1 1 0 1 1 Pullup 83904-02 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View Pulldown Pulldown XTAL_IN0 XTAL_OUT0 XTAL_IN1 XTAL_OUT1 Pulldown CLK_SEL0 XTAL_OUT0 XTAL_IN0 VDD XTAL_IN1 XTAL_OUT1 CLK_SEL1 CLK V DDO GND V DDO OE PIN ASSIGNMENT

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS CLK_SEL1 Input Pulldown Clock select inputs. See Table 3, Input Reference Function Table. LVCMOS / LVTTL interface levels. XTAL_IN0 Input Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT1 Input Crystal oscillator interface. XTAL_IN1 is the input. 8 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 9 OE Input Pullup Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. 11, 12, 14, 15 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 13 GND Power Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 3. INPUT REFERENCE FUNCTION TABLE

©2016 Integrated Device Technology, Inc Revision A March 17, 20163 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θ JA 100.3°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speciﬁ cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO = 3.3V±5%, TA = 0°C TO 70°C TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO = 2.5V±5%, TA = 0°C TO 70°C TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO = 2.5V±5%, TA = 0°C TO 70°C TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current No Load & XTALx selected @ 12MHz 7 mA No Load & CLK selected 1 mA I DDO Output Supply Current No Load & CLK selected 1 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current No Load & XTALx selected @ 12MHz 7 mA No Load & CLK selected 1 mA I DDO Output Supply Current No Load & CLK selected 1 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 1.6 1.8 2.0 V I DD Power Supply Current No Load & XTALx selected @ 12MHz 7 mA No Load & CLK selected 1 mA I DDO Output Supply Current No Load & CLK selected 1 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 2.375 2.5 2.625 V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current No Load & XTALx selected @ 12MHz 3 mA No Load & CLK selected 1 mA I DDO Output Supply Current No Load & CLK selected 1 mA

/2. See Parameter Measurement section, “Load Test Circuit” diagrams. TABLE 5. CRYSTAL CHARACTERISTICS

©2016 Integrated Device Technology, Inc Revision A March 17, 20165 TABLE 6B. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO TABLE 6A. AC CHARACTERISTICS, V DD = V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency w/external XTAL 12 38.88 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.4 1.9 2.4 ns tsk(o) Output Skew; NOTE 2 40 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 2, 4 25MHz, Integration Range: 100Hz – 1MHz 0.16 ps t R / t F Output Rise/Fall Time 20% to 80% 100 800 ps odc Output Duty Cycle w/external XTAL 45 55 % w/external CLK ƒ < 150MHz 46 54 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency w/external XTAL 12 38.88 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.5 2.0 2.5 ns tsk(o) Output Skew; NOTE 2 40 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 2, 4 25MHz, Integration Range: 100Hz - 1MHz 0.16 ps t R / t F Output Rise/Fall Time 20% to 80% 100 800 ps odc Output Duty Cycle w/external XTAL 45 55 % w/external CLK ƒ < 150MHz 46 54 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

©2016 Integrated Device Technology, Inc Revision A March 17, 20166 TABLE 6D. AC CHARACTERISTICS, V DD = V DDO TABLE 6C. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency w/external XTAL 12 38.88 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.7 2.2 2.7 ns tsk(o) Output Skew; NOTE 2 40 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 2, 4 25MHz, Integration Range: 100Hz - 1MHz 0.16 ps t R / t F Output Rise/Fall Time 20% to 80% 100 1000 ps odc Output Duty Cycle w/external XTAL 45 55 % w/external CLK ƒ < 150MHz 46 54 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency w/external XTAL 12 38.88 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.5 2.2 3.0 ns tsk(o) Output Skew; NOTE 2 40 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 2, 4 25MHz, Integration Range: 100Hz - 1MHz 0.20 ps t R / t F Output Rise/Fall Time 20% to 80% 100 800 ps odc Output Duty Cycle w/external XTAL 45 55 % w/external CLK ƒ < 150MHz 48 52 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

©2016 Integrated Device Technology, Inc Revision A March 17, 20167 TABLE 6E. AC CHARACTERISTICS, V DD = 2.5V ± 5%, V DDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency w/external XTAL 12 38.88 MHz w/external CLK 200 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 1.7 2.5 3.3 ns tsk(o) Output Skew; NOTE 2 40 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 700 ps tjit(Ø) RMS Phase Jitter, Random; NOTE 2, 4 25MHz, Integration Range: 100Hz - 1MHz 0.19 ps t R / t F Output Rise/Fall Time 20% to 80% 100 1000 ps odc Output Duty Cycle w/external XTAL 45 55 % w/external CLK ƒ < 150MHz 46 54 % t EN Output Enable Time; NOTE 5 10 ns t DIS Output Disable Time; NOTE 5 10 ns NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

©2016 Integrated Device Technology, Inc Revision A March 17, 20168 TYPICAL PHASE NOISE AT 25MHZ -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 25MHz RMS Phase Jitter (Random) 100Hz to 1MHz = 0.16ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Raw Phase Noise Data

©2016 Integrated Device Technology, Inc Revision A March 17, 20169 PARAMETER MEASUREMENT INFORMATION 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW

©2016 Integrated Device Technology, Inc Revision A March 17, 201610 OUTPUT RISE/FALL TIME PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT SKEW 20% 80% 80% 20% tR tF Q0:Q3 PARAMETER MEASUREMENT INFORMATION, CONTINUED

APPLICATION INFORMATION

INPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left ﬂ oating. Though not required, but for additional protection, a 1k Ω resistor can be tied from XTAL_IN to ground. CLK I NPUT For applications not requiring the use of the clock input, it can be left ﬂ oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. S ELECT PINS All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVCMOS OUTPUTS All unused LVCMOS output can be left ﬂ oating. There should be no trace attached.

TABLE 7. θ

TABLE 9. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision A March 17, 201615 REVISION HISTORY SHEET Rev Table Page Description of Change Date A T9 Updated Overdriving the Crystal Interface section. Ordering Information Table - deleted the “ICS” preﬁ x in the Part/Order Number column and corrected the Temperature column. Updated header/footer. 9/3/10 Updated data sheet format. 3/25/15 Updated header and footer. 3/17/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or speciﬁ cations described herein at any time, without notice, at IDT's sole discretion. Performance speciﬁ cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signiﬁ cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type deﬁ nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

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Product Information

83904AG-02LF specifications and overview.

Summary

Low Skew, 1-to-4, Crystal-to-LVCMOS/LVTTL Fanout Buffer

Description

Low Skew, 1-to-4, Crystal-to-LVCMOS/LVTTL Fanout Buffer

Source title 83904AG-02LF Datasheet(PDF) - Integrated Device Technology

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