83210 Datasheet

Document overview

  • Manufacturer or author: rdvorak
  • PDF pages: 10

Technical content

Low Skew, 1-to-10, HSTL Fanout Buffer 83210 Data Sheet ©2016 Integrated Device Technology, Inc Revision A March 10, 20161 GENERAL DESCRIPTION The 83210 is a low skew, 1-to-10 HSTL Fanout Buffer. The class II HSTL outputs are balanced push-pull in design, capable of delivering 16mA into a 10pF load. This class allows both source series termination and symmetrically double parallel termination.

FEATURES

  • Ten single-ended HSTL outputs
  • One single-ended HSTL clock input
  • Maximum input frequency: 150MHz
  • Output skew: 110ps (maximum)
  • Part-to-part skew: 2ns (maximum)
  • 1.5V power supply
  • 0°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package BLOCK DIAGRAM P IN ASSIGNMENT 32-Lead TQFP 7mm x 7mm x 1.0mm package body Y package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 GND V DD VDD GND V DD GND VDD nOE GND IN VDD GND GND V DD VDD GND GND GND V DD VDD GND GND ICS83210 Pulldown IN nOE

83210 Data Sheet

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 16, 17, 24, 25, 31, 32 GND Power Power supply ground. enabled. When HIGH, Qx outputs are disabled low. LVCMOS/LVTTL interface levels. 5 IN Input Single-ended reference clock input. HSTL interface levels. Output Single-ended HSTL clock outputs. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

©2016 Integrated Device Technology, Inc Revision A March 10, 20163 TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V DD TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V DD NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 1.38 1.5 1.62 V I DD Power Supply Current Outputs Loaded @ 62.5MHz 215 250 mA I DDQ Quiescent Supply Current V IN = 0V, outputs disabled 1 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage nOE 0.7*V DD V DD + 0.3 V V IL Input Low Voltage nOE -0.3 0.3*V DD V I IH Input High Current nOE 150 µA I IL Input Low Current nOE -5 µA TABLE 3C. HSTL DC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage IN V REF = 0.75V 0.85 1.8 V V IL Input Low Voltage IN -0.3 0.65 V V OH Output High Voltage I OH = -16mA 1.0 V DD + 0.3 V V OL Output Low Voltage I OL = 16mA -0.3 0.4 V ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DD + 0.5V Package Thermal Impedance, θ JA 75.5°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C

TABLE 4. AC CHARACTERISTICS, V thermal equilibrium has been reached under these conditions. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

©2016 Integrated Device Technology, Inc Revision A March 10, 20165 PARAMETER MEASUREMENT INFORMATION 1.5V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW PROPAGATION DELAYOUTPUT SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 20% 80% 80% 20% tR tF Q0:Q9

that there is no trace attached. TABLE 5. θ

TABLE 6. PACKAGE DIMENSIONS

TABLE 7. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision A March 10, 20169 REVISION HISTORY SHEET Rev Table Page Description of Change Date A T3C HSTL DC Characteristics Table - deleted NOTE 1, does not apply. AC Characteristics Table - added thermal note. Updated Package Outline. Ordering Information Table - Deleted “ICS” prefi x from Part/Order Number column. Changed DT format header/footer. 9/9/10 Updated data sheet format. 4/28/15 AT 7 8 Removed ICS from the part number where needed. Ordering Information - Deleted LF note below table. Updated Header and footer. 3/10/16

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