8308AGILF

8308I RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
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Low Skew, 1-to-8 Differential/LVCMOS-to- LVCMOS Fanout Buffer 8308I Data Sheet ©2015 Integrated Device Technology, Inc December 10, 20151 BLOCK DIAGRAM P IN ASSIGNMENT 8308I 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.925mm body package G Package Top View GND CLK_SEL LVCMOS_CLK CLK nCLK CLK_EN OE VDD GND VDDO VDDO GND V DDO GND V DDO GND GENERAL DESCRIPTION The 8308I is a low-skew, 1-to-8 Fanout Buffer. The 8308I has two selectable clock inputs. The CLK, nCLK pair can accept most differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 8 to 16 by utilizing the ability of the outputs to drive two series terminated transmission lines. The 8308I is characterized for 3.3V core/3.3V output, Guaranteed output and part-part skew characteristics make the 8308I ideal for those clock distribution applications requiring well defi ned performance and repeatability.

FEATURES

• Eight LVCMOS/LVTTL outputs, (7Ω typical output impedance)
• Selectable LVCMOS_CLK or differential CLK, nCLK inputs
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum Output Frequency: 350MHz
• Output Skew: (3.3V± 5%): 100ps (maximum)
• Part to Part Skew: (3.3V± 5%): 1ns (maximum)
• Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V
• -40 °C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package LVCMOS_CLK CLK nCLK CLK_SEL CLK_EN OE D LE Q Pullup Pullup Pullup Pulldown Pullup Pullup

TABLE 1. PIN DESCRIPTIONS Q5, Q4,Q3, Q2 Output Clock outputs. LVCMOS / LVTTL interface levels. 2, 10, 14, 18, 22 GND Power Power supply ground.

3 CLK_SEL Input Pullup

Clock select input. Selects LVCMOS clock input when HIGH. Selects CLK, nCLK inputs when LOW. See Table 3A. LVCMOS / LVTTL interface levels. 4 LVCMOS_CLK Input Pullup Clock input. LVCMOS / LVTTL interface levels. 5 CLK Input Pullup Non-inverting differential clock input. 6 nCLK Input Pulldown Inverting differential clock input. 7 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels. 8 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS

0 CLK, nCLK is selected

1 LVCMOS_CLK is selected

NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.

0 Outputs Q0:Q7 are in Hi-Z (disabled)

1 Outputs Q0:Q7 are active (enabled)

©2015 Integrated Device Technology, Inc December 10, 20153 TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θ JA 70°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current 46 mA I DDO Output Supply Current 11 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current 46 mA I DDO Output Supply Current 10 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, V DD , V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 2.375 2.5 2.625 V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current 43 mA I DDO Output Supply Current 10 mA

©2015 Integrated Device Technology, Inc December 10, 20154 TABLE 4D. DC CHARACTERISTICS, V DD = V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage LVCMOS 2 V DD + 0.3 V V IL Input Low Voltage LVCMOS_CLK -0.3 1.3 V CLK_EN, OE 0.8 V I IN Input Current V IN = V DD or V IN = GND 300 µA V OH Output High Voltage; NOTE 1 I OH = -24mA 2.4 V V OL Output Low Voltage; NOTE 1 I OL = 24mA 0.55 V I OL = 12mA 0.30 V V PP Peak-to-Peak Input Voltage CLK, nCLK 0.15 1.3 V V CMR Input Common Mode Voltage; NOTE 2, 3 CLK, nCLK GND + 0.5 V DD - 0.85 V NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to V DDO /2. See Parameter Measurement section, “3.3V Output Load AC Test Circuit”. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V DD + 0.3V. NOTE 3: Common mode voltage is defi ned as V IH TABLE 4E. DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage LVCMOS 2 V DD + 0.3 V V IL Input Low Voltage LVCMOS_CLK -0.3 1.3 V CLK_EN, OE 0.8 V I IN Input Current V IN = V DD or V IN = GND 300 µA V OH Output High Voltage; NOTE 1 I OH = -15mA 1.8 V V OL Output Low Voltage; NOTE 1 I OL = 15mA 0.6 V V PP Peak-to-Peak Input Voltage CLK, nCLK 0.15 1.3 V V CMR Input Common Mode Voltage; NOTE 2, 3 CLK, nCLK GND + 0.5 V DD - 0.85 V NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to V DDO /2. See Parameter Measurement section, “3.3V Output Load AC Test Circuit”. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V DD + 0.3V. NOTE 3: Common mode voltage is defi ned as V IH

©2015 Integrated Device Technology, Inc December 10, 20155 TABLE 4F. DC CHARACTERISTICS, V DD , V DDO TABLE 5A. AC CHARACTERISTICS, V DD = V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage LVCMOS 1.7 V DD + 0.3 V V IL Input Low Voltage LVCMOS_CLK -0.3 0.7 V CLK_EN, OE 0.7 V I IN Input Current V IN = V DD or V IN = GND 300 µA V OH Output High Voltage; NOTE 1 I OH = -15mA 1.8 V V OL Output Low Voltage; NOTE 1 I OL = 15mA 0.6 V V PP Peak-to-Peak Input Voltage CLK, nCLK 0.15 1.3 V V CMR Input Common Mode Voltage; NOTE 2, 3 CLK, nCLK GND + 0.5 V DD - 0.85 V NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to V DDO /2. See Parameter Measurement section, “3.3V Output Load AC Test Circuit”. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V DD + 0.3V. NOTE 3: Common mode voltage is defi ned as V IH Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 350 MHz t PD Propagation Delay; CLK, nCLK; NOTE 1 ƒ ≤ 350MHz 2 4 ns LVCMOS_CLK; NOTE 2 ƒ ≤ 350MHz 2 4 ns tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge @V DDO /2 100 ps tsk(pp) Part-to-Part Skew; NOTE 4, 7 Measured on rising edge @V DDO /2 1 ns t R / t F Output Rise/Fall Time 0.8V to 2V 0.2 1 ns odc Output Duty Cycle ƒ ≤ 150MHz, Ref = CLK, nCLK 45 55 % t PZL , t PZH Output Enable Time; NOTE 5 5n s t PLZ , t PHZ Output Disable Time; NOTE 5 5n s t S Clock Enable Setup Time; NOTE 6 CLK_EN to CLK, nCLK 1n s CLK_EN to LVC- MOS_CLK 0n s t H Clock Enable Hold Time; NOTE 6 CLK, nCLK to CLK_EN 0n s LVCMOS_CLK to CLK_EN 1n s NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to V DDO /2 of the output. NOTE 2: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO /2. NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO /2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.

©2015 Integrated Device Technology, Inc December 10, 20156 TABLE 5B. AC CHARACTERISTICS, V DD = 3.3V±5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 350 MHz t PD Propagation Delay; CLK, nCLK; NOTE 1 ƒ ≤ 350MHz 24 n s LVCMOS_CLK; NOTE 2 ƒ ≤ 350MHz 24 n s tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge @V DDO /2 100 ps tsk(pp) Part-to-Part Skew; NOTE 4, 7 Measured on rising edge @V DDO /2 1 ns t R / t F Output Rise/Fall Time 0.6V to 1.8V 0.2 1.0 ns odc Output Duty Cycle ƒ ≤ 150MHz, Ref = CLK, nCLK 45 55 % t PZL , t PZH Output Enable Time; NOTE 5 5n s t PLZ , t PHZ Output Disable Time; NOTE 5 5n s t S Clock Enable Setup Time; NOTE 6 CLK_EN to CLK, nCLK 1n s CLK_EN to LVC- MOS_CLK 0n s t H Clock Enable Hold Time; NOTE 6 CLK, nCLK to CLK_EN 0n s LVCMOS_CLK to CLK_EN 1n s NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to V DDO /2 of the output. NOTE 2: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO /2. NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO /2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.

©2015 Integrated Device Technology, Inc December 10, 20157 TABLE 5C. AC CHARACTERISTICS, V DD = V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 350 MHz t PD Propagation Delay; CLK, nCLK; NOTE 1 ƒ ≤ 350MHz 1.5 4.2 ns LVCMOS_CLK; NOTE 2 ƒ ≤ 350MHz 1.7 4.4 ns tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge @V DDO /2 160 ps tsk(pp) Part-to-Part Skew; NOTE 4, 7 Measured on rising edge @V DDO /2 2 ns t R / t F Output Rise/Fall Time 0.6V to 1.8V 0.2 1.0 ns odc Output Duty Cycle ƒ ≤ 150MHz, Ref = CLK, nCLK 40 60 % t PZL , t PZH Output Enable Time; NOTE 5 5n s t PLZ , t PHZ Output Disable Time; NOTE 5 5n s t S Clock Enable Setup Time; NOTE 6 CLK_EN to CLK, nCLK 1n s CLK_EN to LVC- MOS_CLK 0n s t H Clock Enable Hold Time; NOTE 6 CLK, nCLK to CLK_EN 0n s LVCMOS_CLK to CLK_EN 1n s NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to V DDO /2 of the output. NOTE 2: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO /2. NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO /2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.

©2015 Integrated Device Technology, Inc December 10, 20158 PARAMETER MEASUREMENT INFORMATION 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEW PART-TO-PART SKEW

©2015 Integrated Device Technology, Inc December 10, 20159 OUTPUT RISE/FALL TIME PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PARAMETER MEASUREMENT INFORMATION, CONTINUED

TABLE 6. θ TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION

©2015 Integrated Device Technology, Inc December 10, 201515 REVISION HISTORY SHEET Rev Table Page Description of Change Date A 11 Added Schematic Layout 4/16/04 B T4B T4E T5B Features section - added mix supply voltage bullet. Added Mix Power Supply Table. Added Mix DC Characteristics Table. Added Mix AC Characteristics Table. Added Mix Output Load AC Test Circuit Diagram. 10/20/04 B Corrected Block Diagram, added CLK_SEL. Added “Recommendations for Unused Input and Output Pins”. Ordering Information Table - added Lead-Free note. 7/25/05 B 1 Pin Assignment - corrected package information from 300-MIL to 173-MIL. 8/4/06 B T3B 2 Added OE Select Function Table. 10/16/07 C T4F T5A - T5C 5 -7 DC Characteristics - corrected V IH min. from 2V to 1.7V; V IL max. from 1.3V to 0.7V. AC Characteristics - added thermal note. Ordering Information Table - deleted ICS prefi x from Part/Order Number column. 7/16/09 C 10 Updated Wiring the Differential Input to Accept Single-ended Levels application note. Added Power On Sequence application note. 3/23/11 C T8 Recommended for Unusted I/O Pins - changed CLK Input: to LVCMOS_CLK. deleted lead-free note. 4/4/13 Removed ICS from the part numbers thoughout the datasheet. Removed reference to leaded devices in features section. Updated header and footer. 12/10/15

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