8305AGLF

ICS8305 IDT | Alldatasheet

Document overview

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• PDF pages: 17

Technical content

Features

• Four LVCMOS / LVTTL outputs, 7Ω output impedance
• Selectable differential or LVCMOS / LVTTL clock inputs
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• LVCMOS_CLK supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 350MHz
• Output skew: 35ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)
• Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 3.3V/1.5V
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS ICS8305 16-Lead TSSOP 4.4mm x 3.0mm x 0.925mm package body G Package 9LVCMOS_CLK CLK_SEL nCLK CLK CLK_EN VDD OE GND Q0 VDDO GND VDDO GND Pin Assignment LVCMOS_CLK CLK nCLK CLK_SEL CLK_EN OE D Q LE Pullup Pullup Pullup Pulldown Pulldown Pullup/ Pulldown Block Diagram

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 2 OE Input Pullup Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS/LVTTL interface levels. 3V DD Power Power supply pin. 4 CLK_EN Input Pullup Synchronizing clock enable. When LOW, the output clocks are disabled. When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels. 5 CLK Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. VDD/2 default when left floating. selects LVCMOS_CLK input. LVCMOS/LVTTL interface levels. 8 LVCMOS_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 10, 12, 14, 16 Q3, Q2, Q1, Q0 Output Single-ended clock outputs. 7Ω output impedance. LVCMOS/LVTTL interface levels. 11, 15 V DDO Power Output supply pins.

Table 3. Control Input Function Table After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. Figure 1. CLK_EN Timing Diagram

0 X X Hi-Z

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 4 ICS8305AG REV. C OCTOBER 23, 2008 ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO+ 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.65 1.8 1.95 V 1.425 1.5 1.575 V IDD Power Supply Current 21 mA IDDO Output Supply Current 5m A

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 5 ICS8305AG REV. C OCTOBER 23, 2008 Table 4B. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Table 4C. Differential DC Characteristics, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage CLK_EN, CLK_SEL, OE 2 V DD + 0.3 V LVCMOS_CLK 2 V DD + 0.3 V VIL Input Low Voltage CLK_EN, CLK_SEL, OE -0.3 0.8 V LVCMOS_CLK -0.3 1.3 V I IH Input High Current CLK_EN, CLK_SEL, OE V DD = VIN = 3.465V 5 µA LVCMOS_CLK V DD = VIN = 3.465V 150 µA IIL Input Low Current CLK_EN, CLK_SEL, OE V DD = 3.465V, VIN = 0V -150 µA LVCMOS_CLK V DD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 VDDO = 3.3V ± 5% 2.6 V VDDO = 2.5V ± 5% 1.8 V VDDO = 1.8V ± 0.15V 1.5 V VDDO = 1.5V ± 5% V DDO - 0.3 V VOL Output Low Voltage; NOTE 1 VDDO = 3.3V ± 5% 0.5 V VDDO = 2.5V ± 5% 0.5 V VDDO = 1.8V ± 0.15V 0.4 V VDDO = 1.5V ± 5% 0.35 V IOZL Output Hi-Z Current Low -5 µA IOZH Output Hi-Z Current High 5µ A Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current nCLK V DD = VIN = 3.465V 150 µA CLK V DD = VIN = 3.465V 150 µA IIL Input Low Current nCLK V DD = 3.465V, VIN = 0V -150 µA CLK V DD = 3.465V, VIN = 0V -5 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 6 ICS8305AG REV. C OCTOBER 23, 2008 ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C All parameters measured at ƒ ≤ 350MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Driving only one input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C For NOTES, see Table 5A above. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tpLH Propagation Delay, Low to High LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B 1.75 2.75 ns tsk(o) Output Skew; NOTE 2, 6 Measured on the Rising Edge 35 ps tsk(pp) Part-to-Part Skew; NOTE 3, 6 700 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 0.04 ps t R / tF Output Rise/Fall Time; NOTE 4 20% to 80% 100 700 ps odc Output Duty Cycle Ref = CLK/nCLK 45 55 % Ref = LVCMOS_CLK, ƒ ≤ 300MHz 45 55 % tEN Output Enable Time; NOTE 4 5n s tDIS Output Disable Time; NOTE 4 5n s Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tpLH Propagation Delay, Low to High LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B 1.8 2.9 ns tsk(o) Output Skew; NOTE 2, 6 Measured on the Rising Edge 35 ps tsk(pp) Part-to-Part Skew; NOTE 3, 6 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 0.04 ps t R / tF Output Rise/Fall Time; NOTE 4 20% to 80% 100 700 ps odc Output Duty Cycle Ref = CLK/nCLK 44 56 % Ref = LVCMOS_CLK, ƒ ≤ 300MHz 44 56 % tEN Output Enable Time; NOTE 4 5n s tDIS Output Disable Time; NOTE 4 5n s

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 7 ICS8305AG REV. C OCTOBER 23, 2008 Table 5C. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.15V, TA = 0°C to 70°C All parameters measured at ƒ ≤ 350MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: Driving only one input clock. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.5V ± 5%, TA = 0°C to 70°C For NOTES, see Table 5C above. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tpLH Propagation Delay, Low to High LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B 1.95 3.65 ns tsk(o) Output Skew; NOTE 2, 6 Measured on the Rising Edge 35 ps tsk(pp) Part-to-Part Skew; NOTE 3, 6 900 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 0.04 ps t R / tF Output Rise/Fall Time; NOTE 4 20% to 80% 100 700 ps odc Output Duty Cycle Ref = CLK/nCLK 44 56 % Ref = LVCMOS_CLK, ƒ ≤ 300MHz 44 56 % tEN Output Enable Time; NOTE 4 5n s tDIS Output Disable Time; NOTE 4 5n s Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 350 MHz tpLH Propagation Delay, Low to High LVCMOS_CLK; NOTE 1A CLK/nCLK; NOTE 1B 24 n s tsk(o) Output Skew; NOTE 2, 6 Measured on the Rising Edge 35 ps tsk(pp) Part-to-Part Skew; NOTE 3, 6 1n s tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 5 0.04 ps t R / tF Output Rise/Fall Time; NOTE 4 20% to 80% 200 900 ps odc Output Duty Cycle ƒ ≤ 166MHz 45 55 % ƒ > 166MHz 42 58 % tEN Output Enable Time; NOTE 4 5n s tDIS Output Disable Time; NOTE 4 5n s

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 8 ICS8305AG REV. C OCTOBER 23, 2008 ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. SSB Phase Noise dBc/Hz Offset Frequency (Hz) 100 1k 10k 100k 1M 10M 100M -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 Additive Phase Jitter at 155.52MHz = 0.04ps (typical)

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 9 ICS8305AG REV. C OCTOBER 23, 2008 Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 3.3V Core/1.8V LVCMOS Output Load AC Test Circuit Differential Input Level 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 3.3V Core/1.5V LVCMOS Output Load AC Test Circuit Output Skew SCOPE Qx LVCMOS CL ≤ 25pF* *For tR/tF measurement only VDD, 1.65V±5% -1.65V±5% VDDO SCOPE Qx LVCMOS GND VDDO VDD 0.9V±0.075V -0.9V±0.075V 2.4V±0.09V VDD GND VCMR Cross Points VPP nCLK CLK SCOPE Qx LVCMOS GND VDD 1.25V±5% -1.25V±5% VDDO 2.05V±5% SCOPE Qx LVCMOS GND VDDO VDD 0.75V±5% -0.9V±0.75V 2.55V±5% Qx Qy tsk(b) VCCO VCCO

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 10 ICS8305AG REV. C OCTOBER 23, 2008 Parameter Measurement Information, continued Part-to-Part Skew Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period Propagation Delay Qx Qy tsk(pp) VDDO VDDO Part 1 Part 2 Clock Outputs 20% 80% 80% 20% tR tF Q0:Q3 tPERIOD tPW tPERIOD odc = VDDO x 100% tPW tPD VDDO ➤ ➤ VDDO Q0:Q3 nCLK CLK LVCMOS_CLK

Figure 4. ICS8305 LVCMOS Clock Output Buffer Schematic Example

Table 6. θJA vs. Air Flow Table for a 16 Lead TSSOP NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 15 ICS8305AG REV. C OCTOBER 23, 2008

Ordering Information

Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. IDT product for use in life support devices or critical medical instruments.

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER 16 ICS8305AG REV. C OCTOBER 23, 2008 ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Revision History Sheet Rev Table Page Description of Change Date ICS88305AGT to ICS8305AGT. 1/20/04 B T5A - T5C 5 & 6 Added Additive Phase Jitter to AC Characteristics Tables. Added Additive Phase Jitter Section. 2/26/04 B T1 2 Pin Description Table - corrected CLK_EN description. 12/6/04 C T4A T4B T5D Features Section - added 1.5V output to Supply Mode bullet and added Lead-Free buttlet. Power Supply DC Characteristics Table - added VDDO 1.5V. LVCMOS DC Characteristics Table - added VOH/VOL 1.5V. Added 3.3V/1.5V AC Characteristics Table. Added 3.3V/1.5V Output Load AC Test Circuit Drawing. Added Recommendations for Unused Input and Output Pins. Added Lead-Free part number. 11/17/05 Corrected non-lead free marking from ICS8305AG to 8305AG. 2/22/08

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER www.IDT.com © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support netcom@idt.com 480-763-2056 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com Corporate Headquarters Integrated Device Technology, Inc.

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