8305AGILF

ICS8305I RENESAS | Alldatasheet

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8305AGI REV . B SEPTEMBER 17, 2012 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-to- LVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the ICS8305I ideal for those applications demanding well de- fined performance and repeatability. BLOCK D IAGRAM PIN A SSIGNMENT GND OE VDD CLK_EN CLK nCLK CLK_SEL LVCMOS_CLK V DDO GND V DDO GND ICS8305I 16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm package body G Package Top View

FEATURES

• 4 LVCMOS/LVTTL outputs  Selectab le differential or LVCMOS/LVTTL clock inputs
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  LVCMOS_CLK supports the following input types: LVCMOS, LVTTL  Maximum output frequency: 350MHz  Output skew: 40ps (maximum)  Part-to-part skew: 700ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)  3.3V core, 3.3V, 2.5V or 1.8V output operating supply  -40°C to 85°C ambient operating temperature  Lead-Free package fully RoHS compliant LVCMOS_CLK CLK nCLK CLK_SEL CLK_EN OE D Q LE

TABLE 1. PIN DESCRIPTIONS TABLE 2. P IN CHARACTERISTICS

FIGURE 1. CLK_EN TIMING DIAGRAM

8305AGI REV. B SEPTEMBER 17, 2012 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C l o b m ySr e t e m a r aPs n o i t i d n o C t s eTm u m i n iMl a c i p yTm u m i x aMs t i n U V D D e g a t l o V y l p p u S e r oC5 3 1 .33 .35 6 4 .3V V O D D e g a t l o V y l p p u S t u p t u O 5 3 1 .33 .35 6 4 .3V 5 7 3 .25 .25 2 6 .2V 5 6 .18 .15 9 .1V I D D t n e r r u C y l p p u S r e w o P 12A m I O D D t n e r r u C y l p p u S t u p t u O 5A m l o b m ySr e t e m a r aPs n o i t i d n o C t s eTm u m i n iMl a c i p yTm u m i x aMs t i n U V H I t u p n I e g a t l o V h g i H E O , L E S _ K L C , N E _ K LC2 V D D 3 . 0+V K L C _ S O M C VL2 V D D 3 . 0+V V L I t u p n I e g a t l o V w o L E O , L E S _ K L C , N E _ K LC3 . 0-8 .0V K L C _ S O M C VL3 . 0-3 .1V I H I t u p n I t n e r r u C h g i H E O , L E S _ K L C , N E _ K LCV D D V =N I V 5 6 4 . 3=5 Aµ K L C _ S O M C VLV D D V =N I V 5 6 4 . 3=0 51A µ I L I t u p n I t n e r r u C w o L E O , L E S _ K L C , N E _ K LCV D D V , V 5 6 4 . 3 =N I V 0=0 5 1-A µ K L C _ S O M C VLV D D V , V 5 6 4 . 3 =N I V 0=5 -A µ V H O 1 E T O N ; e g a t l o V h g i H t u p t u O V O D D % 5 ± V 3 . 3=6 .2V V O D D % 5 ± V 5 . 2=8 .1V V O D D V 5 1 . 0 ± V 8 . 1=V O D D 3 . 0-V V L O 1 E T O N ; e g a t l o V w o L t u p t u O V O D D % 5 ± V 3 . 3=5 .0V V O D D % 5 ± V 5 . 2=5 .0V V O D D V 5 1 . 0 ± V 8 . 1=4 .0V I L Z O w o L t n e r r u C e t a t s i r T t u p t u O 5-A µ I H Z O h g i H t n e r r u C e t a t s i r T t u p t u O 5A µ 0 5 h t i w d e t a n i m r e t s t u p t u O : 1 E T O NΩ V o tO D D . t i u c r i C t s e T d a o L t u p t u O , n o i t a m r o f n I t n e m e r u s a e M r e t e m a r a P e e S . 2 / TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C ABSOLUTE MAXIMUM R ATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

8305AGI REV . B SEPTEMBER 17, 2012 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C l o b m ySr e t e m a r aPs n o i t i d n o C t s eTm u m i n iMl a c i p yTm u m i x aMs t i n U I H I t n e r r u C h g i H t u p n I K L CnV N I V =D D V 5 6 4 . 3=0 51A µ K LCV N I V =D D V 5 6 4 . 3=0 51A µ I L I t n e r r u C w o L t u p n I K L CnV N I V , V 0 =D D V 5 6 4 . 3=0 5 1-A µ K LCV N I V , V 0 =D D V 5 6 4 . 3=5 -A µ V P P e g a t l o V t u p n I k a e P - o t - k a e P 5 1 .03 .1V V R M C ; e g a t l o V t u p n I e d o M n o m m o C 2 , 1 E T O N 5 . 0 + D NGV D D 5 8 . 0-V s n o i t a c i l p p a d e d n e e l g n i s r o F : 1 E T O N, V s i K L C n , K L C r o f e g a t l o v t u p n i m u m i x a m e h tD D . V 3 . 0 + V s a d e n i f e d s i e g a t l o v e d o m n o m m o C : 2 E T O NH I. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C l o b m ySr e t e m a r aPs n o i t i d n o C t s eTm u m i n iMl a c i p yTm u m i x aMs t i n U f X A M y c n e u q e r F t u p t u O K L C n / K L C = f eR0 53z H M K L C _ S O M C V L = f eR0 03z H M p tH L , y a l e D n o i t a g a p o r P h g i H o t w o L ; K L C _ S O M C V L A 1 E T O N ; K L C n , K L C B 1 E T O N 5 7 .18 .2s n t ) o ( ks6 , 2 E T O N ; w e k S t u p t uOe g d E g n i s i R e h t n o d e r u s a eM0 4s p t ) p p ( ks6 , 3 E T O N ; w e k S t r a P - o t - t r a P 0 07s p t t i j ; S M R , r e t t i J e s a h P e v i t i d d A r e f f u B , n o i t c e s r e t t i J e s a h P e v i t i d d A o t r e f e r

5 E T O N

4 0 .0s p tR t /F e m i T l l a F / e s i R t u p t uO% 0 8 o t % 020 010 07s p c doe l c y C y t u D t u p t u O ƒ≤ z H M 0 025 45 5% z H M 0 0 2 >ƒ2 48 5% t N E 4 E T O N ; e m i T e l b a n E t u p t u O 5s n t S I D 4 E T O N ; e m i T e l b a s i D t u p t u O 5s n d e h s i l b a t s e s i h c i h w , e g n a r e r u t a r e p m e t g n i t a r e p o t n e i b m a d e i f i c e p s e h t r e v o d e e t n a r a ug e r a s r e t e m a r a p l a c i r t c e l E : E T O N t e e m l l i w e c i v e d e h T . m p f l 0 0 5 n a h t r e t a e r g w o l f r i a e s r e v s n a r t d e n i a t n i a m h t i w t e k c o s t s e t a n i d e t n u o m s i e c i v e d e h t n e h w . s n o i t i d n o c e s e h t r e d n u d e h c a e r n e e b s a h m u i r b i l i u q e l a m r e h t r e t f a s n o i t a c i f i c e p s V e h t m o r f d e r u s a e M : A 1 E T O ND D V o t t u p n i e h t f o 2 /O D D . t u p t u o e h t f o 2 / V o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e M : B 1 E T O NO D D . t u p t u o e h t f o 2 / . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e D : 2 E T O N V t a d e r u s a e MO D D. 2 / d n a s e g a t l o v y l p p u s e m a s e h t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e D : 3 E T O N V t a d e r u s a e m s i t u p t u o e h t , e c i v e d h c a e n o t u p n i f o e p y t e m a s e h t g n i s U . s n o i t i d n o c d a o l l a u q e h t i wO D D. 2 / . n o i t c u d o r p n i d e t s e t t o N . n o i t a z i r e t c a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h T : 4 E T O N . k c o l c t u p n i e n o y l n o g n i v i r D : 5 E T O N . 5 6 d r a d n a t S C E D E J h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h T : 6 E T O N

8305AGI REV. B SEPTEMBER 17, 2012 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± -0.15V , TA = -40°C TO 85°C TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C l o b m ySr e t e m a r aPs n o i t i d n o C t s eTm u m i n iMl a c i p yTm u m i x aMs t i n U f X A M y c n e u q e r F t u p t u O K L C n / K L C = f eR0 53z H M K L C _ S O M C V L = f eR0 03z H M p tH L , y a l e D n o i t a g a p o r P h g i H o t w o L ; K L C _ S O M C V L A 1 E T O N ; K L C n , K L C B 1 E T O N 5 7 .15 9 .2s n t ) o ( ks6 , 2 E T O N ; w e k S t u p t uOe g d E g n i s i R e h t n o d e r u s a eM0 4s p t ) p p ( ks6 , 3 E T O N ; w e k S t r a P - o t - t r a P 0 08s p tti j ; S M R , r e t t i J e s a h P e v i t i d d A r e f f u B , n o i t c e s r e t t i J e s a h P e v i t i d d A o t r e f e r 4 0 .0s p tR t /F e m i T l l a F / e s i R t u p t uO% 0 8 o t % 020 010 07s p c doe l c y C y t u D t u p t u O ƒ≤ z H M 6 615 45 5% z H M 6 6 1 >f2 48 5% t N E 4 E T O N ; e m i T e l b a n E t u p t u O 5s n t S I D 4 E T O N ; e m i T e l b a s i D t u p t u O 5s n d e h s i l b a t s e s i h c i h w , e g n a r e r u t a r e p m e t g n i t a r e p o t n e i b m a d e i f i c e p s e h t r e v o d e e t n a r a ug e r a s r e t e m a r a p l a c i r t c e l E : E T O N t e e m l l i w e c i v e d e h T . m p f l 0 0 5 n a h t r e t a e r g w o l f r i a e s r e v s n a r t d e n i a t n i a m h t i w t e k c o s t s e t a n i d e t n u o m s i e c i v e d e h t n e h w . s n o i t i d n o c e s e h t r e d n u d e h c a e r n e e b s a h m u i r b i l i u q e l a m r e h t r e t f a s n o i t a c i f i c e p s V e h t m o r f d e r u s a e M : A 1 E T O ND D V o t t u p n i e h t f o 2 /O D D . t u p t u o e h t f o 2 / V o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e M : B 1 E T O NO D D . t u p t u o e h t f o 2 / V t a d e r u s a e M . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e D : 2 E T O NO D D. 2 / d n a s e g a t l o v y l p p u s e m a s e h t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e D : 3 E T O N V t a d e r u s a e m s i t u p t u o e h t , e c i v e d h c a e n o t u p n i f o e p y t e m a s e h t g n i s U . s n o i t i d n o c d a o l l a u q e h t i wO D D. 2 / . n o i t c u d o r p n i d e t s e t t o N . n o i t a z i r e t c a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h T : 4 E T O N . k c o l c t u p n i e n o y l n o g n i v i r D : 5 E T O N . 5 6 d r a d n a t S C E D E J h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h T : 6 E T O N l o b m ySr e t e m a r aPs n o i t i d n o C t s eTm u m i n iMl a c i p yTm u m i x aMs t i n U f X A M y c n e u q e r F t u p t u O K L C n / K L C = f eR0 53z H M K L C _ S O M C V L = f eR0 03z H M p tH L , y a l e D n o i t a g a p o r P h g i H o t w o L ; K L C _ S O M C V L A 1 E T O N ; K L C n , K L C B 1 E T O N 5 7 .17 .3s n t ) o ( ks6 , 2 E T O N ; w e k S t u p t uOe g d E g n i s i R e h t n o d e r u s a eM5 4s p t ) p p ( ks6 , 3 E T O N ; w e k S t r a P - o t - t r a P 0 09s p tj ti ; S M R , r e t t i J e s a h P e v i t i d d A r e f f u B , n o i t c e s r e t t i J e s a h P e v i t i d d A o t r e f e r 4 0 .0s p tR t /F e m i T l l a F / e s i R t u p t uO% 0 8 o t % 020 010 07s p c doe l c y C y t u D t u p t u O ƒ≤ z H M 6 615 45 5% z H M 6 6 1 >f2 48 5% t N E 4 E T O N ; e m i T e l b a n E t u p t u O 5s n t S I D 4 E T O N ; e m i T e l b a s i D t u p t u O 5s n . B 5 e l b a T e e s , s e t o n r o F

8305AGI REV . B SEPTEMBER 17, 2012 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER ADDITIVE PHASE JITTER Input/Output Additive Phase Jitter at 155.52MHz = 0.04ps typical -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fun- damental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- the 1Hz band to the power in the fundamental. When the re- quired offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the funda- mental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

8305AGI REV. B SEPTEMBER 17, 2012 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION PART-TO-PART S KEW t sk(o) VDDO VDDO Qx Qy DIFFERENTIAL INPUT LEVEL OUTPUT SKEW 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx LVCMOS VCMRCross Points VPP GND CLK nCLK VDD t sk(pp) VDDO VDDO Qx Qy PART 1 PART 2 -1.65V±5% 1.65V±5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT -1.25V±5% 1.25V±5% SCOPE Qx LVCMOS -0.9V±0.075V 0.9V±0.075V VDD VDDO 2.4V±0.09V SCOPE Qx LVCMOS VDD VDDO 2.05V±5% VDD, VDDO GND GND GND

8305AGI REV . B SEPTEMBER 17, 2012 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER PROPAGATION D ELAY OUTPUT RISE/FALL TIME Clock Outputs 20% 80% 80% 20% tR tF nCLK CLK Q0:Q3 tPD VDDO ➤ ➤ VDD OUTPUT D UTY C YCLE/PULSE WIDTH/PERIOD tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0:Q3 LVCMOS_CLK

TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. FIGURE 4. E XAMPLE ICS8305I LVCMOS CLOCK OUTPUT BUFFER SCHEMATIC

TABLE 7. P ACKAGE DIMENSIONS

TABLE 8. O RDERING INFORMATION

8305AGI REV . B SEPTEMBER 17, 2012 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER T E E H S Y R O T S I H N O I S I V E R v eRe l b aTe g aPe g n a h C f o n o i t p i r c s eDe t a D A8 T4 1 m o r f o p y t r e b m u N r e d r O / t r a P d e t c e r r o c - e l b a t n o i t a m r o f n I g n i r e d r O . T I G A 5 0 3 8 S C I o t T I G A 5 0 3 8 8 S C I 4 0 / 0 2 / 1 B C 5 T - A 5T6 & 5 . l a c i p y t s p 4 0 . 0 o t l a c i p y t s p 5 0 . 0 m o r f t i j t d e g n a h c - s e l b a T s c i t s i r e t c a r a h C C A . t o l p r e t t i J e s a h P e v i t i d d A d e t a d p U 4 0 / 6 2 / 2 B1 T2 .n o i t p i r c s e d N E _ K L C d e t c e r r o c - e l b a T n o i t p i r c s e D n i P4 0 / 7 / 2 1 B8 T4 1r e b m u n t r a p e e r F - d a e L d e d d a - e l b a T n o i t a m r o f n I g n i r e d r O5 0 / 9 1 / 5 B8 T4 1 6 1 . S C I m o r f T D I h t i w r e t o o f / r e d a e h s ' t e e h s a t a d d e t a d p U . n m u l o c r e b m u N r e d r O / t r a P m o r f x i f e r p S C I d e v o m e R . e g a P t c a t n o C d e d d A 0 1 / 9 2 / 7 B B 5 T , A 5 T 8 T 6 & 5 0 1 4 1 e r a s r e t e m a r a p l a c i r t c e l E : E T O N ' ; d e d d a - s e l b a T s c i t s i r e t c a r a h C C A . ' . . . d e e t n a r a u g , n o i t c e s s n i P t u p t u O d n a t u p n I d e s u n U r o f n o i t a d n e m m o c e R d e d d A ' s l e v e L d e d n E e l g n i S t p e c c A o t t u p n I l a i t n e r e f f i D e h t g n i r i W ' e h t d e t a d p U g n i g a k c a P g n i p p i h S m o r f y t i t n a u Q d e t e l e D 2 1 / 7 1 / 9

8305AGI www.idt.com REV. B SEPTEMBER 17, 2012 ICS8305I LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER We’ve Got Your Timing Solution. Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 Tech Support netcom@idt.com

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