ICS8305I-02 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 21
Technical content
Features
- Four LVCMOS/LVTTL outputs, (two banks of two LVCMOS outputs)
- Selectable differential CLK, nCLK pair or LVCMOS_CLK input
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL
- LVCMOS_CLK supports the following input types: LVCMOS, LVTTL
- Maximum output frequency: 250MHz
- Output skew: 100ps (maximum)
- Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 3.3V/1.5V
- -40°C to 85°C ambient operating temperature
- Lead-free (RoHS 6) packaging
- For functional replacement device use 8305 QA0 VDDO_A QA1 GND QB0 VDDO_B QB1 GNDLVCMOS_CLK CLK_SEL nCLK CLK CLK_EN VDD OEB OEA LVCMOS _CLK CLK nCLK CLK_S EL QA0 QA1 QB0 QB1 CLK_EN OEB OEA D Q LE Pullup Pullup Pullup Pullup Pulldown Pulldown Pullup ICS8305I-02 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View Pin AssignmentBlock Diagram PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2016
ICS8305AGI-02 REVISION A May 6, 2016 2 ©2016 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics
1 OEA Input Pullup
2 OEB Input Pullup
DD Power Positive supply pins. HIGH, output clocks are enabled. LVCMOS / LVTTL interface levels. 5 CLK Input Pulldown Non-inverting differential clock input. 6 nCLK Input Pullup Inverting differential clock input. 7 CLK_SEL Input Pullup Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW, selects LVCMOS_CLK input. LVCMOS / LVTTL interface levels. 8 LVCMOS_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 9, 13 GND Power Power supply ground. 10, 12 QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. DDO_B Power Output supply pin for Bank B outputs. 14, 16 QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. 15 VDDO_A Power Output supply pin for Bank A outputs.
ICS8305AGI-02 REVISION A May 6, 2016 3 ©2016 Integrated Device Technology, Inc. Table 3. Clock Input Function Table falling input clock edge as shown in Figure 1. Figure 1. CLK_EN Timing Diagram
0 X X High-Impedance
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 4 ©2016 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 1.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 100.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO_A, VDDO_B Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.65 1.8 1.95 V 1.425 1.5 1.575 V IDD Power Supply Current 21 mA IDDO_A + IDDO_B Output Supply Current No Load 5 mA
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 5 ©2016 Integrated Device Technology, Inc. 1.5V±5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_A and VDDO_B. NOTE 1: Outputs terminated with 50 to VDDO_X/2. See Parameter Measurement Information section, Output Load Test Circuit diagrams. TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Symbol Parameter Test Conditi ons Minimum Typical Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current OEA, OEB, CLK_SEL, CLK_EN VDD = VIN = 3.465V 5 µA LVCMOS_CLK VDD = VIN = 3.465V 150 µA IIL Input Low Current OEA, OEB, CLK_SEL, CLK_EN V DD = 3.465V, VIN = 0V -150 µA LVCMOS_CLK VDD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 VDDO_X = 3.3V ± 5% 2.6 V VDDO_X = 2.5V ± 5% 1.8 V VDDO_X = 1.8V ± 0.15V 1.5 V VDDO_X = 1.5V ± 5% VDDO_X – 0.3 V VOL Output Low Voltage; NOTE 1 VDDO_X = 3.3V ± 5% 0.5 V VDDO_X = 2.5V ± 5% 0.4 V VDDO_X = 1.8V ± 0.15V 0.35 V VDDO_X = 1.5V ± 5% 0.30 V IOZL Output High-Impedance Low -5 µA IOZH Output High-Impedance High 5µ A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current CLK, VDD = VIN = 3.465V 150 µA nCLK VDD = VIN = 3.465V 5 µA IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA nCLK VDD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Input Common Mode Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 6 ©2016 Integrated Device Technology, Inc. Table 5A. AC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input clock (LVCMOS_CLK) or from the differential input crossing point (CLK, nCLK) to VDDO_X/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO_X/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO_X/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 6: Driving only one input clock. NOTE 7: These parameters are guaranteed by characterization. Not tested in production. NOTE 8: Input duty cycle must be 50%. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 250 MHz tPD Propagation Delay; NOTE 1 1.9 3.2 ns tsk(o) Output Skew; NOTE 2, 4 Measured on the Rising Edge 100 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 900 ps tsk(b) Bank Skew; NOTE 4, 5 35 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 6 CLK, nCLK 156.25MHz, Integration Range: 12kHz - 20MHz 0.25 ps t R / tF Output Rise/Fall Time; NOTE 7 20% to 80% 100 700 ps odc Output Duty Cycle; NOTE 8 CLK, nCLK ƒOUT 156.25MHz 45 55 % LVCMOS_CLK ƒ OUT 156.25MHz 40 60 % tEN Output Enable Time: NOTE 7 5n s tDIS Output Disable Time: NOTE 7 5n s
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 7 ©2016 Integrated Device Technology, Inc. Table 5B. AC Characteristics, VDD = 3.3V±5%, VDDO_A = VDDO_B = 2.5V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input clock (LVCMOS_CLK) or from the differential input crossing point (CLK, nCLK) to VDDO_X/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO_X/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO_X/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 6: Driving only one input clock. NOTE 7: These parameters are guaranteed by characterization. Not tested in production. NOTE 8: Input duty cycle must be 50%. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 250 MHz tPD Propagation Delay; NOTE 1 1.9 3.2 ns tsk(o) Output Skew; NOTE 2, 4 Measured on the Rising Edge 100 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 900 ps tsk(b) Bank Skew; NOTE 4, 5 35 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 6 CLK, nCLK 156.25MHz, Integration Range: 12kHz - 20MHz 0.25 ps tR / tF Output Rise/Fall Time; NOTE 7 20% to 80% 100 700 ps odc Output Duty Cycle; NOTE 8 CLK, nCLK ƒOUT 156.25MHz 45 55 % LVCMOS_CLK ƒ OUT 156.25MHz 40 60 % tEN Output Enable Time: NOTE 7 5n s tDIS Output Disable Time: NOTE 7 5n s
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 8 ©2016 Integrated Device Technology, Inc. Table 5C. AC Characteristics, VDD = 3.3V±5%, VDDO_A = VDDO_B = 1.8V±0.15V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input clock (LVCMOS_CLK) or from the differential input crossing point (CLK, nCLK) to VDDO_X/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO_X/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO_X/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 6: Driving only one input clock. NOTE 7: These parameters are guaranteed by characterization. Not tested in production. NOTE 8: Input duty cycle must be 50%. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 250 MHz tPD Propagation Delay; NOTE 1 2.2 3.9 ns tsk(o) Output Skew; NOTE 2, 4 Measured on the Rising Edge 100 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 1.2 ns tsk(b) Bank Skew; NOTE 4, 5 50 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 6 CLK, nCLK 156.25MHz, Integration Range: 12kHz - 20MHz 0.28 ps t R / tF Output Rise/Fall Time; NOTE 7 20% to 80% 100 800 ps odc Output Duty Cycle; NOTE 8 CLK, nCLK ƒOUT 156.25MHz 45 55 % LVCMOS_CLK ƒ OUT 156.25MHz 40 60 % tEN Output Enable Time: NOTE 7 5n s tDIS Output Disable Time: NOTE 7 5n s
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 9 ©2016 Integrated Device Technology, Inc. Table 5D. AC Characteristics, VDD = 3.3V±5%, VDDO_A = VDDO_B = 1.5V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at ƒ 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input clock (LVCMOS_CLK) or from the differential input crossing point (CLK, nCLK) to VDDO_X/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO_X/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO_X/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 6: Driving only one input clock. NOTE 7: These parameters are guaranteed by characterization. Not tested in production. NOTE 8: Input duty cycle must be 50%. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 250 MHz tPD Propagation Delay; NOTE 1 2.5 4.3 ns tsk(o) Output Skew; NOTE 2, 4 Measured on the Rising Edge 100 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 1.6 ns tsk(b) Bank Skew; NOTE 4, 5 50 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, NOTE 6 CLK, nCLK 156.25MHz, Integration Range: 12kHz - 20MHz 0.35 ps t R / tF Output Rise/Fall Time; NOTE 7 20% to 80% 100 800 ps odc Output Duty Cycle; NOTE 8 CLK, nCLK ƒOUT 156.25MHz 45 55 % LVCMOS_CLK ƒ OUT 156.25MHz 40 60 % tEN Output Enable Time: NOTE 7 5n s tDIS Output Disable Time: NOTE 7 5n s
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 10 ©2016 Integrated Device Technology, Inc. Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements have issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Measured using a Rohde & Schwarz SMA100 as the input source. Additive Phase Jitter @ 156.25MHz 12kHz to 20MHz = 0.25ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 11 ©2016 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load Test Circuit 3.3V Core/1.8V LVCMOS Output Load Test Circuit Differential Input Level 3.3V Core/2.5V LVCMOS Output Load Test Circuit 3.3V Core/1.5V LVCMOS Output Load Test Circuit Output Skew SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO_A, VDDO_B SCOPE Qx GND VDD -0.9V±0.075V 0.9V±0.075V 2.4V±0.09V VDDO_A, VDDO_B VDD GND CLK nCLK V CMR Cross PointsVPP SCOPE Qx GND VDD -1.25V±5% 1.25V±5% 2.05V±5% VDDO_A, VDDO_B SCOPE Qx GND VDD -0.75V±5% 0.75V±5% VDDO_A, VDDO_B 2.55V±5% tsk(o) VDDO_X VDDO_X Qx Qy
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 12 ©2016 Integrated Device Technology, Inc. Parameter Measurement Information, continued Part-to-Part Skew Output Rise/Fall Time Propagation Delay Bank Skew Output Duty Cycle/Pulse Width/Period tsk(pp) VDDO_X VDDO_X Part 1 Part 2 Qx Qy 20% 80% 80% 20% tR tF QA[0:1], QB[0:1] nCLK QA[0:1], QB[0:1] CLK tpLH VDDO_X VDD 2LVCMOS_CLK tsk(b) VDDO_X VDDO_X QX0 QX1 Where X denotes outputs in the same Bank tPERIOD tPW tPERIOD odc = VDDO_X x 100% tPW QA[0:1], QB[0:1]
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 14 ©2016 Integrated Device Technology, Inc. Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS_CLK Input For applications not requiring the use of the single-ended clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the LVCMOS_CLK input to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached.
ICS8305AGI-02 REVISION A May 6, 2016 16 ©2016 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8305I-02. Equations and example calculations are also provided. The total power dissipation for the ICS8305I-02 is the sum of the core power plus the power dissipation due to loading. DD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 100.3°C/W per Table 6 below. Table 6. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
ICS8305AGI-02 REVISION A May 6, 2016 17 ©2016 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 16 Lead TSSOP
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER ICS8305AGI-02 REVISION A May 6, 2016 18 ©2016 Integrated Device Technology, Inc.
Ordering Information
Table 9. Ordering Information
ICS8305AGI-02 REVISION A May 6, 2016 19 ©2016 Integrated Device Technology, Inc.
Revision History
Revision Date Description of Change May 19, 2016 ▪ Product Discontinuation Notice - Last time buy expires May 6, 2017. ▪ PDN CQ-16-01
ICS8305I-02 Data Sheet LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. Performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without re presentation or warranty of a ny kind, whether express or implie d, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi- cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2016. All rights reserved.
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