830584I

830584I RENESAS | Alldatasheet

Document overview

• Manufacturer or author: rdvorak
• PDF pages: 13

Technical content

Low Skew, PCI-X 1-to-4 Fanout Buffer 830584I Datasheet ©2015 Integrated Device Technology, Inc December 16, 20151 GENERAL DESCRIPTION The 830584I is a low skew, general purpose PCI-X 1-to-4 Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. Guaranteed output and part-to-part skew characteristics make the 830584I ideal for those clock distribution applications demanding well defi ned performance and repeatablility. The 830584I is designed and characterized from -40°C to 85°C for industrial applications and is packaged in an 8 TSSOP package. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

• General purpose and PCI-X 1:4 clock buffer
• Four single-ended LVCMOS/LVTTL clock outputs
• One single-ended LVCMOS/LVTTL clock input
• Maximum output frequency: 140MHz
• Output enable control (outputs disabled in logic low state)
• Output skew: 100ps (maximum)
• Part-to-part skew: 400ps (maximum)
• Additive phase jitter, RMS: 0.15ps (typical)
• Space-saving 8 lead TSSOP package
• Full 3.3V operating supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages CLKIN OE 830584I 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View CLKIN OE GND V DD

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. FUNCTION TABLE 1 CLKIN Input Single-ended clock input reference signal. LVCMOS/LVTTL interface levels. 2 OE Input Output enable control input pin. See Table 3, Function Table. LVCMOS / LVTTL interface levels. 3, 5, 7. 8 Q0, Q1, Q2, Q3 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 4 GND Power Power supply ground.

©2015 Integrated Device Technology, Inc December 16, 20153 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DD + 0.5V Package Thermal Impedance, θ JA 121.5°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. RECOMMENDED OPERATING CONDITIONS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Positive Supply Voltage 3.0 3.3 3.6 V V IH High Level Input Voltage 0.7*V DD V V IL Low Level Input Voltage 0.3*V DD V V I Input Voltage 0 V DD V I OH High-Level Output Current -24 mA I OL Low-Level Output Current 24 mA T A Operating Free-Air Temperature -40 85 °C TABLE 4B. DC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical† Maximum Units V IK Input Voltage I I = -18mA –1.2 V V OH Output High Voltage I OH = -1mA V DD – 0.2 V I OH = -24mA 2 V I OH = -12mA 2.4 V V OL Output Low Voltage I OL = 1mA 0.2 V I OL = 24mA 0.8 V I OL = 12mA 0.55 V I OH Output High Current V O = 1V –50 mA V O = 1.65V –55 mA I OL Output Low Current V O = 2V 60 mA V O = 1.65V 70 mA I I Input Current V I = 0V or V DD ±150 µA I DD Dynamic Current f = 67MHz 37 mA C i Input Capacitance V I = 0V or V DD 3p F C o Output Capacitance V I = 0V or V DD 3.2 pF All typical values are at respective nominal V DD and 25°C.

This symbol is according to PCI-X terminology. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. TABLE 5. AC CHARACTERISTICS, V

©2015 Integrated Device Technology, Inc December 16, 20155 ADDITIVE PHASE JITTER The spectral purity in a band at a specifi c offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels As with most timing specifi cations, phase noise measurements has issues relating to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor of the device. (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. This is illustrated above. The device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ Input/Output Additive Phase Jitter at 140MHz (12kHz – 20MHz) = 0.15ps typical

©2015 Integrated Device Technology, Inc December 16, 20156 PARAMETER MEASUREMENT INFORMATION PART-TO-PART SKEW OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT PROPAGATION DELAY OUTPUT RISE/FALL SLEW RATES CLOCK WAVEFORM OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

©2015 Integrated Device Technology, Inc December 16, 20157 PARAMETER MEASUREMENT INFORMATION, CONTINUED Supply Current vs Frequency 0 20 40 60 80 100 120 140 160 f - Frequency - MHz IDD - Supply Current - mA VDD=3.6V TA=85oC

©2015 Integrated Device Technology, Inc December 16, 20158 RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for 830584I is: 307 TABLE 6. θ The OE pin must be tied either HIGH or LOW. Do not leave fl oating.

APPLICATION INFORMATION

OUTPUTS: LVCMOS OUTPUTS All unused LVCMOS outputs can be left fl oating. We recommend that there is no trace attached.

TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION

©2015 Integrated Device Technology, Inc December 16, 201511 REVISION HISTORY SHEET Rev Table Page Description of Change Date B T4B 3 DC Characteristics Table - corrected Input Current typo from ±5µA max. to ±150µA max. 3/18/08 B T8 General Description - removed ICS Chip and HiPerClockS. Ordering Information - removed ICS under Part/Order Number. Removed 2500 for Tape & Reel. Removed LF Note below table. Updated Header and Footer. 12/16/15

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