ICS83056I-01 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 15

Technical content

Features

  • 6-Bit, 2:1 single-ended LVCMOS multiplexer
  • Maximum output frequency: 250MHz
  • Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz): 0.18ps (typical)
  • Operating supply modes: Core/Output VDD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V
  • -40°C to 85°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS VDD CLK1 SEL4 GND VDDO SEL5 SEL3 SEL0 VDDO GND SEL1 CLK0 OE SEL2 CLK0 Pulldown CLK1 Pulldown Pulldown Pullup SEL0 OE PulldownSEL1 PulldownSEL2 PulldownSEL3 PulldownSEL4 PulldownSEL5 ICS83056I-01 20-Lead TSSOP 6.50mm x 4.40mm x 0.925mm package body G Package Top View Pin Assignment Block Diagram

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Control Input Function Table Input Pulldown Clock select inputs. See Tabl e 3. LVCMOS / LVTTL interface levels. Q2, Q1, Q0 Output Single-ended clock output. LV CMOS/LVTTL interface levels. 3, 18 V DDO Power Output supply pins. 4, 17 GND Power Power supply ground. 7, 14 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 8V DD Power Power supply pin. 13 OE Input Pullup Output enable. When LOW, outputs are in a High impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels.

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 3 ICS83056AGI-01 REV. A JANUARY 29, 2009 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 91.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.6 1.8 2.0 V IDD Power Supply Current 45 mA IDDO Output Supply Current No Load 5 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V 1.6 1.8 2.0 V IDD Power Supply Current 40 mA IDDO Output Supply Current No Load 5 mA

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 4 ICS83056AGI-01 REV. A JANUARY 29, 2009 Table 4C. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.465V 2 V DD + 0.3 V VDD = 2.625V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.465V -0.3 1.3 V VDD = 2.625V -0.3 0.7 V IIH Input High Current CLK0, CLK1, SEL[0:5] VDD = VIN = 3.465V or 2.625V 150 µA OE V DD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current CLK0, CLK1, SEL[0:5] VDD = 3.465V or 2.625V, VIN = 0V -5 µA OE V DD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage; VDDO = 3.3V ± 5%, IOH = -24mA 2.6 V VDDO = 2.5V ± 5%, IOH = -12mA 1.8 V VDDO = 1.8V ± 0.2V, IOH = -4mA V DDO - 0.3 V VOL Output Low Voltage VDDO = 3.3V ± 5%, IOL = 24mA 0.5 V VDDO = 2.5V ± 5%, IOL = 12mA 0.45 V VDDO = 1.8V ± 0.2V, IOL = 4mA 0.35 V

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 5 ICS83056AGI-01 REV. A JANUARY 29, 2009 Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Driving only one input clock. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C See notes in Table 5A above. Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 1.8 2.5 3.2 ns tpHL Propagation Delay, High-to-Low; NOTE 1 2.0 2.6 3.2 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 2 155.52MHz, Integration Range: 12kHz – 20MHz 0.18 ps tsk(i) Input Skew; NOTE 3 145 ps tsk(o) Output Skew: NOTE 4 130 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 800 ps tR / tF Output Rise/Fall Time 20% to 80% 300 800 ps odc Output Duty Cycle f OUT ≤ 175MHz 40 60 % MUXISOLATION MUX Isolation 100MHz 45 dB Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 2.1 2.6 3.1 ns tpHL Propagation Delay, High-to-Low; NOTE 1 2.3 2.7 3.1 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 2 155.52MHz, Integration Range: 12kHz – 20MHz 0.14 ps tsk(i) Input Skew; NOTE 3 100 ps tsk(o) Output Skew: NOTE 4 130 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 800 ps tR / tF Output Rise/Fall Time 20% to 80% 300 800 ps odc Output Duty Cycle 40 60 % MUXISOLATION MUX Isolation 100MHz 45 dB

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 6 ICS83056AGI-01 REV. A JANUARY 29, 2009 Table 5C. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Driving only one input clock. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. Table 5D. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C See notes in Table 5C above. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 2.6 3.1 3.6 ns tpHL Propagation Delay, High-to-Low; NOTE 1 2.7 3.2 3.7 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 2 155.52MHz, Integration Range: 12kHz – 20MHz 0.16 ps tsk(i) Input Skew; NOTE 3 110 ps tsk(o) Output Skew: NOTE 4 130 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 800 ps tR / tF Output Rise/Fall Time 20% to 80% 450 850 ps odc Output Duty Cycle 40 60 % MUXISOLATION MUX Isolation 100MHz 45 dB Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 1.5 3.0 4.5 ns tpHL Propagation Delay, High-to-Low; NOTE 1 2.2 2.8 3.4 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 2 155.52MHz, Integration Range: 12kHz – 20MHz 0.22 ps tsk(i) Input Skew; NOTE 3 140 ps tsk(o) Output Skew: NOTE 4 125 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 800 ps tR / tF Output Rise/Fall Time 20% to 80% 300 700 ps odc Output Duty Cycle f OUT ≤ 175MHz 40 60 % MUXISOLATION MUX Isolation 100MHz 45 dB

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 7 ICS83056AGI-01 REV. A JANUARY 29, 2009 Table 5E. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Driving only one input clock. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 2.2 3.2 4.2 ns tpHL Propagation Delay, High-to-Low; NOTE 1 2.2 3.2 4.0 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 2 155.52MHz, Integration Range: 12kHz – 20MHz 0.19 ps tsk(i) Input Skew; NOTE 3 110 ps tsk(o) Output Skew: NOTE 4 125 ps tsk(pp) Part-to-Part Skew; NOTE 3, 5 800 ps tR / tF Output Rise/Fall Time 20% to 80% 450 850 ps odc Output Duty Cycle f OUT ≤ 200MHz 40 60 % MUXISOLATION MUX Isolation 100MHz 45 dB

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 8 ICS83056AGI-01 REV. A JANUARY 29, 2009 Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Offset Frequency (Hz) SSB Phase Noise dBc/Hz Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.18ps (typical)

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 9 ICS83056AGI-01 REV. A JANUARY 29, 2009 Parameter Measurement Information 3.3V Output Load AC Test Circuit 3.3V Core/1.8V Output Load AC Test Circuit 2.5V Core/1.8V Output Load AC Test Circuit 3.3V Core/2.5V Output Load AC Test Circuit 2.5V Core/2.5V Output Load AC Test Circuit Output Skew SCOPE QxLVCMOS GND VDD, 1.65V±5% -1.65V±5% VDDO SCOPE Qx LVCMOS GND VDD 2.4V±0.065V -0.9V±0.1V VDDO 0.9V±0.1V SCOPE Qx LVCMOS GND VDD 1.6V±0.025V -0.9V±0.1V VDDO 0.9V±0.1V SCOPE Qx LVCMOS GND VDD 2.05V±5% -1.25V±5% VDDO 1.25V±5% SCOPE QxLVCMOS GND VDD, 1.25V±5% -1.25V±5% VDDO Qx Qy tsk(o) VDDO VDDO

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 10 ICS83056AGI-01 REV. A JANUARY 29, 2009 Parameter Measurement Information, continued Part-to-Part Skew Propagation Delay Input Skew Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time tsk(pp) VDD VDD Part 1 Part 2 Qx Qy t PD VDD VDD 2Q[0:5] CLK0, CLK1 tPD1 tPD2 tsk(i) = tPD2 – tPD1 tsk (i) CLK1 Q[0:5] CLK0 tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q[0:5] 20% 80% 80% 20% tR tF Q[0:5]

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 11 ICS83056AGI-01 REV. A JANUARY 29, 2009 Parameter Measurement Information, continued MUX Isolation

Application Information

Recommendations for Unused Input and Output Pins Inputs: CLK Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. Amplitude (dB) Spectrum of Output Signal Q MUX_ISOL = A0 – A1 (fundamental) Frequencyƒ MUX selects static input MUX selects active input clock signal L or H SEL Q

Table 6. θJA vs. Air Flow Table for a 20 Lead TSSOP

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER 13 ICS83056AGI-01 REV. A JANUARY 29, 2009

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.

6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER www.IDT.com © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) Contact Information: www.IDT.com

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.