83054AGILFT | DigiCamel IC Datasheet

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4:1, Single-Ended Multiplexer 83054 Data Sheet ©2015 Integrated Device Technology, Inc December 15, 20151 GENERAL DESCRIPTION The 83054 is a low skew, 4:1, Single-ended Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83054 has four selectable single-ended clock inputs and one single-ended clock output. The output has a V DDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug purposes. The device operates up to 250MHz and is pack- aged in a 16 TSSOP package. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

4:1 single-ended multiplexer Q nominal output impedance: 7Ω (V DDO = 3.3V) Maximum output frequency: 250MHz Propagation delay: 3ns (maximum), V DD = V DDO = 3.3V Input skew: 225ps (maximum), V DD = V DDO = 3.3V Part-to-part skew: 780ps (maximum), V DD = V DDO = 3.3V Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V Operating supply modes: V DD DDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package CLK0 CLK1 CLK2 CLK3 SEL1 SEL0 OE Q 83054 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View

83054 Data Sheet

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. CONTROL INPUT FUNCTION TABLE 1 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. 3 OE Input Pullup Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 5 GND Power Power supply ground. 7, 9 SEL1, SEL0 Input Pulldown Clock select input. See Control Input Function Table. LVCMOS / LVTTL interface levels. Power Power and input supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

©2015 Integrated Device Technology, Inc December 15, 20153 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θ JA 89°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speciﬁ cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO = 1.8V±0.2V, TA = -40°C TO 85°C TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, V DD = 2.5V±5%, V DDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current 40 mA I DDO Output Supply Current 5m A Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current 40 mA I DDO Output Supply Current 5m A Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 1.71 1.8 1.89 V I DD Power Supply Current 40 mA I DDO Output Supply Current 5m A Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 2.375 2.5 2.625 V V DDO Output Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current 35 mA I DDO Output Supply Current 5m A Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 2.375 2.5 2.625 V V DDO Output Supply Voltage 1.71 1.8 1.89 V I DD Power Supply Current 35 mA I DDO Output Supply Current 5m A

©2015 Integrated Device Technology, Inc December 15, 20154 TABLE 5A. AC CHARACTERISTICS, V DD = V DDO TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage V DD = 3.3V ± 5% 2 V DD + 0.3 V V DD = 2.5V ± 5% 1.7 V DD + 0.3 V V IL Input Low Voltage V DD V DD I IH Input High Current CLK0:CLK3, SEL0, SEL1 V DD = 3.3V or 2.5V ± 5% 150 µA OE V DD = 3.3V or 2.5V ± 5% 5 µA I IL Input Low Current CLK0:CLK3, SEL0, SEL1 V DD = 3.3V or 2.5V ± 5% -5 µA OE V DD = 3.3V or 2.5V ± 5% -150 µA V OH Output HighVoltage V DDO = 3.3V ± 5%; NOTE 1 2.6 V V DDO = 2.5V ± 5%; NOTE 1 1.8 V V DDO = 1.8V ± 5%; NOTE 1 V DD - 0.3 V V OL Output Low Voltage V DDO = 3.3V ± 5%; NOTE 1 0.5 V V DDO = 2.5V ± 5%; NOTE 1 0.45 V V DDO = 1.8V ± 5%; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50Ω to V DDO /2. See Parameter Measurement section, “Load Test Circuit” diagrams. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.4 2.7 3.0 ns tp HL Propagation Delay, High to Low; NOTE 1 2.5 2.7 2.9 ns tsk(i) Input Skew; NOTE 2 55 225 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 155.52MHz, (12kHz to 20MHz) 0.19 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps t R / t F Output Rise/Fall Time 20% to 80% 50 500 ps odc Output Duty Cycle 45 55 % MUX ISOL MUX Isolation @ 100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2.

©2015 Integrated Device Technology, Inc December 15, 20155 TABLE 5B. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO TABLE 5C. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.5 2.8 3.1 ns tp HL Propagation Delay, High to Low; NOTE 1 2.6 2.8 3.0 ns tsk(i) Input Skew; NOTE 2 45 150 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 155.52MHz, (12kHz to 20MHz) 0.14 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps t R / t F Output Rise/Fall Time 20% to 80% 50 500 ps odc Output Duty Cycle 45 55 % MUX ISOL MUX Isolation @ 100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.7 3.2 3.8 ns tp HL Propagation Delay, High to Low; NOTE 1 2.8 3.3 3.8 ns tsk(i) Input Skew; NOTE 2 50 150 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 155.52MHz, (12kHz to 20MHz) 0.16 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps t R / t F Output Rise/Fall Time 20% to 80% 100 700 ps odc Output Duty Cycle 45 55 % MUX ISOL MUX Isolation @ 100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2.

©2015 Integrated Device Technology, Inc December 15, 20156 TABLE 5D. AC CHARACTERISTICS, V DD = V DDO TABLE 5E. AC CHARACTERISTICS, V DD = 2.5V ± 5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.5 3.0 3.5 ns tp HL Propagation Delay, High to Low; NOTE 1 2.5 2.9 3.4 ns tsk(i) Input Skew; NOTE 2 60 175 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 155.52MHz, (12kHz to 20MHz) 0.21 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps t R / t F Output Rise/Fall Time 20% to 80% 100 500 ps odc Output Duty Cycle 40 60 % MUX ISOL MUX Isolation @ 100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.6 3.3 4.0 ns tp HL Propagation Delay, High to Low; NOTE 1 2.7 3.3 4.0 ns tsk(i) Input Skew; NOTE 2 50 150 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 155.52MHz, (12kHz to 20MHz) 0.17 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 780 ps t R / t F Output Rise/Fall Time 20% to 80% 100 700 ps odc Output Duty Cycle 40 60 % MUX ISOL MUX Isolation @ 100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is deﬁ ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Deﬁ ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2.

©2015 Integrated Device Technology, Inc December 15, 20157 ADDITIVE PHASE JITTER Additive Phase Jitter @ 155.52MHz (12kHz to 20MHz) = 0.19ps typical The spectral purity in a band at a speciﬁ c offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the speciﬁ ed plot in many applications. Phase noise is deﬁ ned as the ratio of the noise power present in a 1Hz band at a speciﬁ ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the As with most timing speciﬁ cations, phase noise measurements has issues relating to the limitations of the equipment. Often the noise ﬂ oor of the equipment is higher than the noise ﬂ oor of the device. fundamental. When the required offset is speciﬁ ed, the phase noise is called a dBc value, which simply means dBm at a speciﬁ ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. This is illustrated above. The device meets the noise ﬂ oor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

©2015 Integrated Device Technology, Inc December 15, 20158 PARAMETER MEASUREMENT INFORMATION 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW

APPLICATION INFORMATION

INPUTS: CLK INPUTS For applications not requiring the use of a clock input, it can be left ﬂ oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT PINS

TABLE 6. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION

©2015 Integrated Device Technology, Inc December 15, 201513 REVISION HISTORY SHEET Rev Table Page Description of Change Date B T5A - T5E 4 - 6 Features Section - added Additive Phase Jitter bullet. AC Characteristics Tables - added tjit row and spec. Added Additive Phase Jitter section. 01/04/07 C T5A - T5E 4 - 6 AC Characteristics Tables - changed part-to-part skew specs. 03/07/08 Updated data sheet format. 3/20/15 CT 8 General Description - Removed HiPerClockS. Ordering Information - removed LF note below the table. Updated header and footer. 12/15/15

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or speciﬁ cations described herein at any time, without notice, at IDT's sole discretion. Performance speciﬁ cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signiﬁ cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type deﬁ nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2015 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

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Product Information

83054AGILFT specifications and overview.

Summary

4:1, Single-Ended Multiplexer

Description

4:1, Single-Ended Multiplexer

Source title 83054AGILFT Datasheet(PDF) - Integrated Device Technology

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