83054AGI-01LF

83054I-01 RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
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4-Bit, 2:1, Single-Ended Multiplexer 83054I-01 Datasheet ©2015 Integrated Device Technology, Inc December 15, 20151 GENERAL DESCRIPTION The 83054I-01 is a 4-bit, 2:1, Single-ended Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83054I-01 has two selectable single-ended clock inputs and four single-ended clock outputs. The output has a V DDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. Possible applications include systems with up to four transceivers which need to be independently set for different rates. For example, a board may have four transceivers, each of which need to be independently confi gured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates. Another possible application may require the ports to be independently set for FEC (Forward Error Correction) or non-FEC rates. The device operates up to 250MHz and is packaged in a 16 TSSOP . BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

• Four-bit, 2:1 single-ended multiplexer
• Nominal output impedance: 15Ω (V DDO = 3.3V)
• Maximum output frequency: 250MHz
• Propagation delay: 3.2ns (maximum), V DD = V DDO = 3.3V
• Input skew: 170ps (maximum), V DD = V DDO = 3.3V
• Output skew: 90ps (maximum), V DD = V DDO = 3.3V
• Part-to-part skew: 800ps (maximum), V DD = V DDO = 3.3V
• Additive phase jitter, RMS at 155.52MHz, (12kHz – 20MHz): 0.18ps (typical)
• Operating supply modes: V DD DDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package SEL0 CLK0 CLK1 SEL3 OE Pulldown Pulldown Pulldown Pulldown Pullup SEL3 VDDO GND SEL2 CLK1 VDD SEL0 V DDO GND SEL1 CLK0 OE 83054I-01 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS SEL1, SEL0 Input Pulldown Clock select inputs. See Control Input Function Table. LVCMOS / LVTTL interface levels. 2, 5, 12, 15 Q3, Q2, Q1, Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 4, 13 GND Power Power supply ground. 7, 10 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 9 OE Input Pullup Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 3. CONTROL INPUT FUNCTION TABLE

0 CLK0

1 CLK1

©2015 Integrated Device Technology, Inc December 15, 20153 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θ JA 100.3°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO = 3.3V±5%, OR 2.5V±5%, OR 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.6 1.8 2.0 V I DD Power Supply Current 45 mA I DDO Output Supply Current No Load 5 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V DD = 2.5V±5%, V DDO = 2.5V±5%, OR 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Power Supply Voltage 2.375 2.5 2.625 V V DDO Output Supply Voltage 2.375 2.5 2.625 V 1.6 1.8 2.0 V I DD Power Supply Current 40 mA I DDO Output Supply Current No Load 5 mA

©2015 Integrated Device Technology, Inc December 15, 20154 TABLE 5A. AC CHARACTERISTICS, V DD = V DDO TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage V DD = 3.3V ± 5% 2 V DD + 0.3 V V DD = 2.5V ± 5% 1.7 V DD + 0.3 V V IL Input Low Voltage V DD V DD I IH Input High Current CLK0, CLK1, SEL0:SEL3 V DD = 3.3V or 2.5V ± 5% 150 µA OE V DD = 3.3V or 2.5V ± 5% 5 µA I IL Input Low Current CLK0, CLK1, SEL0:SEL3 V DD = 3.3V or 2.5V ± 5% -5 µA OE V DD = 3.3V or 2.5V ± 5% -150 µA V OH Output HighVoltage; NOTE 1 V DDO = 3.3V ± 5% 2.6 V V DDO = 2.5V ± 5% 1.8 V V DDO = 1.8V ± 0.2V V DD - 0.3 V V OL Output Low Voltage; NOTE 1 V DDO = 3.3V ± 5% 0.5 V V DDO = 2.5V ± 5% 0.45 V V DDO = 1.8V ± 0.2V 0.35 V NOTE 1: Outputs terminated with 50Ω to V DDO /2. See Parameter Measurement section, “Load Test Circuit” diagrams. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 1.8 2.5 3.2 ns tp HL Propagation Delay, High to Low; NOTE 1 2.0 2.6 3.2 ns tsk(o) Output Skew; NOTE 2, 3 30 90 ps tsk(i) Input Skew; NOTE 2 40 170 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 155.52, Integration Range: 12kHz – 20MHz 0.18 ps t R / t F Output Rise/Fall Time 20% to 80% 300 800 ps odc Output Duty Cycle ƒout ≤ 175MHz 40 60 % MUX ISOL MUX Isolation @100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V DDO /2. NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 5: Driving only one input clock.

©2015 Integrated Device Technology, Inc December 15, 20155 TABLE 5B. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO TABLE 5C. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.1 2.6 3.1 ns tp HL Propagation Delay, High to Low; NOTE 1 2.3 2.7 3.1 ns tsk(o) Output Skew; NOTE 2, 3 40 125 ps tsk(i) Input Skew; NOTE 2 35 190 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 155.52, Integration Range: 12kHz – 20MHz 0.14 ps t R / t F Output Rise/Fall Time 20% to 80% 300 800 ps odc Output Duty Cycle 40 60 % MUX ISOL MUX Isolation @100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V DDO /2. NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 5: Driving only one input clock. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.6 3.1 3.6 ns tp HL Propagation Delay, High to Low; NOTE 1 2.7 3.2 3.7 ns tsk(o) Output Skew; NOTE 2, 3 40 125 ps tsk(i) Input Skew; NOTE 2 35 195 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 155.52, Integration Range: 12kHz – 20MHz 0.16 ps t R / t F Output Rise/Fall Time 20% to 80% 450 850 ps odc Output Duty Cycle 40 60 % MUX ISOL MUX Isolation @100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V DDO /2. NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 5: Driving only one input clock.

©2015 Integrated Device Technology, Inc December 15, 20156 TABLE 5D. AC CHARACTERISTICS, V DD = V DDO TABLE 5E. AC CHARACTERISTICS, V DD = 2.5V ± 5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 1.5 3.0 4.5 ns tp HL Propagation Delay, High to Low; NOTE 1 2.2 2.8 3.4 ns tsk(o) Output Skew; NOTE 2, 3 30 90 ps tsk(i) Input Skew; NOTE 2 45 190 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 155.52, Integration Range: 12kHz – 20MHz 0.22 ps t R / t F Output Rise/Fall Time 20% to 80% 300 700 ps odc Output Duty Cycle ƒout ≤175MHz 40 60 % MUX ISOL MUX Isolation @100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V DDO /2. NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 5: Driving only one input clock. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.2 3.2 4.2 ns tp HL Propagation Delay, High to Low; NOTE 1 2.5 3.2 4.0 ns tsk(o) Output Skew; NOTE 2, 3 40 125 ps tsk(i) Input Skew; NOTE 2 30 145 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 155.52, Integration Range: 12kHz – 20MHz 0.19 ps t R / t F Output Rise/Fall Time 20% to 80% 450 850 ps odc Output Duty Cycle ƒout ≤ 200MHz 40 60 % MUX ISOL MUX Isolation @100MHz 45 dB NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs at the same voltage and with equal load conditions. Measured at V DDO /2. NOTE 4: Defi ned as skew between outputs on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 5: Driving only one input clock.

©2015 Integrated Device Technology, Inc December 15, 20157 ADDITIVE PHASE JITTER Additive Phase Jitter (Random) at 155.52MHz (12kHz - 20MHz) = 0.18ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M The spectral purity in a band at a specifi c offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels As with most timing specifi cations, phase noise measurements has issues relating to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor of the device. (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. This is illustrated above. The device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

©2015 Integrated Device Technology, Inc December 15, 20158 PARAMETER MEASUREMENT INFORMATION 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW

©2015 Integrated Device Technology, Inc December 15, 20159 OUTPUT SKEW OUTPUT RISE/FALL TIMEPROPAGATION DELAY INPUT SKEWOUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

©2015 Integrated Device Technology, Inc December 15, 201510 RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for 83054I-01 is: 967 TABLE 5. θ resistor can be tied from the CLK input to ground. resistance is not required but can be added for additional protection.

APPLICATION INFORMATION

TABLE 6. PACKAGE DIMENSIONS

TABLE 7. ORDERING INFORMATION

©2015 Integrated Device Technology, Inc December 15, 201513 REVISION HISTORY SHEET Rev Table Page Description of Change Date A T7 General Description - removed ICS chip and HiPerClocks. Features Section - removed reference to leaded package. Ordering Information - removed leaded parts and the LF note below the table. Updated header and footer. 12-15-15

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