83052I-01 Final Data Sheet

Document overview

  • Manufacturer or author: Integrated Device Technology
  • PDF pages: 15

Technical content

Features

  • 2-bit, 2:1 single-ended multiplexer
  • Nominal output impedance: 15 (VDDO = 3.3V)
  • Maximum output frequency: 250MHz
  • Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V
  • Input skew: 85ps (maximum), VDD = VDDO = 3.3V
  • Part-to-part skew: 500ps (maximum), VDD = VDDO = 3.3V
  • Output skew: 65ps (maximum), VDD = VDDO = 3.3V
  • Additive phase jitter, RMS (12KHz - 20MHz): 0.15ps (typical)
  • Operating supply modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package 83052I-01 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package 9VDD CLK1 SEL1 GND nc VDDO nc nc VDDO nc GND SEL0 CLK0 OE Pin Assignment SEL0 CLK0 CLK1 SEL1 OE Pulldown Pulldown Pulldown Pulldown Pullup Block Diagram 83052I-01 Datasheet 2-Bit, 2:1, Single-Ended Multiplexer

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Control Input Function Table 1, 3, 14, 16 nc Unused No connect. 2, 15 V DDO Power Output supply pins. 5, 12 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 6, 11 SEL1, SEL0 Input Pulldown Clock select inputs. See Table 3, Control Input Function Table. LVCMOS / LVTTL interface levels. 7, 10 CLK1, CLK0 Input Pulldown Single-ended clo ck input. LVCMOS/LVTTL interface levels. HIGH, outputs are active. LVCMOS / LVTTL interface levels.

3©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO+ 0.5V Package Thermal Impedance, JA 100.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.6 1.8 2.0 V IDD Power Supply Current 40 mA IDDO Output Supply Current No Load 5 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V 1.6 1.8 2.0 V IDD Power Supply Current 40 mA IDDO Output Supply Current No Load 5 mA

4©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet Table 4C. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.465V 2 V DD + 0.3 V VDD = 2.625V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.465V -0.3 1.3 V VDD = 2.625V -0.3 0.7 V IIH Input High Current CLK0, CLK1, SEL0, SEL1 VDD = VIN = 3.465V or 2.625V 150 µA OE VDD = VIN = 3.465V or 2.625V 5µ A IIL Input Low Current CLK0, CLK1, SEL0, SEL1 VDD = 3.465V or 2.625V, VIN = 0V -5 µA OE VDD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VDDO = 3.3V ± 5% 2.6 V VDDO = 2.5V ± 5% 1.8 V VDDO = 1.8V ± 0.2V V DDO - 0.3 V VOL Output Low Voltage; NOTE 1 VDDO = 3.3V ± 5% 0.5 V VDDO = 2.5V ± 5% 0.45 V VDDO = 1.8V ± 0.2V -5 0.35 V

5©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA =-40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same input on each device, the output is measured at VDDO/2. NOTE 5: Driving only one input clock. Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA =-40°C to 85°C NOTE: See Notes above. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.0 2.45 3.0 ns tpHL Propagation Delay, High to Low; NOTE 1 2.0 2.45 3.0 ns tsk(i) Input Skew; NOTE 2 20 85 ps tsk(o) Output Skew; NOTE 2, 3 15 65 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 500 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Integration Range: 12kHz - 20MHz 0.15 ps tR / tF Output Rise/Fall Time 20% to 80% 200 600 ps odc Output Duty Cycle 40 60 % MUX ISOL MUX Isolation Unselected CLK input @100MHz 45 dB Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.2 2.55 3.0 ns tpHL Propagation Delay, High to Low; NOTE 1 2.2 2.55 3.0 ns tsk(i) Input Skew; NOTE 2 10 50 ps tsk(o) Output Skew; NOTE 2, 3 20 70 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 500 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Integration Range: 12kHz - 20MHz 0.12 ps tR / tF Output Rise/Fall Time 20% to 80% 200 600 ps odc Output Duty Cycle 40 60 % MUX ISOL MUX Isolation Unselected CLK input @100MHz 45 dB

6©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet Table 5C. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA =-40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Measured from the V DD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same input on each device, the output is measured at VDDO/2. NOTE 5: Driving only one input clock. Table 5D. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA =-40°C to 85°C NOTE: See Notes above. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.2 3.1 4.0 ns tpHL Propagation Delay, High to Low; NOTE 1 2.2 3.1 4.0 ns tsk(i) Input Skew; NOTE 2 15 60 ps tsk(o) Output Skew; NOTE 2, 3 30 100 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 500 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Integration Range: 12kHz - 20MHz 0.14 ps tR / tF Output Rise/Fall Time 20% to 80% 150 1000 ps odc Output Duty Cycle f OUT < 200MHz 40 60 % MUXISOL MUX Isolation Unselected CLK input @100MHz 45 dB Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.0 2.7 3.4 ns tpHL Propagation Delay, High to Low; NOTE 1 2.0 2.7 3.4 ns tsk(i) Input Skew; NOTE 2 15 55 ps tsk(o) Output Skew; NOTE 2, 3 20 75 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 500 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Integration Range: 12kHz - 20MHz 0.19 ps t R / tF Output Rise/Fall Time 20% to 80% 200 600 ps odc Output Duty Cycle 40 60 % MUX ISOL MUX Isolation Unselected CLK input @100MHz 45 dB

7©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet Table 5E. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA =-40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Measured from the V DD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same input on each device, the output is measured at VDDO/2. NOTE 5: Driving only one input clock. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.0 3.1 4.2 ns tpHL Propagation Delay, High to Low; NOTE 1 2.0 3.1 4.2 ns tsk(i) Input Skew; NOTE 2 30 135 ps tsk(o) Output Skew; NOTE 2, 3 30 95 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 500 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Integration Range: 12kHz - 20MHz 0.17 ps tR / tF Output Rise/Fall Time 20% to 80% 150 1000 ps odc Output Duty Cycle 40 60 % MUX ISOL MUX Isolation Unselected CLK input @100MHz 45 dB

8©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.15ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)

9©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 3.3V Core/ 1.8V LVCMOS Output Load AC Test Circuit 2.5V Core/ 1.8V LVCMOS Output Load AC Test Circuit 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 2.5V Core/ 2.5V LVCMOS Output Load AC Test Circuit Propagation Delay SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO SCOPE Qx GND 2.4V±0.65V -0.9V±0.1V 0.9V±0.1V VDDO VDD SCOPE Qx GND VDDO VDD 1.6V±0.025V 0.9V±0.1V -0.9V±0.1V SCOPE Qx GND VDDO VDD 1.25V±5% -1.25V±5% 2.05V±5% SCOPE Qx GND 1.25V±5% -1.25V±5% VDD, VDDO tpLH tpHL VDDO VDD VDDO VDD Q0, Q1 CLK0, CLK1

10©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet Parameter Measurement Information, continued Part-to-Part Skew Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time Output Skew MUX Isolation Input Skew tsk(pp) VDDO VDDO Part 1 Part 2 Qx Qy tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0, Q1 20% 80% 80% 20% tR tF Q0, Q1 tsk(o) VDDO VDDO Qx Qy CLKx (static) CLKy SELy Qx, Qy Spectrum MUX_ISOL CLKx CLKy tPD1 tsk(i) = ⏐tPD2 – tPD1⏐ tPD2 Q0, Q1 Q0, Q1 CLKy CLKx

11©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet

Application Information

Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k  resistor can be used. CLK Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k  resistor can be tied from the CLK input to ground. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. Reliability Information Table 6. JA vs. Air Flow Table for a 16 Lead TSSOP NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.

Table 7. Package Dimensions for 16 Lead TSSOP

13©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet

Ordering Information

Table 8. Ordering Information

14©2015 Integrated Device Technology, Inc December 16, 2015 83052I-01 Datasheet Revision History Sheet Rev Table Page Description of Change Date A T3 2 Corrected Control Input Function Table. 7/25/08 A T8 13 Removed leaded orderable parts from Ordering Information table 11/14/12 A Features Section - removed reference to leaded packages. General Description - removed ICS Chip and HiPerClockS. Remove prefix of ICS on the part number. Removed LF note below the table. Updated header and footer. 12/16/15

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