83052AGILFT

83052I RENESAS | Alldatasheet

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2:1, Single-Ended Multiplexer 83052I Data Sheet ©2015 Integrated Device Technology, Inc December 15, 20151 GENERAL DESCRIPTION The 83052I is a low skew, 2:1, Single-ended Multiplexer. The 83052I has two selectable single-ended clock inputs and one single-ended clock output. The output has a V DDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage trans-lation applications. An output enable pin places the output in a high im- pedance state which may be useful for testing or debug. The device operates up to 250MHz and is packaged in an 8 TSSOP . BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

 2:1 single-ended multiplexer  Q nominal output impedance: 15Ω (V DDO = 3.3V)  Maximum output frequency: 250MHz  Propagation delay: 2.7ns (maximum), (V DD = V DDO = 3.3V)  Input skew: 160ps (maximum), (V DD = V DDO = 3.3V)  Part-to-part skew: 490ps (maximum), (V DD = V DDO = 3.3V)

• Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz): 0.18ps (typical), (V DD = V DDO = 3.3V)  Operating supply modes: V DD DDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V  -40°C to 85°C ambient operating temperature  Available in lead-free (RoHS 6) package CLK0 CLK1 SEL0 OE Q 83052I 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VDDO GND CLK1 VDD Q SEL0 CLK0 OE

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. CONTROL INPUT FUNCTION TABLE 2 GND Power Power supply ground. 3, 6 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 5 OE Input Pullup Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. 7 SEL0 Input Pulldown Clock select input. See Table 3. Control Input Function Table. LVCMOS / LVTTL interface levels. 8 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

0 CLK0

1 CLK1

©2015 Integrated Device Technology, Inc December 15, 20153 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θ JA 101.7°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD = 3.3V±5%, V DDO TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V DD = 2.5V±5%, V DDO = 2.5V±5% OR 1.8V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.71 1.8 1.89 V I DD Power Supply Current 40 mA I DDO Output Supply Current 5m A Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 2.375 2.5 2.625 V V DDO Output Supply Voltage 2.375 2.5 2.625 V 1.71 1.8 1.89 V I DD Power Supply Current 36 mA I DDO Output Supply Current 5m A

©2015 Integrated Device Technology, Inc December 15, 20154 TABLE 5A. AC CHARACTERISTICS, V DD = V DDO TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage V DD = 3.3V ± 5% 2 V DD + 0.3 V V DD = 2.5V ± 5% 1.7 V DD + 0.3 V V IL Input Low Voltage V DD V DD I IH Input High Current CLK0, CLK1, SEL0 V DD = 3.3V or 2.5V ± 5% 150 µA OE V DD = 3.3V or 2.5V ± 5% 5 µA I IL Input Low Current CLK0, CLK1, SEL0 V DD = 3.3V or 2.5V ± 5% -5 µA OE V DD = 3.3V or 2.5V ± 5% -150 µA V OH Output HighVoltage V DDO = 3.3V ± 5%; NOTE 1 2.6 V V DDO = 2.5V ± 5%; NOTE 1 1.8 V V DDO = 1.8V ± 5%; NOTE 1 V DD - 0.3 V V OL Output Low Voltage V DDO = 3.3V ± 5%; NOTE 1 0.5 V V DDO = 2.5V ± 5%; NOTE 1 0.45 V V DDO = 1.8V ± 5%; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50Ω to V DDO /2. See Parameter Measurement section, “Load Test Circuit” diagrams. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.0 2.4 2.7 ns tp HL Propagation Delay, High to Low; NOTE 1 2.0 2.5 2.9 ns tsk(i) Input Skew; NOTE 4 36 160 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 490 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 155.52MHz, Integration Range: 12kHz - 20MHz 0.18 ps t R / t F Output Rise/Fall Time 20% to 80% 200 700 ps odc Output Duty Cycle 45 55 % MUX ISOLATION MUX Isolation 45 dB NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

©2015 Integrated Device Technology, Inc December 15, 20155 TABLE 5B. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO TABLE 5C. AC CHARACTERISTICS, V DD = 3.3V ± 5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.3 3.1 3.9 ns tp HL Propagation Delay, High to Low; NOTE 1 2.3 3.1 3.9 ns tsk(i) Input Skew; NOTE 4 19 66 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 350 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 155.52MHz, Integration Range: 12kHz - 20MHz 0.16 ps t R / t F Output Rise/Fall Time 20% to 80% 350 850 ps odc Output Duty Cycle 46 54 % MUX ISOLATION MUX Isolation 45 dB NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.3 2.6 2.9 ns tp HL Propagation Delay, High to Low; NOTE 1 2.3 2.6 2.9 ns tsk(i) Input Skew; NOTE 4 23 106 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 350 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 155.52MHz, Integration Range: 12kHz - 20MHz 0.14 ps t R / t F Output Rise/Fall Time 20% to 80% 300 700 ps odc Output Duty Cycle 46 54 % MUX ISOLATION MUX Isolation 45 dB NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

©2015 Integrated Device Technology, Inc December 15, 20156 TABLE 5D. AC CHARACTERISTICS, V DD = V DDO TABLE 5E. AC CHARACTERISTICS, V DD = 2.5V ± 5%, V DDO Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.2 2.7 3.2 ns tp HL Propagation Delay, High to Low; NOTE 1 2.2 2.7 3.2 ns tsk(i) Input Skew; NOTE 4 28 123 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 400 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 155.52MHz, Integration Range: 12kHz - 20MHz 0.22 ps t R / t F Output Rise/Fall Time 20% to 80% 300 700 ps odc Output Duty Cycle 45 55 % MUX ISOLATION MUX Isolation 45 dB NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz tp LH Propagation Delay, Low to High; NOTE 1 2.1 3.1 4.1 ns tp HL Propagation Delay, High to Low; NOTE 1 2.1 3.1 4.2 ns tsk(i) Input Skew; NOTE 4 19 73 ps tsk(pp) Part-to-Part Skew; NOTE 2, 4 350 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 155.52MHz, Integration Range: 12kHz - 20MHz 0.19 ps t R / t F Output Rise/Fall Time 20% to 80% 350 850 ps odc Output Duty Cycle 45 55 % MUX ISOLATION MUX Isolation 45 dB NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from V DD /2 of the input to V DDO /2 of the output. NOTE 2: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDO /2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

©2015 Integrated Device Technology, Inc December 15, 20157 ADDITIVE PHASE JITTER Additive Phase Jitter (Random) at 155.52MHz (12kHz - 20MHz) = 0.18ps (typical) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 The spectral purity in a band at a specifi c offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels As with most timing specifi cations, phase noise measurements has issues relating to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor of the device. (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. This is illustrated above. The device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ 1k 10k 100k 1M 10M 100M

©2015 Integrated Device Technology, Inc December 15, 20158 PARAMETER MEASUREMENT INFORMATION 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW

©2015 Integrated Device Technology, Inc December 15, 20159 INPUT SKEW OUTPUT RISE/FALL TIMEPROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

©2015 Integrated Device Technology, Inc December 15, 201510 INPUTS: CLK INPUT: For applications not requiring the use of the test clock, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. C ONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT PINS APPLICATIONS INFORMATION

©2015 Integrated Device Technology, Inc December 15, 201511 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS830521I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS830521I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation

• Power (core) MAX = V DD_MAX * (I DD + I DDo ) = 3.4565V * (40mA + 5mA) = 155.93mW
• Output Impedance R OUT Power Dissipation due to Loading 50Ω to V DD Output Current I OUT = V DDO_MAX / [2 * (50Ω + R OUT
• Power Dissipation on the R OUT per LVCMOS output Power (R OUT ) = R OUT * (I OUT = 15Ω * (26.7mA) = 10.7mW Dynamic Power Dissipation at 250MHz
• Power (250MHz) = C PD * frequency * (V DD = 18pF * 250MHz * (3.465V) = 54.0mW Total Power Dissipation
• Total Power = Power (core) MAX + Power (R OUT ) Total Power + Power (250MHz) = 155.93mW + 10.7mW + 54.0mW = 220.6mW

ensures that the bond wire and bond pad temperature remains below 125°C. no air fl ow and a multi-layer board, the appropriate value is 101.7°C/W per Table 6. and the type of board (multi-layer). TABLE 6. θ

©2015 Integrated Device Technology, Inc December 15, 201513 RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for 83052I is: 967

TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION

©2015 Integrated Device Technology, Inc December 15, 201516 REVISION HISTORY SHEET Rev Table Page Description of Change Date B 4A, 4B Power Supply Tables - corrected V DDO min/max. Ordering Information Table - added lead-free marking. 8/7/06 B T4B 3 2.5V Power Supply Table - corrected units for I DD & I DDO . 6/25/08 B T5A, 5B, 5C, 5D, 5E, All, 4, 5, 6 11, 12 Updated Header and Footer. Added Note to Tables.Updated Contact Information. Added Power Considerations section. Updated Contact Information. 12/8/11 B T8 Features Section - removed reference to leaded package. Removed prefi x ICS in part number. Ordering Information - Removed leaded parts and the LF note below the table. Updated Header and Footer. 12/15/15

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