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82V3399 REVISION 9 01/05/16 9 ©2016 Integrated Device Technology, Inc. Synchronization Management WAN PLL and Clock Generatiion for IEEE-1588 82V3399 This short form datasheet is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on the last page.

FEATURES

  • Single chip PLL:
  • Features 0.5 mHz to 560 Hz bandwidth
  • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE)
  • Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64) jitter generation requirements
  • Provides node clocks for Cellul ar and WLL base-station (GSM and 3G networks)
  • Provides clocks for DSL access concentrators (DSLAM), espe- cially for Japan TCM-ISDN netwo rk timing based ADSL equip- ments
  • Provides clocks for 1 Gigabi t and 10 Gigabit Ethernet applica- tions
  • It supports clock generation for IEEE-1588 application MAIN FEATURES
  • Provides an integrated single-chip solution for Synchronous Equip- ment Timing Source, including Stratum 3, 4E, 4, SMC, EEC-Option 1 and EEC-Option 2 Clocks
  • Provides SONET clocks with less than 1 ps of RMS Phase Jitter (12 kHz - 20 MHz)
  • Supports 1PPS input and output
  • Employs PLL architecture to feature excellent jitter performance and minimize the number of the external components
  • Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or locks to T0 DPLL
  • Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19 steps) and damping factor (1.2 to 20 in 5 steps)
  • Supports 1.1X10 -5 ppm absolute holdover accuracy and 4.4X10 -8 ppm instantaneous holdover accuracy
  • Supports hitless reference switch ing to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
  • Supports programmable input-to- output phase offset adjustment
  • Limits the phase and frequency offset of the outputs
  • Provides OUT1~OUT6 output cloc ks whose frequencies cover from 1 Hz (1PPS) to 644.53125 MHz
  • Includes 25 MHz, 125 MHz and 156.25 MHz for CMOS outputs
  • Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, for CMOS outputs
  • Includes 25 MHz,125 MHz, 156.25 MHz, 312.5 MHz and 625 MHz for differential outputs
  • Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, 322.265625 MHz and 644.53125 MHz for differential outputs
  • Provides IN1~IN6 input clocks whose frequencies cover from 1 Hz (1PPS) to 625 MHz
  • Includes 25 MHz, 125 MHz and 156.25 MHz for CMOS inputs
  • Includes 25 MHz, 156.25 MHz, 312.5 MHz and 625 MHz for dif- ferential inputs
  • Internal DCO can be controlled by an external processor to be used for IEEE-1588 clock generation
  • Supports Forced or Automatic oper ating mode switch controlled by an internal state machine. It supports Free- Run, Locked and Hold- over modes
  • Supports manual and automatic selected input clock switch
  • Supports automatic hitless selected input clock switch on clock fail- ure
  • Supports three types of input clo ck sources: recovered clock from STM-N or OC-n, PDH network sy nchronization timing and external synchronization reference timing
  • Provides a 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 2 kHz or 8 kHz frame sync output signal
  • Provides a 1PPS sync input signal and a 1PPS sync output signal
  • Provides output clocks for BITS, GPS, 3G, GSM, etc.
  • Supports PECL/LVDS and CMOS input/output technologies
  • Supports master clock calibration
  • Supports Master/Slave applicati on (two chips used together) to enable system protection against single chip failure
  • Supports Telcordia GR-1244-CO RE, Telcordia GR-253-CORE, mendations OTHER FEATURES
  • I2C and Serial microprocessor interface modes
  • IEEE 1149.1 JTAG Boundary Scan
  • Single 3.3 V operation with 5 V tolerant CMOS I/Os
  • 72-pin QFN package, green package options available

APPLICATIONS

  • 1 Gigabit Ethernet and 10 Gigabit Ethernet
  • BITS / SSU
  • SMC / SEC (SONET / SDH)
  • DWDM cross-connect and transmission equipment
  • Synchronous Ethernet equipment
  • Central Office Timing Source and Distribution
  • Core and access IP switches / routers
  • Gigabit and terabit IP switches / routers
  • IP and ATM core switches and access equipment
  • Cellular and WLL base-station node clocks
  • Broadband and multi-service access equipment

82V3399 SHORT FORM DATA SHEET SYNCHRONIZATION MANAGEMENT WAN PLL AND CLOCK GENERATIION FOR IEEE-1588

10 REVISION 9 01/05/16

DESCRIPTION

The 82V3399 is an integrated, single-chip solution for the Synchro- nous Equipment Timing Source for Stratum 3, 4E, 4, SMC, EEC- Option1, EEC-Option2 clocks in SO NET / SDH / Synchronous Ethernet equipment, DWDM and Wireless base station. The device supports several types of input clock sources: recovered clock from Synchronous Ethernet, ST M-N or OC-n, PDH network syn- chronization timing and external synchronization reference timing. The device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to prov ide system clock for node timing synchronization within a SONET / SDH / Synchronous Ethernet network. The T4 path is simpler and less configurable for equipment synchroniza- tion. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 path. Both the T0 and T4 paths s upport three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating condi- tions or silicon process variations. There are 2 high performance APLLs that can be used for low jitter SONET and Ethernet Clocks The device provides programma ble DPLL bandwidths: 0.5 mHz to 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A highly stable input is required for the master clock in different appli- cations. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a microprocessor interface. The device supports I2C and serial microprocessor interface modes. In general, the device can be used in Master/Slave application. In this application, two devices s hould be used together to enable system protection against single chip failure.

Figure 1. Functional Block Diagram

82V3399 SHORT FORM DATA SHEET SYNCHRONIZATION MANAGEMENT WAN PLL AND CLOCK GENERATIION FOR IEEE-1588

12 REVISION 9 01/05/16

ORDERING INFORMATION

Industrial (- 40 °C to + 85 °C) WAN PLL NLG Green Quad Flatpack, No Lead (VFQFP-N, NLG72)

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved. IDT CONFIDENTIAL Corporate Headquarters

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