82V3352T

IDT82V3352 IDT | Alldatasheet

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Technical content

March 23, 2009

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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any res ponsibility for use of any circuitry described other than the circuitry embodied in a n IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe- cuted between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems whic h (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Table of Contents 3 March 23, 2009 Table of Contents

Table of Contents 4 March 23, 2009 IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL

List of Tables 5 March 23, 2009 List of Tables

7 March 23, 2009

 2009 Integrated Device Technology, Inc. DSC-7212/3 SYNCHRONOUS ETHERNET WAN PLL IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

FEATURES

• The first single PLL chip:
• Features 0.1 Hz to 560 Hz bandwidth
• Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet
• Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements
• Provides node clocks for Cellul ar and WLL base-station (GSM and 3G networks)
• Provides clocks for DSL access concentrators (DSLAM), espe- cially for Japan TCM-ISDN netwo rk timing based ADSL equip- ments MAIN FEATURES
• Provides an integrated single-chip solution for Synchronous Equip- ment Timing Source, including Stratum 3, SMC, 4E and 4 clocks
• Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components
• Supports Forced or Automatic ope rating mode switch controlled by an internal state machine; the primary operating modes are Free- Run, Locked and Holdover
• Supports programmable DPLL bandwidth (0.1 Hz to 560 Hz in 11 steps) and damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10 -5 ppm absolute holdover accuracy and 4.4X10 -8 ppm instantaneous holdover accuracy
• Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
• Supports phase absorption w hen phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds
• Supports programmable input-to- output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock fail- ure
• Supports three types of input clo ck sources: recovered clock from STM-N or OC-n, PDH network sy nchronization timing and external synchronization reference timing
• Provides three 2 kHz, 4 kHz or 8 kHz frame sync input signals, and a 2 kHz and an 8 kHz frame sync output signals
• Provides 5 input clocks whos e frequency cover from 2 kHz to

622.08 MHz

• Provides 2 output clocks whos e frequency cover from 1 Hz to
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Supports PECL/LVDS and CMOS input/output technologies
• Supports master clock calibration
• Supports Line Card application
• Meets Telcordia GR-1244-CORE , GR-253-CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria OTHER FEATURES
• Serial microprocessor interface mode
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 64-pin TQFP package, Green package options available

APPLICATIONS

• BITS / SSU
• SMC / SEC (SONET / SDH)
• DWDM cross-connect and transmission equipments
• Synchronous Ethernet equipments
• Central Office Timing Source and Distribution
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• IP and ATM core switches and access equipments
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipments
• Any other telecom equipments that need synchronous equipment system timing

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Description 8 March 23, 2009

DESCRIPTION

The IDT82V3352 is an integrated, single-chip solution for the Syn- chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network appli- cations. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. The T0 path supports three pr imary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different set- tings cover all SONET / SDH clock synchronization requirements. A high stable input is required for t he master clock in different appli- cations. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a serial micropro- cessor interface. The device supports Serial microprocessor interface mode only. The device can be used typically in Chapter 3.17 Line Card Applica- tion.

Figure 1. Functional Block Diagram

77.76 MHz

Note: Configuration of OUTn (n = 1, 2) ETH MUX please refer to Table 25-27.

1 PIN ASSIGNMENT

Figure 2. Pin Assignment (Top View)

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Pin Description 11 March 23, 2009

2 PIN DESCRIPTION

Table 1: Pin Description Name Pin No. I/O Type Description 1 Global Control Signal OSCI 6 I CMOS OSCI: Crystal Oscillator Master Clock A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the master clock for the device. FF_SRCSW 13 I pull-down CMOS FF_SRCSW: External Fast Selection Enable During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH) 2. The EXT_SW bit determines whether the External Fast Selection is enabled. High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is enabled); Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is dis- abled). After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is enabled: High: Pair IN1_CMOS / IN1_DIFF is selected. Low: Pair IN2_CMOS / IN2_DIFF is selected. After reset, the input on this pin takes no effect if the External Fast selection is disabled. SONET/SDH 64 I pull-down CMOS SONET/SDH: SONET / SDH Frequency Selection During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H): High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET); Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH). After reset, the value on this pin takes no effect. RST 48 I pull-up CMOS RST: Reset A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will still be held in reset state for 500 ms (typical). Frame Synchronization Input Signal EX_SYNC1 28 I pull-down CMOS EX_SYNC1: External Sync Input 1 A 2 kHz, 4 kHz or 8 kHz signal is input on this pin. EX_SYNC2 33 I pull-down CMOS EX_SYNC2: External Sync Input 2 A 2 kHz, 4 kHz or 8 kHz signal is input on this pin. EX_SYNC3 35 I pull-down CMOS EX_SYNC3: External Sync Input 3 A 2 kHz, 4 kHz or 8 kHz signal is input on this pin. Input Clock IN1_CMOS 29 I pull-down CMOS IN1_CMOS: Input Clock 1 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, IN2_CMOS 30 I pull-down CMOS IN2_CMOS: Input Clock 2 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, IN1_POS IN1_NEG I PECL/LVDS IN1_POS / IN1_NEG: Positive / Negative Input Clock 1 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 622.08 MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is automatically detected. IN2_POS IN2_NEG I PECL/LVDS IN2_POS / IN2_NEG: Positive / Negative Input Clock 2 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 622.08 MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is automatically detected.

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Pin Description 12 March 23, 2009 IN3_CMOS 34 I pull-down CMOS IN3_CMOS: Input Clock 3 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, Output Frame Synchronization Signal FRSYNC_8K 17 O CMOS FRSYNC_8K: 8 kHz Frame Sync Output An 8 kHz signal is output on this pin. MFRSYNC_2K 18 O CMOS MFRSYNC_2K: 2 kHz Multiframe Sync Output A 2 kHz signal is output on this pin. Output Clock OUT1_POS OUT1_NEG O PECL/LVDS OUT1_POS / OUT1_NEG: Positive / Negative Output Clock 1 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, 5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 622.08 MHz clock is differentially output on this pair of pins. OUT2 56 O CMOS OUT2: Output Clock 2 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, 5 MHz, 10 MHz, 20 MHz, 25 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, this pin. Microprocessor Interface CS 44 I pull-up CMOS CS: Chip Selection A transition from high to low must occur on this pin for each read or write operation and this pin should remain low until the operation is over. INT_REQ 5 O CMOS INT_REQ: Interrupt Request This pin is used as an interrupt request. The output characteristics are determined by the HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH). SDI CLKE I pull-down CMOS SDI: Serial Data Input In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri- ally clocked into the device on the rising edge of SCLK. CLKE: SCLK Active Edge Selection In Serial mode, this pin selects the active edge of SCLK to update the SDO: High - The falling edge; Low - The rising edge. SDO 52 I/O pull-down CMOS SDO: Serial Data Output In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked out of the device on the active edge of SCLK. SCLK 47 I pull-down CMOS SCLK: Shift Clock In Serial mode, a shift clock is input on this pin. Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated on the active edge of SCLK. The active edge is determined by the CLKE. JTAG (per IEEE 1149.1) TRST 37 I pull-down CMOS TRST: JTAG Test Reset (Active Low) A low signal on this pin resets the JTAG test port. This pin should be connected to ground when JTAG is not used. TMS 41 I pull-up CMOS TMS: JTAG Test Mode Select The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. Table 1: Pin Description (Continued) Name Pin No. I/O Type Description 1

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Pin Description 13 March 23, 2009 TCK 49 I pull-down CMOS TCK: JTAG Test Clock The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is updated on the falling edge of TCK. If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state. TDI 51 I pull-up CMOS TDI: JTAG Test Data Input The test data is input on this pin. It is clocked into the device on the rising edge of TCK. TDO 50 O CMOS TDO: JTAG Test Data Output The test data is output on this pin. It is clocked out of the device on the falling edge of TCK. TDO pin outputs a high impedance signal except during the process of data scanning. This pin can indicate the interrupt of T0 selected input clock fail, as determined by the LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details. Power & Ground VDDD1 VDDD2 VDDD3 VDDD4 VDDD5 VDDD6 36, 38, 39, 45, 46 Power - VDDDn: 3.3 V Digital Power Supply Each VDDDn should be paralleled with ground through a 0.1 µF capacitor. VDDA1 VDDA2 VDDA3 Power - VDDAn: 3.3 V Analog Power Supply Each VDDAn should be paralleled with ground through a 0.1 µF capacitor. VDD_DIFF 22 Power - VDD_DIFF: 3.3 V Power Supply for OUT1 DGND1 DGND2 DGND3 DGND4 DGND5 DGND6 Ground - DGNDn: Digital Ground AGND1 AGND2 AGND3 Ground - AGNDn: Analog Ground GND_DIFF 21 Ground - GND_DIFF: Ground for OUT1 AGND 1 Ground - AGND: Analog Ground Table 1: Pin Description (Continued) Name Pin No. I/O Type Description 1

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Pin Description 14 March 23, 2009 Others IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC: Internal Connected Internal Use. These pins should be left open for normal operation. NC 27 - - NC: Not Connected Note: 1. All the unused input pins should be connected to ground; the output of all the unused output pins are don’t-care. 2. The contents in the brackets indicate the position of the register bit/bits. 3. N x 8 kHz: 1 < N < 19440. 6. N x 13.0 MHz: N = 1, 2, 4. 7. N x 3.84 MHz: N = 1, 2, 4, 8, 16, 10, 20, 40. Table 1: Pin Description (Continued) Name Pin No. I/O Type Description 1

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 15 March 23, 2009

3 FUNCTIONAL DESCRIPTION

3.1 RESET

The reset operation resets all regi sters and state machines to their default value or status. After power on, the device must be reset for normal operation. For a complete reset, the RST pin must be asserted low for at least 50 µs. After the RST pin is pulled high, the device will still be in reset state for 500 ms (typical). If the RST pin is held low continuously, the device remains in reset state.

3.2 MASTER CLOCK

A nominal 12.8000 MHz clock, provi ded by a crystal oscillator, is input on the OSCI pin. This clock is provided for the device as a master clock. The master clock is used as a reference clock for all the internal circuits. A better active edge of the master clock is selected by the OSC_EDGE bit to improve jitter and wander performance. In fact, an offset from the nominal frequency may input on the OSCI pin. This offset can be compensated by setting the NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within ±741 ppm. The performance of the master clock should meet GR-1244-CORE, GR-253-CORE, ITU-T G.812 and G.813 criteria. Table 2: Related Bit / Register in Chapter 3.2 Bit Register Address (Hex) NOMINAL_FREQ_VALUE[23:0] NOMINAL_FREQ [23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG 06, 05, 04 OSC_EDGE DIFFERENTIAL_IN_OUT_OSCI_CNFG 0A

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 16 March 23, 2009

3.3 INPUT CLOCKS & FRAME SYNC SIGNALS

Altogether 5 clocks and 3 frame sync signals are input to the device.

3.3.1 INPUT CLOCKS

The device provides 5 input clock ports. According to the input port technology, the input ports support the fol- lowing technologies:

• PECL/LVDS
• CMOS According to the input clock source , the following clock sources are supported:
• T1: Recovered clock from STM-N or OC-n
• T2: PDH network synchronization timing
• T3: External synchronization reference timing IN1_CMOS ~ IN3_CMOS support CM OS input signal only and the clock sources can be from T1, T2 or T3. IN1_DIFF and IN2_DIFF support PE CL/LVDS input signal only and automatically detect whether the si gnal is PECL or LVDS. The clock sources can be from T1, T2 or T3. For SDH and SONET networks, the default frequency is different. SONET / SDH frequency selection is controlled by the IN_SONET_SDH bit. During reset, the default value of the IN_SONET_SDH bit is deter- mined by the SONET/ SDH pin: high for SONET and low for SDH. After reset, the input signal on the SONET/SDH pin takes no effect.

3.3.2 FRAME SYNC INPUT SIGNALS

Three 2 kHz, 4 kHz or 8 kHz fr ame sync signals are input on the EX_SYNC1 to EX_SYNC3 pins respec tively. They are CMOS inputs. The input frequency should match the setting in the SYNC_FREQ[1:0] bits. Only one of the three frame sync input signals is used for frame sync output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC Output Signals for details. Table 3: Related Bit / Register in Chapter 3.3 Bit Register Address (Hex) IN_SONET_SDH INPUT_MODE_CNFG 09SYNC_FREQ[1:0]

3.4 INPUT CLOCK PRE-DIVIDER

DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits. inverted, as determined by the IN_2K_4K_8K_INV bit. Divider, as shown in Figure 3.

1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
3. Write the higher eight bits of the division factor to the
4. Use the HF Divider to divide the clock down to 155.52 MHz:
5. Use the DivN Divider to divide the clock down to 6.48 MHz:

PRE_DIVN_VALUE[14:0] bits to ‘10111’. Figure 3. Pre-Divider for An Input Clock

3.5 INPUT CLOCK QUALITY MONITORING

• Activity
• Frequency The qualified clocks are available for T0 DPLL selection. The T0 selected input clocks have to be monitored further. Refer to Chapter 3.7 Selected Input Clock Monitoring for details.

3.5.1 ACTIVITY MONITORING

Each input clock is assigned an in ternal leaky bucket accumulator. respect to the master clock within a 128 ms period. There are four configurations (0 - 3) for a leaky bucket accumulator. INn_DIFF_NO_ACTIVITY_ALARM bit (n = 1 or 2). Figure 4. Input Clock Activity Monitoring

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 19 March 23, 2009

3.5.2 FREQUENCY MONITORING

Frequency is monitored by compari ng the input clock with a refer- ence clock. The reference clock can be derived from the master clock or the output of T0 DPLL, as determined by the FREQ_MON_CLK bit. A frequency hard alarm threshold is set for frequency monitoring. If the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised when the frequency of the input clock with respect to the reference clock is above the threshold; the alarm is cleared when the frequency is below the threshold. The frequency hard alarm threshold can be calculated as follows: Frequency Hard Alarm Thres hold (ppm) = (ALL_FREQ_HARD_ THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0] If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm status of the input clock is indicated by the INn_CMOS_FREQ_HARD_ALARM bit (n = 1, 2 or 3) / INn_DIFF_FREQ_HARD_ALARM bit (n = 1 or 2). When the FREQ_MON_HARD_EN bit is ‘0’, no frequency hard alarm is raised even if the input clock is above the frequency hard alarm threshold. The input clock with a frequency hard alarm is disqualified for clock selection for T0 DPLL. In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges with respect to the reference clock are monitored. If any edge drifts out- side ±5%, the input clock is disqualif ied for clock selection for T0 DPLL. The input clock is qualified if any edge drifts inside ±5%. This function is supported only when the IN_NOISE_WINDOW bit is ‘1’. The frequency of each input clock with respect to the reference clock can be read by doing the following step by step: 1. Select an input clock by setting the IN_FREQ_READ_CH[3:0] bits; 2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate as follows: Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X FREQ_MON_FACTOR[3:0] Note that the value set by the FREQ_MON_FACTOR[3:0] bits depends on the application. Table 5: Related Bit / Register in Chapter 3.5 Bit Register Address (Hex) BUCKET_SIZE_n_DATA[7:0] (3 ≥ n ≥ 0) BUCKET_SIZE_0_CNFG ~ BUCKET_SIZE_3_CNFG 33, 37, 3B, 3F UPPER_THRESHOLD_n_DATA[7:0] (3 ≥ n ≥ 0) UPPER_THRESHOLD_0_CNFG ~ UPPE R_THRESHOLD_3_CNFG 31, 35, 39, 3D LOWER_THRESHOLD_n_DATA[7:0] (3 ≥ n ≥ 0) LOWER_THRESHOLD_0_CNFG ~ LOWER_THRESHOLD_3_CNFG 32, 36, 3A, 3E DECAY_RATE_n_DATA[1:0] (3 ≥ n ≥ 0) DECAY_RATE_0_CNFG ~ DECAY_RATE_3_CNFG 34, 38, 3C, 40 BUCKET_SEL[1:0] IN1_CMOS_CNFG, IN2_CMOS_CNFG, IN1_DIFF_CNFG, IN2_DIFF_CNFG, IN3_CMOS_CNFG 16, 17, 19, 1A, 1D INn_CMOS_NO_ACTIVITY_ALARM (n = 1, 2, or 3) IN1_IN2_CMOS_STS, IN3_CMOS_STS 44, 47INn_CMOS_FREQ_HARD_ALARM (n = 1, 2 or 3) INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2) IN1_IN2_DIFF_STS 45INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2) FREQ_MON_CLK MON_SW_PBO_CNFG 0BFREQ_MON_HARD_EN ALL_FREQ_HARD_THRESHOLD[3:0] ALL_FREQ_MON_THRESHOLD_CNFG 2F FREQ_MON_FACTOR[3:0] FREQ_MON_FACTOR_CNFG 2E IN_NOISE_WINDOW PH ASE_MON_PBO_CNFG 78 IN_FREQ_READ_CH[3:0] IN_FREQ_READ_CH_CNFG 41 IN_FREQ_VALUE[7:0] IN_FREQ_READ_STS 42

3.6 DPLL INPUT CLOCK SELECTION

Forced selection is done by setting the related registers. ity monitoring and the related registers configuration. The selected input clock is attempted to be locked in T0 DPLL.

3.6.1 EXTERNAL FAST SELECTION

toring) do not affect input clock selection. Figure 5. External Fast Selection

0000 Automatic selection

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 21 March 23, 2009

3.6.2 FORCED SELECTION

In Forced selection, the selected input clock is set by the T0_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring ) do not affect the input clock selection.

3.6.3 AUTOMATIC SELECTION

In Automatic selection, the input clock selection is determined by its validity and priority. The validity depends on the results of input clock quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring ). In all the qualified input clocks, the one with the highest priority is selected. The priority is c onfigured by the corresponding INn_CMOS_SEL_PRIORITY[3:0] bits (n = 1, 2 or 3) / the INn_DIFF_SEL_PRIORITY[3:0] bits (n = 1 or 2). If more than one quali- fied input clock is avai lable and has the same priority, the input clock with the smallest ‘n’ is selected. See Table 8 for the ‘n’ assigned to the input clock. Table 8: ‘n’ Assigned to the Input Clock Input Clock ‘n’ Assigned to the Input Clock IN1_CMOS 1 IN1_DIFF 2 IN2_CMOS 3 IN2_DIFF 4 IN3_CMOS 5 Table 9: Related Bit / Register in Chapter 3.6 Bit Register Address (Hex) EXT_SW MON_SW_PBO_CNFG 0B T0_INPUT_SEL[3:0] T0_INPUT_SEL_CNFG 50 INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3) IN1_IN2_CMOS_SEL_PRIORITY_CNFG, IN3_CMOS_SEL_PRIORITY_CNFG 27 *, 2A * INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2) IN1_IN2_DIFF_SEL_PRIORITY_CNFG 28 *

3.7 SELECTED INPUT CLOCK MONITORING

3.7.1 DPLL LOCKING DETECTION

• Fast Loss;
• Coarse Phase Loss;
• Fine Phase Loss;
• Hard Limit Exceeding.

3.7.1.1 Fast Loss

secutive clock cycles. It is cleared once an active clock edge is detected.

3.7.1.2 Coarse Phase Loss

result is within the coarse phase limit. Table 10. When the selected input clock is of other frequencies but 2 bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 11. unlocked if the COARSE_PH_LOS_LIMT_EN bit is ‘1’.

3.7.1.3 Fine Phase Loss

if the FINE_PH_LOS_LIMT_EN bit is ‘1’.

3.7.1.4 Hard Limit Exceeding

FREQ_LIMT_PH_LOS bit is ‘1’.

3.7.2 LOCKING STATUS

The DPLL locking status depends on the locking monitoring results. during 2 seconds; otherwise, the DPLL is unlocked.

• Fast Loss (the FAST_LOS_SW bit is ‘1’);
• Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is ‘1’);
• Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
• DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’). If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the FINE_PH_LOS_LIMT_EN bit or the FR EQ_LIMT_PH_LOS bit is ‘0’, the DPLL locking status will not be affected even if the corresponding event is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2 seconds. The DPLL locking status is indicated by the T0_DPLL_LOCK.

3.7.3 PHASE LOCK ALARM

INn_DIFF_PH_LOCK_ALARM bit (n = 1 or 2).

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 23 March 23, 2009

• Be cleared when a ‘1’ is written to the corresponding INn_CMOS_PH_LOCK_ALARM / INn_DIFF_PH_LOCK_ ALARM bit;
• Be cleared after the period ( = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0] in second ) which starts from when the alarm is raised. The selected input clock with a phase lock alarm is disqualified for T0 DPLL locking. Table 12: Related Bit / Register in Chapter 3.7 Bit Register Address (Hex) FAST_LOS_SW PHASE_LOSS_FINE_LIMIT_CNFG 5B *PH_LOS_FINE_LIMT[2:0] FINE_PH_LOS_LIMT_EN PHASE_LOSS_COARSE_LIMIT_CNFG 5A *WIDE_EN PH_LOS_COARSE_LIMT[3:0] COARSE_PH_LOS_LIMT_EN T0_DPLL_SOFT_FREQ_ALARM OPERATING_STS 52T0_DPLL_LOCK DPLL_FREQ_SOFT_LIMT[6:0] DPLL_FREQ_SOFT_LIMIT_CNFG 65FREQ_LIMT_PH_LOS DPLL_FREQ_HARD_LIMT[15:0] DPLL_FREQ_HARD_LIMIT[15:8]_CNFG, DPLL_FREQ_HARD_LIMIT[7:0]_CNFG 67, 66 TIME_OUT_VALUE[5:0] PHASE_ALARM_TIME_OUT_CNFG 08MULTI_FACTOR[1:0] INn_CMOS_PH_LOCK_ALARM (n = 1, 2, or 3) IN1_IN2_CMOS_STS, IN3_CMOS_STS 44, 47 INn_DIFF_PH_LOCK_ALARM (n = 1 or 2) IN1_IN2_DIFF_STS 45 PH_ALARM_TIMEOUT INPUT_MODE_CNFG 09

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 24 March 23, 2009

3.8 SELECTED INPUT CLOCK SWITCH

If the input clock is selected by Exte rnal Fast selection or by Forced selection, it can be switched by se tting the related registers (refer to Chapter 3.6.1 External Fast Selection & Chapter 3.6.2 Forced Selection) any time. In this case, whether the input clock is qualified for DPLL lock- ing does not affect the clock switch. When the input clock is selected by Automatic selection, the input clock switch depends on its validity and priority. If the current selected input clock is disqualified, a new qualified input clock may be switched to.

3.8.1 INPUT CLOCK VALIDITY

For all the input clocks, the validity depends on the results of input clock quality monitoring (refer to Chapter 3.5 Input Clock Quality Moni- toring). When all of the following condition s are satisfied, the input clock is valid; otherwise, it is invalid.

• No no-activity alarm (the IN n_CMOS_NO_ACTIVITY_ALARM / INn_DIFF_NO_ACTIVITY_ALARM bit is ‘0’);
• No frequency hard alarm (t he INn_CMOS_FREQ_HARD_ ALARM / INn_DIFF_FREQ_HARD_ALARM bit is ‘0’);
• If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the IN_NOISE_WINDOW bit is ‘0’, this condition is ignored. The T0 selected input clock is valid when all of the above and the fol- lowing conditions are satisfied; otherwise, it is invalid.
• No phase lock alarm, i.e., the INn_CMOS_PH_LOCK_ALARM / INn_DIFF_PH_LOCK_ALARM bit is ‘0’;
• If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock misses less than (<) 2 consecutive clock cycles; if the ULTR_FAST_SW bit is ‘0’, this condition is ignored. The validities of all the input clocks are indicated by the INn_CMOS bit (n = 1, 2 or 3) / INn_DIFF 1 bit (n = 1 or 2). When the input clock valid- ity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), the INn_CMOS 2 / INn_DIFF 2 bit will be set. If the INn_CMOS 3 / INn_DIFF 3 bit is ‘1’, an interrupt will be generated. When the T0 selected input clock has failed, i.e., the validity of the T0 selected input clock changes from ‘valid’ to ‘invalid’, the T0_MAIN_REF_FAILED 1 bit will be set. If the T0_MAIN_REF_FAILED 2 bit is ‘1’, an interrupt will be generated. This interrupt can also be indi- cated by hardware - the TDO pin, as determined by the LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this interrupt, it will be set high when this interrupt is generated and will remain high until this interrupt is cleared.

3.8.2 SELECTED INPUT CLOCK SWITCH

Revertive and Non-Revertive switches are supported, as selected by the REVERTIVE_MODE bit. The difference between Revertiv e and Non-Revertive switches is that whether the selected input clock is switched when another qualified input clock with a higher priority t han the current selected input clock is available for selection. In Non-Reve rtive switch, input clock switch is minimized. Conditions of the qualified input cloc ks available for T0 selection are as shown in Table 13: The input clock is disqualified if any of the above conditions is not satisfied. In summary, the selected input clock can be switched by:

• External Fast selection;
• Forced selection;
• Revertive switch;
• Non-Revertive switch;

3.8.2.1 Revertive Switch

In Revertive switch, the selected input clock is switched when another qualified input clock with a higher priority than the current selected input clock is available. The selected input clock is switched if any of the following is satis- fied:

• the selected input clock is disqualified;
• another qualified input clock with a higher priority than the selected input clock is available. A qualified input clock with the highest priority is selected by revertive switch. If more than one qualified i nput clock is available and has the same priority, the input clock with the smallest ‘n’ is selected. See Table 8 for the ‘n’ assigned to each input clock.

3.8.2.2 Non-Revertive Switch

In Non-Revertive switch, the T0 selected input clock is not switched when another qualified input clock with a higher priority than the current selected input clock is available. In this case, the selected input clock is switched and a qualified input clock wi th the highest priority is selected only when the T0 selected input clock is disqualified. If more than one qualified input clock is available and has the same priority, the input clock with the smallest ‘n’ is selected. See Table 8 for the ‘n’ assigned to each input clock.

3.8.3 SELECTED / QUALIFIED INPUT CLOCKS INDICATION

The selected input clock is indicated by the CURRENTLY_SELECTED_INPUT[3:0] bits. The qualified input clocks with the three highest priorities are indi- cated by HIGHEST_PRIORITY_VALIDATED[3:0] bits, the SECOND_ PRIORITY_VALIDATED[3:0] bits and the THIRD_PRIORITY _VALIDATED[3:0] bits respectively. If more than one input clock has the same priority, the input clock with th e smallest ‘n’ is indicated by the Table 13: Conditions of Qualified Input Clocks Available for T0 Selection Conditions of Qualified Input Clocks Available for T0 Selection

• Valid, i.e., the INn_CMOS 1 / INn_DIFF 1 bit is ‘1’;
• Priority enabled, i.e., the corresponding INn_CMOS_SEL _PRIORITY[3:0] / INn_DIFF_SEL_PRIORITY[3:0] bits are not ‘0000’

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 25 March 23, 2009 HIGHEST_PRIORITY_VALIDATED[3:0] bits. See Table 8 for the ‘n’ assigned to the input clock. When the device is configured in Automatic selection and Revertive switch is enabled, the input clock indicated by the CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi- cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise, they are not the same. Table 14: Related Bit / Register in Chapter 3.8 Bit Register Address (Hex) INn_CMOS 1 (n = 1, 2 or 3) / INn_DIFF 1 (n = 1 or 2) INPUT_VALID1_STS, INPUT_VALID2_STS 4A, 4B INn_CMOS 2 (n = 1, 2 or 3) / INn_DIFF 2 (n = 1 or 2) INTERRUPTS1_STS, INTERRUPTS2_STS 0D, 0E INn_CMOS 3 (n = 1, 2 or 3) / INn_DIFF 3 (n = 1 or 2) INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG 10, 11 INn_CMOS_NO_ACTIVITY_ALARM (n = 1, 2 or 3) IN1_IN2_CMOS_STS, IN3_CMOS_STS 44, 47INn_CMOS_FREQ_HARD_ALARM (n = 1, 2 or 3) INn_CMOS_PH_LOCK_ALARM (n = 1, 2 or 3) INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2) IN1_IN2_DIFF_STS 45INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2) INn_DIFF_PH_LOCK_ALARM (n = 1 or 2) IN_NOISE_WINDOW PHASE_MON_PBO_CNFG 78 ULTR_FAST_SW MON_SW_PBO_CNFG 0BLOS_FLAG_TO_TDO T0_MAIN_REF_FAILED 1 INTERRUPTS2_STS 0E T0_MAIN_REF_FAILED 2 INTERRUPTS2_ENABLE_CNFG 11 REVERTIVE_MODE INPUT_MODE_CNFG 09 INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3) IN1_IN2_CMOS_ SEL_PRIORITY_CNFG, IN3_CMOS_SEL_PRIORITY_CNFG 27 *, 2A * INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2) IN1_IN2_DIFF_SEL_PRIORITY_CNFG 28 * CURRENTLY_SELECTED_INPUT[3:0] PRIORITY_TABLE1_STS 4E *HIGHEST_PRIORITY_VALIDATED[3:0] SECOND_PRIORITY_VALIDATED[3:0] PRIORITY_TABLE2_STS 4F *THIRD_PRIORITY_VALIDATED[3:0]

Locked, Pre-Locked2 and Lost-Phase. mode switch is applicable for special cases, such as testing. the internal state machine is shown in Figure 6. T0_OPERATING_MODE 2 bit is ‘1’, an interrupt will be generated. Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode

000 Automatic

001 Forced - Free-Run

010 Forced - Holdover

100 Forced - Locked

101 Forced - Pre-Locked2

110 Forced - Pre-Locked

111 Forced - Lost-Phase

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 27 March 23, 2009 Notes to Figure 6: 1. Reset. 2. An input clock is selected. 3. The T0 selected input clock is disqualified AND No qualified input clock is available. 4. The T0 selected input clock is switched to another one. 5. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’). 6. The T0 selected input clock is disqualified AND No qualified input clock is available. 7. The T0 selected input clock is unlocked (the T0_DPLL_LOCK bit is ‘0’). 8. The T0 selected input clock is locked again (the T0_DPLL_LOCK bit is ‘1’). 9. The T0 selected input clock is switched to another one. 10. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’). 11. The T0 selected input clock is disqualified AND No qualified input clock is available. 12. The T0 selected input clock is switched to another one. 13. The T0 selected input clock is disqualified AND No qualified input clock is available. 14. An input clock is selected. 15. The T0 selected input clock is switched to another one. The causes of Item 4, 9, 12, 15 - ‘the T0 selected input clock is switched to another one’ - are: (The T0 selected input clock is disquali- fied AND Another input clock is switched to) OR (In Revertive switch, a qualified input clock with a hi gher priority is switched to) OR (The T0 selected input clock is switched to another one by External Fast selec- tion or Forced selection). Refer to Table 13 for details about the input clock qualification for T0 path.

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 28 March 23, 2009

3.10 DPLL OPERATING MODE

The DPLL gives a stable performance in different applications with- out being affected by operating conditi ons or silicon process variations. It integrates a PFD (Phase & Frequency Detector), a LPF (Low Pass Fil- ter) and a DCO (Digital Controlled Oscillator), which forms a closed loop. If no input clock is selected, the loop is not closed, and the PFD and LPF do not function. The PFD detects the phase error, including the fast loss, coarse phase loss and fine phase loss (refer to Chapter 3.7.1.1 Fast Loss to Chapter 3.7.1.3 Fine Phase Loss ). The averaged phase error of the DPLL feedback with respect to the selected input clock is indicated by the CURRENT_PH_DATA[15:0] bits. It can be calculated as follows: Averaged Phase Error (ns) = CURRENT_PH_DATA[15:0] X 0.61 The LPF filters jitters. Its 3 dB bandwidth and damping factor are pro- grammable. A range of bandwidth s and damping factors can be set to meet different application requirem ents. Generally, the lower the damp- ing factor is, the longer the locking time is and the more the gain is. The DCO controls the DPLL output. The frequency of the DPLL out- put is always multiplied on the basis of the master clock. The phase and frequency offset of the DPLL output may be locked to those of the selected input clock. The current frequency offset with respect to the master clock is indicated by the CURRENT_DPLL_FREQ[23:0] bits, and can be calculated as follows: Current Frequency Offset (ppm ) = CURRENT_DPLL_FREQ[23:0] X 0.000011

3.10.1 T0 DPLL OPERATING MODE

The T0 DPLL loop is closed exc ept in Free-Run mode and Holdover mode. For a closed loop, different bandw idths and damping factors can be used depending on DPLL locking stages: starting, acquisition and locked. In the first two seconds when the T0 DPLL attempts to lock to the selected input clock, the starti ng bandwidth and damping factor are used. They are set by the T0_DPLL_START_BW[4:0] bits and the T0_DPLL_START_DAMPING[2:0] bits respectively. During the acquisition, the acquisition bandwidth and damping factor are used. They are set by the T0_DPLL_ACQ_BW[4:0] bits and the T0_DPLL_ACQ_DAMPING[2:0] bits respectively. When the T0 selected input clock is locked, the locked bandwidth and damping factor are used. They are set by the T0_DPLL_LOCKED_BW[4:0] bits and the T0_DPLL_LOCKED_DAMPING[2:0] bits respectively. The corresponding bandwidth and damping factor are used when the T0 DPLL operates in different DPLL locking stages: starting, acquisition and locked, as controlled by the device automatically. Only the locked bandwidth and damping factor can be used regard- less of the T0 DPLL locking stage, as controlled by the AUTO_BW_SEL bit.

3.10.1.1 Free-Run Mode

In Free-Run mode, the T0 DPLL output refers to the master clock and is not affected by any input clock. The accuracy of the T0 DPLL out- put is equal to that of the master clock.

3.10.1.2 Pre-Locked Mode

In Pre-Locked mode, the T0 DPLL output attempts to track the selected input clock. The Pre-Locked mode is a secondary, temporary mode.

3.10.1.3 Locked Mode

In Locked mode, the T0 selected input clock is locked. The phase and frequency offset of the T0 DPLL output track those of the T0 selected input clock. In this mode, if the T0 selected input clock is in fast loss status and the FAST_LOS_SW bit is ‘1’, the T0 DPLL is unlocked (refer to Chapter 3.7.1.1 Fast Loss ) and will enter Lost-Phase mode when the operating mode is switched automatically ; if the T0 selected input clock is in fast loss status and the FAST_LOS_SW bit is ‘0’, the T0 DPLL lock- ing status is not affected and the T0 DPLL will enter Temp-Holdover mode automatically. 3.10.1.3.1 Temp-Holdover Mode The T0 DPLL will automatically enter Temp-Holdover mode with a selected input clock switch or no qualified input clock available when the operating mode switch is under external control. In Temp-Holdover mode, the T0 DPLL has temporarily lost the selected input clock. The T0 DP LL operation in Temp-Holdover mode and that in Holdover mode are alike (refer to Chapter 3.10.1.5 Holdover Mode) except the frequency offset acquiring methods. See Chapter 3.10.1.5 Holdover Mode for details about the methods. The method is selected by the TEMP _HOLDOVER_MODE[1:0] bits, as shown in Table 16: The device automatically controls the T0 DPLL to exit from Temp- Holdover mode.

3.10.1.4 Lost-Phase Mode

In Lost-Phase mode, the T0 DPLL output attempts to track the selected input clock. The Lost-Phase mode is a secondary, temporary mode.

3.10.1.5 Holdover Mode

In Holdover mode, the T0 DPLL resorts to the stored frequency data acquired in Locked mode to control its output. The T0 DPLL output is not Table 16: Frequency Offset Control in Temp-Holdover Mode TEMP_HOLDOVER_MODE[1:0] Freque ncy Offset Acquiring Method 00 the same as that used in Holdover mode

01 Automatic Instantaneous

10 Automatic Fast Averaged

11 Automatic Slow Averaged

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 29 March 23, 2009 phase locked to any input clock. The frequency offset acquiring method is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the FAST_AVG bit, as shown in Table 17: 3.10.1.5.1 Automatic Instantaneous By this method, the T0 DPLL freezes at the operating frequency when it enters Holdover mode. The accuracy is 4.4X10-8 ppm.

3.10.1.5.2 Automatic Slow Averaged

By this method, an internal IIR (I nfinite Impulse Response) filter is employed to get the frequency offset. The IIR filter gives a 3 dB attenua- tion point corresponding to a period of 110 minutes. The accuracy is 1.1X10 -5 ppm.

3.10.1.5.3 Automatic Fast Averaged

By this method, an internal IIR (I nfinite Impulse Response) filter is employed to get the frequency offset. The IIR filter gives a 3 dB attenua- tion point corresponding to a period of 8 minutes. The accuracy is 1.1X10 -5 ppm.

3.10.1.5.4 Manual

By this method, the frequency offset is set by the T0_HOLDOVER_FREQ[23:0] bits. The accuracy is 1.1X10-5 ppm. The frequency offset of the T0 DPLL output is indicated by the CURRENT_DPLL_FREQ[23:0] bits. The device provides a reference for the value to be written to the T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to the value read from the CURRENT _DPLL_FREQ[23:0] bits or the T0_HOLDOVER_FREQ[23:0] bits (refer to Chapter 3.10.1.5.5 Holdover Frequency Offset Read ); or then be processed by external software fil- tering. 3.10.1.5.5 Holdover Frequency Offset Read The offset value, which is ac quired by Automatic Slow Averaged, Automatic Fast Averaged and is set by related register bits, can be read from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG bit and the FAST_AVG bit, as shown in Table 18. The frequency offset in ppm is calculated as follows: Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X 0.000011

3.10.1.6 Pre-Locked2 Mode

In Pre-Locked2 mode, the T0 DPLL output attempts to track the selected input clock. The Pre-Locked2 mode is a secondary, temporary mode. Table 17: Frequency Offset Control in Holdover Mode MAN_HOLDOVER AUTO_AVG FAST_AVG Fr equency Offset Acquiring Method 0 don’t-care Automatic Instantaneous 1 0 Automatic Slow Averaged

1 Automatic Fast Averaged

1 don’t-care Manual Table 18: Holdover Frequency Offset Read READ_AVG FAST_AVG Offset Value Read from T0_HOLDOVER_FREQ[23:0] 0 don’t-care The value is equal to the one written to.

0 The value is acquired by Automatic Slow Averaged

method, not equal to the one written to.

1 The value is acquired by Automatic Fast Averaged

method, not equal to the one written to.

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 30 March 23, 2009

3.11 DPLL OUTPUT

The DPLL output is locked to the se lected input clock. According to the phase-compared result of the feedback and the selected input clock, and the DPLL output frequency offset, the PFD output is limited and the DPLL output is frequency offset limited.

3.11.1 PFD OUTPUT LIMIT

The PFD output is limited to be within ±1 UI or within the coarse phase limit (refer to Chapter 3.7.1.2 Coarse Phase Loss), as determined by the MULTI_PH_APP bit.

3.11.2 FREQUENCY OFFSET LIMIT

The DPLL output is limited to be wi thin the DPLL hard limit (refer to Chapter 3.7.1.4 Hard Limit Exceeding). For T0 DPLL, the integral path value can be frozen when the DPLL hard limit is reached. This function, enabled by the T0_LIMT bit, will min- imize the subsequent overshoot when T0 DPLL is pulling in.

3.11.3 PBO

The PBO function is only supported by the T0 path. When a PBO event is triggered, the phase offset of the selected input clock with respect to the T0 DPLL output is measured. The device then automatically accounts for the measured phase offset and compensates an appropriate phase offset into the DPLL output so that the phase tran- sients on the T0 DPLL output are minimized. A PBO event is triggered if an y one of the following conditions occurs:

• T0 selected input clock switches (the PBO_EN bit is ‘1’);
• T0 DPLL exits from Holdover mode or Free-Run mode (the PBO_EN bit is ‘1’);
• Phase-time changes on the T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 sec- onds (the PH_MON_PBO_EN bit is ‘1’). For the first two conditions, the phase transients on the T0 DPLL out- put are minimized to be no more than 0.61 ns with PBO. The PBO can also be frozen at the current phase offset by setting the PBO_FREZ bit. When the PBO is frozen, the device will ignore any further PBO events triggered by the above two conditi ons, and maintain the current phase offset. When the PBO is disabled, there may be a phase shift on the T0 DPLL output and the T0 DPLL output tracks back to 0 degree phase off- set with respect to the T0 selected input clock. The last condition is specially fo r stratum 2 and 3E clocks. The PBO requirement specified in the Telcordia GR-1244-CORE is: ‘Input phase- time changes of 3.5 µs or greater ov er an interval of less than 0.1 sec- onds or less shall be built-out by st ratum 2 and 3E clocks to reduce the resulting clock phase-time chan ge to less than 50 ns. Phase-time changes of 1.0 µs or less over an interval of 0.1 seconds shall not be built-out.’ Based on this requirement, phase-time changes of more than 1.0 µs but less than 3.5 µs that occur over an interval of less than 0.1 seconds may or may not be built-out. An integrated Phase Transient Monitor can be enabled by the PH_MON_EN bit to monitor the phase-time changes on the T0 selected input clock. When the phase-time c hanges are greater than a limit over an interval of less than 0.1 sec onds, a PBO event is triggered and the phase transients on the DPLL output are absorbed. The limit is pro- grammed by the PH_TR_MON_LIMT[3:0] bits, and can be calculated as follows: Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156 The phase offset induced by PBO will never result in a coarse or fine phase loss.

3.11.4 PHASE OFFSET SELECTION

The phase offset of the T0 selected input clock with respect to the T0 DPLL output can be adjusted. T he PH_OFFSET_EN bit determines whether the input-to-output phase offset is enabled. If enabled, the input-to-output phase offset can be adjusted by setting the PH_OFFSET[9:0] bits. The input-to-output phase offset can be calculated as follows: Phase Offset (ns) = PH_OFFSET[9:0] X 0.61

3.11.5 FOUR PATHS OF T0 DPLL OUTPUTS

The T0 DPLL output are phase aligned with the T0 selected input clock respectively every 125 µs period. Each DPLL has four output paths.

3.11.5.1 T0 Path

The four paths for T0 DPLL output are as follows:

• 77.76 MHz path - outputs a 77.76 MHz clock;
• 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by the IN_SONET_SDH bit;
• ETH/OBSAI/16E1/16T1 path - outputs a ETH, OBSAI, 16E1 or 16T1 clock, as selected by the T0_ETH_OBSAI_16E1_16T1_ SEL[1:0 ] bits;
• 12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock, as selected by the T0_12E1_24T1_E3_T3_SEL[1:0] bits. T0 selected input clock is compared with a T0 DPLL output for DPLL locking. The output can only be deriv ed from the 77.76 MHz path or the 16E1/16T1 path. The output path is automatically selected and the out- put is automatically divided to get the same frequency as the T0 selected input clock. T0 DPLL outputs are provided for T0/T4 APLL or device output pro- cess.

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 31 March 23, 2009

3.12 T0 / T4 APLL

A T0 APLL and a T4 APLL are provided for a better jitter and wander performance of the device output clocks. The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0] / T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the better the jitter and wander performance of the T0/T4 APLL output are. The input of the T0/T4 APLL can be derived from the T0 DPLL out- puts, as selected by the T0_APLL_PATH[3:0] / T4_APLL_PATH[3:0] bits respectively. Both the APLL and DPLL outputs are provided for selection for the device output.

3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS

The device supports 2 output clocks and 2 frame sync output signals altogether.

3.13.1 OUTPUT CLOCKS

The device provides 2 output clocks. OUT1 outputs a PECL or LVDS signal, as selected by the OUT1_PECL_LVDS bit. OUT2 outputs a CMOS signal. The outputs on OUT1 and OUT2 are variable, depending on the sig- nals derived from the T0 DPLL and T0/T4 APLL outputs, and the corre- sponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). The derived signal can be from the T0 DPLL and T0/T4 APLL outputs, as selected by the corre- sponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). If the signal is derived from one of the T0 DPLL outputs, please refer to Table 20 for the output frequency. If the signal is derived fr om the T0/T4 APLL output, please refer to Table 21~Table 22 for the output frequency. The outputs on OUT1 and OUT2 can be inverted, as determined by the corresponding OUTn_INV bit (n = 1 or 2). Both the output clocks derived from T0/T4 selected input clock are aligned with the T0/T4 selected i nput clock respectively every 125 µs period. Table 19: Related Bit / Register in Chapter 3.12 Bit Register Address (Hex) T0_APLL_BW[1:0] T0_T4_APLL_BW_CNFG 6AT4_APLL_BW[1:0] T0_APLL_PATH[3:0] T0_DPLL_APLL_PATH_CNFG 55 T4_APLL_PATH[3:0] DPLL_APLL_PATH_CNFG 60 Table 20: Outputs on OUT1 & OUT2 if Derived from T0 DPLL Outputs OUTn_DIVIDER[3:0] (Output Divider) 1 outputs on OUT1 & OUT2 if derived from T0 DPLL outputs 2

77.76 MHz 12E1 16E1 24T1 16T1 E3 T3 GSM

(26 MHz) OBSAI (30.72 MHz) GPS (40 MHz) 0000 Output is disabled (output low). 0001 0010 12E1 16E1 24T1 16T1 E3 T3 0011 6E1 8E1 12T1 8T1 13 MHz 15.36 MHz 20 0100 3E1 4E1 6T1 4T1 10 0101 2E1 4T1 0110 2E1 3T1 2T1 5

0111 E1 2T1

1000 E1 T1

1111 Output is disabled (output high). Note: 1. n = 1 or 2. Each output is assigned a frequency divider.

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 32 March 23, 2009 Table 21: Outputs on OUT1 & OUT2 if Derived from T0 APLL OUTn_DIVIDER[3:0] (Output Divider) 1 outputs on OUT1 & OUT2 if derived from T0 APLL output 2

77.76 MHz X 4 12E1 X 4 16E1 X 4 24T1 X 4 16T1 X 4 E3 T3 GSM

(26 MHz X 2) OBSAI (30.72 MHz X 10) GPS (40 MHz) 0000 Output is disabled (output low). 0001 622.08 MHz 3 0010 311.04 MHz 3 48E1 64E1 96T1 64T1 E3 T3 52 MHz 0011 155.52 MHz 24E1 32E1 48T1 32T1 26 MHz 153.6 MHz 20 MHz 0100 77.76 MHz 12E1 16E1 24T1 16T1 13 MHz 76.8 MHz 10 MHz 0101 51.84 MHz 8E1 16T1 0110 38.88 MHz 6E1 8E1 12T1 8T1 38.4 MHz 5 MHz 0111 25.92 MHz 4E1 8T1 1000 19.44 MHz 3E1 4E1 6T1 4T1 1001 2E1 4T1 61.44 MHz 1010 2E1 3T1 2T1 30.72 MHz 1011 6.48 MHz E1 2T1 15.36 MHz 1100 E1 T1 7.68 MHz 1101 T1 3.84 MHz 1110 1111 Output is disabled (output high). Note: 1. n = 1 or 2. Each output is assigned a frequency divider. reserved. 3. The 622.08 MHz and 311.04 MHz differential signals are only output on OUT1.

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 33 March 23, 2009 Table 22: Outputs on OUT1 & OUT2 if Derived from T4 APLL OUTn_DIVIDER[3 :0] (Output Divider) 1 outputs on OUT1 & OUT2 if derived from T4 APLL output 2 (26 MHz X 2) ETH OBSAI (30.72 MHz X 10) GPS (40 MHz) 0000 Output is disabled (output low). 0001 622.08 MHz 3 0010 311.04 MHz 3 48E1 64E1 96T1 64T1 E3 T3 52 MHz 312.5 MHz 0011 155.52 MHz 24E1 32E1 48T1 32T1 26 MHz 156.25 MHz 153.6 MHz 20 MHz 0100 77.76 MHz 12E1 16E1 24T1 16T1 13 MHz 76.8 MHz 10 MHz 0101 51.84 MHz 8E1 16T1 0110 38.88 MHz 6E1 8E1 12T1 8T1 38.4 MHz 5 MHz 0111 25.92 MHz 4E1 8T1 1000 19.44 MHz 3E1 4E1 6T1 4T1 125 MHz 1001 2E1 4T1 25 MHz 1010 2E1 3T1 2T1 5 MHz 1011 6.48 MHz E1 2T1 1100 E1 T1 62.5 MHz 1101 T1 1110 1111 Output is disabled (output high). Note: 1. n = 1 or 2. Each output is assigned a frequency divider. reserved. 3. The 622.08 MHz and 311.04 MHz differential signals are only output on OUT1.

3.13.2 FRAME SYNC OUTPUT SIGNALS

2K_EN bits respectively. They are CMOS outputs. the three frame sync input signals. tively) will compensate this early/late. Refer to Figure 7 to Figure 10. Figure 7. On Target Frame Sync Input Signal Timing Fi gure 8. 0.5 UI Early Frame Sync Input Signal Timing

01 E n a b l e d

Figure 9. 0.5 UI Late Frame Sync Input Signal Timing Figure 10. 1 UI La te Frame Sync Input Signal Timing

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Functional Description 36 March 23, 2009

3.14 INTERRUPT SUMMARY

The interrupt sources of the device are as follows:

• Input clocks for T0 path validity change
• T0 selected input clock fail
• T0 DPLL operating mode switch
• External sync alarm All of the above interrupt events are indicated by the corresponding interrupt status bit. If the corresponding interrupt enable bit is set, any of the interrupts can be reported by t he INT_REQ pin. The output charac- teristics on the INT_REQ pin are determined by the HZ_EN bit and the INT_POL bit. Interrupt events are cleared by writing a ‘1’ to the corresponding interrupt status bit. The INT_REQ pin will be inactive only when all the pending enabled interrupts are cleared. In addition, the interrupt of T0 selected input clock fail can be reported by the TDO pin, as det ermined by the LOS_FLAG_TO_TDO bit.

3.15 T0 SUMMARY

The main features supported by the T0 path are as follows:

• Phase lock alarm;
• Forced or Automatic input clock selection/switch;
• 3 primary and 3 secondary, temporary DPLL operating modes, switched automatically or under external control;
• Automatic switch between starting, acquisition and locked band- widths/damping factors;
• Programmable DPLL bandwidths from 0.1 Hz to 560 Hz in 11 steps;
• Programmable damping factors: 1.2, 2.5, 5, 10 and 20;
• Fast loss, coarse phase loss, fine phase loss and hard limit exceeding monitoring;
• Output phase and frequency offset limited;
• Automatic Instantaneous, Automatic Slow Averaged, Automatic Fast Averaged or Manual holdover frequency offset acquiring;
• PBO to minimize output phase transients;
• Programmable output phase offset;
• Low jitter multiple clock outputs with programmable polarity;
• Low jitter 2 kHz and 8 kHz frame sync signal outputs with pro- grammable pulse width and polarity. Table 26: Related Bit / Register in Chapter 3.14 Bit Register Address (Hex) HZ_EN INTERRUPT_CNFG 0CINT_POL LOS_FLAG_TO_TDO MON_SW_PBO_CNFG 0B

3.16 POWER SUPPLY FI LTERING TECHNIQUES

Figure 11. IDT82V3352 Power Decoupling Scheme for the core logic as well as I/O driver circuits. caps to filter out the switching transients. bypass capacitor and ferrite bead should be connected to power pins. placed right next to the VDDA and VDD_DIFF pins as close as possible. capacitors should be placed as close to the VDDD pins as possible. Please refer to evaluation board schematic for details.

3.17 LINE CARD APPLICATION

Figure 12. Line Card Application

4 MICROPROCESSOR INTERFACE

In a read operation, the active edge of SCLK is selected by CLKE. clocked out on the falling edge of SCLK. Figure 13. Serial Read Timing Diagram (CLKE Asserted Low) Figure 14. Serial Read Timing Diagram (CLKE Asserted High)

Figure 15. Serial Write Timing Diagram

• The output boundary scan cells do not capture data from the core and the device does not support EXTEST instruction;
• The TRST pin is set low by default and JTAG is disabled in order to be consistent with other manufacturers. The JTAG interface timing diagram is shown in Figure 16.

Figure 16. JTAG Interface Timing Diagram

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 42 March 23, 2009

6 PROGRAMMING INFORMATION

After reset, all the registers are se t to their default values. The regis- ters are read or written via the microprocessor interface. Before any write operation, the value in register PROTECTION_CNFG is recommended to be confirmed to make sure whether the write operation is enabled. The device provides 3 register protection modes:

• Protected mode: no other registers can be written except register PROTECTION_CNFG itself;
• Fully Unprotected mode: all the writable registers can be written;
• Single Unprotected mode: one mo re register can be written besides register PROTECTION _CNFG. After write operation (not including writing a ‘1’ to clear a bit to ‘0’), the device auto- matically switches to Protected mode. Writing ‘0’ to the registers will take no effect if the registers are cleared by writing ‘1’. The access of the Multi-word Regist ers is different from that of the Single-word Registers. Take the registers (04H, 05H and 06H) for an example, the write operation for the Mu lti-word Registers follows a fixed sequence. The register (04H) is configured first and the register (06H) is configured last. The three regist ers are configured continuously and should not be interrupted by any operat ion. The crystal calibration con- figuration will take effect after all the three registers are configured. Dur- ing read operation, the register (04H) is read first and the register (06H) is read last. The crystal calibration reading should be continuous and not be interrupted by any operation. Certain bit locations within the device register map are designated as Reserved. To ensure proper and predi ctable operation, bits designated as Reserved should not be written by t he users. In addition, their value should be masked out from any testi ng or error detection methods that are implemented.

6.1 REGISTER MAP

Table 30 is the map of all the regist ers, sorted in an ascending order of their addresses. Table 30: Register List and Map Address (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page Global Control Registers

00 ID[7:0] - Device ID 1 ID[7:0] P 47

01 ID[15:8] - Device ID 2 ID[15:8] P 47

NOMINAL_FREQ[7:0]_CNFG - Crys- tal Oscillator Frequency Offset Calibra- tion Configuration 1 NOMINAL_FREQ_VALUE[7:0] P 47 NOMINAL_FREQ[15:8]_CNFG - Crys- tal Oscillator Frequency Offset Calibra- tion Configuration 2 NOMINAL_FREQ_VALUE[15:8] P 48 NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3 NOMINAL_FREQ_VALUE[23:16] P 48 PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configu- ration MULTI_FACTOR[1:0] TIME_OUT_VALUE[5:0] P 49

09 INPUT_MODE_CNFG - Input Mode

AUTO_EX T_SYNC_ EN EXT_SYN C_EN PH_ALAR M_TIMEO UT SYNC_FREQ[1:0] IN_SONET _SDH - REVERTIV E_MODE P5 0 DIFFERENTIAL_IN_OUT_OSCI_CNF G - Differential Input / Output Port & Master Clock Configuration ----- OSC_EDG E OUT1_PE CL_LVDS -P 5 1 MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control FREQ_MO N_CLK LOS_FLA G_TO_TD O ULTR_FAS T_SW EXT_SW PBO_FRE Z PBO_EN - FREQ_MO N_HARD_ EN P5 2 7E PROTECTION_CNFG - Register Pro- tection Mode Configuration PROTECTION_DATA[7:0] P 53 Interrupt Registers 0C INTERRUPT_CNFG - Interrupt Config-

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 43 March 23, 2009 0D INTERRUPTS1_STS - Interrupt Status 1 - - IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS - - P 54 0E INTERRUPTS2_STS - Interrupt Status T0_OPER ATING_MO DE T0_MAIN_ REF_FAIL ED ----- I N 3 _ C M O S P 5 5 0F INTERRUPTS3_STS - Interrupt Status EX_SYNC

10 INTERRUPTS1_ENABLE_CNFG -

Interrupt Control 1 - - IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS - - P 56

11 INTERRUPTS2_ENABLE_CNFG -

T0_OPER ATING_MO DE T0_MAIN_ REF_FAIL ED ----- I N 3 _ C M O S P 5 6

12 INTERRUPTS3_ENABLE_CNFG -

EX_SYNC Input Clock Frequency & Priority Configuration Registers

16 IN1_CMOS_CNFG - CMOS Input

DIRECT_D IV LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] P 58

17 IN2_CMOS_CNFG - CMOS Input

DIRECT_D IV LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] P 59 IN1_IN2_DIFF_HF_DIV_CNFG - Dif- ferential Input Clock 1 & 2 High Fre- quency Divider Configuration IN2_DIFF_DIV[1:0] - - - - IN1_DIFF_DIV[1:0] P 60

19 IN1_DIFF_CNFG - Differential Input

DIRECT_D IV LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] P 61 1A IN2_DIFF_CNFG - Differential Input Clock 2 Configuration DIRECT_D IV LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] P 62 1D IN3_CMOS_CNFG - CMOS Input Clock 3 Configuration DIRECT_D IV LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] P 63

23 PRE_DIV_CH_CNFG - DivN Divider

Channel Selection - - - - PRE_DIV_CH_VALUE[3:0] P 64

24 PRE_DIVN[7:0]_CNFG - DivN Divider

Division Factor Configuration 1 PRE_DIVN_VALUE[7:0] P 64

25 PRE_DIVN[14:8]_CNFG - DivN

Divider Division Factor Configuration 2 - PRE_DIVN_VALUE[14:8] P 65 IN1_IN2_CMOS_SEL_PRIORITY_CN FG - CMOS Input Clock 1 & 2 Priority Configuration * IN2_CMOS_SEL_PRIORITY[3:0] IN1_CMOS_SEL_PRIORITY[3:0] P 66 IN1_IN2_DIFF_SEL_PRIORITY_CNF G - Differential Input Clock 1 & 2 Prior- ity Configuration * IN2_DIFF_SEL_PRIORITY[3:0] IN1_DIFF_SEL_PRIORITY[3:0] P 67 IN3_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 3 Priority Configu- ration * - - - - IN3_CMOS_SEL_PRIORITY[3:0] P 68 Input Clock Quality Monitoring Configuration & Status Registers 2E FREQ_MON_FACTOR_CNFG - Fac- tor of Frequency Monitor Configuration - - - - FREQ_MON_FACTOR[3:0] P 69 ALL_FREQ_MON_THRESHOLD_CN FG - Frequency Monitor Threshold for All Input Clocks Configuration - - - - ALL_FREQ_HARD_THRESHOLD[3:0] P 69 Table 30: Register List and Map (Continued) Address (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 44 March 23, 2009 UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0 UPPER_THRESHOLD_0_DATA[7:0] P 70 LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket Configuration 0 LOWER_THRESHOLD_0_DATA[7:0] P 70

33 BUCKET_SIZE_0_CNFG - Bucket

Size for Leaky Bucket Configuration 0 BUCKET_SIZE_0_DATA[7:0] P 70

34 DECAY_RATE_0_CNFG - Decay Rate

[1:0] P7 1 UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket Configuration 1 UPPER_THRESHOLD_1_DATA[7:0] P 71 LOWER_THRESHOLD_1_CNFG - Lower Threshold for Leaky Bucket Configuration 1 LOWER_THRESHOLD_1_DATA[7:0] P 71

37 BUCKET_SIZE_1_CNFG - Bucket

Size for Leaky Bucket Configuration 1 BUCKET_SIZE_1_DATA[7:0] P 72

38 DECAY_RATE_1_CNFG - Decay Rate

[1:0] P7 2 UPPER_THRESHOLD_2_CNFG - Upper Threshold for Leaky Bucket Configuration 2 UPPER_THRESHOLD_2_DATA[7:0] P 72 LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2 LOWER_THRESHOLD_2_DATA[7:0] P 73 3B BUCKET_SIZE_2_CNFG - Bucket Size for Leaky Bucket Configuration 2 BUCKET_SIZE_2_DATA[7:0] P 73 3C DECAY_RATE_2_CNFG - Decay Rate [1:0] P7 3 UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3 UPPER_THRESHOLD_3_DATA[7:0] P 74 LOWER_THRESHOLD_3_CNFG - Lower Threshold for Leaky Bucket Configuration 3 LOWER_THRESHOLD_3_DATA[7:0] P 74 3F BUCKET_SIZE_3_CNFG - Bucket Size for Leaky Bucket Configuration 3 BUCKET_SIZE_3_DATA[7:0] P 74

40 DECAY_RATE_3_CNFG - Decay Rate

[1:0] P7 5 IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection - - - - IN_FREQ_READ_CH[3:0] P 75

42 IN_FREQ_READ_STS - Input Clock

Frequency Read Value IN_FREQ_VALUE[7:0] P 76

44 IN1_IN2_CMOS_STS - CMOS Input

Clock 1 & 2 Status - IN2_CMOS _FREQ_H ARD_ALA RM IN2_CMOS _NO_ACTI VITY_ALA RM IN2_CMOS _PH_LOC K_ALARM IN1_CMOS _FREQ_H ARD_ALA RM IN1_CMOS _NO_ACTI VITY_ALA RM IN1_CMOS _PH_LOC K_ALARM P7 7 Table 30: Register List and Map (Continued) Address (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 45 March 23, 2009

45 IN1_IN2_DIFF_STS - Differential Input

Clock 1 & 2 Status - IN2_DIFF_ FREQ_HA RD_ALAR M IN2_DIFF_ NO_ACTIV ITY_ALAR M IN2_DIFF_ PH_LOCK _ALARM IN1_DIFF_ FREQ_HA RD_ALAR M IN1_DIFF_ NO_ACTIV ITY_ALAR M IN1_DIFF_ PH_LOCK _ALARM P7 8

47 IN3_CMOS_STS - CMOS Input Clock

3 Status -----

IN3_CMOS _FREQ_H ARD_ALA RM IN3_CMOS _NO_ACTI VITY_ALA RM IN3_CMOS _PH_LOC K_ALARM P7 9 T0 DPLL Input Clock Selection Registers 4A INPUT_VALID1_STS - Input Clocks Validity 1 - - IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS - - P 80 4B INPUT_VALID2_STS - Input Clocks 4E PRIORITY_TABLE1_STS - Priority Status 1 * HIGHEST_PRIORITY_VALIDATED[3:0] CURRENTLY_SELECTED_INPUT[3:0] P 81 4F PRIORITY_TABLE2_STS - Priority Status 2 * THIRD_HIGHEST_PRIORITY_VALIDATED[3:0] SECOND_HIGHEST_PRIORITY_VALIDATED[3:0 ] P8 2

50 T0_INPUT_SEL_CNFG - T0 Selected

Input Clock Configuration - - - - T0_INPUT_SEL[3:0] P 82 T0 DPLL State Machine Control Registers

52 OPERATING_STS - DPLL Operating

EX_SYNC _ALARM_ MON T0_DPLL_ SOFT_FRE Q_ALARM - T0_DPLL_ LOCK T0_DPLL_OPERATING_MODE[2:0] P 83

53 T0_OPERATING_MODE_CNFG - T0

DPLL Operating Mode Configuration - - - - - T0_OPERATING_MODE[2:0] P 84 T0 DPLL & APLL Configuration Registers

55 T0_DPLL_APLL_PATH_CNFG - T0

DPLL & APLL Path Configuration T0_APLL_PATH[3:0] T0_ETH_OBSAI_16E1_ 16T1_SEL[1:0] T0_12E1_24T1_E3_T3 _SEL[1:0] P8 5 T0_DPLL_START_BW_DAMPING_C NFG - T0 DPLL Start Bandwidth & Damping Factor Configuration T0_DPLL_START_DAMPING[2:0] T0_DPLL_START_BW[4:0] P 86 T0_DPLL_ACQ_BW_DAMPING_CNF G - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration T0_DPLL_ACQ_DAMPING[2:0] T0_DPLL_ACQ_BW[4:0] P 87 T0_DPLL_LOCKED_BW_DAMPING_ CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration T0_DPLL_LOCKED_DAMPING[2:0] T0_DPLL_LOCKED_BW[4:0] P 88 T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configu- ration AUTO_BW _SEL - - - T0_LIMT - - - P 88 PHASE_LOSS_COARSE_LIMIT_CNF G - Phase Loss Coarse Detector Limit Configuration * COARSE_ PH_LOS_L IMT_EN WIDE_EN MULTI_PH _APP MULTI_PH _8K_4K_2 K_EN PH_LOS_COARSE_LIMT[3:0] P 89 PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Con- figuration * FINE_PH_ LOS_LIMT _EN FAST_LOS _SW - - - PH_LOS_FINE_LIMT[2:0] P 90 5C T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration MAN_HOL DOVER AUTO_AV G FAST_AVG READ_AV G TEMP_HOLDOVER_M ODE[1:0] -- P 9 1 T0_HOLDOVER_FREQ[7:0]_CNFG - T0 DPLL Holdover Frequency Config- uration 1 T0_HOLDOVER_FREQ[7:0] P 91 Table 30: Register List and Map (Continued) Address (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 46 March 23, 2009 T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Con- figuration 2 T0_HOLDOVER_FREQ[15:8] P 92 T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Con- figuration 3 T0_HOLDOVER_FREQ[23:16] P 92

60 DPLL_APLL_PATH_CNFG - DPLL &

APLL Path Configuration T4_APLL_PATH[3:0] - - P 92

62 CURRENT_DPLL_FREQ[7:0]_STS -

DPLL Current Frequency Status 1 * CURRENT_DPLL_FREQ[7:0] P 93

63 CURRENT_DPLL_FREQ[15:8]_STS -

DPLL Current Frequency Status 2 * CURRENT_DPLL_FREQ[15:8] P 93

64 CURRENT_DPLL_FREQ[23:16]_STS

• DPLL Current Frequency Status 3 * CURRENT_DPLL_FREQ[23:16] P 93

65 DPLL_FREQ_SOFT_LIMIT_CNFG -

DPLL Soft Limit Configuration FREQ_LIM T_PH_LOS DPLL_FREQ_SOFT_LIMT[6:0] P 94

66 DPLL_FREQ_HARD_LIMIT[7:0]_CNF

G - DPLL Hard Limit Configuration 1 DPLL_FREQ_HARD_LIMT[7:0] P 94

67 DPLL_FREQ_HARD_LIMIT[15:8]_CN

FG - DPLL Hard Limit Configuration 2 DPLL_FREQ_HARD_LIMT[15:8] P 94

68 CURRENT_DPLL_PHASE[7:0]_STS -

DPLL Current Phase Status 1 * CURRENT_PH_DATA[7:0] P 95

69 CURRENT_DPLL_PHASE[15:8]_STS

• DPLL Current Phase Status 2 * CURRENT_PH_DATA[15:8] P 95 6A T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration - - T0_APLL_BW[1:0] - - T4_APLL_BW[1:0] P 95 Output Configuration Registers 6D OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration OUT2_PATH_SEL[3:0] OUT2_DIVIDER[3:0] P 96

71 OUT1_FREQ_CNFG - Output Clock 1

Frequency Configuration OUT1_PATH_SEL[3:0] OUT1_DIVIDER[3:0] P 96

72 OUT1_INV_CNFG - Output Clock 1

73 OUT2_INV_CNFG - Output Clock 2

Invert Configuration ----- O U T 2 _ I N V -- P 9 7 FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configura- tion IN_2K_4K_ 8K_INV 8K_EN 2K_EN 2K_8K_PU L_POSITI ON 8K_INV 8K_PUL 2K_INV 2K_PUL P 98 PBO & Phase Offset Control Registers PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configura- tion IN_NOISE _WINDOW - PH_MON_ EN PH_MON_ PBO_EN PH_TR_MON_LIMT[3:0] P 99 7A PHASE_OFFSET[7:0]_CNFG - Phase Offset Configuration 1 PH_OFFSET[7:0] P 99 7B PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2 PH_OFFS ET_EN ----- P H _ O F F S E T [ 9 : 8 ] P 1 0 0 Synchronization Configuration Registers 7C SYNC_MONITOR_CNFG - Sync Mon- itor Configuration SYNC_BY PASS SYNC_MON_LIMT[2:0] - - - - P 101 Table 30: Register List and Map (Continued) Address (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 47 March 23, 2009

6.2 REGISTER DESCRIPTION

6.2.1 GLOBAL CONTROL REGISTERS

ID[7:0] - Device ID 1 ID[15:8] - Device ID 2 NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1 7D SYNC_PHASE_CNFG - Sync Phase Configuration - - SYNC_PH3[1:0] SYNC_PH2[ 1:0] SYNC_PH1[1:0] P 102 Table 30: Register List and Map (Continued) Address (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page Address: 00H Type: Read Default Value: 10001000 Bit Name Description 7 - 0 ID[7:0] Refer to the description of the ID[15:8] bits (b7~0, 01H). Address: 01H Type: Read Default Value: 00010001 Bit Name Description 7 - 0 ID[15:8] The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3352. Address: 04H Type: Read / Write Default Value: 00000000 Bit Name Description 7 - 0 NOMINAL_FREQ_VALUE[7:0] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H). 76543210 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 76543210 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 76543210 NOMINAL_FRE Q_VALUE7 NOMINAL_FRE Q_VALUE6 NOMINAL_FRE Q_VALUE5 NOMINAL_FRE Q_VALUE4 NOMINAL_FRE Q_VALUE3 NOMINAL_FRE Q_VALUE2 NOMINAL_FRE Q_VALUE1 NOMINAL_FRE Q_VALUE0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 48 March 23, 2009 NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2 NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3 Address: 05H Type: Read / Write Default Value: 00000000 Bit Name Description 7 - 0 NOMINAL_FREQ_VALUE[15:8] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H). Address: 06H Type: Read / Write Default Value: 00000000 Bit Name Description 7 - 0 NOMINAL_FREQ_VALUE[23:16] The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.0000884, the calibration value for the master clock in ppm will be gotten. For example, the frequency offset on OSCI is +3 ppm. Though -3 ppm should be compensated, the calibration value is calculated as +3 ppm: 3 ÷ 0.0000884 = 33937 (Dec.) = 8490 (Hex); So ‘008490’ should be written into these bits. The calibration range is within ±741 ppm. 76543210 NOMINAL_FRE Q_VALUE15 NOMINAL_FRE Q_VALUE14 NOMINAL_FRE Q_VALUE13 NOMINAL_FRE Q_VALUE12 NOMINAL_FRE Q_VALUE11 NOMINAL_FRE Q_VALUE10 NOMINAL_FRE Q_VALUE9 NOMINAL_FRE Q_VALUE8 76543210 NOMINAL_FRE Q_VALUE23 NOMINAL_FRE Q_VALUE22 NOMINAL_FRE Q_VALUE21 NOMINAL_FRE Q_VALUE20 NOMINAL_FRE Q_VALUE19 NOMINAL_FRE Q_VALUE18 NOMINAL_FRE Q_VALUE17 NOMINAL_FRE Q_VALUE16

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 49 March 23, 2009 PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration Address: 08H Type: Read / Write Default Value: 00110010 Bit Name Description 7 - 6 MULTI_FACTOR[1:0] These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the TIME_OUT_VALUE[5:0] bits (b5~0, 08H). 00: 2 (default) 01: 4 10: 8 11: 16 5 - 0 TIME_OUT_VALUE[5:0] These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0] bits (b7~6, 08H), a period in seconds will be gotten. A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the alarm is raised). 76543 2 1 0 MULTI_FACTO MULTI_FACTO TIME_OUT_VA LUE5 TIME_OUT_VA LUE4 TIME_OUT_VA LUE3 TIME_OUT_VA LUE2 TIME_OUT_VA LUE1 TIME_OUT_VAL UE0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 50 March 23, 2009 INPUT_MODE_CNFG - Input Mode Configuration Address: 09H Type: Read / Write Default Value: 10100X10 Bit Name Description 7 AUTO_EXT_SYNC_EN This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’. Refer to the description of the EXT_SYNC_EN bit (b6, 09H).

6 EXT_SYNC_EN

This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is ‘0’. This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether the selected frame sync input signal is enabled to synchronize the frame sync output signals.

5 PH_ALARM_TIMEOUT

This bit determines how to clear the phase lock alarm. 0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_CMOS_PH_LOCK_ALARM (n = 1, 2 or 3) / INn_DIFF_PH_LOCK_ALARM (n = 1 or 2) bit (b4/0, 44H/45H/47H). 1: The phase lock alarm will be cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. (default) 4 - 3 SYNC_FREQ[1:0] These bits set the frequency of the frame sync signals input on the EX_SYNC1 ~ EX_SYNC3 pins. 00: 8 kHz (default) 01: 8 kHz. 10: 4 kHz. 11: 2 kHz.

2 IN_SONET_SDH

This bit selects the SDH or SONET network type. 0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 16H, 17H, 19H, 1AH & 1DH) are ‘0001’ and the T0 DPLL output from the 16E1/16T1 path is 16E1. 1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 16H, 17H, 19H, 1AH & 1DH) are ‘0001’ and the T0 DPLL output from the 16E1/16T1 path is 16T1. The default value of this bit is determined by the SONET/ SDH pin during reset. 1- R e s e r v e d .

0 REVERTIVE_MODE

This bit selects Revertive or Non-Revertive switch for T0 path. 0: Non-Revertive switch. (default) 1: Revertive switch. 76543210 AUTO_EXT_SY NC_EN EXT_SYNC_EN PH_ALARM_TI MEOUT SYNC_FREQ1 SYNC_FREQ0 IN_SONET_SD H - REVERTIVE_M ODE AUTO_EXT_SYNC_EN EXT_SYN C_EN Synchronization don’t-care 0 Disabled (default)

11 D i s a b l e d

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 51 March 23, 2009 DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration Address: 0AH Type: Read / Write Default Value: XXXXX00X Bit Name Description 7 -3 - Reserved. 2O S C _ E D G E This bit selects a better active edge of the master clock. 0: The rising edge. (default) 1: The falling edge.

1 OUT1_PECL_LVDS

This bit selects a port technology for OUT1. 0: LVDS. (default) 1: PECL. 0- R e s e r v e d 7654 3 2 1 0 ---- - O S C _ E D G E O U T 1 _ P E C L _ L V D S -

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 52 March 23, 2009 MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control Address: 0BH Type: Read / Write Default Value: 100X01X1 Bit Name Description

7 FREQ_MON_CLK

The bit selects a reference clock for input clock frequency monitoring. 0: The output of T0 DPLL. 1: The master clock. (default)

6 LOS_FLAG_TO_TDO

The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin. 0: Not reported. TDO pin is used as JTAG test data output which complies with IEEE 1149.1. (default) 1: Reported. TDO pin mimics the state of the T0_MAIN_REF_FAILED bit (b6, 0EH) and does not strictly comply with IEEE 1149.1.

5 ULTR_FAST_SW

This bit determines whether the T0 selected input clock is valid when missing 2 consecutive clock cycles or more. 0: Valid. (default) 1: Invalid. 4E X T _ S W This bit determines the T0 input clock selection. 0: Forced selection or Automatic selection, as controlled by the T0_INPUT_SEL[3:0] bits (b3~0, 50H). 1: External Fast selection. The default value of this bit is determined by the FF_SRCSW pin during reset.

3 PBO_FREZ

This bit is valid only when the PBO is enabled by the PBO_EN bit (b2, 0BH). It determines whether PBO is frozen at the cur- rent phase offset when a PBO event is triggered. 0: Not frozen. (default) 1: Frozen. Further PBO events are ignored and the current phase offset is maintained.

2 PBO_EN

This bit determines whether PBO is enabled when the T0 selected input clock switch or the T0 DPLL exiting from Holdover mode or Free-Run mode occurs. 0: Disabled. 1: Enabled. (default) 1- R e s e r v e d .

0 FREQ_MON_HARD_EN

This bit determines whether the frequency hard alarm is enabled when the frequency of the input clock with respect to the reference clock is above the frequency hard alarm threshold. The reference clock can be the output of T0 DPLL or the mas- ter clock, as determined by the FREQ_MON_CLK bit (b7, 0BH). 0: Disabled. 1: Enabled. (default) 76 5 43210 FREQ_MON_C LK LOS_FLAG_TO _TDO ULTR_FAST_SW EXT_SW PBO_FREZ PBO_EN - FREQ_MON_H ARD_EN

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 53 March 23, 2009 PROTECTION_CNFG - Register Protection Mode Configuration Address: 7EH Type: Read / Write Default Value: 10000101 Bit Name Description 7 - 0 PROTECTION_DATA[7:0] These bits select a register write protection mode. 00000000 - 10000100, 10000111 - 11111111: Protected mode. No other registers can be written except this register. 10000101: Fully Unprotected mode. All the writable registers can be written. (default) 10000110: Single Unprotected mode. One more register can be written besides this register. After write operation (not including writing a ‘1’ to clear the bit to ‘0’), the device automatically switches to Protected mode. 76543210 PROTECTION_ DATA7 PROTECTION_ DATA6 PROTECTION_ DATA5 PROTECTION_ DATA4 PROTECTION_ DATA3 PROTECTION_ DATA2 PROTECTION_ DATA1 PROTECTION_ DATA0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 54 March 23, 2009

6.2.2 INTERRUPT REGISTERS

INTERRUPT_CNFG - Interrupt Configuration INTERRUPTS1_STS - Interrupt Status 1 Address: 0CH Type: Read / Write Default Value: XXXXXX10 Bit Name Description 7 - 2 - Reserved. 1H Z _ E N This bit determines the output characteristics of the INT_REQ pin. 0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive. 1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt is inactive. (default) 0I N T _ P O L This bit determines the active level on the INT_REQ pin for an active interrupt indication. 0: Active low. (default) 1: Active high. Address: 0DH Type: Read / Write Default Value: XX1111XX Bit Name Description 7 - 6 - Reserved. 5 - 4 INn_DIFF This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn_DIFF; i.e., whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn_DIFF bit (b5/4, 4AH). Here n is 2 or 1. 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a ‘1’. 3 - 2 INn_CMOS This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn_CMOS; i.e., whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn_CMOS bit (b3/2, 4AH). Here n is 2 or 1. 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a ‘1’. 1 - 0 - Reserved. 76543210 76543210 - - IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS - -

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 55 March 23, 2009 INTERRUPTS2_STS - Interrupt Status 2 INTERRUPTS3_STS - Interrupt Status 3 Address: 0EH Type: Read / Write Default Value: 00XXXXX1 Bit Name Description

7 T0_OPERATING_MODE

This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes. 0: Has not switched. (default) 1: Has switched. This bit is cleared by writing a ‘1’.

6 T0_MAIN_REF_FAILED

This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn_CMOS / INn_DIFF bit (4AH, 4BH). 0: Has not failed. (default) 1: Has failed. This bit is cleared by writing a ‘1’. 5 - 1 - Reserved. 0I N 3 _ C M O S This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for IN3_CMOS for T0 path, i.e., whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding IN3_CMOS bit (b0, 4BH). 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a ‘1’. Address: 0FH Type: Read / Write Default Value: 11X1XXXX Bit Name Description

7 EX_SYNC_ALARM

This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the EX_SYNC_ALARM_MON bit (b7, 52H). 0: Has not occurred. 1: Has occurred. (default) This bit is cleared by writing a ‘1’. 6-0 - Reserved. 7 6 543210 T0_OPERATING _MODE T0_MAIN_REF_F AILED ----- I N 3 _ C M O S 7 6543210

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 56 March 23, 2009 INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1 INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2 Address: 10H Type: Read / Write Default Value: XX0000XX Bit Name Description 7 - 6 - Reserved. 5 - 4 INn_DIFF This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (fro m ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn_DIFF bit (b5/4, 0DH) is ‘1’. Here n is 2 or 1. 0: Disabled. (default) 1: Enabled. 3 - 2 INn_CMOS This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (fro m ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn_CMOS bit (b3/2, 0DH) is ‘1’. Here n is 2 or 1. 0: Disabled. (default) 1: Enabled. 1 - 0 - Reserved. Address: 11H Type: Read / Write Default Value:00XXXXX0 Bit Name Description This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’. 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’. 0: Disabled. (default) 1: Enabled. 5 - 1 - Reserved. 0I N 3 _ C M O S This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding IN3_CMOS bit (b0, 0EH) is ‘1’. 0: Disabled. (default) 1: Enabled. 76543210 - - IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS - - 7 6 543210 T0_OPERATING _MODE T0_MAIN_REF_F AILED ----- I N 3 _ C M O S

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 57 March 23, 2009 INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3 Address: 12H Type: Read / Write Default Value: 00X0XXXX Bit Name Description This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’. 0: Disabled. (default) 1: Enabled. 6 - 0 - Reserved. 7 6543210

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 58 March 23, 2009

6.2.3 INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS

IN1_CMOS_CNFG - CMOS Input Clock 1 Configuration Address: 16H Type: Read / Write Default Value: 00000000 Bit Name Description 7 DIRECT_DIV Refer to the descript ion of the LOCK_8K bit (b6, 16H). 6L O C K _ 8 K This bit, together with the DIRECT_DIV bit (b7, 16H), determine s whether the DivN Divider or the Lock 8k Divider is used for IN1_CMOS: 5 - 4 BUCKET_SEL[1:0] These bits select one of the four groups of leaky bucket configuration registers for IN1_CMOS: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. 3 - 0 IN_FREQ[3:0] These bits set the DPLL required frequency for IN1_CMOS: 0000: 8 kHz. (default) 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. 0100: 25.92 MHz. 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN1_CMOS, the required frequency should not be set higher than that of the input clock. 76543210 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL 0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 Both bypassed (default) 0 1 Lock 8k Divider

10 D i v N D i v i d e r

11 R e s e r v e d

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 59 March 23, 2009 IN2_CMOS_CNFG - CMOS Input Clock 2 Configuration Address: 17H Type: Read / Write Default Value: 00000000 Bit Name Description 7 DIRECT_DIV Refer to the descript ion of the LOCK_8K bit (b6, 17H). 6L O C K _ 8 K This bit, together with the DIRECT_DIV bit (b7, 17H), determines whether the DivN Divider or the Lock 8k Divider is used for IN2_CMOS: 5 - 4 BUCKET_SEL[1:0] These bits select one of the four groups of leaky bucket configuration registers for IN2_CMOS: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. 3 - 0 IN_FREQ[3:0] These bits set the DPLL required frequency for IN2_CMOS: 0000: 8 kHz. (default) 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. 0100: 25.92 MHz. 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For the IN2_CMOS, the required frequency should not be set higher than that of the input clock. 76543210 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL 0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 Both bypassed (default) 0 1 Lock 8k Divider

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 60 March 23, 2009 IN1_IN2_DIFF_HF_DIV_CNFG - Differential Input Clock 1 & 2 High Frequency Divider Configuration Address: 18H Type: Read / Write Default Value: 00XXXX00 Bit Name Description 7 - 6 IN2_DIFF_DIV[1:0] These bits determine whether the HF Divider is used and what the division factor is for IN2_DIFF frequency division: 00: Bypassed. (default) 01: Divided by 4. 10: Divided by 5. 11: Reserved. 5 - 2 - Reserved. 1 - 0 IN1_DIFF_DIV[1:0] These bits determine whether the HF Divider is used and what the division factor is for IN1_DIFF frequency division: 00: Bypassed. (default) 01: Divided by 4. 10: Divided by 5. 11: Reserved. 76543210 IN2_DIFF_DIV1 IN2_DIFF_DIV0 - - - - IN1_DIFF_DIV1 IN1_DIFF_DIV0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 61 March 23, 2009 IN1_DIFF_CNFG - Differential Input Clock 1 Configuration Address: 19H Type: Read / Write Default Value: 00000011 Bit Name Description 7 DIRECT_DIV Refer to the descript ion of the LOCK_8K bit (b6, 19H). 6L O C K _ 8 K This bit, together with the DIRECT_DIV bit (b7, 19H), determines whether the DivN Divider or the Lock 8k Divider is used for IN1_DIFF: 5 - 4 BUCKET_SEL[1:0] These bits select one of the four groups of leaky bucket configuration registers for IN1_DIFF: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. 3 - 0 IN_FREQ[3:0] These bits set the DPLL required frequency for IN1_DIFF: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. The required frequency should not be set higher than that of the input clock. 76543210 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL 0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 Both bypassed (default) 0 1 Lock 8k Divider

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 62 March 23, 2009 IN2_DIFF_CNFG - Differential Input Clock 2 Configuration Address: 1AH Type: Read / Write Default Value: 00000011 Bit Name Description 7 DIRECT_DIV Refer to the descriptio n of the LOCK_8K bit (b6, 1AH). 6L O C K _ 8 K This bit, together with the DIRECT_DIV bit (b7, 1AH), determine s whether the DivN Divider or the Lock 8k Divider is used for IN2_DIFF: 5 - 4 BUCKET_SEL[1:0] These bits select one of the four groups of leaky bucket configuration registers for IN2_DIFF: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. 3 - 0 IN_FREQ[3:0] These bits set the DPLL required frequency for IN2_DIFF: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN2_DIFF, the required frequency should not be set higher than that of the input clock. 76543210 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL 0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 Both bypassed (default) 0 1 Lock 8k Divider

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 63 March 23, 2009 IN3_CMOS_CNFG - CMOS Input Clock 3 Configuration Address: 1DH Type: Read / Write Default Value: 00000011 Bit Name Description 7 DIRECT_DIV Refer to the descriptio n of the LOCK_8K bit (b6, 1DH). 6L O C K _ 8 K This bit, together with the DIRECT_DIV bit (b7, 1DH), determines whether the DivN Divider or the Lock 8k Divider is used for IN3_CMOS: 5 - 4 BUCKET_SEL[1:0] These bits select one of the four groups of leaky bucket configuration registers for IN3_CMOS: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. 3 - 0 IN_FREQ[3:0] These bits set the DPLL required frequency for IN3_CMOS: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN3_CMOS, the required frequency should not be set higher than that of the input clock. 76543210 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL 0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 Both bypassed (default) 0 1 Lock 8k Divider

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 64 March 23, 2009 PRE_DIV_CH_CNFG - DivN Divider Channel Selection PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1 Address: 23H Type: Read / Write Default Value: XXXX0000 Bit Name Description 7 - 4 - Reserved. 3 - 0 PRE_DIV_CH_VALUE[3:0] This register is an indirect address register for Register 24H and 25H. These bits select an input clock. The value set in the PRE_DIVN_VALUE[14:0] bits (25H, 24H) is available for the selected input clock. 0000: Reserved. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. 0100: IN2_CMOS. 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. Address: 24H Type: Read / Write Default Value: 00000000 Bit Name Description 7 - 0 PRE_DIVN_VALUE[7:0] Refer to the description of the PRE_DIVN_VALUE[14:8] bits (b6~0, 25H). 7654 3 2 1 0 - - - - PRE_DIV_CH_VALUE3 PRE _DIV_CH_VALUE2 PR E_DIV_CH_VALUE1 PRE_DIV_CH_VALUE0 76543210 PRE_DIVN_VA LUE7 PRE_DIVN_VA LUE6 PRE_DIVN_VA LUE5 PRE_DIVN_VA LUE4 PRE_DIVN_VA LUE3 PRE_DIVN_VA LUE2 PRE_DIVN_VA LUE1 PRE_DIVN_VA LUE0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 65 March 23, 2009 PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2 Address: 25H Type: Read / Write Default Value: X0000000 Bit Name Description 7- R e s e r v e d . 6 - 0 PRE_DIVN_VALUE[14:8] If the value in the PRE_DIVN_VALUE[14:0] bits is plus 1, the division factor for an input clock will be gotten. The input clock is selected by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H). A value from ‘0’ to ‘4BEF’ (Hex) can be written into, corresponding to a division factor from 1 to 19440. The others are reserved. So the DivN Divider only supports an input clock whose frequency is lower than (<) 155.52 MHz. The division factor setting should observe the following order: 1. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits; 2. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits. 7 6543210 - PRE_DIVN_VAL UE14 PRE_DIVN_VAL UE13 PRE_DIVN_VAL UE12 PRE_DIVN_VAL UE11 PRE_DIVN_VAL UE10 PRE_DIVN_VAL UE9 PRE_DIVN_VAL UE8

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 66 March 23, 2009 IN1_IN2_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 1 & 2 Priority Configuration * Address: 27H Type: Read / Write Default Value: 00110010 Bit Name Description 7 - 4 INn_CMOS_SEL_PRIORITY[3:0] These bits set the priority of the corresponding INn_CMOS. Here n is 2. 0000: Disable INn_CMOS for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. (default) 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. 3 - 0 INn_CMOS_SEL_PRIORITY[3:0] These bits set the priority of the corresponding INn_CMOS. Here n is 1. 0000: Disable INn_CMOS for automatic selection. 0001: Priority 1. 0010: Priority 2. (default) 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. 76543210 IN2_CMOS_SE L_PRIORITY3 IN2_CMOS_SE L_PRIORITY2 IN2_CMOS_SE L_PRIORITY1 IN2_CMOS_SE L_PRIORITY0 IN1_CMOS_SE L_PRIORITY3 IN1_CMOS_SE L_PRIORITY2 IN1_CMOS_SE L_PRIORITY1 IN1_CMOS_SE L_PRIORITY0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 67 March 23, 2009 IN1_IN2_DIFF_SEL_PRIORITY_CNFG - Differential Input Clock 1 & 2 Priority Configuration * Address: 28H Type: Read / Write Default Value: 00000000 Bit Name Description 7 - 4 INn_DIFF_SEL_PRIORITY[3:0] These bits set the priority of the corresponding INn_DIFF. Here n is 2. 0000: Disable INn_DIFF for automatic selection. (default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. 3 - 0 INn_DIFF_SEL_PRIORITY[3:0] These bits set the priority of the corresponding INn_DIFF. Here n is 1. 0000: Disable INn_DIFF for automatic selection. (default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. 76543210 IN2_DIFF_SEL_ PRIORITY3 IN2_DIFF_SEL_ PRIORITY2 IN2_DIFF_SEL_ PRIORITY1 IN2_DIFF_SEL_ PRIORITY0 IN1_DIFF_SEL_ PRIORITY3 IN1_DIFF_SEL_ PRIORITY2 IN1_DIFF_SEL_ PRIORITY1 IN1_DIFF_SEL_ PRIORITY0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 68 March 23, 2009 IN3_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 3 Priority Configuration * Address: 2AH Type: Read / Write Default Value: XXXX0100 Bit Name Description 7 - 4 - Reserved. 3 - 0 IN3_CMOS_SEL_PRIORITY[3:0] These bits set the priority of the corresponding IN3_CMOS. 0000: Disable INn for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. (default) 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. 76543210 ---- IN3_CMOS_SE L_PRIORITY3 IN3_CMOS_SE L_PRIORITY2 IN3_CMOS_SE L_PRIORITY1 IN3_CMOS_SE L_PRIORITY0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 69 March 23, 2009

6.2.4 INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS

FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration ALL_FREQ_MON_THRESHOLD_CNFG - Frequency Monitor Threshold for All Input Clocks Configuration Address: 2EH Type: Read / Write Default Value: XXXX1011 Bit Name Description 7 - 4 - Reserved. 3 - 0 FREQ_MON_FACTOR[3:0] These bits determine a factor. The factor has a relationship with the frequency hard alarm threshold in ppm (refer to the description of the ALL_FREQ_HARD_THRESHOLD[3:0] bi ts (b3~0, 2FH)) and with the frequency of the input clock with respect to the master clock in ppm (refer to the description of the IN_FREQ_VALUE[7:0] bits (b7~0, 42H)). The factor represents the accuracy of the frequency monitor and should be set according to the requirements of differ- ent applications. 0000: 0.0032. 0001: 0.0064. 0010: 0.0127. 0011: 0.0257. 0100: 0.0514. 0101: 0.103. 0110: 0.206. 0111: 0.412. 1000: 0.823. 1001: 1.646. 1010: 3.292. 1011: 3.81. (default) 1100 - 1111: 4.6. Address: 2FH Type: Read / Write Default Value: XXXX0011 Bit Name Description 7 - 4 - Reserved. 3 - 0 ALL_FREQ_HARD_THRESHOLD[3:0] These bits represent an unsigned integer. The frequency hard alarm threshold in ppm can be calculated as follows: Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0] (b3~0, 2EH) This threshold is symmetrical about zero. 76543210 ---- FREQ_MON_F ACTOR3 FREQ_MON_F ACTOR2 FREQ_MON_F ACTOR1 FREQ_MON_F ACTOR0 7654 3210 ---- ALL_FREQ_HARD_ THRESHOLD3 ALL_FREQ_HARD_ THRESHOLD2 ALL_FREQ_HARD_ THRESHOLD1 ALL_FREQ_HARD_ THRESHOLD0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 70 March 23, 2009 UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0 LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket Configuration 0 BUCKET_SIZE_0_CNFG - Bucket Size for Leaky Bucket Configuration 0 Address: 31H Type: Read / Write Default Value: 00000110 Bit Name Description 7 - 0 UPPER_THRESHOLD_0_DATA[7:0] These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumu- lated events is above this threshold, a no-activity alarm is raised. Address: 32H Type: Read / Write Default Value: 00000100 Bit Name Description 7 - 0 LOWER_THRESHOLD_0_DATA[7:0] These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared. Address: 33H Type: Read / Write Default Value: 00001000 Bit Name Description 7 - 0 BUCKET_SIZE_0_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. 76543210 UPPER_THRE SHOLD_0_DAT UPPER_THRE SHOLD_0_DAT UPPER_THRE SHOLD_0_DAT UPPER_THRE SHOLD_0_DAT UPPER_THRE SHOLD_0_DAT UPPER_THRE SHOLD_0_DAT UPPER_THRE SHOLD_0_DAT UPPER_THRE SHOLD_0_DAT 76543210 LOWER_THRE SHOLD_0_DAT LOWER_THRE SHOLD_0_DAT LOWER_THRE SHOLD_0_DAT LOWER_THRE SHOLD_0_DAT LOWER_THRE SHOLD_0_DAT LOWER_THRE SHOLD_0_DAT LOWER_THRE SHOLD_0_DAT LOWER_THRE SHOLD_0_DAT 76543210 BUCKET_SIZE _0_DATA7 BUCKET_SIZE _0_DATA6 BUCKET_SIZE _0_DATA5 BUCKET_SIZE _0_DATA4 BUCKET_SIZE _0_DATA3 BUCKET_SIZE _0_DATA2 BUCKET_SIZE _0_DATA1 BUCKET_SIZE _0_DATA0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 71 March 23, 2009 DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0 UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket Configuration 1 LOWER_THRESHOLD_1_CNFG - Lower Threshold for Leaky Bucket Configuration 1 Address: 34H Type: Read / Write Default Value: XXXXXX01 Bit Name Description 7 - 2 - Reserved. 1 - 0 DECAY_RATE_0_DATA[1:0] These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. Address: 35H Type: Read / Write Default Value: 00000110Bit Name Description 7 - 0 UPPER_THRESHOLD_1_DATA[7:0] These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumu- lated events is above this threshold, a no-activity alarm is raised. Address: 36H Type: Read / Write Default Value: 00000100 Bit Name Description 7 - 0 LOWER_THRESHOLD_1_DATA[7:0] These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared. 76543210 0_DATA1 DECAY_RATE_ 0_DATA0 76543210 UPPER_THRE SHOLD_1_DAT UPPER_THRE SHOLD_1_DAT UPPER_THRE SHOLD_1_DAT UPPER_THRE SHOLD_1_DAT UPPER_THRE SHOLD_1_DAT UPPER_THRE SHOLD_1_DAT UPPER_THRE SHOLD_1_DAT UPPER_THRE SHOLD_1_DAT 76543210 LOWER_THRE SHOLD_1_DAT LOWER_THRE SHOLD_1_DAT LOWER_THRE SHOLD_1_DAT LOWER_THRE SHOLD_1_DAT LOWER_THRE SHOLD_1_DAT LOWER_THRE SHOLD_1_DAT LOWER_THRE SHOLD_1_DAT LOWER_THRE SHOLD_1_DAT

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 72 March 23, 2009 BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1 DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration 1 UPPER_THRESHOLD_2_CNFG - Upper Threshold for Leaky Bucket Configuration 2 Address: 37H Type: Read / Write Default Value: 00001000 Bit Name Description 7 - 0 BUCKET_SIZE_1_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. Address: 38H Type: Read / Write Default Value: XXXXXX01 Bit Name Description 7 - 2 - Reserved. 1 - 0 DECAY_RATE_1_DATA[1:0] These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. Address: 39H Type: Read / Write Default Value: 00000110Bit Name Description 7 - 0 UPPER_THRESHOLD_2_DATA[7:0] These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumu- lated events is above this threshold, a no-activity alarm is raised. 76543210 BUCKET_SIZE _1_DATA7 BUCKET_SIZE _1_DATA6 BUCKET_SIZE _1_DATA5 BUCKET_SIZE _1_DATA4 BUCKET_SIZE _1_DATA3 BUCKET_SIZE _1_DATA2 BUCKET_SIZE _1_DATA1 BUCKET_SIZE _1_DATA0 76543210 1_DATA1 DECAY_RATE_ 1_DATA0 76543210 UPPER_THRE SHOLD_2_DAT UPPER_THRE SHOLD_2_DAT UPPER_THRE SHOLD_2_DAT UPPER_THRE SHOLD_2_DAT UPPER_THRE SHOLD_2_DAT UPPER_THRE SHOLD_2_DAT UPPER_THRE SHOLD_2_DAT UPPER_THRE SHOLD_2_DAT

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 73 March 23, 2009 LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2 BUCKET_SIZE_2_CNFG - Bucket Size for Leaky Bucket Configuration 2 DECAY_RATE_2_CNFG - Decay Rate for Leaky Bucket Configuration 2 Address: 3AH Type: Read / Write Default Value: 00000100 Bit Name Description 7 - 0 LOWER_THRESHOLD_2_DATA[7:0] These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumu- lated events is below this threshold, the no-activity alarm is cleared. Address: 3BH Type: Read / Write Default Value: 00001000 Bit Name Description 7 - 0 BUCKET_SIZE_2_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. Address: 3CH Type: Read / Write Default Value: XXXXXX01 Bit Name Description 7 - 2 - Reserved. 1 - 0 DECAY_RATE_2_DATA[1:0] These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. 76543210 LOWER_THRE SHOLD_2_DAT LOWER_THRE SHOLD_2_DAT LOWER_THRE SHOLD_2_DAT LOWER_THRE SHOLD_2_DAT LOWER_THRE SHOLD_2_DAT LOWER_THRE SHOLD_2_DAT LOWER_THRE SHOLD_2_DAT LOWER_THRE SHOLD_2_DAT 76543210 BUCKET_SIZE _2_DATA7 BUCKET_SIZE _2_DATA6 BUCKET_SIZE _2_DATA5 BUCKET_SIZE _2_DATA4 BUCKET_SIZE _2_DATA3 BUCKET_SIZE _2_DATA2 BUCKET_SIZE _2_DATA1 BUCKET_SIZE _2_DATA0 7654321 0 2_DATA1 DECAY_RATE_ 2_DATA0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 74 March 23, 2009 UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3 LOWER_THRESHOLD_3_CNFG - Lower Threshold for Leaky Bucket Configuration 3 BUCKET_SIZE_3_CNFG - Bucket Size for Leaky Bucket Configuration 3 Address: 3DH Type: Read / Write Default Value: 00000110 Bit Name Description 7 - 0 UPPER_THRESHOLD_3_DATA[7:0] These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumu- lated events is above this threshold, a no-activity alarm is raised. Address: 3EH Type: Read / Write Default Value: 00000100 Bit Name Description 7 - 0 LOWER_THRESHOLD_3_DATA[7:0] These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumu- lated events is below this threshold, the no-activity alarm is cleared. Address: 3FH Type: Read / Write Default Value: 00001000 Bit Name Description 7 - 0 BUCKET_SIZE_3_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. 76543210 UPPER_THRE SHOLD_3_DAT UPPER_THRE SHOLD_3_DAT UPPER_THRE SHOLD_3_DAT UPPER_THRE SHOLD_3_DAT UPPER_THRE SHOLD_3_DAT UPPER_THRE SHOLD_3_DAT UPPER_THRE SHOLD_3_DAT UPPER_THRE SHOLD_3_DAT 76543210 LOWER_THRE SHOLD_3_DAT LOWER_THRE SHOLD_3_DAT LOWER_THRE SHOLD_3_DAT LOWER_THRE SHOLD_3_DAT LOWER_THRE SHOLD_3_DAT LOWER_THRE SHOLD_3_DAT LOWER_THRE SHOLD_3_DAT LOWER_THRE SHOLD_3_DAT 76543210 BUCKET_SIZE _3_DATA7 BUCKET_SIZE _3_DATA6 BUCKET_SIZE _3_DATA5 BUCKET_SIZE _3_DATA4 BUCKET_SIZE _3_DATA3 BUCKET_SIZE _3_DATA2 BUCKET_SIZE _3_DATA1 BUCKET_SIZE _3_DATA0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 75 March 23, 2009 DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3 IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection Address: 40H Type: Read / Write Default Value: XXXXXX01 Bit Name Description 7 - 2 - Reserved. 1 - 0 DECAY_RATE_3_DATA[1:0] These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. Address: 41H Type: Read / Write Default Value: XXXX0000Bit Name Description 7 - 4 - Reserved. 3 - 0 IN_FREQ_READ_CH[3:0] These bits select an input clock, the frequency of which with respect to the reference clock can be read. 0000: Reserved. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. 0100: IN2_CMOS. 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. 76543210 3_DATA1 DECAY_RATE_ 3_DATA0 7654 3 2 1 0 ---- IN_FREQ_READ _CH3 IN_FREQ_READ _CH2 IN_FREQ_READ _CH1 IN_FREQ_READ _CH0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 76 March 23, 2009 IN_FREQ_READ_STS - Input Clock Frequency Read Value Address: 42H Type: Read Default Value: 00000000 Bit Name Description 7 - 0 IN_FREQ_VALUE[7:0] These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will be gotten. The input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H). The value in these bits is updated every 16 seconds, starting when an input clock is selected. 76543210 IN_FREQ_VAL UE7 IN_FREQ_VAL UE6 IN_FREQ_VAL UE5 IN_FREQ_VAL UE4 IN_FREQ_VAL UE3 IN_FREQ_VAL UE2 IN_FREQ_VAL UE1 IN_FREQ_VAL UE0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 77 March 23, 2009 IN1_IN2_CMOS_STS - CMOS Input Clock 1 & 2 Status Address: 44H Type: Read Default Value: X110X110 Bit Name Description 7 - Reserved.

6 IN2_CMOS_FREQ _HARD_ALARM

This bit indicates whether IN2_CMOS is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default)

5 IN2_CMOS_NO_ACTIVITY_ALARM

This bit indicates whether IN2_CMOS is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default)

4 IN2_CMOS_PH_LOCK_ALARM

This bit indicates whether IN2_CMOS is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. 3 - Reserved.

2 IN1_CMOS_FREQ _HARD_ALARM

This bit indicates whether IN1_CMOS is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default)

1 IN1_CMOS_NO_ACTIVITY_ALARM

This bit indicates whether IN1_CMOS is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default)

0 IN1_CMOS_PH_LOCK_ALARM

This bit indicates whether IN1_CMOS is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. 7 654 3 210 IN2_CMOS_FRE Q_HARD_ALAR M IN2_CMOS_NO_ ACTIVITY_ALAR M IN2_CMOS_PH_ LOCK_ALARM - IN1_CMOS_FRE Q_HARD_ALAR M IN1_CMOS_NO_ ACTIVITY_ALAR M IN1_CMOS_PH_ LOCK_ALARM

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 78 March 23, 2009 IN1_IN2_DIFF_STS - Differential Input Clock 1 & 2 Status Address: 45H Type: Read Default Value: X110X110 Bit Name Description 7- R e s e r v e d .

6 IN2_DIFF_FREQ_HARD_ALARM

This bit indicates whether IN2_DIFF is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default)

5 IN2_DIFF_NO_ACTIVITY_ALARM

This bit indicates whether IN2_DIFF is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default)

4 IN2_DIFF_PH_LOCK_ALARM

This bit indicates whether IN2_DIFF is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. 3- R e s e r v e d .

2 IN1_DIFF_FREQ_HARD_ALARM

This bit indicates whether IN1_DIFF is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default)

1 IN1_DIFF_NO_ACTIVITY_ALARM

This bit indicates whether IN1_DIFF is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default)

0 IN1_DIFF_PH_LOCK_ALARM

This bit indicates whether IN1_DIFF is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. 7 654 3 210 - IN2_DIFF_FREQ _HARD_ALARM IN2_DIFF_NO_A CTIVITY_ALARM IN2_DIFF_PH_L OCK_ALARM - IN1_DIFF_FREQ _HARD_ALARM IN1_DIFF_NO_A CTIVITY_ALARM IN1_DIFF_PH_L OCK_ALARM

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 79 March 23, 2009 IN3_CMOS_STS - CMOS Input Clock 3 Status Address: 47H Type: Read Default Value: XXXXX110 Bit Name Description 7 - 3 - Reserved.

2 IN3_CMOS_FREQ_HARD_ALARM

This bit indicates whether IN3_CMOS is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default)

1 IN3_CMOS_NO_ACTIVITY_ALARM

This bit indicates whether IN3_CMOS is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default)

0 IN3_CMOS_PH_LOCK_ALARM

This bit indicates whether IN3_CMOS is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period ( = TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. 7 6 5 4 3 210 -- - -- IN3_CMOS_FRE Q_HARD_ALAR M IN3_CMOS_NO_ ACTIVITY_ALAR M IN3_CMOS_PH_ LOCK_ALARM

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 80 March 23, 2009

6.2.5 T0 DPLL INPUT CLOCK SELECTION REGISTERS

INPUT_VALID1_STS - Input Clocks Validity 1 INPUT_VALID2_STS - Input Clocks Validity 2 Address: 4AH Type: Read Default Value: XX0000XX Bit Name Description 7 - 6 - Reserved. 5 - 4 INn_DIFF This bit indicates the validity of the corresponding INn_DIFF. Here n is 2 or 1. 0: Invalid. (default) 1: Valid. 3 - 2 INn_CMOS This bit indicates the validity of the corresponding INn_CMOS. Here n is 2 or 1. 0: Invalid. (default) 1: Valid. 1 - 0 - Reserved. Address: 4BH Type: Read Default Value: XXXXXXX0 Bit Name Description 7 - 1 - Reserved. 0I N 3 _ C M O S This bit indicates the validity of the corresponding IN3_CMOS. 0: Invalid. (default) 1: Valid. 76543210 - - IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS - - 76543210

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 81 March 23, 2009 PRIORITY_TABLE1_STS - Priority Status 1 * Address: 4EH Type: Read Default Value: 00000000 Bit Name Description 7 - 4 HIGHEST_PRIORITY_VALIDATED[3:0] These bits indicate a qualified input clock with the highest priority. 0000: No input clock is qualified. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. 0100: IN2_CMOS. 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. 3 - 0 CURRENTLY_SELECTED_INPUT[3:0] These bits indicate the selected input clock. 0000: No input clock is selected. (default) 0001, 0010: Reserved. 0011: IN1_CMOS is selected. 0100: IN2_CMOS is selected. 0101: IN1_DIFF is selected. 0110: IN2_DIFF is selected. 0111, 1000: Reserved. 1001: IN3_CMOS is selected. 1010 ~ 1111: Reserved. 76543210 HIGHEST_PRI ORITY_VALIDA TED3 HIGHEST_PRI ORITY_VALIDA TED2 HIGHEST_PRI ORITY_VALIDA TED1 HIGHEST_PRI ORITY_VALIDA TED0 CURRENTLY_S ELECTED_INP UT3 CURRENTLY_S ELECTED_INP UT2 CURRENTLY_S ELECTED_INP UT1 CURRENTLY_S ELECTED_INP UT0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 82 March 23, 2009 PRIORITY_TABLE2_STS - Priority Status 2 * T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration Address: 4FH Type: Read Default Value: 00000000 Bit Name Description 7 - 4 THIRD_HIGHEST_PRIORITY_VALIDATED[3:0] These bits indicate a qualified input clock with the third highest priority. 0000: No input clock is qualified. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. 0100: IN2_CMOS. 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. 3 - 0 SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] These bits indicate a qualified input clock with the second highest priority. 0000: No input clock is qualified. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. 0100: IN2_CMOS. 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. Address: 50H Type: Read / Write Default Value: XXXX0000 Bit Name Description 7 - 4 - Reserved. 3 - 0 T0_INPUT_SEL[3:0] This bit determines T0 input clock selection. It is valid only when the EXT_SW bit (b4, 0BH) is ‘0’. 0000: Automatic selection. (default) 0001, 0010: Reserved. 0011: Forced selection - IN1_CMOS is selected. 0100: Forced selection - IN2_CMOS is selected. 0101: Forced selection - IN1_DIFF is selected. 0110: Forced selection - IN2_DIFF is selected. 0111, 1000: Reserved. 1001: Forced selection - IN3_CMOS is selected. 1010 ~ 1111: Reserved. 76543210 THIRD_HIGHE ST_PRIORITY_ VALIDATED3 THIRD_HIGHE ST_PRIORITY_ VALIDATED2 THIRD_HIGHE ST_PRIORITY_ VALIDATED1 THIRD_HIGHE ST_PRIORITY_ VALIDATED0 SECOND_HIGH EST_PRIORITY _VALIDATED3 SECOND_HIGH EST_PRIORITY _VALIDATED2 SECOND_HIGH EST_PRIORITY _VALIDATED1 SECOND_HIGH EST_PRIORITY _VALIDATED0 7654 3 2 1 0 - - - - T0_INPUT_SEL3 T0_INPUT_SEL2 T0_INPUT_SEL1 T0_INPUT_SEL0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 83 March 23, 2009

6.2.6 T0 DPLL STATE MACHINE CONTROL REGISTERS

OPERATING_STS - DPLL Operating Status Address: 52H Type: Read Default Value: 10000001 Bit Name Description

7 EX_SYNC_ALARM_MON

This bit indicates whether the selected frame sync input signal is in external sync alarm status. 0: No external sync alarm. 1: In external sync alarm status. (default) 6 - Reserved.

5 T0_DPLL_SOFT_FREQ_ALARM

This bit indicates whether the T0 DPLL is in soft alarm status. 0: No T0 DPLL soft alarm. (default) 1: In T0 DPLL soft alarm status. 4 - Reserved.

3 T0_DPLL_LOCK

This bit indicates the T0 DPLL locking status. 0: Unlocked. (default) 1: Locked. 2 - 0 T0_DPLL_OPERATING_MODE[2:0] These bits indicate the current operating mode of T0 DPLL. 000: Reserved. 001: Free-Run. (default) 010: Holdover. 011: Reserved. 100: Locked. 101: Pre-Locked2. 110: Pre-Locked. 111: Lost-Phase. 7 6 54 3 210 EX_SYNC_ALA RM_MON - T0_DPLL_SOFT _FREQ_ALARM - T0_DPLL_LO CK T0_DPLL_OPER ATING_MODE2 T0_DPLL_OPER ATING_MODE1 T0_DPLL_OPER ATING_MODE0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 84 March 23, 2009 T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration Address: 53H Type: Read / Write Default Value: XXXXX000 Bit Name Description 7 - 3 - Reserved. 2 - 0 T0_OPERATING_MODE[2:0] These bits control the T0 DPLL operating mode. 000: Automatic. (default) 001: Forced - Free-Run. 010: Forced - Holdover. 011: Reserved. 100: Forced - Locked. 101: Forced - Pre-Locked2. 110: Forced - Pre-Locked. 111: Forced - Lost-Phase. 76543 2 1 0 ----- T 0 _ O P E R A T I N G _ M O D E 2 T0_OPERATING_MODE1 T 0_OPERATING_MODE0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 85 March 23, 2009

6.2.7 T0 DPLL & APLL CONFIGURATION REGISTERS

T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration Address: 55H Type: Read / Write Default Value: 00000X0X Bit Name Description 7 - 4 T0_APLL_PATH[3:0] These bits select an input to the T0 APLL. 0000: The output of T0 DPLL 77.76 MHz path. (default) 0001: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0010: The output of T0 DPLL 16E1/16T1 path. 0011: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path. 0100~1XXX: Reserved. 3 - 2 T0_ETH_OBSAI_ 16E1_16T1_SEL[1:0] These bits select an output clock from the T0 DPLL ETH/OBSAI/16E1/16T1 path. 00: 16E1. 01: 16T1. 10: ETH. 11: OBSAI. The default value of the T0_ETH_OBSAI_16E1_16T1_SEL0 bit is determined by the SONET/ SDH pin dur- ing reset. These bits select an output clock from the T0 DPLL 12E1/24T1/E3/T3 path. 00: 12E1. 01: 24T1. 10: E3. 11: T3. The default value of the T0_12E1_24T1_E3_T3_SEL0 bit is determined by the SONET/ SDH pin during reset. 76 5 4 3 2 1 0 T0_APLL_PATH T0_APLL_PA TH2 T0_APLL_PA TH1 T0_APLL_PA TH0 T0_ETH_OBSAI_ 16E1_16T1_SEL1 T0_ETH_OBSAI_ 16E1_16T1_SEL0 T0_12E1_24T1_ E3_T3_SEL1 T0_12E1_24T1_ E3_T3_SEL0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 86 March 23, 2009 T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration Address: 56H Type: Read / Write Default Value: 01101111 Bit Name Description 7 - 5 T0_DPLL_START_DAMPING[2:0] These bits set the starting damping factor for T0 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. 4 - 0 T0_DPLL_START_BW[4:0] These bits set the starting bandwidth for T0 DPLL. 00XXX: Reserved. 01000: 0.1 Hz. 01001: 0.3 Hz. 01010: 0.6 Hz. 01011: 1.2 Hz. 01100: 2.5 Hz. 01101: 4 Hz. 01110: 8 Hz. 01111: 18 Hz. (default) 10000: 35 Hz. 10001: 70 Hz. 10010: 560 Hz. 10011 ~ 11111: Reserved. 76543210 T0_DPLL_STA RT_DAMPING2 T0_DPLL_STA RT_DAMPING1 T0_DPLL_STA RT_DAMPING0 T0_DPLL_STA RT_BW4 T0_DPLL_STA RT_BW3 T0_DPLL_STA RT_BW2 T0_DPLL_STA RT_BW1 T0_DPLL_STA RT_BW0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 87 March 23, 2009 T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration Address: 57H Type: Read / Write Default Value: 01101111 Bit Name Description 7 - 5 T0_DPLL_ACQ_DAMPING[2:0] These bits set the acquisition damping factor for T0 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. 4 - 0 T0_DPLL_ACQ_BW[4:0] These bits set the acquisition bandwidth for T0 DPLL. 00XXX: Reserved. 01000: 0.1 Hz. 01001: 0.3 Hz. 01010: 0.6 Hz. 01011: 1.2 Hz. 01100: 2.5 Hz. 01101: 4 Hz. 01110: 8 Hz. 01111: 18 Hz. (default) 10000: 35 Hz. 10001: 70 Hz. 10010: 560 Hz. 10011 ~ 11111: Reserved. 76543210 T0_DPLL_ACQ _DAMPING2 T0_DPLL_ACQ _DAMPING1 T0_DPLL_ACQ _DAMPING0 T0_DPLL_ACQ _BW4 T0_DPLL_ACQ _BW3 T0_DPLL_ACQ _BW2 T0_DPLL_ACQ _BW1 T0_DPLL_ACQ _BW0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 88 March 23, 2009 T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration Address: 58H Type: Read / Write Default Value: 01101111 Bit Name Description 7 - 5 T0_DPLL_LOCKED_DAMPING[2:0] These bits set the locked damping factor for T0 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. 4 - 0 T0_DPLL_LOCKED_BW[4:0] These bits set the locked bandwidth for T0 DPLL. 00XXX: Reserved. 01000: 0.1 Hz. 01001: 0.3 Hz. 01010: 0.6 Hz. 01011: 1.2 Hz. (default) 01100: 2.5 Hz. 01101: 4 Hz. 01110: 8 Hz. 01111: 18 Hz. 10000: 35 Hz. 10001: 70 Hz. 10010: 560 Hz. 10011 ~ 11111: Reserved. Address: 59H Type: Read / Write Default Value: 1XXX1XXX Bit Name Description

7 AUTO_BW_SEL

This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL. 0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used regardless of the T0 DPLL locking stage. 1: The starting, acquisition or locked bandwidth / damping factor is used automatically depending on different T0 DPLL locking stages. (default) 6 - 4 - Reserved.

3 T0_LIMT

This bit determines whether the integral path value is frozen when the T0 DPLL hard limit is reached. 0: Not frozen. 1: Frozen. It will minimize the subsequent overshoot when T0 DPLL is pulling in. (default) 2 - 0 - Reserved. 7 6 543210 T0_DPLL_LOCK ED_DAMPING2 T0_DPLL_LOCK ED_DAMPING1 T0_DPLL_LOCK ED_DAMPING0 T0_DPLL_LOC KED_BW4 T0_DPLL_LOC KED_BW3 T0_DPLL_LOC KED_BW2 T0_DPLL_LOC KED_BW1 T0_DPLL_LOC KED_BW0 7 6 5 43210 AUTO_BW_SEL - - - T0_LIMT - - -

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 89 March 23, 2009 PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration * Address: 5AH Type: Read / Write Default Value: 10000101 Bit Name Description

7 COARSE_PH_LOS_LIMT_EN

This bit controls whether the occurrence of the coarse phase loss will result in the T0 DPLL unlocked. 0: Disabled. 1: Enabled. (default) 6 WIDE_EN Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH).

5 MULTI_PH_APP

This bit determines whether the PFD output of T0 DPLL is limited to ±1 UI or is limited to the coarse phase limit. 0: Limited to ±1 UI. (default) 1: Limited to the coarse phase limit. When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits; when the selected input clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH) for details. This bit, together with the WIDE_EN bit (b6, 5AH) and th e PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH), determines the coarse phase limit when the selected input clock is of 2 kHz, 4 kHz or 8 kHz. When the selected input clock is of other frequen- cies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. 3 - 0 PH_LOS_COARSE_LIMT[3:0] These bit set the coarse phase limit. The limit is used only in some cases. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH). 0000: ±1 UI. 0001: ±3 UI. 0010: ±7 UI. 0011: ±15 UI. 0100: ±31 UI. 0101: ±63 UI. (default) 0110: ±127 UI. 0111: ±255 UI. 1000: ±511 UI. 1001: ±1023 UI. 1010-1111: Reserved. 7 6 5 43210 COARSE_PH_L OS_LIMT_EN WIDE_EN MULTI_PH_APP MULTI_PH_8K_ 4K_2K_EN PH_LOS_COA RSE_LIMT3 PH_LOS_COA RSE_LIMT2 PH_LOS_COA RSE_LIMT1 PH_LOS_COA RSE_LIMT0 Selected Input Clock MULTI_PH_8K_4K_2K_EN WIDE_EN Coarse Phase Limit 2 kHz, 4 kHz or 8 kHz 0 don’t-care ±1 UI 0± 1 U I 1 set by the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH). other than 2 kHz, 4 kHz and 8 kHz don’t-care 0± 1 U I 1 set by the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH).

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 90 March 23, 2009 PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration * Address: 5BH Type: Read / Write Default Value: 10XXX010 Bit Name Description

7 FINE_PH_LOS_LIMT_EN

This bit controls whether the occurrence of the fine phase loss will result in the T0 DPLL unlocked. 0: Disabled. 1: Enabled. (default)

6 FAST_LOS_SW

The value in this bit can be switched only when it is available for T0 path. This bit controls whether the occurrence of the fast loss will result in the T0 DPLL unlocked. 0: Does not result in the T0 DPLL unlocked. T0 DPLL will enter Temp-Holdover mode automatically. (default) 1: Results in the T0 DPLL unlocked. For T0 path, T0 DPLL will enter Lost-Phase mode if the T0 DPLL operating mode is switched automatically. 5 - 3 - Reserved. 2 - 0 PH_LOS_FINE_LIMT[2:0] These bits set a fine phase limit. 000: 0. 110: ± (120 ns ~ 125 ns). 111: ± (950 ns ~ 955 ns). 7 6 5 43210 FINE_PH_LOS_ LIMT_EN FAST_LOS_SW - - - PH_LOS_FINE _LIMT2 PH_LOS_FINE _LIMT1 PH_LOS_FINE _LIMT0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 91 March 23, 2009 T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration T0_HOLDOVER_FREQ[7:0]_CNFG - T0 DPLL Holdover Frequency Configuration 1 Address: 5CH Type: Read / Write Default Value: 010001XX Bit Name Description 7 MAN_HOLDOVER Refer to the descriptio n of the FAST_AVG bit (b5, 5CH). 6 AUTO_AVG Refer to the description of the FAST_AVG bit (b5, 5CH).

5 FAST_AVG

This bit, together with the AUTO_AVG bit (b6, 5CH) and the MAN_HOLDOVER bit (b7, 5CH), determines a fre- quency offset acquiring method in T0 DPLL Holdover Mode.

4 READ_AVG

This bit controls the holdover frequency offset readi ng, which is read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH). 0: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is equal to the one written to them. (default) 1: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is not equal to the one written to them. The value is acquired by Automatic Slow Averaged method if the FAST_AVG bit (b5, 5CH) is ‘0’; or is acquired by Automatic Fast Averaged method if the FAST_AVG bit (b5, 5CH) is ‘1’. 3 - 2 TEMP_HOLDOVER_MODE[1:0] These bits determine the frequency offset acquiring method in T0 DPLL Temp-Holdover Mode. 00: The method is the same as that used in T0 DPLL Holdover mode. 01: Automatic Instantaneous. (default) 10: Automatic Fast Averaged. 11: Automatic Slow Averaged. 1 - 0 - Reserved. Address: 5DH Type: Read / Write Default Value: 00000000 Bit Name Description 7 - 0 T0_HOLDOVER_FREQ[7:0] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH). 7 6 5 43210 MAN_HOLDOV ER AUTO_AVG FAST_AVG READ_AVG TEMP_HOLDO VER_MODE1 TEMP_HOLDO VER_MODE0 -- MAN_HOLDOVER AUTO_AVG FAST_AVG Fr equency Offset Acquiring Method 0 don’t-care Automatic Instantaneous 1 0 Automatic Slow Averaged (default) 1 don’t-care Manual 7 6 5 43210 T0_HOLDOVER _FREQ7 T0_HOLDOVER _FREQ6 T0_HOLDOVER _FREQ5 T0_HOLDOVE R_FREQ4 T0_HOLDOVE R_FREQ3 T0_HOLDOVE R_FREQ2 T0_HOLDOVE R_FREQ1 T0_HOLDOVE R_FREQ0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 92 March 23, 2009 T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2 T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3 DPLL_APLL_PATH_CNFG - DPLL & APLL Path Configuration Address: 5EH Type: Read / Write Default Value: 00000000 Bit Name Description 7 - 0 T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH). Address: 5FH Type: Read / Write Default Value: 00000000 Bit Name Description 7 - 0 T0_HOLDOVER_FREQ[23:16] The T0_HOLDOVER_FREQ[23:0] bits represent a 2’s complement signed integer. In T0 DPLL Holdover mode, the value written to these bits multiplied by 0.000011 is the frequency offset set manu- ally; the value read from these bits multiplied by 0.000011 is the frequency offset automatically slow or fast aver- aged or manually set, as determined by the READ_AVG bit (b4, 5CH) and the FAST_AVG bit (b5, 5CH). Address: 60H Type: Read / Write Default Value: 01000X0X Bit Name Description 7 - 4 T4_APLL_PATH[3:0] These bits select an input to the T4 APLL. 0000: The output of T0 DPLL 77.76 MHz path. 0001: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0010: The output of T0 DPLL 16E1/16T1 path. 0011: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path. 0100~1XXX: Reserved. 3 -0 - Reserved. 7 6 5 43210 T0_HOLDOVER _FREQ15 T0_HOLDOVER _FREQ14 T0_HOLDOVER _FREQ13 T0_HOLDOVE R_FREQ12 T0_HOLDOVE R_FREQ11 T0_HOLDOVE R_FREQ10 T0_HOLDOVE R_FREQ9 T0_HOLDOVE R_FREQ8 7 6 5 43210 T0_HOLDOVER _FREQ23 T0_HOLDOVER _FREQ22 T0_HOLDOVER _FREQ21 T0_HOLDOVE R_FREQ20 T0_HOLDOVE R_FREQ19 T0_HOLDOVE R_FREQ18 T0_HOLDOVE R_FREQ17 T0_HOLDOVE R_FREQ16 76 5 4 3 2 1 0 T4_APLL_PATH T4_APLL_PA TH2 T4_APLL_PA TH1 T4_APLL_PA TH0 -- - -

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 93 March 23, 2009 CURRENT_DPLL_FREQ[7:0]_STS - DPLL Current Frequency Status 1 * CURRENT_DPLL_FREQ[15:8]_STS - DPLL Current Frequency Status 2 * CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 * Address: 62H Type: Read Default Value: 00000000 Bit Name Description 7 - 0 CURRENT_DPLL_FREQ[7:0] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H). Address: 63H Type: Read Default Value: 00000000 Bit Name Description 7 - 0 CURRENT_DPLL_FREQ[15:8] Refer to the descripti on of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H). Address: 64H Type: Read Default Value: 00000000 Bit Name Description 7 - 0 CURRENT_DPLL_FREQ[23:16] The CURRENT_DPLL_FREQ[23:0] bits represent a 2’s complement signed integer. If the value in these bits is mul- tiplied by 0.000011, the current frequency offset of the T0 DPLL output in ppm with respect to the master clock will be gotten. 76543210 CURRENT_DP LL_FREQ7 CURRENT_DP LL_FREQ6 CURRENT_DP LL_FREQ5 CURRENT_DP LL_FREQ4 CURRENT_DP LL_FREQ3 CURRENT_DP LL_FREQ2 CURRENT_DP LL_FREQ1 CURRENT_DP LL_FREQ0 76543210 CURRENT_DP LL_FREQ15 CURRENT_DP LL_FREQ14 CURRENT_DP LL_FREQ13 CURRENT_DP LL_FREQ12 CURRENT_DP LL_FREQ11 CURRENT_DP LL_FREQ10 CURRENT_DP LL_FREQ9 CURRENT_DP LL_FREQ8 76543210 CURRENT_DP LL_FREQ23 CURRENT_DP LL_FREQ22 CURRENT_DP LL_FREQ21 CURRENT_DP LL_FREQ20 CURRENT_DP LL_FREQ19 CURRENT_DP LL_FREQ18 CURRENT_DP LL_FREQ17 CURRENT_DP LL_FREQ16

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 94 March 23, 2009 DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1 DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2 Address: 65H Type: Read / Write Default Value: 10001100 Bit Name Description

7 FREQ_LIMT_PH_LOS

This bit determines whether the T0 DPLL in hard alarm status will result in it unlocked. 0: Disabled. 1: Enabled. (default) 6 - 0 DPLL_FREQ_SOFT_LIMT[6:0] These bits represent an unsigned integer. If the value is multiplied by 0.724, the DPLL soft limit for T0 path in ppm will be gotten. The DPLL soft limit is symmetrical about zero. Address: 66H Type: Read / Write Default Value: 10101011Bit Name Description 7 - 0 DPLL_FREQ_HARD_LIMT[7:0] Refer to the description of the DPLL_FREQ_HARD_LIMT[15:8] bits (b7~0, 67H). Address: 67H Type: Read / Write Default Value: 00011001Bit Name Description 7 - 0 DPLL_FREQ_HARD_LIMT[15:8] The DPLL_FREQ_HARD_LIMT[15:0] bits represent an unsigned integer. If the value is multiplied by 0.0014, the DPLL hard limit for T0 path in ppm will be gotten. The DPLL hard limit is symmetrical about zero. 765 4 3 2 1 0 FREQ_LIMT_P H_LOS DPLL_FREQ_S OFT_LIMT6 DPLL_FREQ_S OFT_LIMT5 DPLL_FREQ_S OFT_LIMT4 DPLL_FREQ_S OFT_LIMT3 DPLL_FREQ_S OFT_LIMT2 DPLL_FREQ_S OFT_LIMT1 DPLL_FREQ_S OFT_LIMT0 765 4 3 2 1 0 DPLL_FREQ_H ARD_LIMT7 DPLL_FREQ_H ARD_LIMT6 DPLL_FREQ_H ARD_LIMT5 DPLL_FREQ_H ARD_LIMT4 DPLL_FREQ_H ARD_LIMT3 DPLL_FREQ_H ARD_LIMT2 DPLL_FREQ_H ARD_LIMT1 DPLL_FREQ_H ARD_LIMT0 765 4 3 2 1 0 DPLL_FREQ_H ARD_LIMT15 DPLL_FREQ_H ARD_LIMT14 DPLL_FREQ_H ARD_LIMT13 DPLL_FREQ_H ARD_LIMT12 DPLL_FREQ_H ARD_LIMT11 DPLL_FREQ_H ARD_LIMT10 DPLL_FREQ_H ARD_LIMT9 DPLL_FREQ_H ARD_LIMT8

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 95 March 23, 2009 CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 * CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2 * T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration Address: 68H Type: Read Default Value: 00000000 Bit Name Description 7 - 0 CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H). Address: 69H Type: Read Default Value: 00000000 Bit Name Description 7 - 0 CURRENT_PH_DATA[15:8] The CURRENT_PH_DATA[15:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the averaged phase error of the T0 DPLL feedback with respect to the selected input clock in ns will be gotten. Address: 6AH Type: Read / Write Default Value: XX01XX01 Bit Name Description 7 - 6 - Reserved. 5 - 4 T0_APLL_BW[1:0] These bits set the bandwidth for T0 APLL. 00: 100 kHz. 01: 500 kHz. (default) 10: 1 MHz. 11: 2 MHz. 3 - 2 - Reserved. 1 - 0 T4_APLL_BW[1:0] These bits set the bandwidth for T4 APLL. 00: 100 kHz. 01: 500 kHz. (default) 10: 1 MHz. 11: 2 MHz. 76543210 CURRENT_PH _DATA7 CURRENT_PH _DATA6 CURRENT_PH _DATA5 CURRENT_PH _DATA4 CURRENT_PH _DATA3 CURRENT_PH _DATA2 CURRENT_PH _DATA1 CURRENT_PH _DATA0 76543210 CURRENT_PH _DATA15 CURRENT_PH _DATA14 CURRENT_PH _DATA13 CURRENT_PH _DATA12 CURRENT_PH _DATA11 CURRENT_PH _DATA10 CURRENT_PH _DATA9 CURRENT_PH _DATA8 76543210 - - T0_APLL_BW1 T0_APLL_BW0 - - T4_APLL_BW1 T4_APLL_BW0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 96 March 23, 2009

6.2.8 OUTPUT CONFIGURATION REGISTERS

OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration Address: 6DH Type: Read / Write Default Value: 00001000 Bit Name Description 7 - 4 OUT2_PATH_SEL[3:0] These bits select an input to OUT2. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. 0111: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100 ~ 1111: Reserved. 3 - 0 OUT2_DIVIDER[3:0] These bits select a division factor of the divider for OUT2. The output frequency is determined by the division factor and the signal derived from T0 DPLL or T0/T4 APLL output (selected by the OUT2_PATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0 DPLL outputs, please refer to Table 20 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 21~Table 22 for the division factor selection. Address:71H Type: Read / Write Default Value: 00001000 Bit Name Description 7 - 4 OUT1_PATH_SEL[3:0] These bits select an input to OUT1. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. 0111: The output of T0 DPLL ETH/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100 ~ 1111: Reserved. 3 - 0 OUT1_DIVIDER[3:0] These bits select a division factor of the divider for OUT1. The output frequency is determined by the division factor and the signal derived from T0 DPLL or T0/T4 APLL output (selected by the OUT1_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0 DPLL outputs, please refer to Table 20 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 21~Table 22 for the division factor selection. 76543210 OUT2_PATH_S EL3 OUT2_PATH_S EL2 OUT2_PATH_S EL1 OUT2_PATH_S EL0 OUT2_DIVIDER OUT2_DIVIDER OUT2_DIVIDER OUT2_DIVIDER 76543210 OUT1_PATH_S EL3 OUT1_PATH_S EL2 OUT1_PATH_S EL1 OUT1_PATH_S EL0 OUT1_DIVIDER OUT1_DIVIDER OUT1_DIVIDER OUT1_DIVIDER

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 97 March 23, 2009 OUT1_INV_CNFG - Output Clock 1 Invert Configuration OUT2_INV_CNFG - Output Clock 2 Invert Configuration Address:72H Type: Read / Write Default Value: XXXXXX0X Bit Name Description 7 - 2 - Reserved. 1O U T 1 _ I N V This bit determines whether the output on OUT1 is inverted. 0: Not inverted. (default) 1: Inverted. 0- R e s e r v e d . Address:73H Type: Read / Write Default Value: XXXXX0XX Bit Name Description 7 - 3 - Reserved. 2O U T 2 _ I N V This bit determines whether the output on OUT2 is inverted. 0: Not inverted. (default) 1: Inverted. 1 - 0 - Reserved. 76543210 76543210 ----- O U T 2 _ I N V --

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 98 March 23, 2009 FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configuration Address:74H Type: Read / Write Default Value: 01100000 Bit Name Description

7 IN_2K_4K_8K_INV

This bit determines whether the input clock is inverted before locked by the T0 DPLL when the input clock is 2 kHz, 4 kHz or 8 kHz. 0: Not inverted. (default) 1: Inverted. 6 8K_EN This bit determines whether an 8 kHz signal is enabled to be output on FRSYNC_8K. 0: Disabled. FRSYNC_8K outputs low. 1: Enabled. (default) 5 2K_EN This bit determines whether a 2 kHz signal is enabled to be output on MFRSYNC_2K. 0: Disabled. MFRSYNC_2K outputs low. 1: Enabled. (default) 4 2K_8K_PUL_POSITION This bit is valid only when FRSYNC_8K and/or MFRSYNC_2K out put pulse; i.e., when one of the 8K_PUL bit (b2, 74H) and the 2K_PUL bit (b0, 74H) is ‘1’ or when the 8K_PUL bit (b2, 74H) and the 2K_PUL bit (b0, 74H) are both ‘1’. It deter- mines the pulse position referring to the standard 50:50 duty cycle. 0: Pulsed on the falling edge of the standard 50:50 duty cycle position. (default) 1: Pulsed on the rising edge of the standard 50:50 duty cycle position.

38 K _ I N V

This bit determines whether the output on FRSYNC_8K is inverted. 0: Not inverted. (default) 1: Inverted. 2 8K_PUL This bit determines whether the output on FRSYNC_8K is 50:50 duty cycle or pulsed. 0: 50:50 duty cycle. (default) 1: Pulsed. The pulse width is defined by the period of the output on OUT2.

12 K _ I N V

This bit determines whether the output on MFRSYNC_2K is inverted. 0: Not inverted. (default) 1: Inverted. 0 2K_PUL This bit determines whether the output on MFRSYNC_2K is 50:50 duty cycle or pulsed. 0: 50:50 duty cycle. (default) 1: Pulsed. The pulse width is defined by the period of the output on OUT2. 76543210 IN_2K_4K_8K_I NV 8K_EN 2K_EN 2K_8K_PUL_P OSITION 8K_INV 8K_PUL 2K_INV 2K_PUL

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 99 March 23, 2009

6.2.9 PBO & PHASE OFFSET CONTROL REGISTERS

PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration PHASE_OFFSET[7:0]_CNFG - Phase Offset Configuration 1 Address:78H Type: Read / Write Default Value: 0X000110 Bit Name Description

7 IN_NOISE_WINDOW

This bit determines whether the input clock whose edge respect to the reference clock is outside ±5% is enabled to be selected for T0 DPLL. 0: Disabled. (default) 1: Enabled. 6- R e s e r v e d . 5P H _ M O N _ E N This bit is valid only when the PH_MON_PBO_EN bit (b4, 78H) is ‘1’. It determines whether the Phase Transient Monitor is enabled to monitor the phase-time changes on the T0 selected input clock. 0: Disabled. (default) 1: Enabled.

4 PH_MON_PBO_EN

This bit determines whether a PBO event is triggered when the phase-time changes on the T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds with the PH_MON_EN bit being ‘1’. The limit is programmed by the PH_TR_MON_LIMT[3:0] bits (b3~0, 78H). 0: Disabled. (default) 1: Enabled. 3 - 0 PH_TR_MON_LIMT[3:0] These bits represent an unsigned integer. The Phase Transient Monitor limit in ns can be calculated as follows: Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156. Address:7AH Type: Read / Write Default Value: 00000000 Bit Name Description 7 - 0 PH_OFFSET[7:0] Refer to the description of the PH_OFFSET[9:8] bits (b1~0, 7BH). 76543210 IN_NOISE_WIN DOW - PH_MON_EN PH_MON_PBO _EN PH_TR_MON_L IMT3 PH_TR_MON_L IMT2 PH_TR_MON_L IMT1 PH_TR_MON_L IMT0 76543210 PH_OFFSET7 PH_OFFSET6 PH_OFFSET5 PH_OFFSET4 P H_OFFSET3 PH_OFFSET2 P H_OFFSET1 PH_OFFSET0

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 100 March 23, 2009 PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2 Address:7BH Type: Read / Write Default Value: 0XXXXX00 Bit Name Description 7P H _ O F F S E T _ E N This bit determines whether the input-to-output phase offset is enabled. 0: Disabled. (default) 1: Enabled. 6 - 2 - Reserved. 1 - 0 PH_OFFSET[9:8] These bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the input-to-output phase offset in ns to adjust will be gotten. 76543210 PH_OFFSET_E N - - - - - PH_OFFSET9 PH_OFFSET8

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 101 March 23, 2009

6.2.10 SYNCHRONIZATION CONFIGURATION REGISTERS

SYNC_MONITOR_CNFG - Sync Monitor Configuration Address:7CH Type: Read / Write Default Value: 00101011 Bit Name Description

7 SYNC_BYPASS

This bit selects one frame sync input signal to synchronize the frame sync output signals. 0: EX_SYNC1 is selected. (default) 1: When the T0 selected input clock is IN1_CMOS or IN1_DIFF, EX_SYNC1 is selected; when the T0 selected input clock is IN2_CMOS or IN2_DIFF, EX_SYNC2 is selected; when the T0 selected input clock is IN3_CMOS, EX_SYNC3 is selected; when there is no T0 selected input clock, no frame sync input signal is selected. 6 - 4 SYNC_MON_LIMT[2:0] These bits set the limit for the external sync alarm. 000: ±1 UI. 001: ±2 UI. 010: ±3 UI. (default) 011: ±4 UI. 100: ±5 UI. 101: ±6 UI. 110: ±7 UI. 111: ±8 UI. 3 - 0 - These bits must be set to ‘1011’. 7 6 5 4 3210 S Y N C _ B Y P A S S S Y N C _ M O N _ L I M T 2 S Y N C _ M O N _ L I M T 1 S Y N C _ M O N _ L I M T 0 ----

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Programming Information 102 March 23, 2009 SYNC_PHASE_CNFG - Sync Phase Configuration Address:7DH Type: Read / Write Default Value: XX000000 Bit Name Description 7 - 6 - Reserved. 5 - 4 SYNC_PH3[1:0] These bits set the sampling of EX_SYNC3 when EX_SYNC3 is enabled to synchronize the frame sync output signal. Nomi- nally, the falling edge of EX_SYNC3 is aligned with the rising edge of the T0 selected input clock. 00: On target. (default) 01: 0.5 UI early. 10: 1 UI late. 11: 0.5 UI late. 3 - 2 SYNC_PH2[1:0] These bits set the sampling of EX_SYNC2 when EX_SYNC2 is enabled to synchronize the frame sync output signal. Nomi- nally, the falling edge of EX_SYNC2 is aligned with the rising edge of the T0 selected input clock. 00: On target. (default) 01: 0.5 UI early. 10: 1 UI late. 11: 0.5 UI late. 1 - 0 SYNC_PH1[1:0] These bits set the sampling of EX_SYNC1 when EX_SYNC1 is enabled to synchronize the frame sync output signal. Nomi- nally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock. 00: On target. (default) 01: 0.5 UI early. 10: 1 UI late. 11: 0.5 UI late. 76543210 - - SYNC_PH31 SYNC_PH30 SYNC_PH21 SYNC_PH20 SYNC_PH11 SYNC_PH10

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Thermal Management 103 March 23, 2009

7 THERMAL MANAGEMENT

The device operates over the industry temperature range -40°C ~ +85°C. To ensure the functionality and reliability of the device, the maxi- mum junction temperature T jmax should not exceed 125°C. In some applications, the device will consume more power and a thermal solution should be provided to ensure the junction temperature T j does not exceed the Tjmax.

7.1 JUNCTION TEMPERATURE

Junction temperature Tj is the temperature of package typically at the geographical center of the chip where the device's electrical circuits are. It can be calculated as follows: Equation 1: Tj = TA + P X θJA Where: θJA = Junction-to-Ambient Thermal Resistance of the Package Tj = Junction Temperature TA = Ambient Temperature P = Device Power Consumption In order to calculate juncti on temperature, an appropriate θJA must be used. The θJA is shown in Table 32: Power consumption is the core power excluding the power dissipated in the loads. Table 31 provides power consumpt ion in special environ- ments.

7.2 EXAMPLE OF JUNCTION TEMPERATURE

Assume: TA = 85°C θJA = 21.7°C/W (TQFP/EDG64 Soldered & when airfow rate is 0 m/ P = 1.57W The junction temperature Tj can be calculated as follows: Tj = TA + P X θJA = 85°C + 1.57W X 21.7°C/W = 119.1°C The junction temperature of 119.1°C is below the maximum junction temperature of 125°C so no extra heat enhancement is required. In some operation environments, the calculated junction temperature might exceed the maximum junction temperature of 125°C and an exter- nal thermal solution such as a heatsink is required.

7.3 HEATSINK EVALUATION

A heatsink is expanding the surface area of the device to which it is attached. θJA is now a combination of device case and heat-sink thermal resistance, as the heat flowing fr om the die junction to ambient goes through the package and the heatsink. θJA can be calculated as follows: Equation 2: θJA = θJC + θCH+ θHA Where: θJC = Junction-to-Case Thermal Resistance θCH = Case-to-Heatsink Thermal Resistance θHA = Heatsink-to-Ambient Thermal Resistance θCH+ θHA determines which heatsink and heatsink attachment can be selected to ensure the junction temperature does not exceed the maximum junction temperature. According to Equation 1 and 2, θCH+ θHA can be calculated as follows: Equation 3: θCH+ θHA = (Tj - TA) / P - θJC Assume: Tj = 125°C (Tjmax) TA = 85°C P = 1.57W θJC = 12.6°C/W (TQFP/EDG64) θCH+ θHA can be calculated as follows: That is, if a heatsink and heatsink attachment whose θCH+ θHA is below or equal to 12.9°C/W is used in such operation environment, the junction temperature will not exceed the maximum junction temperature. Table 31: Power Consumption and Maximum Junction Temperature Package Power Consumption (W) Operating Voltage (V) TA (°C) Maximum Junction Temperature (°C) LQFP/PP64 1.57 3.6 85 125 TQFP/EDG64 1.57 3.6 85 125 Table 32: Thermal Data Package Pin Count Thermal Pad θJC (°C/W) θJB (°C/W) θJA (°C/W) Air Flow in m/s 012345

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Electrical Specifications 104 March 23, 2009

8 ELECTRICAL SPECIFICATIONS

8.1 ABSOLUTE MAXIMUM RATING

8.2 RECOMMENDED OPER ATION CONDITIONS

Table 33: Absolute Maximum Rating Symbol Parameter Min Max Unit VDD Supply Voltage VDD -0.5 3.6 V VIN Input Voltage (non-supply pins) 5.5 V VOUT Output Voltage (non-supply pins) 5.5 V TA Ambient Operating Temperature Range -40 +85 °C TSTOR Storage Temperature -50 +150 °C Table 34: Recommended Operation Conditions Symbol Parameter Min Typ Max Unit Test Condition VDD Power Supply (DC voltage) VDD 3.0 3.3 3.6 V TA Ambient Temperature Range -40 +85 °C IDD Supply Current 388 436 mA Exclude the loading current and powerPTOT Total Power Dissipation 1.28 1.57 W

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Electrical Specifications 105 March 23, 2009

8.3 I/O SPECIFICATIONS

8.3.1 CMOS INPUT / OUTPUT PORT

From Table 35 to Table 38, VDD is 3.3 V. Table 35: CMOS Input Port Electrical Characteristics Parameter Description Min Typ Max Unit Test Condition VIH Input Voltage High 0.7VDD V VIL Input Voltage Low 0.2VDD V IIN Input Current 10 µA VIN Input Voltage -0.5 5.5 V Table 36: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics Parameter Description Min Typ Max Unit Test Condition VIH Input Voltage High 0.7VDD V VIL Input Voltage Low 0.2VDD V PU Pull-Up Resistor 10 80 K Ω IIN Input Current 250 µA VIN Input Voltage -0.5 5.5 V Table 37: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics Parameter Description Min Typ Max Unit Test Condition VIH Input Voltage High 0.7VDD V VIL Input Voltage Low 0.2VDD V PD Pull-Down Resistor 10 80 KΩ other CMOS input port with internal pull-down resistor 54 0 TRST and TCK pin 100 300 SDI, CLKE pin IIN Input Current 350 µA other CMOS input port with internal pull-down resistor

700 TRST and TCK pin

40 SDI, CLKE pin

VIN Input Voltage -0.5 5.5 V Table 38: CMOS Output Port Electrical Characteristics Application Pin Parameter Description Min Typ Max Unit Test Condition Output Clock VOH Output Voltage High 2.4 VDD V IOH = 8 mA VOL Output Voltage Low 0 0.4 V IOL = 8 mA tR Rise time 3 4 ns 15 pF tF Fall time 3 4 ns 15 pF Other Output VOH Output Voltage High 2.5 VDD V IOH = 4 mA VOL Output Voltage Low 0 0.4 V IOL= 4 mA tR Rise Time 10 ns 50 pF tF Fall Time 10 ns 50 pF

8.3.2 PECL / LVDS INPUT / OUTPUT PORT

8.3.2.1 PECL Input / Output Port

Figure 17. Recommended PECL Input Port Line Termi- Figure 18. Recommended PECL Output Port Line Ter-

667 MHz

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Electrical Specifications 107 March 23, 2009 Table 39: PECL Input / Output Port Electrical Characteristics Parameter Description Min Typ Max Unit Test Condition VIL Input Low Voltage, Differential Inputs 1 VDD - 2.5 V DD - 0.5 V VIH Input High Voltage, Differential Inputs 1 VDD - 2.4 V DD - 0.4 V VID Input Differential Voltage 0.1 1.4 V VIL_S Input Low Voltage, Single-ended Input 2 VDD - 2.4 V DD - 1.5 V VIH_S Input High Voltage, Single-ended Input 2 VDD - 1.3 V DD - 0.5 V IIH Input High Current, Input Differential Voltage VID = 1.4 V -10 10 µA IIL Input Low Current, Input Differential Voltage VID = 1.4 V -10 10 µA VOL Output Voltage Low 3 VDD - 2.1 V DD - 1.62 V VOH Output Voltage High 3 VDD - 1.25 V DD - 0.88 V VOD Output Differential Voltage3 580 900 mV tRISE Output Rise time (20% to 80%) 200 300 pS tFALL Output Fall time (20% to 80%) 200 300 pS tSKEW Output Differential Skew 50 pS Note: 1. Assuming a differential input voltage of at least 100 mV. 2. Unused differential input terminated to VDD-1.4 V. 3. With 50 Ω load on each pin to VDD-2 V, i.e. 82 to GND and 130 to VDD.

8.3.2.2 LVDS Input / Output Port

Figure 19. Recommended LVDS Input Port Line Termi- Figure 20. Recommended LVDS Output Port Line Ter-

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Electrical Specifications 109 March 23, 2009

8.4 JITTER & WANDER PERFORMANCE

Table 41: Output Clock Jitter Generation Test Definition 1 Peak to Peak Typ RMS Typ Note Test Filter 25 MHz with T4 APLL <1 ns 16 ps See Table 42: Output Clock Phase Noise for details 1.875 MHz - 20 MHz <1 ns 22 ps See Table 42: Output Clock Phase Noise for details 12 kHz - 20 MHz 125 MHz with T4 APLL <1 ns 4.3 ps See Table 42: Output Clock Phase Noise for details 1.875 MHz - 20 MHz <1 ns 15 ps See Table 42: Output Clock Phase Noise for details 12 kHz - 20 MHz 156.25 MHz with T4 APLL <1 ns 6.9 ps See Table 42: Output Clock Phase Noise for details 1.875 MHz - 20 MHz <1 ns 25 ps See Table 42: Output Clock Phase Noise for details 12 kHz - 20 MHz N x 2.048 MHz without APLL <2 ns <200 ps 20 Hz - 100 kHz N x 2.048 MHz with T0/T4 APLL <1 ns <100 ps See Table 42: Output Clock Phase Noise for details 20 Hz - 100 kHz N x 1.544 MHz without APLL <2 ns <200 ps 10 Hz - 40 kHz N x 1.544 MHz with T0/T4 APLL <1 ns <100 ps See Table 42: Output Clock Phase Noise for details 10 Hz - 40 kHz

44.736 MHz without APLL <2 ns <200 ps See Table 42: Output Clock Phase Noise for details 100 Hz - 800 kHz

44.736 MHz with T0/T4 APLL <1 ns <100 ps 100 Hz - 800 kHz

34.368 MHz without APLL <2 ns <200 ps See Table 42: Output Clock Phase Noise for details 10 Hz - 400 kHz

34.368 MHz with T0/T4 APLL <1 ns <100 ps 10 Hz - 400 kHz

62.5 MHz with T4 APLL <1 ns 4.6 ps See Table 42: Output Clock Phase Noise for details 1.875 MHz - 20 MHz OC-3 (Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, MHz, 311.04 MHz, 622.08 MHz output 0.004 UI p-p 0.001 UI RMS GR-253, G.813 Option 2 limit 0.1 UI p-p (1 UI-6430 ps) 12 kHz - 1.3 MHz 0.004 UI p-p 0.001 UI RMS G.813 Option 1, G.812 limit 0.5 UI p-p (1 UI-6430 ps) 500 Hz - 1.3 MHz 0.001 UI p-p 0.001 UI RMS G.813 Option 1 limit 0.1 UI p-p (1 UI-6430 ps) 65 kHz - 1.3 MHz OC-12 (Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, MHz, 311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical transceiver) 0.018 UI p-p 0.007 UI RMS GR-253, G.813 Option 2 limit 0.1 UI p-p (1 UI-1608 ps) 12 kHz - 5 MHz 0.028 UI p-p 0.009 UI RMS G.813 Option 1, G.812 limit 0.5 UI p-p (1 UI-1608 ps) 1 kHz - 5 MHz 0.002 UI p-p 0.001 UI RMS G.813 Option 1, G.812 limit 0.1 UI p-p (1 UI-160 8ps) 250 kHz - 5 MHz STM-16 (Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, MHz, 311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical transceiver) 0.162 UI p-p 0.03 UI RMS G.813 Option 1, G.812 limit 0.5 UI p-p (1 UI-402 ps) 5 kHz - 20 MHz 0.01 UI p-p 0.009 UI RMS G.813 Option 1, G.812 limit 0.1 UI p-p (1 UI-402 ps)

1 MHz - 20 MHz

Note: 1. CMAC E2747 TCXO is used.

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Electrical Specifications 110 March 23, 2009 Table 42: Output Clock Phase Noise Output Clock 1 @100Hz Offset Typ @1kHz Offset Typ @10kHz Offset Typ @100kHz Offset Typ @1MHz Offset Typ @5MHz Offset Typ Unit

622.08 MHz (T0 DPLL + T0/T4 APLL) -70 -86 -95 -100 -107 -128 dBC/Hz

155.52 MHz (T0 DPLL + T0/T4 APLL) -82 -98 -107 -112 -119 -140 dBC/Hz

25 MHz (T0 DPLL + T4 APLL) -105 -117 -116 -122 -131 -135 dBC/Hz

125 MHz (T0 DPLL + T4 APLL) -92 -100 -103 -107 -116 -135 dBC/Hz

156.25 MHz (T0 DPLL + T4 APLL) -93 -102 -100 -105 -115 -127 dBC/Hz

38.88 MHz (T0 DPLL + T0/T4 APLL) -104 -116 -118 -123 -129 -149 dBC/Hz

62.5 MHz (T0 DPLL + T4 APLL) -100 -110 -110 -114 -123 -132 dBC/Hz

16E1 (T0/T4 APLL) -103 -117 -118 -125 -130 -139 dBC/Hz 16T1 (T0/T4 APLL) -114 -121 -120 -126 -130 -140 dBC/Hz E3 (T0/T4 APLL) -107 -119 -117 -123 -129 -139 dBC/Hz T3 (T0/T4 APLL) -106 -115 -115 -121 -128 -139 dBC/Hz Note: 1. CMAC E2747 TCXO is used.

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Electrical Specifications 111 March 23, 2009 Table 43: Input Jitter Tolerance (155.52 MHz) Jitter Frequency Jitter Tolerance Amplitude (UI p-p) 12 µHz > 2800 178 µHz > 2800 1.6 mHz > 311 15.6 mHz > 311

0.125 Hz > 39

19.3 Hz > 39

500 Hz > 1.5 6.5 kHz > 1.5 65 kHz > 0.15 1.3 MHz > 0.15 Table 44: Input Jitter Tolerance (1.544 MHz) Jitter Frequency Jitter Tolerance Amplitude (UI p-p)

1 Hz 150

5 Hz 140

20 Hz 130

300 Hz 38

400 Hz 25

700 Hz 15

2400 Hz 5

10 kHz 1.2 40 kHz 0.5 Table 45: Input Jitter Tolerance (2.048 MHz) Jitter Frequency Jitter Tolerance Amplitude (UI p-p)

300 Hz 40

400 Hz 33

700 Hz 18

2400 Hz 5.5 10 kHz 1.3 50 kHz 0.4 100 kHz 0.4 Table 46: Input Jitter Tolerance (8 kHz) Jitter Frequency Jitter Tolerance Amplitude (UI p-p) 1 Hz 0.8 5 Hz 0.7 20 Hz 0.6 300 Hz 0.16 400 Hz 0.14 700 Hz 0.07 2400 Hz 0.02 3600 Hz 0.01 Table 47: T0 DPLL Jitter Transfer & Damping Factor 3 dB Bandwidth Programmable Damping Factor 4 Hz 1.2, 2.5, 5, 10, 20 8 Hz 1.2, 2.5, 5, 10, 20 18 Hz 1.2, 2.5, 5, 10, 20 35 Hz 1.2, 2.5, 5, 10, 20 70 Hz 1.2, 2.5, 5, 10, 20 560 Hz 1.2, 2.5, 5, 10, 20

8.5 OUTPUT WANDER GENERATION

Figure 21. Output Wander Generation

8.6 INPUT / OUTPUT CLOCK TIMING

The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs. Figure 22. Input / Output Clock Timing

1. Typical delay provided as reference only.

6.48 MHz Input Clock

6.48 MHz Output Clock

19.44 MHz Input Clock

19.44 MHz Output Clock

25.92 MHz Input Clock

25.92 MHz Output Clock

38.88 MHz Input Clock

38.88 MHz Output Clock

51.84 MHz Input Clock

51.84 MHz Output Clock

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Electrical Specifications 114 March 23, 2009

8.7 OUTPUT CLOCK TIMING

N X T1 (1.544 MHz) t3 N X E1 (2.048 MHz) E3 (34.368 MHz)

6.48 MHz

19.44 MHz

25.92 MHz

38.88 MHz

51.84 MHz

155.52 MHz

311.04 MHz

MFRSYNC_2K/ FRSYNC_8K T3 (44.736 MHz) t10 t11 t13 t14 t15 t16 N X 5 (5 MHz) t1 N X 156.25 (156.25 MHz) t2

62.5 MHz

IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL Electrical Specifications 115 March 23, 2009 Table 49: Output Clock Timing Symbol Typical Delay (ns) Peak to Peak Delay Variation (ns) t1 02 t2 02 t3 02 t4 02 t5 02 t6 02 t7 02 t8 02 t9 02 t10 02 t11 02 t12 02 t13 02 t14 01 . 5 t15 0 1.5 (not recommended to use) t16 0 1.5 (not recommended to use)

Glossary 116 March 23, 2009 3G --- Third Generation ADSL --- Asymmetric Digital Subscriber Line AMI --- Alternate Mark Inversion APLL --- Analog Phase Locked Loop ATM --- Asynchronous Transfer Mode BITS --- Building Integrated Timing Supply CMOS --- Complementary Metal-Oxide Semiconductor DCO --- Digital Controlled Oscillator DPLL --- Digital Phase Locked Loop DSL --- Digital Subscriber Line DSLAM --- Digital Subscriber Line Access MUX DWDM --- Dense Wavelength Division Multiplexing EPROM --- Erasable Programmable Read Only Memory ETH --- Synchronous Ethernet System GPS --- Global Positioning System GSM --- Global System for Mobile Communications IIR --- Infinite Impulse Response IP --- Internet Protocol ISDN --- Integrated Services Digital Network JTAG --- Joint Test Action Group LOS --- Loss Of Signal LPF --- Low Pass Filter LVDS --- Low Voltage Differential Signal MTIE --- Maximum Time Interval Error MUX --- Multiplexer OBSAI --- Open Base Station Architecture Initiative Glossary

Glossary 117 March 23, 2009 IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL OC-n --- Optical Carried rate, n = 1, 3, 12, 48, 192, 768; 51 Mbi t/s, 155 Mbit/s, 622 Mbit/s, 2.5 Gbit/s, 10 Gbit/s, 40 Gbit/s. PBO --- Phase Build-Out PDH --- Plesiochronous Digital Hierarchy PECL --- Positive Emitte r Coupled Logic PFD --- Phase & Frequency Detector PLL --- Phase Locked Loop RMS --- Root Mean Square PRS --- Primary Reference Source SDH --- Synchronous Digital Hierarchy SEC --- SDH / SONET Equipment Clock SMC --- SONET Minimum Clock SONET --- Synchronous Optical Network SSU --- Synchronization Supply Unit STM --- Synchronous Transfer Mode TCM-ISDN --- Time Compression Multiplexing Integrated Services Digital Network TDEV --- Time Deviation UI --- Unit Interval WLL --- Wireless Local Loop

Index 118 March 23, 2009 A B C D E F H I L M N P Index

Index 119 March 23, 2009 IDT82V3352 SYNCHRONOUS ETHERNET WAN PLL R S V

120 March 23, 2009

Figure 23. 64-Pin PP Package Dimensions (a) (in Millimeters)

121 March 23, 2009

Figure 24. 64-Pin PP Package Dimensions (b) (in Millimeters)

122 March 23, 2009

Figure 25. 64-Pin EDG Package Dimensions (a) (in Millimeters)

123 March 23, 2009

Figure 26. 64-Pin EDG Package Dimensions (b) (in Millimeters)

124 March 23, 2009

Figure 27. EDG64 Recommended Land Pattern with Exposed Pad (in Millimeters)

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DATASHEET DOCUMENT HISTORY 11/18/2008 pgs. 103, 104, 109, 120, 121, 122, 123, 124, 125 12/03/2008 pg. 125 03/23/2009 pg. 11 XXXXXXX XX X Device Type Blank Process/ Temperature Range TF 82V3352 Industrial (-40 °C to +85 °C) Thin Quad Flatpack (LQFP, PP64) WAN PLL TFG Green Thin Quad Flatpack (LQFP, PPG64) EDG Green Thermal Enhanced Thin Quad Flatpack, ExposedPadTM (TQFP, EDG64)