82C86H RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • Full Eight Bit Bi-Directional Bus Interface
  • Industry Standard 8286 Compatible Pinout
  • High Drive Capability
  • Three-State Outputs
  • Gated Inputs - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors
  • Single 5V Power Supply
  • Operating Temperature Range

Description

The Intersil 82C86H is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C86H provides a full eight-bit bi-directional bus interface in a 20 lead package. The Transmit (T) control determines the data direction. The active low output enable (OE) permits simple interface to the 80C86, 80C88 and other microprocesso rs. The 82C86H has gated inputs, eliminating the need for pull-up/pull-down resistors and reducing overall system operating power dissipation.

Ordering Information

PACKAGE TEMP. RANGE PKG DWG. #8MHz ID82C86H 20 Ld CERDIP -40 oC to +85oC F20.3 Pinout 82C86H (CERDIP) TOP VIEW 1A0 OE GND VCC T TRUTH TABLE TO E AB X H Hi-Z Hi-Z HL IO LLOI H = Logic One L = Logic Zero I = Input Mode O = Output Mode X = Don’t Care Hi-Z = High Impedance PIN NAMES PIN DESCRIPTION A 0-A7 Local Bus Data I/O Pins B0-B7 System Bus Data I/O Pins T Transmit Control Input OE Active Low Output Enable NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

FN2977 Rev 2.00 Page 3 of 6 June 2004 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical) JA (oC/W) JC (oC/W) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impl ied. SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One 2.0 - V C82C86H, I82C86H Input Voltage 2.2 V M82C86H (Note 1) VIL Logical Zero Input Voltage - 0.8 V VOH Logical One Output Voltage B Outputs 3.0 V I OH = -8mA A Outputs 3.0 V I OH = -4mA A or B Outputs V CC -0.4 V I OH = -100A VOL Logical Zero Output Voltage B Outputs 0.45 V I OL = 20mA A Outputs 0.45 V I OL = 12mA II Input Leakage Current -10.0 10.0 AV IN = GND or VCC DIP Pins 9, 11 IO Output Leakage Current -10.0 10.0 A VO = GND or V CC, OE Š ŠVCC -0.5V DIP Pins 1 - 8, 12 - 19 ICCSB Standby Power Supply Current -1 0 AV IN = VCC or GND, VCC = 5.5V, Outputs Open ICCOP Operating Power Supply Current -1 m A / M H z T A = +25oC, Typical (See Note 2) NOTES: 1. VIH is measured by applying a pulse of magnitude = VIH(MIN) to one data input at a time and checking the corresponding device output for a valid logical “1” during valid input high time. Control pins (T, OE) are tested separately with all device data input pins at VCC -0.4 2. Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0s read/write cycle time = 1mA). Capacitance TA = +25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance B Inputs 18 pF Freq = 1MHz, all measurements are referenced to device GND A Inputs 14 pF

FN2977 Rev 2.00 Page 4 of 6 June 2004 Timing Waveform SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS (1) TIVOV Input to Output Delay Notes 1, 2 Inverting 5 30 ns Non-Inverting 5 32 ns (2) TEHTV Transmit/Receive Hold Time 5 - ns Notes 1, 2 (3) TTVEL Transmit/Receive Setup Time 10 - ns Notes 1, 2 (4) TEHOZ Output Disable Time 5 30 ns Notes 1, 2 (5) TELOV Output Enable Time 10 50 ns Notes 1, 2 (6) TR, TF Input Rise/Fall Times - 20 ns Notes 1, 2 (7) TEHEL Minimum Output Enable High Time Note 3 82C86H 30 - ns 82C86H-5 35 - ns NOTES: 1. All AC parameters tested as per test circuits and definitions in timing waveforms and test load circuits. Input rise and fall times are driven at 1ns/V. 2. Input test signals must switch between V IL - 0.4V and VIH +0.4V. 3. A system limitation only when changing direction. Not a measured parameter. NOTE: All timing measurements are made at 1.5V unless otherwise noted. INPUTS TR, TF (6) 2.0V 0.8V VOH -0.1V TELOV (5) VOL +0.1V TTVEL (3) 3.0V 0.45VOUTPUTS T TEHEL (7) TIVOV (1) TEHOZ (4) TEHTV (2) OE

FN2977 Rev 2.00 Page 5 of 6 June 2004 Die Characteristics DIE DIMENSIONS: 138.6 x 155.5 x 19  1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ  1kÅ Test Load Circuits A SIDE OUTPUTS TIVOV LOAD CIRCUIT TELOV OUTPUT HIGH ENABLE LOAD CIRCUIT TELOV OUTPUT LOW ENABLE LOAD CIRCUIT TEHOZ OUTPUT LOW/HIGH DISABLE LOAD CIRCUIT B SIDE OUTPUTS TIVOV LOAD CIRCUIT TELOV OUTPUT HIGH ENABLE LOAD CIRCUIT TELOV OUTPUT LOW ENABLE LOAD CIRCUIT TEHOZ OUTPUT LOW/HIGH DISABLE LOAD CIRCUIT NOTE: Includes jig and stray capacitance. OUTPUT TEST POINT 2.36V 100pF 160 (SEE NOTE) OUTPUT TEST POINT 1.5V 100pF 375 (SEE NOTE) OUTPUT TEST POINT 1.5V 100pF 91 (SEE NOTE) OUTPUT TEST POINT 2.36V 50pF 160 (SEE NOTE) OUTPUT TEST POINT 2.27V 300pF 91 (SEE NOTE) OUTPUT TEST POINT 1.5V 300pF 180 (SEE NOTE) OUTPUT TEST POINT 1.5V 300pF 51 (SEE NOTE) OUTPUT TEST POINT 2.27V 50pF 91 (SEE NOTE)

FN2977 Rev 2.00 Page 6 of 6 June 2004 82C86H Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1997-2004. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Metallization Mask Layout 82C86H A2 A1 A0 V CC B0 B1 B6B7TGNDOEA7