82C82 RENESAS | Alldatasheet
Document overview
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Technical content
Features
- Full Eight-Bit Parallel Latching Buffer
- Bipolar 8282 Compatible
- Three-State Noninverting Outputs
- Gated Inputs: - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors
- Single 5V Power Supply
- Operating Temperature Ranges oC to +70oC
Description
The Intersil 82C82 is a high performance CMOS Octal Latching Buffer manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C82 provides an eight-bit parallel latch/buffer in a 20 pin package. The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this signal. The active low output enable (OE ) permits simple interface to state-of-the-art microprocessor systems. Pinouts 82C82 (PDIP, CERDIP) TOP VIEW 82C82 (PLCC, CLCC) TOP VIEW 1DI0 DI1 DI2 DI3 DI4 DI5 DI7 DI6 OE GND VCC DO1 DO2 DO3 DO0 DO4 DO5 DO6 DO7 STB 193 2 201 9 10 11 12 13 DI DI5 DI6 DI7 DI3 OE GND STB DO7 DO6 DO2 DO3 DO4 DO5 DO1 DI2 DI1 DI0 VCC DO0 NO LONGER AVAILABLE OR SUPPORTED TRUTH TABLE STB OE DI DO XH X H i - Z HL LL HL HH LX † H = Logic One L = Logic Zero X = Don’t Care † = Latched to Value of Last Data Hi-Z = High Impedance = Neg. Transition PIN NAMES PIN DESCRIPTION DI0-DI7 Data Input Pins DO0-DO7 Data Output Pins STB Active High Strobe OE Active Low Output Enable
FN2975 Rev 2.00 Page 2 of 8 Aug 25, 2015 Functional Diagram Gated Inputs During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transi- tions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between V CC and GND when the signal is at or near the input switching threshold. Additionally, if the driv- ing signal becomes high impedance (“float” condition), it could create an indeterminate logic state at the input and cause a dis- ruption in device operation. The Intersil 82C8X Series of bus drivers eliminates these condi- tions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for 82C86H/87H). These gated inputs disconnect the input circuitry from the V CC and ground power supply pins by turning off the upper P-channel and lower N-channel (see Fig- ures 1, 2). No new current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level inter- nal to the device.
Ordering Information
PART NUMBER TEMP. RANGE PACKAGE PKG. NO. CP82C82 (No longer available) 0oC to +70oC 20 Ld PDIP E20.3 IP82C82 (No longer available) -40oC to +85oC CS82C82 (No longer available) 0oC to +70oC 20 Ld PLCC N20.35 IS82C82 (No longer available) -40oC to +85oC CD82C82 (No longer available) 0oC to +70oC 20 Ld CERDIP F20.3 ID82C82 (No longer available) -40oC to +85oC MD82C82/B (No longer available) -55oC to +125oC 8406701RA SMD # MR82C82/B (No longer available) -55oC to +125oC 20 Pad CLCC J20.A 84067012A(No longer available) S M D # DIO DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 OESTB DQ CLK
FN2975 Rev 2.00 Page 4 of 8 Aug 25, 2015 Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Typical) JA JC oC to +150oC Maximum Junction Temperature (PLCC Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -40oC to +85oC (I82C82); TA = -55oC to +125oC (M82C82) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 - V C82C82, I82C82 (Note 1) 2.2 - V M82C82 (Note 1) VIL Logical Zero Input Voltage - 0.8 V VOH Logical One Output Voltage 2.9 - V I OH = -8mA, OE = GND VCC -0.4V - V I OH = -100A, OE = GND VOL Logical Zero Output Voltage - 0.4 V I OL = 8mA, OE = GND II Input Leakage Current -1.0 1.0 AV IN = GND or VCC, DIP Pins 1-9, 11 IO Output Leakage Current -10.0 10.0 AV O = GND or VCC, OE VCC -0.5V DIP Pins 12-19 ICCSB Standby Power Supply Cur- rent -1 0 AV IN = VCC or GND, VCC = 5.5V, Outputs Open ICCOP Operating Power Supply Current -1 m A / M H z T A = +25oC, VCC = 5V, Typical (See Note 2) NOTES: 1. VIH is measured by applying a pulse of magnitude = VIH min to one data input at a time and checking the corresponding device output for a valid logical “1” during valid input high time. Control pins (STB, OE) are tested separately with all device data input pins at VCC -0.4. Capacitance TA = +25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 13 pF Freq = 1MHz, all measurements are referenced to device GND C OUT Output Capacitance 20 pF
FN2975 Rev 2.00 Page 5 of 8 Aug 25, 2015 Timing Waveforms CL = 300pF (Note 1), Freq = 1MHz TA = -40oC to +85oC (I82C82); TA = -55oC to +125oC (M82C82) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS (1) TIVOV Propagation Delay Input to Output - 35 ns Notes 2, 3 (2) TSHOV Propagation Delay STB to Output - 55 ns Notes 2, 3 (3) TEHOZ Output Disable Time - 35 ns Notes 2, 3 (4) TELOV Output Enable Time - 50 ns Notes 2, 3 (5) TIVSL Input to STB Setup Time 0 - ns Notes 2, 3 (6) TSLIX Input to STB Hold Time 25 - ns Notes 2, 3 (7) TSHSL STB High Time 25 - ns Notes 2, 3 (8) TR, TF Input Rise/Fall Times - 20 ns Notes 2, 3 NOTES: 1. Output load capacitance is rated at 300pF for ceramic and plastic packages. 2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V. 3. Input test signals must switch between V IL - 0.4V and VIH +0.4V. TR, TF (8) TIVSL (5) TSLIX (6) 2.0V 0.8V VOH -0.1V TELOV (4) VOL +0.1V 2.4V 0.8V TEHOZ (3) TSHSL (7) (1) TIVOV TSHOV (2) INPUTS STB OUTPUTS OE Test Load Circuits NOTE: Includes stray and jig capacitance. OUTPUT TEST 300pF 150 1.7V POINT (NOTE) TIVOV, TSHOV, TELOV OUTPUT TEST 50pF 300 0.6V POINT (NOTE) TEHOZ OUTPUT HIGH DISABLE OUTPUT TEST 50pF 300 3.3V POINT (NOTE) TEHOZ OUTPUT LOW DISABLE
FN2975 Rev 2.00 Page 6 of 8 Aug 25, 2015 Burn-In Circuits MD82C82 CERDIP MR82C82 CLCC NOTES: 1. VCC = 5.5 0.5V, GND = 0V. 3. VIL = -0.2V to 0.4V. 4. R1 = 47k 5%. 5. R2 = 2.0k 5%. 6. R3 = 4.2k 5%. 7. R4 = 470k 5%. 8. C1 = 0.01F minimum. 9. F0 = 100kHz 10%. R1F2 A VCC R1F2 F0 R1 A A A A A A A A VCC R3 R3 F2 VCC/2 10 11 12 139 321 2 0 1 9 R3 VCC/2 R3 VCC/2 R3 VCC/2 R3 VCC/2 R3 VCC/2 R3 R3R3R3 F0 F1 V CC/2 VCC VCC/2
FN2975 Rev 2.00 Page 7 of 8 Aug 25, 2015 Die Characteristics DIE DIMENSIONS: 118.1 x 92.1 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11k Å 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ 1kÅ WORST CASE CURRENT DENSITY: 2.00 x 105 A/cm2 Metallization Mask Layout 82C82 1 20 19 18 1414 121110 8 9 D11 D10 V CC DO0 D01 D12 D13 D14 D15 D16 D17 OE GND STB DO7 DO6 DO5 DO4 DO3 DO2
FN2975 Rev 2.00 Page 8 of 8 Aug 25, 2015 82C82 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1997-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE August 25, 2015 FN2975.2 - Ordering Information Table on page 2. - Added Revision History. - Added About Intersil Verbiage.