82C59A

82C59A RENESAS | Alldatasheet

Document overview

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• PDF pages: 23

Technical content

Features

• Pb-Free Plus Anneal Available (RoHS Compliant)
• 12.5MHz, 8MHz and 5MHz Versions Available
• High Speed, “No Wait-State” Operation with 12.5MHz 80C286 and 8MHz 80C86/88
• Pin Compatible with NMOS 8259A
• 80C86/88/286 and 8080/85/86/88/286 Compatible
• Eight-Level Priority Controller, Expandable to

64 Levels

• Programmable Interrupt Modes
• Individual Request Mask Capability
• Fully Static Design
• Fully TTL Compatible
• Low Power Operation
• Single 5V Power Supply
• Commercial, Industrial and Military Operating Temperature Ranges Available

FN2784 Rev 6.00 Page 2 of 23 Sep 8, 2015

Ordering Information

RANGE (°C) PKG. DWG. #5MHz PART MARKING 8MHz PART MARKING 12.5MHz PART MARKING CP82C59A CP82C59A CP82C59A-12 (No longer available, recommended replacement: CP82C59A-12Z) CP82C59A-12 28 Ld PDIP 0 to +70 E28.6 CP82C59AZ (Note) CP82C59AZ CP82C59A-12Z (Note) CP82C59A-12Z 28 Ld PDIP* (Pb-Free) 0 to +70 E28.6 CS82C59A (No longer available, recommended replacement: CS82C59AZ) CS82C59A CS82C59A-12 (No longer available, recommended replacement: CS82C59A-12Z) CS82C59A-12 28 Ld PLCC 0 to +70 N28.45 CS82C59A96 (No longer available, recommended replacement: CS82C59AZ96) CS82C59A CS82C59A-1296 (No longer available or supported) CS82C59A-12 28 Ld PLCC (Tape & Reel) 0 to +70 N28.45 CS82C59AZ (Note) CS82C59AZ CS82C59A-12Z (Note) CS82C59A-12Z 28 Ld PLCC (Pb-Free) 0 to +70 N28.45 CS82C59AZ96 (Note) CS82C59AZ CS82C59A-12Z96 (Note) CS82C59A-12Z 28 Ld PLCC (Pb-Free, Tape & Reel) 0 to +70 N28.45 IS82C59A IS82C59A IS82C59A-12 IS82C59A-12 28 Ld PLCC -40 to +85 N28.4 5 IS82C59AX96 No longer available, recommended replacement: IS82C59A, IS82C59AZX96) IS82C59A IS82C59A-12X96 IS82C59A-12 28 Ld PLCC (Tape & Reel) -40 to +85 N28.45 IS82C59AZ (Note) IS82C59AZ IS82C59A-12Z (Note) IS82C59A-12Z 28 Ld PLCC (Pb-Free) -40 to +85 N28.45 IS82C59AZX96 (Note) IS82C59AZ IS82C59A-12Z96 (Note) IS82C59A-12Z 28 Ld PLCC (Pb-Free, Tape & Reel) -40 to +85 N28.45 ID82C59A ID82C59A 28 Ld CERDIP -40 to +85 F28.6 MD82C59A/B MD82C59A/B -55 to +125 F28.6 5962-8501601YA 5962- 8501601YA 5962-8501602YA 5962- 8501602YA SMD# -55 to +125 F28.6 5962-85016023A 5962- 85016023A

28 Pad CLCC -

SMD# -55 to +125 J28.A *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN2784 Rev 6.00 Page 3 of 23 Sep 8, 2015 Functional Diagram Pinouts 82C59A (PDIP, CERDIP) TOP VIEW 82C59A (PLCC, CLCC) TOP VIEW CS WR RD CAS 0 CAS 1 GND V CC INTA IR7 IR6 IR5 IR3 IR1 IR0 INT SP /EN CAS 2 IR4 IR2 1911 3 2 14 14 15 16 17 1812 13 28 27 26 VCC RD WR CS INTA IR7 IR6 IR5 IR4 IR3 IR2 IR1 CAS 0 IR0 CAS 1 GND CAS 2 SP/ EN INT PIN DESCRIPTION D7 - D0 Data Bus (Bidirectional) RD Read Input WR Write Input A0 Command Select Address CS Chip Select CAS 2 - CAS 0 Cascade Lines SP/EN Slave Program Input Enable INT Interrupt Output INTA Interrupt Acknowledge Input IR0 - IR7 Interrupt Request Inputs PRIORITY RESOLVER IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 INTERRUPT REQUEST REG (IRR) INTERRUPT MASK REG (IMR) CONTROL LOGIC INTERNAL BUS INT DATA BUS BUFFER CASCADE BUFFER COMPARATOR CAS 0 CAS 1 CAS 2 READ/ WRITE LOGIC SP/EN WR RD INTA IN - SERVICE REG (ISR) CS D7-D0 FIGURE 1.

microcomputer with little or no effect on throughput. effectiveness of using such devices. VCC I V CC: The +5V power supply pin. A 0.1F capacitor between pins 28 and 14 is recommended for decoupling. functions are independent of CS. WR I WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from the CPU. RD I READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus for the CPU. D7 - D0 I/O BIDIRECTIONAL DATA BUS: Control, status, and interrup t-vector information is transferred via this bus. pins are outputs for a master 82C59A and inputs for a slave 82C59A. designate a master (SP = 1) or slave (SP = 0). thus, it is connected to the CPU's interrupt pin. (Level Triggered Mode). Internal pull-up resistors are implemented on IR0 - 7. a sequence of interrupt acknowledge pulses issued by the CPU. to the CPU A0 address line (A1 for 80C86/88/286). FIGURE 2. POLLED METHOD

FN2784 Rev 6.00 Page 6 of 23 Sep 8, 2015 Interrupt Request Register (IRR) and In-Service Register (ISR) The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register (lRR) and the In- Service Register (lSR). The IRR is used to indicate all the interrupt levels which are requesting service, and the ISR is used to store all the interrupt levels which are currently being serviced. Priority Resolver This logic block determines the priorities of the bits set in the lRR. The highest priority is selected and strobed into the corresponding bit of the lSR during the INTA sequence. Interrupt Mask Register (IMR) The lMR stores the bits which disable the interrupt lines to be masked. The IMR operates on the output of the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower priority. Interrupt (INT) This output goes directly to the CPU interrupt input. The VOH level on this line is designed to be fully compatible with the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286 input levels. Interrupt Acknowledge (INTA INTA pulses will cause the 82C59A to release vectoring information onto the data bus. The format of this data depends on the system mode (PM) of the 82C59A. Data Bus Buffer This 3-state, bidirectional 8-bit buffer is used to interface the 82C59A to the System Data Bus. Control words and status information are transferred through the Data Bus Buffer. Read/Write Control Logic The function of this block is to accept output commands from the CPU. It contains the Initialization Command Word (lCW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 82C59A to be transferred onto the Data Bus. Chip Select (CS) A LOW on this input enables the 82C59A. No reading or writing of the device will occur unless the device is selected. Write (WR) A LOW on this input enables the CPU to write control words (lCWs and OCWs) to the 82C59A. Read (RD) A LOW on this input enables the 82C59A to send the status of the Interrupt Request Register (lRR), In-Service Register (lSR), the Interrupt Mask Register (lMR), or the interrupt level (in the poll mode) onto the Data Bus. This input signal is used in conjunction with WR and RD signals to write commands into the various command registers, as well as to read the various status registers of the chip. This line can be tied directly to one of the system address lines. The Cascade Buffer/Comparator This function block stores and compares the IDs of all 82C59As used in the system. The associated three I/O pins (CAS0 - 2) are outputs when the 82C59A is used as a master and are inputs when the 82C59A is used as a slave. As a master, the 82C59A sends the ID of the interrupting slave device onto the CAS0 - 2 lines. The slave, thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses. (See section “Cascading the 82C59A”.) Interrupt Sequence The powerful features of the 82C59A in a microcomputer system are its programmability and the interrupt routine addressing capability. The latter allows direct or indirect jumping to the specified interrupt routine requested without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of CPU being used.

1. One or more of the INTERRUPT REQUEST lines
2. The 82C59A evaluates those requests in the priority
3. The CPU acknowledges the lNT and responds with an
4. Upon receiving an lNTA from the CPU group, the highest

code (11001101) onto the 8-bit data bus through D0 - D7.

1. This CALL instruction will initiate two additional INTA

pulses to be sent to 82C59A from the CPU group.

1. These two INTA pulses allow the 82C59A to release its

preprogrammed subroutine address onto the data bus.

1. This completes the 3-byte CALL instruction released by

at the end of the interrupt sequence.

1. The 82C59A does not drive the data bus during the first
2. The 80C86/88/286 CPU will initiate a second INTA pulse.
3. This completes the interrupt cycle. In the AEOI mode, the

command is issued at the end of the interrupt subroutine. output from the master 82C59A. lNTA pulse, the CALL opcode is enabled onto the data bus. appropriate service routine is enabled onto the data bus. FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE

FN2784 Rev 6.00 Page 8 of 23 Sep 8, 2015 When interval = 4 bits, A5 - A7 are programmed, while A0 - A4 are automatically inserted by the 82C59A. When interval = 8, only A6 and A7 are programmed, while A0 - A5 are automatically inserted. During the third INTA pulse, the higher address of the appropriate service routine, which was programmed as byte 2 of the initialization sequence (A8 - A15), is enabled onto the bus. 80C86, 8OC88, 80C286 Interrupt Response Mode 80C86/88/286 mode is similar to 8080/85 mode except that only two Interrupt Acknowledge cycles are issued by the processor and no CALL opcode is sent to the processor. The first interrupt acknowledge cycle is similar to that of 8080/85 systems in that the 82C59A uses it to internally freeze the state of the interrupts for priority resolution and, as a master, it issues the interrupt code on the cascade lines. On this first cycle, it does not issue any data to the processor and leaves its data bus buffers disabled. On the second interrupt acknowledge cycle in the 86/88/286 mode, the master (or slave if so programmed) will send a byte of data to the processor with the acknowledged interrupt code composed as follows (note the state of the ADI mode control is ignored and A5 - A11 are unused in the 86/88/286 mode). Programming the 82C59A The 82C59A accepts two types of command words generated by the CPU: 1. Initialization Command Words (ICWs): Before normal operation can begin, each 82C59A in the system must be brought to a starting point - by a sequence of 2 to 4 bytes timed by WR pulses. 2. Operation Command Words (OCWs): T h e s e a r e t h e command words which command the 82C59A to operate in various interrupt modes. Among these modes are: a. Fully nested mode. b. Rotating priority mode. c. Special mask mode. d. Polled mode. The OCWs can be written into the 82C59A anytime after initialization. Initialization Command Words (lCWs) General Whenever a command is issued with A0 = 0 and D4 = 1, this is interpreted as Initialization Command Word 1 (lCW1). lCW1 starts the initialization sequence during which the following automatically occur: a. The edge sense circuit is reset, which means that follow- ing initialization, an interrupt request (IR) input must make a low-to-high transition to generate an interrupt. b. The Interrupt Mask Register is cleared. c. lR7 input is assigned priority 7. d. Special Mask Mode is cleared and Status Read is set to lRR. CONTENT OF SECOND INTERRUPT VECTOR BYTE IR INTERVAL = 4 D7 D6 D5 D4 D3 D2 D1 D0

7 A 7 A 6 A 5 11100

6 A 7 A 6 A 5 11000

5 A 7 A 6 A 5 10100

4 A 7 A 6 A 5 10000

3 A 7 A 6 A 5 01100

2 A 7 A 6 A 5 01000

1 A 7 A 6 A 5 00100

0 A 7 A 6 A 5 00000

IR INTERVAL = 8 D7 D6 DS D4 D3 D2 D1 D0

7 A 7 A 6 111000

6 A 7 A 6 110000

5 A 7 A 6 101000

4 A 7 A 6 100000

3 A 7 A 6 011000

2 A 7 A 6 010000

1 A 7 A 6 001000

0 A 7 A 6 000000

CONTENT OF THIRD INTERRUPT VECTOR BYTE D7 D6 D5 D4 D3 D2 D1 D0 A15 A14 A13 A12 A11 A10 A9 A8 CONTENT OF INTERRUPT VECTOR BYTE FOR 80C86/88/286 SYSTEM MODE D7 D6 D5 D4 D3 D2 D1 D0 l R 7 T 7T 6T 5T 4T 3 1 1 1 l R 6 T 7T 6T 5T 4T 3 1 1 0 I R 5 T 7T 6T 5T 4T 3 1 0 1 I R 4 T 7T 6T 5T 4T 3 1 0 0 I R 3 T 7T 6T 5T 4T 3 0 1 1 I R 2 T 7T 6T 5T 4T 3 0 1 0 I R 1 T 7T 6T 5T 4T 3 0 0 1 I R 0 T 7T 6T 5T 4T 3 0 0 0

NOTE: Master/Slave in ICW4 is onl y used in the buffered mode. the 82C59A while A6 - A15 are programmed externally. system. If SNGL = 1, no ICW3 will be issued. 286, only byte 2) through the cascade lines. 80C86/88/286) are released by it on the Data Bus. connected to in the master ID). and the master/slave determination is by M/S. BUF = 0, M/S has no function. 82C59A for 80C86/88/286 system operation. FIGURE 6. 82C59A INITIALIZATION SEQUENCE

0 A7 A6 A5 LTIM1A D I S N G L I C 4

1 A15 A14 A13 A11 A10 A9 A8A12

FIGURE 7. 82C59A INITIALIZATION COMMAND WORD FORMAT NOTE: Slave ID is equal to the corresponding master IR input.

FN2784 Rev 6.00 Page 11 of 23 Sep 8, 2015 Operation Command Words (OCWs) After the Initialization Command Words (lCWs) are programmed into the 82C59A, the device is ready to accept interrupt requests at its input lines. However, during the 82C59A operation, a selection of algorithms can command the 82C59A to operate in various modes through the Operation Command Words (OCWs). Operation Command Word 1 (OCW1) OCW1 sets and clears the mask bits in the Interrupt Mask Register (lMR) M7 - M0 represent the eight mask bits. M = 1 indicates the channel is masked (inhibited), M = 0 indicates the channel is enabled. Operation Command Word 2 (OCW2) R, SL, EOI - These three bits control the Rotate and End of Interrupt modes and combinations of the two. A chart of these combinations can be found on the Operation Command Word Format. L2, L1, L0 - These bits determine the interrupt level acted upon when the SL bit is active. Operation Command Word 3 (OCW3) ESMM - Enable Special Mask Mode. When this bit is set to 1 it enables the SMM bit to set or reset the Special Mask Mode. When ESMM = 0, the SMM bit becomes a “don’t care”. SMM - Special Mask Mode. If ESMM = 1 and SMM = 1, the 82C59A will enter Special Mask Mode. If ESMM = 1 and SMM = 0, the 82C59A will revert to normal mask mode. When ESMM = 0, SMM has no effect. Fully Nested Mode This mode is entered after initialization unless another mode is programmed. The interrupt requests are ordered in priority from 0 through 7 (0 highest). When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus. Additionally, a bit of the Interrupt Service register (IS0 - 7) is set. This bit remains set until the microprocessor issues an End of Interrupt (EOI) command immediately before returning from the service routine, or if the AEOI (Automatic End of Interrupt) bit is set, until the trailing edge of the last INTA . While the IS bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels will generate an interrupt (which will be acknowledged only if the microprocessor internal interrupt enable flip-flop has been re-enabled through software). After the initialization sequence, IR0 has the highest priority and IR7 the lowest. Priorities can be changed, as will be explained in the rotating priority mode or via the set priority command.OPERATION COMMAND WORDS (OCWs) A 0 D 7D 6 D 5D 4D 3D 2D 1D 0 OCW1

1 M 7M 6 M 5M 4M 3M 2M 1M 0

0 R SL EOI 0 0 L2 L1 L0

0 R SL EOI 0 L 2 L1 L00

FIGURE 8. 82C59A OPERATION COMMAND WORD FORMAT

FN2784 Rev 6.00 Page 13 of 23 Sep 8, 2015 End of Interrupt (EOI) The In-Service (IS) bit can be reset either automatically following the trailing edge of the last in sequence INTA pulse (when AEOI bit in lCW1 is set) or by a command word that must be issued to the 82C59A before returning from a service routine (EOI Command). An EOI command must be issued twice if servicing a slave in the Cascade mode, once for the master and once for the corresponding slave. There are two forms of EOl command: Specific and Non- Specific. When the 82C59A is operated in modes which preserve the fully nested structure, it can determine which IS bit to reset on EOI. When a Non-Specific command is issued the 82C59A will automatically reset the highest IS bit of those that are set, since in the fully nested mode the highest IS level was necessarily the last level acknowledged and serviced. A non-specific EOI can be issued with OCW2 When a mode is used which may disturb the fully nested structure, the 82C59A may no longer be able to determine the last level acknowledged. In this case a Specific End of Interrupt must be issued which includes as part of the command the IS level to be reset. A specific EOl can be issued with OCW2 (EOI = 1, SL = 1, R = 0, and L0 - L2 is the binary level of the IS bit to be reset). An lRR bit that is masked by an lMR bit will not be cleared by a non-specific EOI if the 82C59A is in the Special Mask Mode. Automatic End of Interrupt (AEOI) Mode If AEOI = 1 in lCW4, then the 82C59A will operate in AEOl mode continuously until reprogrammed by lCW4. In this mode the 82C59A will automatically perform a non-specific EOI operation at the trailing edge of the last interrupt acknowledge pulse (third pulse in 8080/85, second in 80C86/88/286). Note that from a system standpoint, this mode should be used only when a nested multilevel interrupt structure is not required within a single 82C59A. Automatic Rotation (Equal Priority Devices) In some applications there are a number of interrupting devices of equal priority. In this mode a device, after being serviced, receives the lowest priority, so a device requesting an interrupt will have to wait, in the worst case until each of 7 other devices are serviced at most once. For example, if the priority and “in service” status is: Before Rotate (lR4 the highest priority requiring service) After Rotate (lR4 was serviced, all other priorities rotated correspondingly) There are two ways to accomplish Automatic Rotation using OCW2, the Rotation on Non-Specific EOI Command (R = 1, SL = 0, EOI = 1) and the Rotate in Automatic EOI Mode which is set by (R = 1, SL = 0, EOI = 0) and cleared by Specific Rotation (Specific Priority) The programmer can change priorities by programming the lowest priority and thus, fixing all other priorities; i.e., if IR5 is programmed as the lowest priority device, then IR6 will have the highest one. The Set Priority command is issued in OCW2 where: R = 1, SL = 1, L0 - L2 is the binary priority level code of the lowest priority device. Observe that in this mode internal status is updated by soft- ware control during OCW2. However, it is independent of the End of Interrupt (EOI) command (also executed by OCW2). Priority changes can be executed during an EOI command by using the Rotate on Specific EOl command in OCW2 (R = 1, SL = 1, EOI = 1, and L0 - L2 = IR level to receive lowest priority). Interrupt Masks Each Interrupt Request input can be masked individually by the Interrupt Mask Register (IMR) programmed through OCW1. Each bit in the lMR masks one interrupt channel if it is set (1). Bit 0 masks IR0, Bit 1 masks IR1 and so forth. Masking an IR channel does not affect the operation of other channels. Special Mask Mode Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 “ I S ” S t a t u s 01010000 Priority Status 76543210 lowest highest IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0 “ I S ” S t a t u s 01000000 Priority Status 21076543 highest lowest

FN2784 Rev 6.00 Page 14 of 23 Sep 8, 2015 The difficulty here is that if an Interrupt Request is acknowledged and an End of Interrupt command did not reset its IS bit (i.e., while executing a service routine), the 82C59A would have inhibited all lower priority requests with no easy way for the routine to enable them. That is where the Special Mask Mode comes in. In the Special Mask Mode, when a mask bit is set in OCW1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. Thus, any interrupts may be selectively enabled by loading the mask register. The Special Mask Mode is set by OCW3 where: ESMM = 1, SMM = 1, and cleared where ESMM = 1, SMM = 0. Poll Command In this mode, the INT output is not used or the microprocessor internal Interrupt Enable flip flop is reset, disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P = 1 in OCW3. The 82C59A treats the next RD pulse to the 82C59A (i.e., RD = 0, CS = 0) as an interrupt acknowledge, sets the appropriate IS bit if there is a request, and reads the priority level. Interrupt is frozen from WR to RD. The word enabled onto the data bus during RD is: W0 - W2: Binary code of the highest priority level request- ing service. I: Equal to a “1” if there is an interrupt. This mode is useful if there is a routine command common to several levels so that the INTA sequence is not needed (saves ROM space). Another application is to use the poll mode to expand the number of priority levels to more than 64. D7 D6 D5 D4 D3 D2 D1 D0 I---- W 2 W 1 W 0 EDGE SENSE LATCH LTIM BIT 0 = EDGE 1 = LEVEL VCC IR MODE 80C86/ MODE INTA FREEZE INTA FREEZE FREEZE READ IRR WRITE MASK READ IMR READ ISR MASTER CLEAR MASK LATCH REQUEST LATCH IN - SERVICE LATCH NON- MASKED REQ CLR Q SET TO OTHER PRIORITY CELLS PRIORITY RESOLVER CONTROL LOGIC SET ISR CLR ISR ISR BIT QD C CLR QD CQ CLR SET Q NOTES: 1. Master clear active only during ICW1. 2. FREEZE is active during INTA and poll sequence only. 3. Truth Table for D-latch. C D Q Operation 1D 1 D 1 F o l l o w 0X Q n - 1 H o l d

when an End of Interrupt Command is issued. interrupt request lines which are masked. Register Command is issued with OCW3 (RR = 1, RIS = 0). Register Command is issued with OCW3 (RR = 1, RIS = 1). following a “poll write” operation as an INTA. After initialization, the 82C59A is set to lRR. will contain the lMR whenever RD is active and A0 = 1 (OCW1). Polling overrides status read when P = 1, RR = 1 in OCW3. This mode is programmed using bit 3 in lCW1. without generating another interrupt. level on an IR input, and there is no need for an edge detection. second interrupt from occurring. sure to note that the request latch is a transparent D type latch. another lR7 occurs it is a default. internal pull-up resistors on the IR pins.

1. Edge triggered mode only.

FIGURE 10. IR TRIGGERING TIMING REQUIREMENTS

then reading its In-Service register and checking for zero. ter, too. If not, no EOI should be sent. SP/EN output becomes active. determines whether it is a master or a slave. decoding is required to activate each 82C59A. NOTE: Auto EOI is supported in the slave mode for the 82C59A. address of 0 (zero) only after all other addresses are used. FIGURE 11. CASCADING THE 82C59A

FN2784 Rev 6.00 Page 17 of 23 Sep 8, 2015 Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Typical) JA (°C/W) JC (°C/W) (PLCC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings ” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VlH Logical One Input Voltage 2.0 2.2 V C82C59A, I82C59A M82C59A VIL Logical Zero Input Voltage - 0.8 V VOH Output HIGH Voltage 3.0 VCC -0.4 V IOH = -2.5mA lOH = -100A VOL Output LOW Voltage - 0.4 V l OL = +2.5mA II Input Leakage Current -1.0 +1.0 AV IN = GND or VCC, Pins 1-3, 26-27 IO Output Leakage Current -10.0 +10.0 AV OUT = GND or VCC, Pins 4-13, 15-16 ILIR IR Input Load Current - -200 VIN = 0V VIN = VCC lCCSB Standby Power Supply Current - 10 AV CC = 5.5V, VIN = VCC or GND Outputs Open, (Note 1) ICCOP Operating Power Supply Current - 1 mA/MHz V CC = 5.0V, VIN = VCC or GND, Outputs Open, TA = 25°C, (Note 2) NOTES: 1. Except for IR0 - lR7 where VIN = VCC or open. 2. ICCOP = 1mA/MHz of peripheral read/write cycle time. (ex: 1.0s I/O read/write cycle time = 1mA). Capacitance TA = +25°C SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance 15 pF FREQ = 1MHz, all measurements reference to device GND.COUT Output Capacitance 15 pF CI/O I/O Capacitance 15 pF SYMBOL PARAMETER 5MHz 8MHz 12.5MHz UNITS TEST CONDITIONSMIN MAX MIN MAX MIN MAX TIMING REQUIREMENTS (1) TAHRL A0/CS Setup to RD/INTA 10 - 10 - 5 - ns (2) TRHAX A0/CS Hold after RD/INTA 5-5-0- n s (3) TRLRH RD /lNTA Pulse Width 235 - 160 - 60 - ns

FN2784 Rev 6.00 Page 18 of 23 Sep 8, 2015 AC Test Circuit (4) TAHWL A0/CS Setup to WR 0-0-0- n s (5) TWHAX A0/CS Hold after WR 5-5-0- n s (6) TWLWH WR Pulse Width 165 - 95 - 60 - ns (7) TDVWH Data Setup to WR 240 - 160 - 70 - ns (8) TWHDX Data Hold after WR 5-5-0- n s (9) TJLJH Interrupt Request Width Low 100 - 100 - 40 - ns (10) TCVlAL Cascade Setup to Second or Third INTA (Slave Only) 55 - 40 - 30 - ns (11) TRHRL End of RD to next RD, End of INTA (within an INTA sequence only) 160 - 160 - 90 - ns (12) TWHWL End of WR to next WR 190 - 190 - 60 - ns (13) TCHCL (Note 1) End of Command to next command (not same command type), End of INTA sequence to next INTA sequence 500 - 400 - 90 - ns TIMING RESPONSES (14) TRLDV Data Valid from RD /INTA - 160 - 120 - 40 ns 1 (15) TRHDZ Data Float after RD /INTA 5 100 5 85 5 22 ns 2 (16) TJHlH Interrupt Output Delay - 350 - 300 - 90 ns 1 (17) TlALCV Cascade Valid from First INTA (Master Only) - 565 - 360 - 50 ns 1 (18) TRLEL Enable Active from RD or INTA - 125 - 100 - 40 ns 1 (19) TRHEH Enable Inactive from RD or INTA -6 0-5 0-2 2 n s 1 (20) TAHDV Data Valid from Stable Address - 210 - 200 - 60 ns 1 (21) TCVDV Cascade Valid to Valid Data - 300 - 200 - 70 ns 1 NOTE: 1. Worst case timing for TCHCL in an actual microprocessor system is typically greater than the values specified for the 82C59A, (i.e. 8085A = 1.6s, 8085A -2 = 1s, 80C86 = 1s, 80C286 -10 = 131ns, 80C286 -12 = 98ns). SYMBOL PARAMETER 5MHz 8MHz 12.5MHz UNITS TEST CONDITIONSMIN MAX MIN MAX MIN MAX TEST CONDITION DEFINITION TABLE TEST CONDITION V 1 R1 R2 C1 1 1.7V 523  Open 100pF 2V CC 1.8k 1.8k 50pF R2C1 (NOTE) OUTPUT FROM DEVICE UNDER TEST TEST POINT NOTE: Includes stray and jig capacitance.

1. Interrupt Request (IR) must remain HIGH until leading edge of first INTA.
2. During first INTA the Data Bus is not active in 80C86/88/286 mode.

FIGURE 15. INTA SEQUENCE

FN2784 Rev 6.00 Page 21 of 23 Sep 8, 2015 5962-850160X3A CLCC Burn-In Circuits 1911 3 2 14 14 15 16 17 1812 13 28 27 26 CAS0 CAS1 GND CAS2 SP/EN IR0 VCC/2 IR6 IR5 IR4 IR1 IR7 IR3 IR2 R1 R1 R1 R1 R4 R2 R1 R1 R1R1 R1 R1 D7 RD WR GND A0 INTA VCC C1 NOTES: 1. VCC = 5.5V 0.5V. 3. VIL = -0.2V to 0.4V. 4. GND = 0V. 5. R1 = 47k 5%. 6. R2 = 510 5%. 7. R3 = 10k 5%. 8. R4 = 1.2k 5%. 9. C1 = 0.01F min. 10. F0 = 100kHz 10%.

FN2784 Rev 6.00 Page 22 of 23 Sep 8, 2015 Die Characteristics METALLIZATION: Type: Si-Al-Cu Thickness: Metal 1: 8k Å  0.75kÅ Metal 2: 12kÅ 1.0kÅ GLASSIVATION: Type: Nitrox Thickness: 10k Å  3.0kÅ Metallization Mask Layout 82C59A RD WR CS VCC INTA CAS0 CAS1 GND CAS2 SP/EN INT D0 D1 D2 D3 D4 D5 IR1 IR2 IR3 IR4 IR5 IR6 IR0 IR7

FN2784 Rev 6.00 Page 23 of 23 Sep 8, 2015 82C59A Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1997-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support.

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 8, 2015 FN2784.6 - Ordering Information Table on page 2. - Added Revision History and About Intersil sections.