82C55

TMP82C55A TOSHIBA | Alldatasheet

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CMOS PROGRAMMABLE PERIPHERAL INTERFACE TMP82C55AP-2/TMP82C55AM-2 TMP82C55AP-10/TMP82C55AM-10 1. GENERAL DESCRIPTION AND FEATURES The TMP82C55A (hereinafter referred to as PPI) is a CMOS high Speed programmable input/output interface with three 8-bit I/O ports. 24 I/O Ports are divided into two groups (Port A and Port B) which are programmable independently by control words provided by MPU. The PPI has three operation modes (Mode 0, 1 and 2) and is copable of versatile interface between MPU and peripheral devices. The TMP82C55A is fabricated using Toshiba’s CMOS Silicon Gate Technology. (1) High Speed Version (TRD = 100ns MAX: TMP82C55AP-10/AM-10) (2) Low power consumption. 2mA Type. 10pA Max. (@5V, Stand-by) (3) 5V £10% Single power supply (4) 24 programmable I/O ports (5) Three operation modes (Mode 0, Mode 1, Mode 2) (6) Bit set/reset capability (7) Up to 8 output ports of port B and C are capable of driving a darlington transistor (Min.—1.0mA @VOH=1.5V) (8) Extended operating temperature: —40 °C to +85 °C (9) Available 40pin Standard DIP and SOP See MPU85-133

1. PIN CONNECTIONS (TOP VIEW) PA301 40 1 PAg PA2C2 39 [PAs PAL G3 38 [PA PAgI4 37 [IPAz ROGS 36 1 WR sae 35 [IRESET (GND) Vss 7 34 Do Aig8 33 1Dy Aodg 32 [D2 PC7 10 31 [D3 PC6Q 11 30 [Dg PCs] 12 29 Ds PCa 13 28 Ds PCof 14 27 D7 PC, G15 26 DVcc(+5V) PC? 16 25 1 PB7 P3017 24 DPBe PBo fl 18 23 [PBs PB, 019 22 DPBa PB2 1 20 21 DPB3 TMP82C55AP-2/AP-10 TMP82C55AM-2/AM-10 950409 3. BLOCK DIAGRAM D7xDo it BIDIRECTIONAL DATA RD ——>d WR ——>q rad READ WRITE CONTROL LOGIC Ao —" DATA BUS BUFFER A, —— RESET ——" GROUPA GROUP B CONTROL CONTROL |__INTERNAL 8-BIT BUS | GROUP A GROUP B fat 4a igs 8| JO 170 vO. 1/0 PA7~PAg PC7~PC4 — PC3~PCo PB7~PBo 050889 MPU85-134

SSSSSSSSSSSSSSSSSsSSsSessseee Oe’ 4. PINNAMES AND PIN FUNCTIONS | it/Output Pin Name | Number |inputOutpu Function of Pin 3-state 3-state bidirectional 8-bit data bus. Used for data transfer with Do~D7 VO 3-state |MPU. Also, used for transfer of contro! words to PPI and status information from PPI. 3-state 8-bit I/O Port A. PAg~PA7 VO 3-state | Operation mode and input/output configuration are defined by software. Port A contains the output latch buffer and input latch. 3-state 8-bit I/O Port B. PBo~PB7 1/0 3-state {Operation mode and input/output configuration are defined by software. Port B contains the output latch buffer and input latch. 3-state 8-bit I/O Port C. Operation mode and input/output configuration are defined by software. Port C can be divided into two 4-bit ports by the mode PCo~Pt VO 3- o~ PC? © Sstate control and also, used as the control signal for Port A and Port B. In this case, 3 bits of PCo to PC2 are used for Port B and 5 bits of PC3 to PC7 for Port A. | if Chip select input. ZT | 1 | input [When this terminal is at “L” level, data transfer PPI and MPU Pp becomes possible. At “H” level, the data bus is placed in the high impedance state and control from the processor is ignored. Read signal Input When this terminal is at “L" level, data that is input into the port is transferred to MPU. - Write signal. WR 1 Input When this terminal is at “L" level, data or control word is written into PPI from MPU. Ro, A 2 Input | Used for selecting Port A, B, C and the control registers. Normally, om p this terminal is connected to low order 2 bits of the address bus. When this terminals is at “H” level, all internal registers including RESET 1 Input the control register are cleared. In addition, all ports (Port A, B, C) are placed in the input mode (high impedance) of mode 0. |_vec | + fPowersuppisy 050489 SSeS MPU85-135

1. FUNCTIONAL DESCRIPTION The PPI is a programmable peripheral interface device with three 8-bit ports (Port A, B and C) and two control registers. 24 I/O ports are divided into 12-bit group A and group B. Group A consists of Port A and high order 4 bits of Port C, while Group B consists of Port B and low order 4 bits of Port C. Each group is independently programmable by control words provided from MPU. There are three operation modes available for the PPI. In mode 0, two 8-bit I/O ports and two 4-bit I/O ports can be programmed as input or output ports, respectively. In mode 1, 24 I/O ports are divided into Group A and Group B. 8 bits of each group are used as input or output port and of the remaining 4 bits, 3 bits are used as handshaking and interrupt control signal. Mode 2 is applicable only to group A and the ports are used as a bidirectional 8-bit data bus and 5-bit control signal. In case of Port C being used as the output, any bits of Port C can be set/reset. There are two control registers; one is used for mode setting and the other for bit set/reset contro!. The control registers can only be written into. Further, when the reset input (RESET) becomes “1”, the control registers are reset and all I/O ports are placed in input mode (high impedance status). Table 5.1 Basic Operation of TMP82C55A. 0 0 it) 0 1 Data bus <— PortA G 1 Qo 0 1 | Data bus < PortB 1 0 i 0 1 | Data bus <— Port 0} o0/}o0 1 0 | Porta <— Data bus it} 1 0 1 i} PortB < Data bus 1 1 0 1 | 0 | Control register — Data bus x x 1 x | x | Data bus = 3-state x x it) 1 | 1 Data bus = 3-state 1 1 it) 0 1 inhibition of combination 9050489

5.1 MODE SELECTION

There are three basic modes of operation that can be selected by control words. Mode 0-Basic /O (Group A, Group B) Mode 1-Strobe input/Strobe output (Group A, Group B) Mode 2-Two-way bus (Port A only) Operation modes for Group A and Group B can be independently defined by the control word form the MPU. If D7 is set to “1” in writing a control word into the PPI, operation mode is selected, while of D7=“0”, the set/reset function for Port C is selected. MPU85-136

5.1.1 Control word to define operation mode

Figure 5.1 shows the control words to define operation mode of the TMP82C55A. Control word [1 | Groupacentol [Group 8 contro Lo [os [os [oe fos | % [oo | oo | Input/output selection of low order 4 bits of Port C ‘0’ = Output ‘1’ sInput | input/output selection of Port B ‘0’ = Output “1'= Input | Mode selection of Group B | ‘0’ =Mode 0 ‘1’ =Mode 1 Input/output selection of high | order 4 bits of Port C ‘0’ = Output "1" = Input i a Input/output selection of Port A ‘0’ = Output “q's Input Mode Selection Group A ‘0'=ModeO D6 DS 0 0 =Moded 1 = Designation of mode set flag $ } =modes x: Don't care osoae9 Figure 5.1 Control Word for Mode Selection ee MPU85-137

5.1.2 Port C bit set/reset control word

Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset control word. Fig. 5.2 shows the Port C bit set/reset control word. Control Word [or [os [os [ba [os Joe | on | bv | : Bit set/reset selection Don't care "0" = Reset "1" =Set Bit set/reset flag [Peo | Lo jo [a [Pc | po ft fo | Pe | po | a ft | Pca | F- aitsetection pa fo fo | pce | ea [re | os _ 050489 Figure 5.2 Control Word for Bit Set/Reset

5.2 OPERATION MODES

5.2.1 Mode 0 (Basic 1/0)

; This functional configuration is used for simple input or output operations. No | ‘handshaking’ is required and data is simply written to or read from a specified part. Output data to the ports from MPU are latched out but input data from the ports are not latched. In Mode 0, 24 I/O terminals are divided into four groups of Port A (8 bits), Port B (8 bits), high order 4 bits of Port C and low order 4 bits of Port C. Each port can be programmed to be input or output. The configuration of each port are determined according to the contents of Bit 4 (D4), 3 (Dg), 1 (Dj) and 0 (Do) of the control word for mode selection. The I/O configuration of each port in Mode 0 are shown in Table 5.2. MPU85-138

Mode Setting Control Word Port C Port C Port A PortB

0 Q i) 0 Out Out Out Out

0 0 i} 1 Out Out Out In

0 QO 1 i) Out Out In Out

0 Q 1 1 Out Out In In

LY) 1 i} 0 Out In Out Out 0 1 0 1 Out In Out In 0 1 1 0 Out In In Out i?) 1 1 1 Out In In In

1 Q 0 i} In Out Out Out

1 1 i) 0 In In Out Out 1 1 0 1 In In Out In 1 1 1 0 In In In Out 1 1 1 1 In In In { In . oo 050489 Figure 5.3 Port Definition in Mode 0

5.2.2 Mode 1 (Strobe I/O)

In Mode 1, input/output of port data is performed in conjunction with the strobe signals or ‘handshaking’ signals. Port C is used to control Port A or Port B. The basic operatings in Mode 1 are as follows: @ Mode 1 can be set for two groups of Group A and Group B. e Each group consist of 8-bit data port and 4-bit control/data port. | ° The 8-bit data port can be set as input or output port. e The control/data port is used as control or status of the 8-bit data port. (1) When used as the input port in Mode 1: e STB (Strobe Input) At “0”, input data is loaded in the internal input latch in the port. In this case, a control signal from MPU is not concerned and data is input from the port any time. This data is not read out on the data bus unless MPU executes an input instruction. e IBF (Input Buffer Full F/F Output) When data is loaded in the internal input latch from the port, this output is set to “1”. IBF is set (“1”) by STB input being reset and is reset (“0”) by the rising edge of RD input. MPU85-139

. INTR (Interrupt Request Output) Used for the interrupt process of data loaded in the internal input latch. When STB input is at “0” if INTE (INTE flag) in the PPI is in the enabled state (“1”) , IBF is set to “1”. INTR is set to “1” immediately after the rising edge of this STB input and reset to “0” by the falling edge of RD input. The INTE flag of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PC4 INTEB-Control by bit set/reset of PC2 (2) When used as the output port in Mode 1: e = OBF (Output Buffer Full F/F Output) This is a flag which shows that MPU has written data into a specified port. OBF is set to becomes “0” at the rising edge of WR signal and is set to “1” at the falling edge of ACK (Acknowledge input) signal. e ACK (Acknowledge Input) ACK signal is sent to the PPI as a response from a peripheral device taht received data from the port. e INTR (Interrupt Request Output) When a peripheral device received data from MPU, INTR is set to “1” and the interrupt is requested to MPU. If ACK signal is received when INTE flag is in the enable state, OBF is set to “1” and INTR signal becomes “1” immediately after the rising edge of ACK signal. Further, INTR is reset at the falling edge of WR signal when data is written into the PPI by MPU. The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PCg INTEB-Control by bit set/reset of PC2 eee MPU85-140

MODE 1 (PORT A) CONTROL WORD PA; ~ PAg [are D7 Dg Ds Dg D3 Dz Dy Do FINTE} [Pc, |<— STBA te ALS Cle polxxtx] |e (BFA don Vill sn U nal PCg, PCy — INTRA 0 = OUTPUT RO—+d > IBF 1= INPUT PCg~ PC7 | 1/0 MODE 1 (PORT B) INTR { CONTROL WORD PB) ~ PBy Jar? RD ——/ Dy Dg Ds Dg D3 02 D; D, FINTE? [bc | TRE

7 Dg Ds Da D3 02 Di o LINE} PC) |<— STRB port

CEEEEDET] [perf iors RUE RO—>d 050489 Figure 5.4 Example of Strobe Input in Mode 1 MODE 1 (PORT A) CONTROL WORD PAz~ PA Law? Dy Dg Ds Dg D3 D2 Dy Do | ———[ Pcs} OBFA (TOT Polvo Tx] x] |TMFEe—acca As WR PCa, PCs _ [PCs f INTRA, Oar o= oureuT = WR—>d | Ee 2 ° | 1= INPUT PCy~ PCs e110 — ACK MODE 1 (PORT 8) | CONTROL WORD PB, ~ PB bem? INTR | D7 Dg Ds Dg D3 Dp Dy Do Bre REI ESESESRIRIES) [Pc |+— acks 98% —— OUTPUT — [PCo } INTRB WR—»d PCo 050489 Figuire 5.5 Example of Strobe Output in Mode 1 MPU85-141

PA; ~ PAg PA? ~ Pg [= WR PC, |» OBFA Ra PCa |<—STBA CONTROL WORD | PCs |<—ACKA CONTROL WORD PCs }—> IBFA Dy Dg Ds Da Dz Dz 1 Do | PC3 INTRA D7 Dg Ds Da D3 Dz Dy Do PC; INTRA, L ToT: To fof Ti [x] 2 [i To [+ [+ [vols ToT x] 2 PCa ~ PCs V0 PCs ~ PCy o> 1/0 PCy, PCs PB) ~ PB [ae PCg, PCy PB, ~ PBy O= OUTPUT __ — O = OUTPUT __ — 1= INPUT RD PC) }<—STBB i= inpuT) WR—d PCy OBFB PC 1868 PC; |<— ACKB Po | > INTRB PCo > INTRB PORT A (STROBE OUTPUT) PORT A (STROBE INPUT) PORT 8 (STROBE INPUT) PORT 8 (STROBE OUTPUT) osoas9 Figure5.6 Example of Port A Output, Figure 5.7 Example of Port A input, Port B Input in Mode 1 Port B Output in Mode 1

5.2.3 Mode 2 (Strobed Bidirectional Bus I/O)

In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a peripheral device. This mode is applicable only to Group A, which consists of an 8-bit bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits of Port C). The bidirectional bus (Port A) has both the internal input and output registers. When group A is set in Mode 2, Group B can be set independently. There are 5 control signals as follows when Group A is used in Mode 2. e = ~—- OBF (Output buffer Full F/F Output) When MPU writes data into of Port A, OBF is set to “0” to inform a peripheral device that the PPI is ready to output data. However, Port A is kept in the floating (high impedance) state until ACK input signal is received. e ACK (Acknowledge Input) When ACK signal is set to “0”, the data of the 3-state output buffer of Port A is send out. If ACK signal is at “1”, Port A is in the high impedance state. e STB (Strobe Input) When STB input is set to “0”, the data from peripheral devices are held in the input latch, When the active RD signal is input into the PPI, the latched input data are output on the system data bus (D7-Dg). MPU85-142

e ‘IBF (Input Buffer Full F/F Output) When data from peripheral devices are held in the input latch, IBF is set to “1”. e INTR (Interrupt Request Output) INTR is the output to request the interrupt to MPU and its function is the same as that in Mode 1. There are two interrupt enable flip-flop (INTE), INTE1 corresponds to INTEA in Mode 1 output and INTE2 to INTEA in Mode 1 input. INTE 1-Used to generate INTR signal in conjunction with OBF and ACK signals, and is controlled by PCg bit set/reset. INTE 2-Used to generate INTR signal in conjunction with IBF and STB signals, and is controlled by PC4 bit set/reset. Fig. 5.8 shows the operating example and the timing diagram in Mode 2. i | > INTRA ORF 8 ‘ INTR % 5 . Linge ERR KK ; te Zed 4 — IBFA \\y WR—>9 IBF rd PCy~ PCy [ete 1/0 PORTA ~~ == — = — -{npuroatay CourpaToaTay= Ne = = a RD os0a89 Figure 5.8 Operating Example in Mode 2 MPU85-143

5.2.4 Precautions for use in mode 1 and 2

When used in Mode J and 2, bits which are not used as control or status in Port C can be used as follow. If programmed as the input, they are accessed by normal Port C read. If programmed as the output, high order bits of Port C (PC7-PC4) are accessed using the bit set/reset function. As to low order bits of Port C (PC3-PCo), in additions to access by the bit set/reset function, only 3 bits can be accessed by normal writing.

5.3 READING PORT C STATUS

When Port C is used as the control port, that is, when Port C is used in Mode 1 or Mode 2, the status information of the control word can be read out by a normal read operation of Port C. Table 5.2 Status Word Format of Port C Data mT [=[o[s[olalalel osoaeo MPU85-145

1. ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

Supply Voltage -0.5t07.0 Soldering Temperature (10 sec) c Operating Temperature =40 to +85 osoaes

6.2 DC ELECTRICAL CHARACTERISTICS

TA= -40T to +850, Voc =5V 410%, Ves = OV SYMBOL iTeM TEST CONDITION UNIT Fie Yostankcoent —Josinsvee [= [=| se | OutputLeak Current [oo + Lo (High Impedance State) |°= Yours Vee - [| - | #10 BA (Note) | Darlington Drive Vext=1.5V 50 | ma Ipar Current Rext= 1.1K Operating Supply 1/Ocycle Time leer Current Ipsec 2.0 5.0 ma ; CS = Vec-0.2V lee2 tand-by Supply Vin Vec-0.2V BA Vis 0.20 05009 Note: Applied for optional 8 VO terminals in Port B and Port C. MPU85-146

6.3 AC ELECTRICAL CHARACTREISTICS

TAs -40T to +850, Voc =5V + 10%, Veg = OV symeou | PARAMETER UNIT Delay from RD fall to decided data output | = | 140 [ = | 100] ns | Time from RD rise to data bus floating [of a] of ao] ns | | tev _ | Time from RD or WR rise to next RD or WA fall | 200; — | 150) — [ns | taw Address set-up time for WR fall a) | = | of - | as | twa | Address holding time for WR rise i - | of = | ns | tww WR pulse width | - | ns | tow | Bus data set-up time for WR rise Bus data holding time for WR rise | of - | Delay from WR rise to decided data output | - | 350 | tie _| Port data set-up time for RD fall | of - | of tur _| Portdata holding time for RD rise | of = | of — | os | Port data set-up time for ST8 rise fof ~ | 0] = | ns | Delay from ACK fall to decided data output | = | 300] = | 300] ns | te Time from ACK rise up to port (Port A in Mode 2) 25| 250 250 ns floating | tsa | Delay from STB fall to IBF rise [ = | 300! — | 300 [ns _| trig | Delay from RD fall to IBF rise | - | 300) — tait | Delay from RD fall to INTR fall | - | aoo| — | a00| ns Delay from ACK rise to INTR rise | - | 300 | -_| 300 | ns Delay from ACK rise to INTR rise =| 350 150085 Note: 1, When the power supply is turned ON, reset pulse duration must be active for at least 500 ns or more. 2, AC Measuring Point Input Voltage Vir=2.4V, Vi.=0.45V Output Voltage Vou =2.2V, VoL =0.8V CL=150pF. MPU85-147

6.4 CAPACITANCE

TA=25C, Vec=Vs5 =0V [Fence] row [ vovconmon [own [v6 [ome [wh] a P= f= | 20 | oF | (*}: All terminals except that to be measured should be earthed. MPU85-148

1. TIMING DIAGRAM MODE 0 INPUT OPERATION _ tre RD j <tr tHR INPUT — tar tra CS, At, Ao MODEO OUTPUT OPERATION . WR Dr~Do a a a taw twa G, Ai, Ao a OUTPUT —_ | MODE 1 INPUT. OPEARATION tps si teH INPUT PORT DATA rs tsT STB (BF : <—tsit |<tais INTR ‘i | j<trit 35 ter RD asoeae Figure 7.1. Timing Diagram MPU85-149

|<— tww WR ‘twits twos tar, INTR | QUTPUT PORT DATA tao. OBF &KCK_ MODE 2 BIDIRECTION OPERATION be tww we Q3_@] $$ WR - twit tsi, twos taos OBF | + I<— tak ACK ven ts — ah BUS yO tst —_ ($4 STB tsip IBF i} ——_ Bp SS — RD ter 050489 Figure 7.2 Timing Diagram MPU85-150

1. PACKAGE DIMENSION

8.1 PLASTIC PACKGE

Unit : mm 40 24 Z 5 monmsoonmns) 3 =| ha “8 2) = $7 1 20 S I. 50.7+0.2 s$ ns wm oo aed I TET LT Oy tlm al ij 2 By | ——~2 m 1.22TYP + 14201 Jlost0s pracy 3 2.54 270289 Note: Each lead pitch is 2.54mm, and all the leads are located witchin +0.25mm from their || theoretical positions with respect to No.1 and No.4 leads, MPU85-151

8.2 40PIN SMALL OUTLINE PACKAGE SSOP40-P-450 Unit: mm 40 21 COQO0H0qggqqqgggqnen + = HHHERERHHERRRARARARE ato = + 4 S\\lE ©) 7 S > | 2 3 3 ELLE EEEEEL TEE GUUCEWOUUGUCOUCUUUOy 1 | 20) [os] 17.5402 nN [ ae x CTT 3 oF lo] 2 2 3 S 0.840.2 270209 MPU85-152

PROGRAMMABLE PERIPHERAL INTERFACE TMP8255AP-5 1. GENERAL DESCRIPTION AND FEATURES The TMP8255A (hereinafter referred to as PPI) is a high Speed programmable input/output interface with three 8-bit I/O ports. 24 I/O ports are divided into two groups (Port A and Port B) which are programmable independently by control words provided by MPU. The PPI has three operation modes (Mode 0, 1 and 2) and is capable of versatile interface between MPU and peripheral devices. (1) 5V+5% Single power supply (2) 24 programmable I/O ports (3) Three operation modes (Mode 0, Mode 1, Mode 2) (4) Bit set/reset capability 2. PIN CONNECTIONS (TOP VIEW) PA3q1 40 DPAg PA2O2 39 PAs PA, 03 38 DPAg PAgh 4 37 DPA7 RDGS 36 PWR csiq6 35 [RESET (GND) Vss 7 34 [1D Aids 33 f1D1 Aod9 32 DD PC7 10 31 D3 PCe 11 30 1Daq PCs q 12 29 [Ds PCq4 qj 13 28 11D6 PCof] 14 27 11D PC; 415 26 [1 Vcc (+5V) PC2q 16 25 0 PB7 Pc3Q 17 24 DPBe PBoO 18 23 DPBs PB, 19 22 DPBa PB2 1] 20 21 [1 PB3 TMP825SAP-5 050489 MPU85-153

1. BLOCK DIAGRAM D7~Do BIDIRECTIONAL DATA RD ——+q WR ——+d CS ——»dq READ WRITE CONTROL LOGIC Ao ——| DATA BUS BUFFER A, ——+| RESET ——> GROUP A GROUP B CONTROL CONTROL | INTERNAL 8-BIT BUS : GROUP A GROUP B [PORT A] PORT C PORT C | PORT B vO fo Jo 170 PA7~PAg PC7~PCq — PC3~PCo PB7~PBo osoa89 MPU85-154

1. PIN NAMES AND PIN FUNCTIONS | t/Output Pin Name | Number |inputOutpu | Function of Pin 3-state vO 3-state bidirectional 8-bit data bus. Do~D7 3-STATE Used for data transfer with MPU. Also, used for transfer of control words to PPI and status information from PPI. vO 3-state 8-bit I/O Port A. PA7~PAg 3.state |OPeration mode and input/output configuration are defined by software. Port A contains the output latch buffer and input latch. vo 3-state 8-bit /O Port B. PB7~PBo Operation mode and input/output configuration are defined by 3-STATE software. Port B contains the output latch buffer and input latch. 3-state 8-bit /O Port C. Operation mode and input/output configuration are defined by pcy~Pe, vO software. Port C can be divided into two 4-bit ports by the mode ° 3-STATE | control and also, used as the control signal for Port A and Port B. In this case, 3 bits of PCo to PC2 are used for Port B and 5 bits of PC3 to PC7 for Port A. Chip select input. lad Input When this terminal is at "L" level, data transfer PP! and MPU becomes possible. At "H" level, the data bus is placed in the high impedance state and control from the processor is ignored. Read signal.

1 Input When this terminal is at “L“ level, data that is input into the port is

transferred to MPU. _ Write signal. WR 1 Input When this terminal is at "L" level, data or control word is written into PPI from MPU. ho, At 2 Input Used for selecting Port A, B, C and the control registers. Nurmally, OM P this terminal is connected to low order 2 bits of the address bus. When this terminal is at “H" level, all internal registers including the RESET 1 Input control register are cleared. In addition, all ports (Port A, B, C) are placed in the input mode (high impedance) of mode 0. Power Supply a Power Supply “ue 050489 MPU85-155

1. FUNCTIONAL DESCRIPTION The PPI is a programmable peripheral interface with three 8-bit ports (Port A, B and C) and two control registers. 24 I/O ports are divided into 12-bit group A and group B. Group A consists of Port A and high order 4 bits of Port C, while Group B consists of Port B and low order 4 bits of Port C. Each group is independently programmable by control words provided from MPU. There are three operation modes available for the PPI. In mode 0, two 8-bit I/O ports and two 4-bit I/O ports can be programmed as input or output ports, respectively. In mode 1, 24 I/O ports are divided into Group A and Group B. 8 bits of each group are used as input or output port and of the remaining 4 bits, 3 bits are used as handshaking and interrupt control signal. Mode 2 is applicable only to group A and the ports are used as a bidirectional 8-bit data bus and 5-bit control signal. In case of Port C being used as the output, any bits of Port C can be set/reset. There are two control registers; one is used for mode setting and the other for bit set/reset control. The control registers can only be written into. Further, when the reset input (RESET) becomes "1", the control registers are reset and all I/O ports are placed in input mode (high impedance status) . Table 5.1 Basic Operation of TMP8255A as 0} 140 | 0 | 1 | Databus © PortB 0} 0} 0 | 1 | Oo | Porta < Data bus 0 1 0 1 | 0 | PortB < Data bus 1 0 0 1 QO | Porte < Data bus 1 1 | 0 | 1 | 0 | Control register — Data bus x x 1 x x | Databus = 3-state x x tY) 1 1 | Data bus = 3-state 1 1 i) 0 1_| inhibition of combination 050489

There are three basic modes of operation that can be selected by control words. Mode 0-Basic I/O (Group A, Group B) Mode 1-Strobe input/Strobe output (Group A, Group B) Mode 2-Two-way bus (Port A only) Operation modes for Group A and Group B can be independently defined by the control word from the MPU. If D7 is set to"1" in writing a control word into the PPI, on operation mode is selected, while of D7="0", the set/reset function for Port C is selected. MPU85-156

Figure 5.1 shows the control words to define operation mode of the TMP8255A. Control Word Group A Condtol Group B Control Lor [bs [os | be [os | oe | ov fF oo | us | —- Input/output selection of low i order 4 bits of Port C | ‘O' = Output ‘t'sInput Input/output selection of | PortB | ‘O' = Output | ‘1's Input | Mode selection of Group B ‘0' = Mode 0 ‘1'=Mode 1 input/output selection of high order 4 bits of PortC | ‘O' = Output ‘t'=Input | input/output selection of PortA | ‘0’ = Output | "q" = Input to Made Selection Group A ‘0'=ModeO D6D5 00=ModeOd 1 = Designation of mode set flag Oh Mode | x: Don't care 950489 Figure 5.1 Control Word for Mode Selection MPU85-157

Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset control word. Figure 5.2 shows the Port C bit set/reset control word. Control Word + Bit set/reset selection Don't care "0" = Reset "1" =Set Bit set/reset flag [Pe | "9" = Active [9 [| o fo [Pe re Lo ft [ro | res | [o [i | 1 [Pcs | — eitselection [+ fo [io Tees | ji [a J oT Pee | osoaes Figure 5.2 Control Word for Bit Set/Reset

5.2.1 Mode 0 (Basic I/O)

This functional configuration is used for simple input or output operations. No ‘handshaking’ is required and data is simply written to or read from a specified part. Output data to the ports from MPU are latched out but input data from the ports are not latched. In Mode 0, 24 I/O ports are divided into four groups of Port A (8 BITS), Port B (8 bits), high order 4 bits of Port C and low order 4 bits of Port C. Each port can be programmed to be input or output. The configuration of each port are determined according to the contents of Bit 4 (D4), 3 (D3), 1 (Dy) and 0 (Dg) of the control word for mode selection. The I/O configuration of each port in Mode 0 are shown in Table 5.2. MPU85-158

i) 0 i | 0 Out Out Out Out ie) 0 0 | 1 Out Out Out In t) 0 1 | 0 Out Out | In Out 0 0 yj 1 Out Out | In In 0 1 0 | 0 Out In | Out Out i?) 1 0 | 1 Out In Out In 0 1 1 0 Out In In Out 0 1 | 4 1 Out In In In 1 o | oO 0 In Out Out Out 1 0 | 0 1 In Out Out in 1 o j 1 0 In Out In Out 1 0 1 1 In Out In In 1 1 0 i‘) In In Out Out 1 1 0 1 In In Out in 1 1 1 0 In In In Out 1 1 1 1 In In In In . ere : 050489 Figure 5.3 Port definition in Mode 0 In Mode 1, input/output of port data is performed in conjunction with the strobe signals or ‘handshaking’ signals. Port C is used to control Port A or Port B. The basic operatings in Mode 1 are as follows: ° Mode 1 can be set for two groups of Group A and Group B. e Each group consist of 8-bit data port and 4-bit control/data port. | e The 8-bit data port can be set as input or output port. ° The control/data port is used as control or status of the 8-bit data port. (1) When used as the input port in Mode 1: ° STB (Strobe Input) At "0", input data is loaded in the internal input latch in the port. In this case, a control signal from MPU is not concerned and data is input from the port any time. This data is not read out on the data bus unless MPU executes an input instruction. e IBF (Input Buffer Full F/F Output) When data is loaded in the internal input latch from the port, this output is set to"1". IBF is set ("1") by STB input being reset and is reset ("0") by the rising edge of RD input. MPU85-159

e INTR (Interrupt Request Output) Used for the interrupt process of data loaded in the internal input latch. When STB input is at "0" if INTE (INTE flag) in the PPI is in the enabled state ("1") , IBF is set to"1". INTR is set to "1" immediately after the rising edge of this STB input and reset to "0" by the falling edge of RD input. The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PC4 INTEB-Control by bit set/reset of PC2 (2) When used as the output port in Mode 1: e «© OBF (Output Buffer Full F/F Output) This is a flag which shows that MPU has written data into a specified port. OBF is set to becomes "0" at the rising edge of WR signal and is set to"1" at the falling edge of ACK (Acknowledge input) signal. e = ACK (Acknowledge Input) ACK signal is sent to the PP1 as a response from a peripheral device that received data from the port. e INTR (Interrupt Request Output) When a peripheral device received data from MPU, INTR is set to "1" and the interrupt is requested to MPU. If ACK signal is received when INTE flag is in the enable state, OBF is set to "1" and INTR signal becomes "1" immediately after the rising edge of ACK signal. Further, INTR is reset at the falling edge of WR signal when data is written into the PPI by MPU. The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PCg INTEB-Control by bit set/reset of PC2 MPU85-160

MODE 1 (PORT A) CONTROL WORD PA)~ Pag jar® Dy Dg Ds Dg D3 Dp Dy Dg TINTE? [ PC, j<~ STBA LAL Gs Jofs [4 fio Tx Tx] is \\aFA 318 PCg, PCy __ | INTRA | 0 = OUTPUT RD—+a 2 IRE 1 = INPUT PC5~ PCr 1/0 MODE 1 (PORT B) INTR { CONTROL WORD PBy~PBo |x? RD —— 4 Dy De Ds Da D3 Dz Di D TINTE | Ppc, j<— STRE

7 De O5 Da D3 Dz lo INTE | LPC STR PONT

EZESEI EIR s| alia INPUT RD—+d 050499 Figure 5.4 Example of Strobe Input in Mode 1 MODE 1 (PORTA) CONTROL WORD PAz~ Pay bm? Dy Dg Ds Da Dy Dz Dy Do OBFA io] LINE Hees we | PCa, PCs _ INTRA OBF O= OUTPUT WR—>q {fess 2 } \\ | 1 = INPUT PCa ~ PCs 110 — ACK / MODE 1 (PORT 8) | CONTROL WORD PB, ~ PB, L»® INTR Dy Dg Ds Dg D3 D2 Dy Do Tey [Pa |} Sas (i[xTxTx Tx [Tote] |) [ee |] acxe Port v y OUTPUT X — {PCy f> INTRB w—d4 fra 50499 Figure 5.5 Example of Strobe Output in Mode 1 MPU85-161

PA7~ PAg 8 PA; ~ PAg lad wR—-d PC; |» OBFA RD PCy <—STBA CONTROL WORD PCg |< ACKA CONTROL WORD PCs > BFA Dy De Ds Da Dz Dy Di Do PC3 }—> INTRA Dz Dg Ds Dg D3 Dz Di Do PC3 > INTRA Ls To[s To [vols Ti Tx] 2 Dots [i fof ToT x] 2 PCa ~ PCs Jo 1/0 PCg~ PC; eo 1/0 PCa, PCs PB) ~ PBy jx PC5, PCy PB; ~ Pp fo 0 = OUTPUT — O = OUTPUT ee — 1 = INPUT RDG PC; }x—STBB 1 = INPUT WR a PCy Ogre PC, IBFB PC, |<— ACKB PCq > INTRB PCy p> INTRB PORT A (STROBE OUTPUT) PORT A (STROBE INPUT) PORT 8 (STROBE INPUT) PORT B (STROBE OUTPUT) 050489 Figure 5.6 Example of Port A output, Figure 5.7 Example of Port A Input, Port B Input in Mode 1 Port B Output in Mode 1 In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a peripheral device. This mode is applicable only to Group A, which consists of an 8-bit bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits of Port C). The bidirectional bus (Port A) has both the internal input and output registers. When group A is set in Mode 2, Group B can be set independently. These are 5 control signals as follows when Group A is used in Mode 2. e OBF (Output buffer Full F/F Output) When MPU writes data into of Port A, OBF is set to "0" to inform a peripheral device that the PPI is ready to output data. However, Port A is dept in the floating (high impedance) state until ACK input signal is received. e ACK (Acknowledge Input) When ACK signal is set to "0", the data of the 3-state output buffer of Port A is send out. If ACK signal is at"1", Port A is in the high impedance state. e STB (Strobe Input) When STB input is set to "0", the data from peripheral devices are held in the input latch. When the active RD signal is input into the PPI, the latched input data are output on the system data bus (D7-Dg) . MPU85-162

5.2.4 Pecautions for use in Mode 1 and 2

When used in Mode 1 and 2, bits which are not used as control or status in Port C can be used as follows. If programmed as the input, they are accessed by normal Port C read. If Programmed as the output, high order bits of Port C (PC7-PC,4) are accessed using the bit set/reset function. As to low order bits of Port C (PC3-PCg), in additions ot access by the bit set/reset function, 3 bits only can be accessed by normal writing. When Port C is used as the control port, that is, when Port C is used in Mode 1 or Mode 2, the status information of the control word can be read out by a normal read operation of Port C. Table 5.2 Status Word Format of Port C Tamm [ol=to[=l=[=]ala| osoasa MPU85-165

1. ELECTRICAL CHARACTERISTICS

Supply Voltage =0.5t07.0 Input Voltage -0.5to Vec +7.0 TSOLDER | Soldering Temperature (10sec) Strobe Temperature ~65to +150 Operating Temperature Oto +70 50889 TA =0°C to 70°C, Vec =5V £5%, Vss = 0V sYMBOL ITEM TEST CONDITION [ ain. | rye. [max unit | vw Input High Voltage | | - [vec] v | vy, Output Low Voltage (D8) lov =2.5mA 045 | v ot (PER) lo. = 1.7mA 0.45 | Vv V Output High Voltage (DB) lou = - 400pA 24 v on (PER) lon = -200nA 24 v Input Leak Current svnsvec | ~ | - | 210) os | Output Leak Current \\ <Vours - |+# (High Impedance State) jsvonsvec | ~ | ~ | 20] wa | (Note 1)) Vext = 1.5V ‘on Darlington Drive Current Re an mA ; 0 cycle Time 1 | -|- 4a Operating Supply Current jscaetine | = | | a0 | ma cs0089 Note: Applied for optional 8 YO terminals in Port B and Port C, ee MPU85-166

6.4 ACELECTRICAL CHARACTREISTICS

TA =0°C to 70°C, VCC = 5V + 5%, VSS = OV Ca ee Sesame ee Ao onion reatermeant ae a [ior fie once tea buestng | we [ | tay __| Time from RD or WR rise to next RD or WR fall ; sso | - | ns | TE Fim faaieting ne foripe | =|] Pw fitetewia e = Fon etn te ee = two Bus data holding time for WR rise | 30 | - | ns | Pia [acrtantnewaneomem [eo tir | Port data set-up time for RD fall ; of - | os | Ria ensnietg inet ef = tak I ACK pulse width | 300 | - | ns | ee [is Ponca aptnetone P= Port data holding time for STB rise [iso | - | ns | fis [aornensttoneseataaeemm ——- fae Time from ACK rise up to port (Port A in Mode2) floating [a A [itr foto Recs Fe =P isis Delay from STB fall to IBF rise | - | 300 | ns | Ra Soreness = Far osistonsbiahenraiot oo | fa eationeeeewmes a [ir loners witerah | oe [J Toes Note: 1. When the power supply is turned ON, reset pulse duration must be active for at least 500 ns or more. 2. AC Measuring Point Input Voltage Vi =2.0V, ViL=0.8V Output Voltage Von =2.0V, VoL =0.8V CL=150pF. MPU85-167

TA = 25°C, Vec = Vss = OV fc tMie [= | = | 0 | oF | a Po or 050089 *; All terminals except that to be measured should be earthed. MPU85-168

1. TIMING DIAGRAM MODE 0 INPUT OPERATION tre RD < tir tHR INPUT tar tra CS, Ai, Ao [ tro |< tof MODE 0 OUTPUT OPERATION tww WR D7~Do a, ee GS, At, Ao a ourpuT [> — | MODE 1 INPUT OPERATION toc tn fo fH INPUT PORT BATA as tst = (>A S$ STB IBF j<—tsiT = tris: INTR j<tait —o tRR RD osoaa9 Figure 7.1. Timing diagram MPU85-169

i<— tww WR twit: }< twos tary INTR | OUTPUT PORT DATA — ‘taos: OBF MODE 2 BIDIRECTION OPERATION tww we i _ WR te twit | sit, INTR 1 | (S$ $$ two! taos OBF <— tak ACK tes tpH tat tko PERIPHERAL ~ ---- BUS Toe tsT STB tsiB IBF ‘ 1} - tri so ir RD tre 050089 Figure 7.2 Timing diagram MPU85-170

1. PACKAGE DIMENSION

Unit: mm 40 21 5 #| [8 = ° a} Le $s oF 7 20 S 50.7202 + fr ~ gs co —- — HS ohn PATE es , =, ° z Pa i es ; ° = - 1.22TYP 14401 []0.540.1 a olss29 pera ° 270289 Note: Each lead pitch is 2.54mm, and all the leads are located within t0.25mm from their a theoretical positions with respect to No.1 and No.40 leads. MPU85-171