82C37

TMP82C37A TOSHIBA | Alldatasheet

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TMP82C37AP-5/TMP82C37AM-5/TMP82C37AT-5 1. GENERAL DESCRIPTION The TMP82C37AP-5/AM-5/AT-5 (hereinafter referred to as TMP82C37A) is a multimode direct memory access (DMA) controller. The TMP82C37A improves the system function by directly transferring information between the system memory and external devices. Memory-to-Memory data transfer capability is also provided. The TMP82C37A is provided with versatile programmable control functions in order to improve data throughput. The TMP82C37A is used with an 8-bit address register connected externally. The TMP82C37A has four built-in independent channels and it is possible to expand channels through cascade connection. There are three basic data transfer modes which are programmable by the user. Each channel is programmable individually and autoinitialization is possible by End of Process (EOP) signal. Each channel has the maximum 64K capability for both address and word count. EOP signal is capable of terminating data transfer between DMA and memories. EOP signal is useful for block search or verify or for terminating erroneous service. 2. FEATURES ° Four independent DMA channels available e Three transfer modes available; block, demand, and single transfer modes e Independent auto initialize function provided to each of all channels ° Memory-to-Memory transfer ° Address increment or decrement ° All DMA request disabled by disabling the master system ® Individual DMA request enable/disable control ° Unrestricted channel expansion by cascade connection ® End of Process (EOP) input for terminating transfer ° Software DMA Request e Polarity control provided for DREQ signal and DACK signal e Option for increasing transfer speed up to 2.5M word/sec (@5MHz) e Single +5V power supply ° Low power consumption 5mA TYP. @5MHz e Extend operating temperature — 40°C to + 85°C MPU85-207

1. PIN CONNECTION (TOP VIEW) 3.1. TMP82C37AP-5 (DIP), TMP82C37AM-5 (SOP) TOR <> 4 40 1—> Az TOW <> 12 39 > Ag MEMR <— (3 38 [i—> As MEMW <4 37 D— Ag READY — (6 350 <> A3 HLDA 07 341 <> A2 ADSTB <—(8 33D <> Ay HRQ <1 10 31 D— Vec(+5V) cq 30 fp <> DBo CLK — 12 29 f <> DB, RESET —> 13 28D <> DB2 DACK2 <—)14 27 fl <> DB3 DACK3 <—015 26 1 <> DB4 DREQ3 —> 016 25 1—> DACKo DREQ2 — 017 24 D— DACK, DREQ; 018 23 0 <> DBs DREQo —> 0) 19 22 [ <> DBs (GND)Vss —C 20 21 <> DB7 osoae9 Note: PIN 5 must be connected to Voc or opened.

3.2 TMP82C37AT-5 (PLCC)

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1. PINNAME & FUNCTION ¢ Vcc +5V power supply e Vss Ground e CLK (Clock, Input) This input controls the internal operation and data transfer rate of the TMP82C37A. @ CS (Chip Select, Input) This input is low active and used to select the TMP82C37A as an I/O device during an I/O read or I/O write by the host MPU. If IOR or IOW is toggled following each transfer when a host MPU and the TMP82C37A are transferring data mutually, CS may be kept at LOW. e RESET (Reset, Input) This input is asynchronous input to clear the command, status, request and temporary registers. In addition, this input is used to clear First/Last flip-flops and set the mask register. Following the reset, the TMP82C37A is placed in the idle cycle. e READY (Ready, Input) This input is used to extend the memory or I/O read and write pulses in DMA cycle in order to adapt to low speed memories or I/O peripheral devices. e HLDA (Hold Acknowledge, Input) By this signal, the TMP82C37A knows that the system bus control is turned over from MPU. e DREQ -DREQ3 (DMA Request, Input) DMA request signals are input from peripheral circuits. If priority is fixed, the highest priority is given to DREQg and the lowest priority to DREQ3. Polarity of DREQ is programmable. DREQ becomes high active by RESET. MPU85-210

@ = DBo-DBz7 (Data Bus, Input/Output) The Data Bus are bidirectional 3-state lines connecnted to the system data bus. During MPU is in I/O read state, output is enabled and contents of the registers (address, status, temporary and word count) are output to MPU. During MPU is in I/O write state, the data bus serves as input and it becomes possible to program the control register of the TMP82C37A. During the DMA cycle, the most significant 8 bits of address are output on the data bus and latched by ADSTB signal externally. During the Memory-to-Memory transfer, the data of the source memory location are loaded into the temporary register of the TMP82C37A by the read operation and the contents of the temporary register are output to the destination memory location by the write operation. e JOR (/O Read, Input/Output) V/O read is a bidirectional, low active and 3-state signal. During the idle cycle, this signal serves as an input control signal used by MPU to read the control registers of the TMP82C37A. During the active cycle, this signal serves as an output control signal used by the TMP82C37A to access data from the peripheral circuit during the DMA read and transfer. e TOW (I/O Write, Input/Output) I/O write is a bidirectional, low active, 3-state signal. During the idle cycle, this signal serves as an input control signal used by MPU to load the information to the TMP82C37A. During the active cycle, this signal served as an output control signal used by TMP82C37A to load the data to the peripheral. For write to the TMP82C37A by MPU, the leading edge of the write signal (IOW) is required for every data transfer. It is not possible to write more than two data by toggling CS while holding the IOW pin at low level. MPU85-211

e EOP (End of Process, Input/Output) EOP (End of Process) is a signal relative to the end of DMA service, and is a low active, bidirectional and open drain signal. When the channel word count reaches from 0000H to FFFFH, the TMP82C37A outputs low pulse of EOP to peripheral devices as the end signal. In addition, it is also possible to pull EOP to the low level by peripheral device in order to cause the end of process. When EOP is received (internally or externally), the channel which is presently active terminates the service, sets that TC bit of the status register and resets that request bit. If that channel is programmed for auto initialization, that current register is updated from the base register. In all other cases, mask bit is set and the content of that register remains unchanged. During the Memory-to-Memory transfer, EOP is output when TC of channel 1 is produced. EOP is always used for channels with active DACK and external EOP has no connection when DACKy-DACKg are all inactive. EOP is an open drain signal and therefore, requires an external pull-up resistor. @ = Ao-Ag (Address, Input/Output) The four least significant address lines are the bidirectional 3-state signals. In the idle cycle, these lines serve as the input signals and used by MPU for write/read of the control register. In the active cycle, they serve as the output signals and become low order 4 bits of output address. e A4-A7 (Address, Output) The four most significant address lines are 3-state output signals. These lines are enabled for the period of DMA service only. e HRQ (Hold Request, Output) This is the hold request signal to MPU, and is used to request the system bus control. HRQ is output by the TMP82C37A according to a software request or unmasked DREQ. @ DACKo-DACK3 (DMA Acknowledge, Output) The DMA acknowledge lines indicate that channels are active. Normally, these are used for selecting peripheral devices. Only one DACK becomes active but it does not become active unless DMA is controlling the system bus. Polarity of these lines are programmable. After reset, they initialize low active. MPU85-212

e AEN (Address Enable, Output) Address Eanble is a high active signal and used to enable output of the external latch which holds high order byte of address and to disable the system bus during the DMA cycle. During the DMA transfer, HLDA and AEN are used to disable all I/O except programmed I/O, The TMP82C37A disables CS input for DMA transfer to prevent itself from being selected automatically. ° ADSTB (Address Strobe, Output) This signal is a strobe output to an external latch circuit and is used to latch high order 8-bit address from DBo-DBz. e MEMR (Memory Read, Outputd) This is a low active 3-state output used for transferring data from a memory to a peripheral device or for data accessing from a selected memory during the Memory-to-Memory transfer. e MEMW (Memory Write, Output) This is a low active 3-state output used for transferring data from a peripheral device to a memory or for writing data into a selected memory during the Memory- to-Memory transfer. eee MPU85-213

1. OPERATIONAL DESCRIPTION

5.1 DMA OPERARTION

The TMP82C37A has two operations; idle cycle and active cycle. Each of these cycles consists of several states. On the TMP82C37A, it is possible to consider 7 states each of which consists of one clock cycle. State I (SI) is an idle state. This is such a state as there is no valid DMA request pending. SI is a program condition state which is programmable by MPU. State 0 (SO) is the first DMA service state. This is a state that the TMP82C37A made a hold request to MPU but not yet received the acknowledge signal from MPU. When the acknowledge signal is recieved from MPU, the transfer is started. S1, S2, S3 and S4 are the DMA service states. If more time is required by the transfer, it is possible to insert the wait state (SW) before S4 by READY input to the TMP82C37A. In the Memory-to-Memory transfer, in order to assure complete transfer, read from the memory and write to the memory are required. 8 states are necessary for one transfer. The first four states (S11, S12,$13 and S14) are read from the memory and the latter four state (S21,S22, $23 and S24) are write to the memory. The temporary data register is used as an intermediate storage area of memory bytes.

5.2 IDLE CYCLE

When DMA service is not requested by channels, the TMP82C37A enters into the idle cycle and is placed in SI state. In order to check if the channels request DMA service, the TMP82C37A samples DREQ for every clock. The TMP82C37A also samples CS to check if MPU is requesting read or write of internal registers. When CS is low and HLDA is also low, the TMP82C37A is placed in the program condition. At this time, MPU is able to change or check the content of any internal register through read or write from that register. Address lines Ag-Ag are input signals and used for selecting a register being read or written. IOR and IOW are used for selecting read or write and decide read/write timing. The internal flip-flop is used for generating address extension bits according to number and size of internal registers. (First/Last flip-flop) This bit is used for deciding high or low order byte of 16-bit address and word count register. The flip-flop is reset by the master clear or reset. In addition, this flip-flop also can be reset by an independent software command. On a special software command, the execution in the TMP82C37A program conditon is possible. These commands are decoded as in the address setting when both CS and IOW are active. The data bus is not used for this command. This command is available in three types; clear First/Last flip-flop, master clear and clear mask register. MPU85-214

5.3. ACTIVE CYCLE When the TMP82C37A is in idel cycle and the channels are requesting DMA service, the TMP82C37A outputs HRQ to MPU and goes into the active cycle. In this cycle, the DMA service for any one of 4 modes is executed.

5.3.1 Single Transfer Mode:

In this mode, the TMP82C37A performs a single byte transfer during each HRQ/HLDA handshake. When DREQ becomes active, HRQ becomes active. After MPU responds by driving HLDA active, a single byte transfer will take place. After the transfer HRQ becomes inactive, its word count is decreased, and address is increased or decreased. When word count changes from 0000H to FFFFH, a terminal signal is generated and if the channels are programmed, the auto initialization is made. To execute the single byte transfer, it is necessary to hold DREQ until DACK corresponding each DREQ becomes active. If DREQ is continuously active, HRQ becomes inactive following each transfer and then, becomes active again, and the new single byte is executed following the leading edge of HLDA. On the 8085A system, one machine cycle can be executed during the DMA transfer.

5.3.2 Block Transfer Mode:

In this mode the TMP82C37A continues the transfer until terminal count (TC) is generated or an external End of Process signal (EOP) is encountered. Here, TC is produced when the word count changes from 0000H to FFFFH. What is required for DREQ is to hold it in active state until DACK becomes active. Auto initialization (if so programmed) is taken place at the end of DMA service.

5.3.3 Demand Transfer Mode:

In this mode the TMP82C37A continues the transfer until TC is produced or EOP is or DREQ becomes inactive. Thus, it is possible for a device, which is requesting the DMA service, to suspend the transfer by making DREQ inactive. The service is resumed when DREQ is made active again. It is possible to read an intermediate value of address and word count from the current address and current word count register of the TMP82C37A while the system bus is returned to MPU during execution of the DMA service. The auto initialization is taken place following TC or BOP at the end of DMA service. In order to perform a new DMA service following the auto intialization, the active edge of DREQ is necessary. MPU85-215

5.3.4 Cascade Mode:

This mode is used when the TMP82C387A is cascade connected for a simple system expansion. HRQ and HLDA of the additional TMP82C37A are connected to DREQ and DACK of the first TMP82C37A. DMA request to the TMP82C37A which is added for the purpose of system expansion is authorized by the priority circuit of the first TMP82C37A. If the priority is already decided, the additional device must wait till the acknowledge request. The cascade channel of the first TMP82C37A is used only for deciding priority of the additional TMP82C37A and therefore, the channel itself does not output address nor control signal. This is to prevent the added device from colliding with output of the cascade channel. On the TMP82C37A, DACK respond to DREQ. However all other outputs except HRQ are disabled. The state of cascade connection is shown in Figure 5.1. In Figure 5.1, two levels of DMA are formed. To further expand the TMP82C37A, it is possible to add it to the second level using the TMP82C37A, it is possible to add it to the second level using the remaining channel of the first TMP82C37A. To further add another TMP82C37A, the third level can be formed by cascade connecting it to the second level. 2nd Level ——indtevel TMP82C37A_ | Microprocessor — HRQ DREQ } HRQ | HLDA DACK HLDA TMP82C37Aj DREQ | HRQ DACK } HLDA Initial Device TMP82C37A Additional Device soa Figure 5.1 Example of Cascade Connection of TMP82C37A 5.4. TRANSFER FORMAT 3 different transfer format are available for 3 active transfer modes. They are read, write and verify. In the write transfer, data is transferred from I/O device to memory by MEMW and IOR. Im the read transfer, data is transferred from memory to I/O device by MEMR and IOW. The verify transfer is a pseudo transfer. The TMP82C37A perform such operations as address generation for read or write transfer, answer to EOP, etc. However, memory or I/O control line does not become active. MPU85-216

5.5 MEMORY-TO-MEMORY TRANSFER:

The TMP82C37A has the ability of block movement and is capable of transferring data block from one memory address location to another location. When Bit 0 of the command register is programmed at Logic 1, Channel 0 and 1 operate as the Memory-to- Memory transfer channels. Channel 0 serves as source address and Channel 1 as a destination address, and the word count of Channel 1 is used. The Memory-to-Memory transfer is executed when software DMA request is set for Channel 0. The Memory-to-Memory transfer must use the block transfer mode. When Channel 0 is programmed as a fixed source address, it is possible to write single source words into a memory block. When the TMP82C37A is programmed for the Memory-to-Memory transfer, Channel 0 and Channel 1 must be masked. The same value as that is set for Channel 1 must be set for the word count of Channel 0. During the Memory-to-Memory transfer, AEN became active but DACK does not become active. During the Memory-to-Memory transfer, the TMP82C37A respond to external EOP signal. In the block search, the data comparator uses this (EOP) input to terminate the DMA service when match is found. The Memory-to-Memory transfer timing is shown in Timing Diagram 4.

5.6 AUTO INITIALIZATION:

When Bit 4 of the mode register is set to 1, the channels are set up for the auto initialization. During the auto initialization, data are loaded into the current address and current word count registers from the base address and base word count registers, respectively, following EOP. The base registers are loaded by MPU simultaneously with the current registers and remain unchanged during the DMA service. When the channels are under the auto initialization, mask bit is not set by EOP. Following the auto initialization, that channel is prepared to execute the service without interposition of MPU. 5.7. PRIORITY: The TMP82C37A has two types of priority which can be selected by software. The first type is the fixed priority. Channel priority is fixed by channel number. The lowest priority is channel 3, followed by 2, 1, and the highest priority is channel 0. The second type is the rotating priority. In this type, an accepted channels is then given with the lowest priority . On the rotating priority in the singel chip DMA system, the highest priority of any one channel comes after no more than three higher priority services have occurred. This rotating priority prevent a specific channel from occupying the system all the time. (See the following below diagram. ) MPUS85-217

Ist Service 2st Service 3st Service The highest 0 2 <-Service 3 <-Service priority 1 <Service 3 Request \\. 0 The lowest 2 \\° 1 priority 3 1 2 osoaas The priority judging circuit selects a channel with the highest priority requesting the DMA service for every active edge of HLDA. Once the channel starts the service, that operation will not be suspended even when the service is demanded by another channel with higher priority. A channel with higher priority can get the control right only after a channel with lower priority relinquished HRQ. Whenever the control is transferred from a channel to another channel, MPU gets the system bus control right. This assures the leading edge of HLDA which is used for selecting a channel with the highest priority.

5.8 COMPRESSED TRANSFER TIMING:

In order to accomplish greater throughput allowed by system characteristics, the TMP82C37A is capable of compressing the transfer time to 2 clock cycles. As can be seen from Timing Diagram 3, State S3 is used to extend readout pulse access time. When State S3 is removed, readout pulse width becomes equal to write pulse width. Then, the transfer will consist of State S2 for changing address and State $4 for executing read/write. State S1 is produced when Ag to Aj5 are updated (refer to Address Generation). Compressed transfer timing is shown in Timing Diagram 5. During Memory-to-Memory transfer, compressed transfer is not available.

5.9 ADDRESS GENERATION:

To reduce number of pins, the TMP82C37A has the multiplexed address/data bus. State S1 is used to output high order address byte to the external latch. The trailing edge of ADSTB is used to load the address byte from the data line on the external latch circuit. AEN is used to enable latch outputs from 3 states. Low order address byte is ditectly output by the TMP82C87A. Ag to A7 are connected to address bus. Timing Diagram 3 show the relationship among CLK, AEN, ADSTB, DBo to DB7 and Ag to Az. Address produced during the block and demand transfers are sequential. For many transfer the same address data will be held in the external address latch. This address data changes only when carry or borrow from Az to Ag is produced in the normal sequence. To raise system throughput, on the TMP82C37A, S1 state is executed only for updating Ag to Aj5 requiring the external latch. eS MPU85-218

1. DESCRIPTION OF REGISTERS Base address register 16-bit 4 Base word count register 16-bit 4 Curren address register 16-bit 4 Current word count register 16-bit 4 Temporary address register | 16-bit ' i Temporary word count register | 16-bit | 1 Status register | 8-bit | 1 Command register 8-bit | 1 Temporary register 8-bit | 1 Mode register 6-bit 4 Mask register 4bit 1 Request register A-bit 1 Figure 6.1 Internal Registers moe

6.1 CURRENT ADDRESS REGISTER:

Each channel has a 16-bit current address register. This register holds addresses that are used during the DMA transfer. After each transfer, this register is automatically incremented or decremented, and intermediate address values are stored in the current address register during the transfer. Write or read of this register is made by MPU. An original value is initialized again by the auto initialization. | The auto initialization is taken place only after EOP.

6.2 CURRENT WORD COUNT REGISTER:

Each channel has a 16-bit current word count register. For this register, the number of words to be transferned that is one less than that to be tranferred must be programmed. The word counter is decremented after each transfer. Intermediate values of word count are stored in this register during the transfer. When the register value goes from 0000H to FFFFH, TC (Terminal Count) is produced. When this register is in the program condition, load or read is made by MPU. Following the end of DMA service, this register is initialized to original values again by the auto initialization. The auto initialization is taken place only when EOP is produced. Note that the content of the word count register becomes FFFFH following internally produced EOP. MPU85-219

6.3 BASE ADDRESS REGISTER, BASE WORD COUNT REGISTER:

Each channel has a pair of registers; the base address register and base word count register. These 16-bit registers store original values of related current registers. These registers are used to store original values of current registers at time of the auto initialization. Write to the base register is made at the same time of write into equivalent current registers during the programming by MPU. Therefore, write into the current registers which store intermediate values are made over these intermediate values. The base register cannot be read out by MPU.

6.4 COMMAND REGISTER:

This 8-bit register controls the operation of TMP82C37A. This command register is programmed (clear or reset) by MPU when it is in the program condition. The figure below show the functions of command bits. For address codes, refer to Figure 6.2. 7 6 5 4 32 1 oO <—Bit

0 Memory-to-memory transfer disable

{ 1 Memory-to-memory transfer enable

0 Channel 0 address hold disable

{ 1 Channel 0 address hold enable X Incase of bit0=0

0 Controller enable

{ 1 Controller disable J 0 Normal timing

1 Compressed timing

UX Incase of bit =1 {0 Fixed priority at 1 Rotating priority

0 Normal write pulse

{ 1 Extended write pulse X Incase of bit3 =1 0 DREQ sense active high. { 1 DREQ sense active low. 0 DACK sense active low. { 1 DACK sense active high. osoas9 MPU85-220

6.5 MODE REGISTER:

All channels have a 6-bit mode register, respectively. This mode register is written by MPU when it is in the program condition, and Bit 0 and 1 select the channel to be programmed. 7 6 5 4 3 2 1 o ~—Bit aD ae —— 7+ [00 Selection of channel 0 i Selection of channel 1

10 Selection of channel 2

11 Selection of channel 3

1. Verify transfer

01 Write transfer (I/O to Memory)

10 Read transfer (Memory to I/O)

1. Iliegal X Incase of bit6,7=11

0 Auto initialize disable

{ 1 Auto initialize enabie

0 Address increment

{ 1 Address decrement

00 Demand mode

01 Single mode

10 Block mode

11 Cascade mode osaaaa

6.6 REQUEST REGISTER:

The TMP82C37A is capable of responding to DMA service request by software similar || to DREQ. Each channel has a single bit request register which cannot be masked. Further, priority is given by the priority encode circuit. Bit of each register is set or cleared by software and further, cleared by generation of TC or external EOP. All registers are cleared by reset. In order to set or reset bit, a proper form of data word is loaded by software. Address codes are shown in Figure 6.2. DMA service request by software is accepted only when the channels are in the block mode. In the Memory-to-Memory transfer, DMA service request only to Channel 0 by this software command becomes valid. 7 6 5 4 3 2 10 ~— Bit —w_— en anne (0 Channel is selected x | 01. Channel tisselected hs Channel 2is selected

11 Channel 3 isselected

{ 0 Reset of request bit

1 Set of request bit 050089

6.7. MASK REGISTER: For each channel, mask bit are allocated to the mask register to disable DREQ input. If the auto initialization has not been programmed for the channels, the channel corresponding to a mask bit is set when EOP is produced. Each bit of the 4-bit mask register is also set or cleared by the software command. All bits are also set by reset. This will disable all DMA requests until the clear mask register command is enabled. Command addressing is shown in Figure 6.2. 7 6 5 4 3 2 1 Qo ~<—Bit —’—— vor’ [00 Selection of mask bit of channel 0. x 01 Selection of mask bit of channel 1.

10 Selection of mask bit of channel 2

1. Selection of mask bit of channel 3 _ { 0 Clear of mask bit

1 Set of mask bit os0ag9

All four bits of the mask register can be written also by a single command. _7 6 5 4 3 2 1 Qo ~=~—Bit TT Q Clear mask bit of channel 0. x 1 Set mask bit of channel 0 { 0 Clear mask bit of channel 1

1 Set mask bit of channel 1

0 Clear mask bit of channel 2. | 1 Set mask bit of channel 2. {0 Clear mask bit of channel 3. Lo at 1 Set mask bit of channel 3. 050489 MPU85-222

6.8 STATUS REGISTER:

This register is read out by MPU through the TMP82C37A. Status information of the TMP82C37A at time of readout is included. Information as to which channel reaches the terminal count (TC) and which channel is pending the DMA request are included in this information. Bits 0 to 3 are set every time when a channel reaches TC including the auto initialization. These bits are cleared by reset or when each status is read out. Bits 4 to 7 are always set when corresponding channels are requesting the DMA service 7 6 5 4 3 2 1 oO <—Bit 1 Channel 0 reaches TC. 1 Channel 1 reaches TC. | 1 Channel 2 reaches TC. | 1 Channel 3 reaches TC 1 Channel 1 request. 1 Channel 2 request. 1 Channel 3 request. 050089

6.9 TEMPORARY REGISTER:

This register is used for holding data during the Memory-to-Memory transfer. A last word transferred following the end of transfer is read out by MPU that is in the program condition. Unless cleared by reset, this register contains the last word transferred during the preceding Memory-to-Memory transfer. MPU85-223

6.10 SOFTWARE COMMANDS:

These commands are the special software commands which are executed in the program condition and do not depend upon the specified bit pattern on the data bus. These commands are available in following three commands:

6.10.1 Clear First/Last Flip-Flop

This command is executed prior to write or read of address information or word count information of the TMP82C37A. Furthermore, this command is used when low order or high order 8 bits of register are accessed.

6.10.2 Master Clear

This software command has the same effect as the hardware reset. The command, status, request, temporary, and internal First/Last flip-flop registers are all cleared by this command, and the mask register is set. The TMP82C37A enters into the idle cycle.

6.10.3 Clear Mask Register

This command clears all mask bits of four channels, enabling acceptance of the DMA service requests. Address codes of the software command are shown in Figure 6.2. Signal __ | Operation Pe [mT [epee ot | Read orsaturregmer [ao fo fo [1 0 | Wate to command register proto fa Pop [a Po fo [1 [1 | 0 | Wate terequestregiter Jo fo fa fo Popa pT [fo [1 [oo [1 [0 aitset reset oFmaskregiter id fo [0 Witetomoderegiter pip fo Popo |i | 1/0 {0 | 1 [ 0 | CearFirst/Lastfip-flop . Yi [1 [0 [7 [ 0 [| 1 [| Readof temporary register Poppe pep pep Maneriear po fa fa Po fo Pa Po 1] 0 | clear askregiste a CE [or aii brewene of markragiter 050489 Note: The oblique lined codes denote illegal codes, Figure 6.2 Register and Function Addressing MPU85-224

nel Register Operation cry | Data Bus 12 [orf] [a [as [aa] | PP B t | hades write o}1}o;o}aloj}o} o | A ~ a ° " o{+}olojolojo] 1 | Ag ~ ais ofoirjiojololo!} o |a~a | Current Address Read | ° 7 5 o}o;1)ofa}ojoj 1 | ag ~ Ars Base & Current Write ° 7 | Address | Read 0/0 1}o}o]lo}i 1 | We ~ Ww Current Address | 8 18 Base & Current ol: ofo ol: lol o la A Address Write | ° 7 o}1folo;o}1)oa] 4 | Ag ~ As o}o}ilo 1,0] 0 |A ~aA Current Address Read ° ° 7 oo 1}ofo;o}1]1]) 0 | Wo~w Base & Current Write | ° 7 o;}1}ofojoj1]4 1 | We ~ Wis Address | ojoli}o}o,i}1] o | Wo ~ wr Read ofoli;oj;oj1j4 1 | We ~ w Current Address : | 8 15 = a Base & Current 0 1 oto . olo 0 A A | Address Write ; ° 7 | o}1}oj;ofijoj;o}] 1 | As ~ Ars Current Address Read Oyo] 0 | Ao ~ Ar 2 o;o}1folr}ofo}] 1 | Ag ~ Ars 1 4 1 | Wo ~ W Base & Current write ° oy oy 0 o | Wo 7 of}1}olojiijola 1 | We ~ Wis Address Read ojo;1fo ,r1jo}4 1 | We ~ w Current Address 8 15 Base & Current oliiolo | F ilo 0 A A Address Write ° 7 olrjoj;ofi}1to} a Jae ~ Ars | 1 Ao ~ A Current Address Read oj) 0 oP ryt yo} a ° 7 3 ofo}ifolri1]fo} 1 jag ~ Ars Base & Current Write 5 | ilo | olalaial a We W, Address ‘ 8 15 ofofiriof1}r}1! 0 | Wo~ wr Read ofo}1)olafajr}o1 }we~w Current Address \\ 8 15 050889 (*) : Internal First/Last Flip-Flop Figure 6.3. Word Count, Address Registers MPU85-225

1. PROGRAMMING If HLDA of MPU is inactive it is possible to program the TMP82C37A by MPU even when HR@Q is active. However, it is necessary for MPU to take care that programming of the TMP82C37A and anser of HLDA are taken place simultaneously. It requires care when the DMA service is requested to an unmasked channel during the programming of the TMP82C37A. It is considered that an embarrassing trouble may be caused in this case. For instance, if MPU is going to rewrite the address register of channel 2 and in addition, the TMP82C37A is enabled and channel 2 is not masked when channel 2 received a DMA request. The DMA service will be started after one byte of the address register is written. Such a problem as exampled above can be taken place. To avoid such problems as this, it is better to disable the controller or mask unmasked channels before reprogramming any register. It is better to enable the controller or clear the masking when the programming is completed. Example of Program Set (CH2) oI : Interrupt disable OUT == MCLR : Master clear MVI A, XXXXXXXXB OUT CMND : Command register set-up MVI A, XXXXXX10B ouT MODE : Mode register set-up MVI A,37H OUT ADR2 : CH2 Address Reg. (low order) MVIT A,82H OUT ADR2 : CH2 Address Reg. (high order) MVI A,17H ouT WCNT2 : CH2 Word count register (low order) MVI A, 95H ouT WCNT2 : CH2 Word count register (high order) MVI A,00000010B OUT MSKB : CH2 Mask clear (signal bit) EI : Interrupt enable MPU85-226

1. ELECTRIC CHARACTERISTICS

8.1 ABSOLUTE MAXIMUM RATINGS

Supply Voltage =0.5t0 +7.0 | With Respect Vin Input Voltage ToGND. =0.5 to Vcc +0.5 Liv Vout __ | Output Voltage =05toVcc+05 | V Soder Temperature 260 (10sec) °C Strage Temperature ~65to +150 °C 50089

8.2 DC CHARACTERISTICS

Ta= - 40°C to +85°C, VCC = 5V + 10%, VSS (GND) = OV Vin [IinputHigh Voltage | 22 |__Vore [Output High Voltage ve-08} - | - |v [cL =5MHz lees operating Supply I Vw=Vce~0.2V - 10 mA Vip =0.2V | CLK =DC BS 1 | Icer | gland: by Supply {Vin = Vee - 0.2 10} BA \\Vip=0.2V | os0%89 MPU85-227

8.3. AC CHARACTERISTICS

8.3.1 Active Cycle (Notes : 2 and 9)

Ta= -40°Cto + 85°C, Vcc = 5V + 10%, Vss (GND) = OV (1/2) [ise [HGH Fon GROW ST Dempne [am [iar [REN OW fom UKHGHSDOayune = ADR Active to Float Delay from CLK HIGH | - | 90 | ns | [tare [DeaaivetoFestDeeyromeucwo P= 0 | | [ass [oe tom ansto owicigtine | | = | | | Tanw | ADR from WRITE HIGH Hold Time [tey-so[ - | ns | ecigtoneiconoaa rae a | foPtowirencixwicaDewytine | =m | | SE Pi forcement} fp] Fra [eeatow tea 00 = | Pte fever geetine 0] CLK HIGH to READ or WRITE LOW Delay Time (NOTE 3) [ - | 190 | ns | [ Tocw_—[WRTEWGH Fon GHEHGH(SOOeayTine wore. |= [ 30 | we | Pe Pe a aronrenacaneta ee a [Trane [a fosto acne Blayromeuenn ff [se [RADerWATEAervetomeucwign | =p 390 | | [ios nut et tom EUR GH HogTine [=] [or rnutomerowienwicrseuprine [vet = [| Output Data from MEMW HIGH Hold Time [10 | - [as | Output Data ValidtoMEMWHIGH | 125 | - | ns | DREQ to CLK LOW (SI, $4) Setup Time [30 | - | ons | [tax [cictoneapriowneisting Pw fo | 50089 MPU85-228

Ta= -40°C to +85°C, Vcc = 5V t 10%, Veg (GND) = OV (2/2) READY to CLK LOW Setup Time [ oo | - | ns | Tstu ADSTB HIGH from CLK HIGH Delay Time rs os0e9 Notel ; TCLand TDQ2. ‘The following AC specification can be also guaranteed under the conditions :Ta= —40°C to 50°C Voe=5V +5% Vss=0V Note 2 : Value with * is different from AC specification of N-MOS part.

8.3.2 Program Condition (idie Cycle) (Notes : 2, 8 and 9)

Ta= -40°C to + 85°C, Vcc = 5V + 10%, Vsg (GND) = OV TAR ADR Valid or CS LOW to READ LOW so | - | ns | Taw ADR Valid or WRITE HIGH Setup Time - 730 | - | as | Tow [CS LOW to WRITE HIGH Setup Time | 130 Data Valid to WRITE HIGH Setup Time eff Tra ADR or CS Hold fromREADHIGH fo | = | os | Troe Data Access from READ LOW (Note 7) [= [140 | ns | : Data Bus Float Delay from READ HIGH | ns Power Supply HIGH to RESET LOW Setup Time et EY RESET to First IOWR 7 2 [| - | te | RESET pulse width ~ [300 | - | ns | READ pulse width 200 | Twa ___|ADR from WRITE HIGH Hold Time ~~ ns | Two |CSHIGH from WRITE HIGH Hold Time | Two __|Data from WRITE HIGH Hold Time | 30 | - | as | [ete Pe os089 Capacity Ta = 25°C, Vcc = GND = OV Pies strana [om [Jom Co Output Capacitance | - | - | si input Capacitance f= 1,0MHz, Input =0V eel

110 Capacitance [ - | - | 2 |

Note 1. TYP. value is that when rated voltage is applied at Ta = 25°C. Note 2. Test conditions; a) Unless otherwise specified, timing defining signal voltage are; Input High level =2.4V, Low level =0.45V Output High level =2.2V, Low level=0.8V_ b) Input rising and falling times are below 20ns. c) Unless otherwise spesified, 1xTTL gate and 150 pF load are provided to output. Note 3. Normal write pulse width is TCY-100 ns. Extension write pulse width is 2TCY-100 ns. Read pulse width is 2TCY-50 ns, and compressed read pulse width is TCY-50 ns. Note 4. TDQ is measured at two different high levels. . TDQ1=2.2V, TDQ2=3.3V. Note 5. Itis necessary to keep DREQ active until DACK is received. Note 6. Both low active and high active level are available for DREQ and DACK. Note 7. Output load of the data bus are provided with 1 XTTL gate and 15 pf as the minimum value, and 1X TTL gate and 150 pF as the maximum value. Note 8. Sucessive read or/and write operations by the MPU to program must be timed to allow at least 400ns as recovery time between active read or write pulses. Note 9. Signal READ and WRITE are IOR and MEMW for the DMA operations from peripheral devices to the memory. In the DMA operations from the memory to peripheral devices, they are MEMR and IOW. Note 10. When N state wait is added at time of write to memory in the latter half memory-to- memory transfer, this parameter increases by N (TCY) ata time. MPU85-230

1. TIMING DIAGRAM ras ew r| Twe Twa Taw H Ar 8S SRENRE input vaio BRR T i Tow. we PF0~D7 ERASE input va RRR 50439 Timing Diagram 1 Program Condition Write Timing cs nots RE ares vaio RRR ior __Trw - Troe TRoE | osoae Timing Diagram 2 Program Condition Read Cycle MPU85-231

s' | si | so | so | s1 | s2 | s3 sa | 52 sz) sa} si | si | si | i | | CLK \\F SF \\ 4 DREQ |_| AANUNUNIAANS Fl HRQ N THS, MUDA LD ANNUNNAAAAANY L TAET TST yst7 | Tees |; TASS) TFADB | | TAHS TAK “ y TFAAB [1 TAFDB TAHWi otal , i J fowhy #— aaah == 4 apne VL ACRES VAI a ve fo lf TDCTR TOCTR) TAEC | | coe t TDCL TAK (FOR EXTENDEDWRITE) ay TEP i” as0a69 Timing Diagram 3 Active Cycle MPU85-232

so $11 $12 $13 $14 $21 $22 $23 S24 sl CLK TSTL, ADSTB i, ry Lf i] {| TEAAB, Cl | TAHS TAFARI i Ao~A7 a - TEADS | TARDE | Irarps | i q TEAC R JTFADB| TOD, TODH D PAFC MEMW 7 >TO : - TAK INT EOP TEDW. mt | EXT EOP WAAAY 777/77 osoaag Timing Diagram 4 Memory-to-Memory Transfer s2 s4 | 82 | $4 CLK TASM. DCL qOCTR TDCL JOCTR ka | Py Joctw WRITE TRH TRS. -| MOCO COCO, OE Be READY UO RARARAAARRNI! RRR NXXXAXXXRXXRXNS 050489 Timing Diagram 5 Compressed Transfer MPU85-233

S2 $3 sw sw S4 CLK : JDCTR, READ TDCL, TOCTW) WRITE nN (FOR EXTENDED WRITE) a - a TRS. TRS mY YM MLL = Timing Diagram 6 Ready Timing Vee ee TRSTD TRSTS TOR or IOW ne 050489 Timing Diagram 7 Reset Timing ee

1. EXTERNAL DIMENSION 10.1 40PIN DIP EXTERNAL DIMENSION DIP40-P-600 Unit : mm 40 - 21 4 _ 5 7 S| lS 2 o| (eh | 36 —1 4 Q 1 - 20 By 50.7+0.2 a ae es { ard a i! A vee it nh —4 <n 270209 Note: Each piteh is 2.54mm, and all the leads are located within +0.25mm from their theoretical | positions with respect to No, 1 and No. 40 leads. MPU85-235

10.2 40PIN SOP EXTERNAL DEMENSION SSOP40-P-450 Unit : mm 49 24 Hee eee eed ao naan og Zz | nto a S| be || )) a al ys DOCG CUCOUGOG Cocoon 1 20) 1A45TYP. it 0.3520.1 1.15TYP 08 {fo 16D I 17.5402 Jou * toe Se te i aims 2 3 fe ia SI ° | 0.8+0.2 a7ozes Note: Package Width and Length do not include Mold Protrusions. Allowable Mold Protrusion is 0.15mm. eee MPU85-236

10.3 44PIN PLCC EXTERNAL DEMENSION QFJ44-P-S650 17.52+0.2 Unit : mm 16.620.2 | 6 1 44 40 Miri Pir iri fifi rir a fo 70 {}39 Cj ( i C {] | a Of 2e s/¢ © 4 q 0 5 x} 2 L i 2 C 0 | Bs vu []29 OO =e 18 28 3 LANGA WU) ‘| t | 0.71201 | rascn 15.762 0.2 270283 MPU85-237

1. EXAMPLE OF APPLICATION CIRCUIT The connecting method of the TMP82C37A and MPU is shown in Figure 11.1. The multimode DMA controller outputs a hold request whenever valid DMA request is produced from peripheral device. When MPU answers by the hold acknowledge signal, the TMP82C37A receives the control right of the address bus, data bus, and control bus. In the first transfer, address (the least significant 8 bits of the address bits and the most significant 8 bits on the data bus) is output. The content of the data bus is latched by the 8-bit latch (TC74HC373P) to make the address bus complete. After execution of the first transfer, that latched data is updated only when carry or borrow is produced on the least significant address byte. When one TMP82C37A is used, four DMA channels are provided. ADDRESS BUS Ag~Ajs _ As~Ais [>< OE | | | TC74HC373P LE Ao~Ais | AEN Ag~A3 Ag~A? CS. ADSTB 8BIT LATCH BUSEN = TMP82C37A oo 8 HLDA |}--—>] HLDA S Ge 3 — a= & & 8 HOLD HRQ vy 4 if Ze & ag s SEE 6s 6 46 Io rn mpu CLOCK i al 4 RESET MEMR b ) MEMW p a CONTROL TOR p = f BUS TOW b —) Do~D7 _ SYSTEM DATA BUS _ osaaeg Figure 11.1. Basic System Connection Diagram MPU85-238

Figure 11.2 shows the expansion method for number of DMA channels. It is possible to realize net 7 DMA channels by connecting the second TMP82C37A to one of the DMA channels of the first TMP82C37A. Two DMA chips commonly use the same 8-bit latch. Thus, any channel is used for expansion. ne om Ss || 2 ame Fy $28 < oF 4 a z oP |} ¢8 wow B dave" 3 | 7 [| $ xova 2s | ofS 7 98 < i a2 nN MO 1 S 180-0 C\\ So | MAIN dO3p<> a | ee ee 2 ee B Me | Nav S 3 % Duy Fo é oe | : 3 | Es ‘ IL 7 i Lv-ov B d3ua nN 2 x2Vva x Jo wt 7 ‘i FSses {; 2 AMO | go d03p a a ee eee eee <a oe rs a ve Pe 7 on a ere Bis be | a ere rover hy x x ¥ seit i si ZRRS $ * ils 5 Zeis2aiss 3) S co | jE TT cs oo lee ay Ey aan lo le S er Zz 2 3 425 iS = ge 5 2 < 8 g 4 ge < 3 o 8 MPU85-239

1. GENERAL DESCRIPTION The TMP8237AP-5 (hereinafter referred to as TMP8237A) is a multimode direct memory access (DMA) controller. The TMP8237A improves the system function by directly transferring information between the system memory and external devices. Memory-to-Memory data transfer capability is also provided. The TMP8237A is provided with versatile programmable control functions in order to improve data throughput. The TMP8237A is used with an 8-bit address register connected externally. The TMP8237A has four built-in independent channels and it is possible to expand channels through cascade connection. There are three basic data transfer modes which are programmable by the user. Each channel is programmable individually and autoinitialization is possible by End of Process (EOP) signal. Each channel has the maximum 64K capability for both address and word count. EOP signal is capable of terminating data transfer between DMA and memories. EOP signal is useful for block search or verify or for terminating erroneous service. 2. FEATURES e Four independent DMA channels e Three transfer modes; block, demand, and single transfer modes e Independent auto initialize function provided to each of all channels e Memory-to-Memory transfer e Address increment or decrement e All DMA request disabled by disabling the master system e Individual DMA request enable/disable control e Unrestricted channel expansion by cascade connection e End of Process (EOP) input for terminating transfer e Software DMA Request e Polarity control provided for DREQ signal and DACK signal e Option for increasing transfer speed up to 2.5M word/sec e Single +5V power supply MPU85-240

1. PIN CONNECTIONS (TOP VIEW) TOR <> qi 40 D—> Az lOoW <> 42 39 1—> Ag MEMW =<—{)4 37 D— Ag (note) —> 5 36 0 <> EOP READY — (6 350 <> Ag HLDA — 17 34) <> Az ADSTB <— 8 33 A; HRQ «—[ 10 31 J— Vec(+5V) cs 11 30 |) <> DBo RESET —> 413 28 {] <> DB2 DACK2 ~~ 14 27) < 083 DACK3 ~~ 15 26 <> DB, DREQ3 — 116 25 J —> DACKo DREQ? — 0117 24 D—» DACK, DREQ, —> 0 18 23 D <> DBs DREQo — 019 22) <> DBs (GND)Vss —1] 20 21 <> DB7 Note: PIN 5 must be connected to VCC or opened 050489 Figure 3.1 Pin Connections MPU85-241

By > o 3 < < a 8 t v 2 5 & < < a [ag a | & ke 23 a rd Se 2 ir

5 EE sé 5

| 2 55 S 2 a| 2 Q Oa 5 9 a| | o = j ge a} | = S| > 8 & | = av | ge stv v { = | a z a = 2 ao a | & 2 eelég (oT ElESEs Zit -Ne 3 f3/8 8 2 5o3e zB We Ze o> w a a id Ssle= 5 1 < eels G 2/28 | & Fa Se|o2 S|BEs ae é 24;3° r|<jeae es 2 SElas 20/8 2/33° 32 AK E88 F «2|s= 5 | |eb— elec « |yase Bios 2} ZQo= Z\\sz jase S125 7 ne a oP a Zz x“ ules a a gs Bs Sjo8 < g ze ge x ' a go o|2%!) =|yae8\\- 8 ef ag7 | a< S 3 8 2 2 g Z2f 2 iC) = 2 Pan 22 = Oo 5 EE oO | x tev i} roo & 2zo t | Loy . . BEM SEzeER 58 ésgeg im 3 <q¥< gE 2 Bory Ca u <2 is 6 = a & 5 fog 4 ted ie] « =? a 3 Figure 3.2 Block Diagram of TMP8237A MPU85-242

1. PINNAME & FUNCTION e = vcc +5V power supply e =6vss Ground e CLK (Clock, Input) This input controls the internal operation and data transfer rate of the TMP8237A. e CS (Chip Select, Input) This input is low active and used to select the TMP8237A as an I/O device during an I/O read or I/O write by the host MPU. If IOR or IOW is toggled following each transfer when a host MPU and the TMP8237A are transferring data mutually, CS may be kept at low. e RESET (Reset, Input) This input is asynchronous input to clear the command, status, request and temporary registers. In addition, this input is used to clear First/Last flip-flops and set the mask register. Following the reset, the TMP8237A is placed in the idle cycle. ° READY (Ready, Input) This input is used to extend the memory or I/O read and write pulses in DMA a cycle in order to adapt to low speed memories or I/O peripheral devices. e HLDA (Hold Acknowledge, Input) By this signal, the TMP8237A knows that the system bus control is turned over from MPU. e DREQo-DREQ3 (DMA Request, Input) DMA request signals are input from peripheral circuits. If priority is fixed, the highest priority is given to DREQg and the lowest priority to DREQ3. Polarity of DREQ is programmable. DREQ becomes high active by RESET. MPU85-243

e DBo-DB7 (Data Bus, Input/Output) The data bus are bidirectional 3-state lines connected to the system data bus. During MPU is in I/O read state, output is enabled and contents of the registers (address, status, temporary and word count) are output to MPU. During MPU is in I/O read state, the data bus serves as input and it becomes possible to program the control register of the TMP8237A. During the DMA cycle, the most significant 8 bits of address are output on the data bus and latched by ADSTB signal externally. During the Memory-to-Memory transfer, the data of the source memory location are loaded into the temporary register of the TMP8237A by the read operation and the contents of the temporary register are output to the destination memory location by the write operation. e TOR (//0 Read, Input/Output) I/O read is a bidirectional, low active and 3-state signal. During the idle cycle, this signal serves as an input control signal used by MPU to read the control registers of the TMP8237A. During the active cycle, this signal serves as an output control signal used by the TMP8237A to access data from the peripheral circuit during the DMA read and transfer. e TOW (I/O Write, Input/Output) V/O write is a bidirectional, low active, 3-state signal. During the idle cycle, this signal serves as an input control signal used by MPU to load the information to the TMP8237A. During the active cycle, this signal served as an output control signal used by TMP8237A to load the data to the peripheral. For write to the TMP8237A by MPU, the leading edge of the write signal (IOW) is required for every data transfer. It is not possible to write more than two data by toggling CS while holding the IOW pin at low level. e@ EOP (End of Process, Input/Ouptut) EOP (End of Process) is a signal relative to the end of DMA service, and is a low active, bidirectional and open drain signal. When the channel word count reaches from 0000H to FFFFH, the TMP8237A output low pulse of EOP to peripheral devices as the end signal. In addition, it is also possible to pull EOP to the low level by peripheral device in order to cause the end of process. When EOP is received (internally or externally), the channel which is presently active terminates the service, sets that TC bit of the status register and resets that request bit. If that channel is programmed for auto initialization, that current register is updated from the base register. In all other cases, mask bit is set and the content of that register remains unchanged. MPU85-244

During the Memory-to-Memory transfer, EOP is output when TC of channel 1 is produced. EOP is always used for channels with active DACK and external EOP has no connection when DACKg-DACK3 are all inactive. EOP is an open drain signal and therefore, requires an external pull-up resistor. . Ao-Ag (Address, Input/Output) The four least significant address lines are the bidirectional 3-state signals. In the idle cycle, these lines serve as the input signals and used by MPU for write/read of the control register. In the active cycle, they serve as the output signals and become low order 4 bits of output address. e A4-Az7 (Address, Output) The four most significant address lines are 3-state output signals. These lines are enabled for the period of DMA service only. . HRQ (Hold Request, Output) This is the hold request signal to MPU, and is used to request the system bus control. HRQ is output by the TMP8237A according to a software request or unmasked DREQ. e DACKoy-DACKg (DMA Acknowledge, Output) The DMA acknowledge lines indicate that channels are active. Normally, these are used for selecting peripheral devices. Only one DACK becomes active but it does not become active unless DMA is controlling the system bus. Polarity of these lines are programmable. After reset, they initialize low active. e AEN (Address Enable, Output) Address Enable is a high active signal and used to enable output of the external latch which holds high order byte of address and to disable the system bus during the DMA cycle. During the DMA transfer, HLDA and AEN are used to disable all I/O except programmed I/O. The TMP8237A disables CS input for DMA transfer to prevent itself from being selected automatically. e ADSTB (Address Strobe, Output) This signal is a strobe output to an external latch circuit and is used to latch high order 8-bit address from DBg-DBz. MPU85-245

e MEMR (Memory Read, Output) This is a low active 3-state output used for transferring data from a memory toa peripheral device or for data accessing from a selected memory during the Memory-to-Memory transfer. e MEMW (Memory Write, Output) This is a low active 3-state output used for transferring data from a peripheral device to a memory or for writing data into a selected memory during the Memory- to-Memory transfer. MPU85-246

1. OPERATIONAL DESCRIPTION

5.1 DMA OPERATION

The TMP8237A has two operations; idle cycle and active cycle. Each of these cycles consists of several states. On the TMP8237A, it is possible to consider 7 states each of which consists of one clock cycle. State I (SI) is an idle state. This is such a state as there is no valid DMA request pending. SI is a program condition state which is programmable by MPU. State 0 (SO) is the first DMA service state. This is a state that the TMP8237A made a hold request to MPU but not yet received the acknowledge signal from MPU. When the acknowledge signal is received from MPU, the transfer is started. S1, $2, S3 and S4 are the DMA service states. If more time is required by the transfer, it is possible to insert the wait state (SW) before S4 by READY input to the TMP8237A. In the Memory-to-Memory transfer, in order to assure complete transfer, read from the memory and write to the memory are required. 8 states are necessary for one transfer. The first four status (S11, $12, S13 and $14) are read from the memory and the latter four state (S21, S22, S23 and $24) are write to the memory. The temporary data register is used as an intermediate storage area of memory bytes. When DMA service is not requested by channels, the TMP8237A enters into the idle cycle and is placed in SI state. In order to check if the channels request DMA service, the TMP8237A samples DREQ for every clock. The TMP8237A also samples CS to check if MPU is requesting read or write of internal registers. When CS is low and HLDA is also low, the TMP8237A is placed in the program condition. At this time, MPU is able to change or check the content of any internal register through read or write from that register. Address lines Ag-Ag are input signals and used for selecting a register being read or written. IOR and [OW are used for selecting read or write and decide read/write timing. The internal flip-flop is used for generating address extension bits according to number and size of internal registers. (First/Last flip-flop) This bit is used for deciding high or low order byte of 16-bit address and word count register. The flip-flop is reset by the master clear or reset. In addition, this flip-flop also can be reset by an idependent software command. Ona special software command, the execution in the TMP8237A program condition is possible. These commands are decoded as in the address setting when both CS and JOW are active. The data bus is not used for this command. This command is available in three types; clear First/Last flip-flop , master clear and clear mask register. MPU85-247

5.3. ACTIVE CYCLE When the TMP8237A is in the idle cycle and the channels are requesting DMA service, the TMP8237A outputs HRQ to MPU and goes into the active cycle. In this cycle, the DMA service for any one of 4 modes is executed. In this mode, the TMP8237A performs a single byte transfer during each HRQ/HLDA handshake. When DREQ becomes active, HRQ becomes active. After MPU responds by driving HLDA active, a single byte transfer will take place. After the transfer HRQ becomes inactive, its word count is decreased, and address is increased or decreased. When word count changes from 0000H to FFFFH, a terminal signal is generated and if the channels are programmed, the auto initialization is made. To execute the single byte transfer, it is necessary to hold DREQ until DACK corresponding each DREQ becomes active. If DREQ is continuously active, HRQ becomes inactive following each transfer and then, becomes active again, and the new single byte is executed following the leading edge of HLDA. On the 8085A system, one machine cycle can be executed during the DMA transfer. In this mode the TMP8237A continues the transfer until terminal count (TC) is generated or an external End of Process signal (EOP) is encountered. Here, TC is produced when the word count changes from 0000H to FFFFH. What is requied for DREQ is to hold it in active state until DACK becomes active. Auto initialization (if so programmed) is taken place at the end of DMA service. In this mode the TMP8237A continues the transfer until TC is produced or EOP is or DREQ becomes inactive. Thus, it is possible for a device, which is requesting the DMA service, to suspend the transfer by making DREQ inactive. The service is resumed when DREQ is made active again. It is possible to read an intermediate value of address and word count from the current address and current word count register of the TMP8237A while the system bus is returned to MPU during execution of the DMA service. The auto initialization is taken place following TC or EOP at the end of DMA service. In order to perform a new DMA service following the auto initialization, the active edge of DREQ is necessary. MPU85-248

This mode is used when the TMP8237A is cascade connected for a simple system expansion. HRQ and HLDA of the additional TMP8237A are connected to DREQ and DACK of the first TMP8237A. DMA request to the TMP8237A which is added for the purpose of system expansion is authorized by the priority circuit of the first TMP8237A. If the priority is already decided, the additional device must wait till the acknowledge request. The cascade channel of the first TMP8237A is used only for deciding priority of the additional TMP8237A and therefore, the channel itself does not output address nor control signal. This is to prevent the added device from colliding with output of the cascade channel. On the TMP8237A, DACK respond to DREQ. However all other outputs except HRQ are disabled. The state of cascade connection is shown in Figure 5.1. In Figure 5.1, two levels of DMA are formed. To further expand the TMP8237, it is possible to add it to the second level using the remaining channel of the first TMP8237A. To further add another TMP8237A, the third level can be formed by cascade connecting it to the second level. 2nd Level ist Level Micro- TMP8237A processor HRQ DREQ HRQ HLDA DACK HLDA TMP8237A | DREQ HRQ = h | Initial Device | TMP8237A Additional device 050489 Figure 5.1 Example of Cascade Connection of TMP8237A

5.4 TRANSFER FORMAT

3 different transfer format are available for 3 active transfer modes. They are read, write and verify. In the write transfer, data is transferred from I/O device to memory by MEMW and IOR. Im the read transfer, data is transferred from memory to I/O device by MEMR and [OW. The verify transfer is a pseudo transfer. The TMP82C37A perform such operations as address generation for read or write transfer, answer to EOP, etc. However, memory or 1/0 control line does not become active. ee MPU85-249

The TMP8237A has the ability of block movement and is capable of transferring data block from one memory address location to another location. When Bit 0 of the command register is programmed at Logic 1, Channel 0 and 1 operate as the Memory-to- Memory transfer channels. Channel 0 serves as a source address and Channel 1 as a destination address, and the word count of Channel 1 is used. The Memory-to-Memory transfer is executed when software DMA request is set for Channel 0. The Memory-to-Memory transfer must use the block transfer mode. When Channel 0 is programmed as a fixed source address, it is possible to write single source words into a memory block. When the TMP8237A is programmed for the Memory-to-Memory transfer, Channel 0 and Channel 1 must be masked. The same value as that is set for Channel 1 must be set for the word count of Channel 0. During the Memory-to-Memory transfer, AEN became active but DACK does not become active. During the Memory-to-Memory trnasfer, the TMP8237A respond to external EOP signal. In the block search, the data comparator uses this (EOP) input to terminate the DMA service when match is found. The Memory-to-Memory transfer timing is shown in Timing Diagram 4. When Bit 4 of the mode register is set to 1, the channels are set up for the auto initialization. During the auto initialization, data are loaded into the current address and current word count registers from the base address and base word count registers, respectively, following EOP. The base registers are loaded by MPU simultaneously with the current registers and remain unchanged during the DMA service. When the channels are under the auto initialization, mask bit is not set by EOP. Following the auto initialization, that channel is prepared to execute the service without interposition of MPU. 5.7. PRIORITY: The TMP8237A has two types of priority which can be selected by software. The first type is the fixed priority. Channel priority is fixed by channel number. The lowest priority is channel 3, followed by 2, 1, and the highest priority is channel 0. The second type is the rotating priority. In this type, an accepted channels is then given with the lowest priority . On the rotating priority in the single chip DMA system, the highest priority of any one channel comes after no more than three higher priority services have occurred. This rotating priority prevent a specfic channel from occupying the system all the time.{(See the following next page diagram.) MPU85-250

Ast Service 2nd Service 3rd Service prengnest 0 2 =< Service 3 < Service 1 <-Service 3 ~— Request 0 The lowest 2 “\\s \\ priority 3 1 050089 The priority judging circuit selects a channel with the highest priority requesting the DMA service for every active edge of HLDA Once the channel starts the service, that operation will not be suspended even when the service is demanded by another channel with higher priority. A channel with higher priority can get the control right only after a channel with lower priority relinquished HRQ. Whenever the control is transferred from a channel to another channel, MPU gets the system bus control right. This assures the leading edge of HLDA which is used for selecting a channel with the highest priority. In order to accomplish greater throughout allowed by system characteristics, the TMP8237A is capable of compressing the transfer time to 2 clock cycles. As can be seen from Timing Diagram 3, State S3 is used to extend readout pulse access time. When State S3 is removed, readout pulse width becomes equal to write pulse width. Then, the transfer will consist of State S2 for changing address and State S4 for executing read/write. State Sl is produced when Ag to Aj5 are updated (refer to Address Generation). Compressed transfer timing is shown in Timing Diagram 5. During Memory-to Memory transfer, compressed transfer is not available. To reduce number of pins, the TMP8237A has the multiplexed address/data bus. State S1 is used to output high order address byte to the external latch. The trailing edge of ADSTB is used to load the address byte from the data line on the external latch circuit. AEN is used to enable latch outputs from 3 states. Low order address byte is directly output by the TMP8237A. Ao to A7 are connected to address bus. Timing Diagram 3 show the relationship among CLK, AEN, ADSTB, DBg to DB7 and Ag to Az. Addresses produced during the block and demand transfers are sequential. For many transfer the same address data will be held in the external address latch. This address data changes only when carry or borrow from Az to Ag is produced in the normal sequence. To raise system through put, on the TMP8237A, S1 state is executed only for updating Ag to Aj5 requiring the external latch. MPU85-251

1. DESCRIPTION OF REGISTERS Base address register 16-bit 4 Base word count register 16-bit 4 Count address register 16-bit 4 Current word count register 16-bit 4 Temporary address register 16-bit 1 Temporary word count register 16-bit 1 Status register 8-bit 1 Command register 8-bit 1 Temporary register { 8-bit 1 Mode register 6-bit 4 Mask register 4-bit 1 Request register 4-bit 1 050869 Figure 6.1 Internal Registers

Each channel has a 16-bit current address register. This register holds addreses that are used during the DMA trnasfer. After each transfer, this register is automatically incremented or decremented, and intermediate address values are stored in the current address register during the transfer. Write or read of this register is made by MPU. An original value is initialized again by the auto initialization. The auto initialization is taken place only after EOP. Each channel has a 16-bit current word count register. For this register, the number of words to be transferred that is one less than that to be transferred must be programmed. The word counter is decremented after each transfer. Intermediate values of word count are stored in this register during the transfer. When the register value goes from 0000H to FFFFH, TC (Terminal Count) is produced. When this register is in the program condition, load or read is made by MPU. Following the end of DMA service, this register is initialized to original values again by the auto initialization. The auto initialization is taken place only when EOP is produced. Note that the content of the word count register becomes FFFFH following internally produced EOP. MPU85-252

Each channel has a pair of registers; the base address register and base word count register. These 16-bit registers store original values of related current registers. These registers are used to store original values of current registers at time of the auto imitialization. Write to the base register is made at the same time of write into equivalent current registers during the programming by MPU. Therefore, write into the current registers which store intermediate values are made over these intermediate values. The base register cannot be read out by MPU. This 8-bit register controls the operation of TMP8237A. This command register is programmed (clear or reset) by MPU when it is in the program condition. The figure presented below show the functions of command bits. For address codes, refer to Figure 6.2. 7 6 5 4 3 2 1 0 = Bit { 1 Memory-to-memory transfer enable | 1 Channel 0 address hold enable X Incase of bit0 =0 { 1 Controlter disable

0 Normal timing

| 1 Compressed timing X Incase of bitO=1

0 Fixed priority

{ 1 Rotating priority

0 Normal write puise

{ 1 Extended write pulse X Incase of bit3=1 0 DREQ sense active high. { 1 DREQ sense active low. 0 DACK sense active low. { 1 DACKsense active high 050489 MPU85-253

All channels have a 6-bit mode register, respectively. This mode register is written by MPU when it is in the program condition, and Bit 0 and 1 select the channel to be programmed is to be written. 7 6 5 4 3 2 1 0 =< Bit —— ~~~ [00 Selection of channel 0 J01 Selection of channel 1 ie Selection of channel 2 | 11. Selection of channel 3

00 Verify transfer

{ 01 Write transfer (I/O te Memory)

11 Illegal

(XX In case of bit 6,7 =11 ! {0 Auto initialize disable \\ at 1 Auto initialize enable { 1 Address decrement G0 Demand mode 01. Single mode

11 Cascade mode 050469

The TMP8237A is capable of responding to DMA service request by software similar to DREQ. Each channel has a single bit request register which cannot be masked. Further, priority is given by the priority encode circuit. Bit of each register is set or cleared by software and further, cleared by generation of TC or external EOP. All registers are cleared by reset. In order to set or reset bit, a proper form of data word is loaded by software. Address codes are shown in Figure 6.2. DMA service request by software is accepted only when the channels are in the block mode. In the Memory-to-Memory transfer, DMA service request to only channel 0 by this software command becomes valid. 7 6 5 4 3 2 1 Oo ~<—Bit a —~—— [00 Channel disselected. x | 01 Channel 1isselected. U_§_, 110 Channel 2 isselected. Lit channel 3 is selected

0 Reset of request bit

1 Set of request bit 050489

6.7 MASK REGISTER:

For each channel, mask bit are allocated to the mask register to disable DREQ input. If the auto initialization has not been programmed for the channels, the channel corresponding to a mask bit is set when EOP is produced. Each bit of the 4-bit mask register is also set or cleared by the software command. All bits are also set by reset. This will disable all DMA requests until the clear mask register command is enabled. Command addressing is shown in Figure 6.2. 7 6 5 4 3 201 o ~—Bit ee ~~“ [00 Selection of mask bit of channel 0 x 01 Selection of mask bit of channel 1 10 Selection of mask bit of channel 2. 11 Selection of mask bit of channel 3. { 0 Clear of mask bit

1 Set of mask bit osoce9

All four bits of the mask register can be written also by a single command. 7 6 5 4 3 2 1 Oo ~<—~Bit TO 0 Clear mask bit of channel 0. x 1 Set mask bit of channel 0. { 0 Clear mask bit of channel 1 { 0 Clear mask bit of channel 2.

1 Set mask bit of channel 2

0 Clear mask bit of channel 3. 1 Set mask bit of channel 3. osoae9 MPU85-256

6.8 STATUS REGISTER

This register is read out by MPU through the TMP8237A. Status information of the TMP8237A at time of readout is included. Information as to which channel reaches the terminal count (TC) and which channel is pending the DMA request are included in this information. Bits 0 to 3 are set every time when a channel reaches TC including the auto initialization. These bits are cleared by reset or when each status is read out. Bits 4 to 7 are always set when corresponding channels are requesting the DMA service 7 6 5 4 3 2 1 oO ~—Bit | 1 Channel 0 reaches TC. | 1 Channel 2 reaches TC. | —--» 1 Channel 3 reaches TC. | 1 Channel 0 request. > 1 Channel 1 request. + 1 Channel 2 request. 1 Channel 3 request. 050889 This register is used for holding data during the Memory-to-Memory transfer. A last word transferred following the end of transfer is read out by MPU that is in the program condition. Unless cleared by reset, this register contains the last word transferred during the preceding Memory-to-Memory transfer. These commands are special software commands which are executed in the program condition and do not depend upon the specified bit pattern on the data bus. These commands are available in following third commands: This command is executed prior to write or read of address information or word count information of the TMP8237A. Furthermore, this command is used when low order or high order 8 bits of register are accessed. MPU85-257

This software command has the same effect as the hardware reset. The command, status, request, temporary, and internal First/Last flip-flop registers are all cleared by this command, and the mask register is set. The TMP8237A enters into the idle cycle. This command clears all mask bits of four channels, enabling acceptance of the DMA service requests. Address codes of the software commands are shown in Figure 6.2. —— Operation Pare taeyerem een Lo | 0 0 | 1 [Read ofstotus register | o | o | i | |Writetocommandregister [i fo fo Pao Pp [oo [a Po [wiite to reauestreginer i pr fofifofola| = _ [a0 | 1 | 0 | 110 [Bitset, reset of mask register pi fotatitoya| = |i fo | 1 [i [tJ 6 [Write to mode register HY _0 | Clear First/Last flip-flop 1_ [Read of temporary register = Tia [0 fwasterdear SSCS ififtito Ee i [a [a fo Ta Jo [etear mask register [i] i fi [1] i [0 |allbitwrite of mask register Note: The oblique lined codes denote illegal codes. 050489 Figure 6.2 Register and Function Addressing MPU85-258

Chan- Register Operation 1 oy |[ [0 nal obs ba, CS HORTOW! a3} A2] Ar | Ao! FF Base & Current Write 0)/1]/0};0;0;/0]}/0] 0 | Ag ~ Ay Address o}1]}/o clo}olo 1 | Ag ~ Ais Current Address Read 0;o0}]/1;,0]}]0]}/0j;0] © | Ag ~ Ay 0 o;o}i}sajo | ojo 1 Ag ~ Ais Base & Current Write oli}/olofolo}ia 0 | Wo ~ W7 | address o/1foj;o}loj/oi4 1 | We ~ Wis Current Address Read 0 ie} 1 0 L) 0 1 i¢) Wo ~ W7 | o;o;1j;o}o};oj}.4 1 We ~ Wis Base & Current Write oli ola}loj;ifo 0 | Ay ~ Ay Address o/1;o;o}o}ifo 1 | Ag ~ Ais Current Address Read o}o/1}o};oj1]o0} o | a9 ~ A 1 010 1 i} 0 1 it} 1 Ag ~ Ais Base & Current Write o}1}olo}oli]a 0 | Wo ~ Wr Address o,1}o}]oyotr1}i 1 | We ~ Wis Current Address Read of}o}i}ofo,1]1] 0 | Wo~ we ofo};1io};oj,i}tai 4 Wg ~ Wis Base &Current | Write FO} 1!}0/¢e]1]o]}o, 0 | & ~ aA, Address Fol}1!oj;of1}oto}] 1 }ag ~ Ais Current Address | Read ;O}O0)}4}o0;1}0]0 0 | Ag ~ Ar

2 O;O;t oO 1) o;0 1 | Ag ~ Ais a

Base & Current Write oltfo;o}lifola 0 | Wo ~ Wr Address o}1!ofofli}ojia 1 We ~ Wis Current Address Read ojo;+}o}isto}i 0 | Wo ~ W Base & Current. Write 10 1 0 0 1 1 ie) 0 Ao ~ Az Address jolriofo}liiajfo 1 | Ag ~ Ais Current Address Read poyol}rto}1)4)o] 0 | Ag ~ ay

3 Q 0 1 0 1 1 0 1 Ag ~ Ais

Base & Current Write 0 1 i} 0 1 1 1 0 Wo ~ W7 Address olifojo}iliaiia 1 Weg ~ Wis Current Address Read of}o rtoliiafa 0 | Wo ~ W aq/o;tfo;irsa]a 1 | We ~ Wis 05089 Figure 6.3 Word Count, Address Registers MPU85-259

1. PROGRAMMING If HLDA of MPU is inactive it is possible to program the TMP8237A by MPU even when HR@Q is active. However, it is necessary for MPU to take care that programming of the TMP8237A and answer of HLDA are taken place simultaneously. It requires care when the DMA service is requested to an unmasked channel during the programming of the TMP8237A. It is considered that an embarrassing trouble may be caused in this case. For instance, if MPU is going to rewrite the address register of channel 2 and in addition, the TMP8237A is enabled and channel 2 is not masked when channel 2 received a DMA request. The DMA service will be started after one byte of the address register is written. Such a problem as exampled above can be taken place. To avoid such problems as this, it is better to disable the controller or mask unmasked channels before reprogramming any register. It is better to enable the controller or clear the masking when the programming is completed. Example of Program Set (CH2) DI : Interrupt disable OUT MCLR : Master clear MVI A, XXXXXXXXB OUT CMND : Command register set-up MVI A, XXXXXX10B OUT MODE : Mode register set-up MV! A, 37H OUT ADR2 : CH2 Address Reg. (low order) MVi A, 82H OUT ADR2 : CH2 Address Reg. (high order) MVI A, 17H OUT WCNT2 : CH2 Word count register (low order) MVI A, 95H OUT WCNT2 : CH2 Word count register (high order) Mv! A, 000000108 OUT MSKB2 : CH2 Mask clear (single bit) El : Interrupt enable MPU85-260

1. ELECTRIC CHARACTERISTICS

With Respect | ov | Vin___| Input Voltage | to GND -0.5~+7.0 v Solder Temperature = 260 (10 sec) °C Strage Temperature = | -65~ +150 *C 50889 Ta=0T to 70, Vcc = 5V + 5%, Vg (GND) = OV lon2 = - 100pA Vou2 Output High Voltage {HR ONLY) 33 v Output Leakage < < + lore Coneent 0.45VS VourS Vec £10 pA 950089 8.3. AC CHARACTERISTICS

8.3.1 Active Cycle (1/3) (Notes : 2 and 9)

Ta=0 to 70, Vcc = 5V + 5%, Vs5 = OV TAEL AEN HIGH from CLK LOW (S1) Delay Time | — | 200] ns | | Taer [AEN LOW from CLK HIGH (SI) Delay Time [| — | 730] as | ADR Active to FLoat Delay from CLK HIGH [| - | 90] ns | READ or WRITE Float Delay from CLK HIGH [= _[ 120] as | 50889 ee MPU85-261

Active Cycle (2/3) [inrn [peace Fondo fomcgnaH |] va) mr v | DACK valid from CLK LOW Delay Time | - | 170] os | Tak EOP HIGH from CLK HIGH Delay Time | = | 170] ns | FEOPLOWtoCLKHIGHDelayTime | - | 170 ns | [isa [aorsabiefomcixmon | 10} | Fras [ostoaostaiowsewptiae | ww [- bn] Clock HIGH Level Width | 30 | — | ns| Fe festa FP [er eoace tine 0 Pr] peerage READ HIGH from CLK HIGH (54) Delay Time Note 3) |= | 90) os | | Tocrw _ [WRITE HIGH from CLK HIGH ($4) Delay (Note 3) [= _| 130] ns | eon eta =P] | Ters | EOP Low from CLK LOW Setup Time | 40 | = | ns | DB Float to Active Delay from CLK HIGH [=| 170] ns | [ince RAB ocWATE Acie rom cucGH [0 | [iron [ob osttoncive Deaytoneakhigt | — 20) | Foam netontam acronis To} = fa] [ics [nour sie on HGHSeupTine | wo | = [| [ioosoputonisroMtnGHHeTine Pw} — Far onascicon te snseuptne | [ies [cicioneabyiowvotstine | 20 1 Tes] 950889 MPU85-262

Active Cycle (3/3) SYMBOL | PARAMETER MIN. |MAX. TRs READY to CLK LOW Setup Time [= | ns | Tste ADSTB HIGH from CLK HIGH Delay Time ADSTB LOW from CLK HIGH Delay Time [30] ns | Os0as9

8.3.2 Program Condition (Idle Cycle) (Notes : 2, 8 and 9)

Ta =0°C to 70°C, Vec = 5V 5%, Veg = OV TaR ADR Valid or CS LOW to READ LOW | 50 | — [9s | Taw ADR Valid or WRITE HIGH Setup Time 130 Tow CS LOW to WRITE HIGH Setup Time Data Valid to WRITE HIGH Setup Time [130 | — | ns] | Tra | ADR or CS Hold from READ HIGH [0 | = [ns | Data Bus Float Delay from READ HIGH [| 0 | 70{ ns | | Trsto _ | Power Supply HIGH to RESET LOW Setup Time | 500 | — | ns | ADR from WRITE HIGH Hold Time | 20 | — [ns | | Two [CSHIGH from WRITE HIGH Hold Time [| 20 | = | ns] Two _| Data from WRITE HIGH Hold Time | 30 | — | as | Twws | WRITE pulse width [_160 | — [ns | 050089

8.4 CAPACITY

Ta = 25°C, Vec GND = 0V SYMBOL PARAMETER TEST CONDITION Output Capacitance p= fs | Input Capacitance c= 1.0MHz, Input = 0V 50489 MPU85-263

Note 1: Typ. value is that when rated voltage is applied at Ta=25°C. Note 2: Testconditions; a) Unless otherwise specified, timing defining signal voltages are; Input High level =2.4V, Low level=0.45V Output High level=2.0V, Low level=0.8V b) Unless otherwise specified, 1x TTL gate and 150pF load are provided to output. Note 3: Normal write pulse width is TCY—100 ns. Extension write pulse width is 2TCY—100 ns. Read pulse width is 2TCY-50 ns, and compressed read pulse width is TCY —50 ns. Note 4: TDQ is measured at two different high levels. TDQi=2.0V, TDQ2=3.3V Note 5: Itis necessary to keep DREQ active until DACK is received. Note 6: Both low active and high active level ae available for DREQ and DACK. Note 7: Output load of the data bus are provided with 1XTTL gate and 15 pF as the minimum value, and 1x TTL gate and 150 pF as the maximum value. Note 8: Sucessive read or/and write operations by the MPU to program must be timed to allow at least 600ns for the TMP8237AP and at least 400ns for the TMP8237AP-5 as recovery time between active read or write pulses. Note 9: Signal READ and WRITE are IOR and MEMW for the DMA operations from peripheral devices to the memory. In the DMA operations from the memory to peripheral devices, they are MEMR and IOW. Notel0: When N state wait is added at time of write to memory in the latter half of memory-to-memory transfer, this parameter increases by N (TCY) ata time. MPU85-264

1. TIMING DIAGRAM rad t Tow : [| Twe ow pes Twa Taw ll Ao~As BERR iwpur va BERR T D80~087 BERNA, neu va BRR osoaga Timing Diagram 1 Program Condition Write Timing cs Ama RRR Apress vation Tar TRA ioR a Troe Troe | 050489 Timing Diagram 2 Program Condition Read Cycle MPU85-265

si | SI so | so | s1 s2.| s3 | sa} s2 | s3 sa] si | s SI CLK | \\ ; 4 | DREQ Y a Wits ; ors HRQ \\ THS. Hoa ZZ AAAAAAUANNAN iH _Taet TTL pt |_| Teps ania TFADB | Tans | TAK DBo~DB7 = — — = = = — ee 4 Rg RE E - -E - Ra “ap Taaar 777 TFAAB LL TAFOR TAHW | JAHW, | a AorAy oo memo n te = A apones va MC agpaess vals ~~ —~- =~ ILL tane i; | _ ITOCTR TDCTR TAFC scr [i | t TDCI TAK (FOR EXTENDED WRITE) TEPW| in osoaeg Timing Diagram 3 Active Cycle MPU85-266

CLK j [ n STL, ost | FT = TFAAB. | ,TAHS TAFAB) Po | Ao~Ay ===> H = - TEADB TAFDB | | ITAFDB | TEAC R iIFADg FrODy, TOON 5 ' LJAFC j MEMW T7777 } a TAK INT EOP Tew m | | EXT EOP WAAAY 777777 osoaga Timing Diagram 4 Memory-to-Memory Transfer CLK PON : TASM | TASM. ToC JOCTR Toc JDCTR IDCTW WRITE TRH TRH _TRS TRS 4 GSN LE NN NON CN ING READY RARER EKER RRR 050489 Timing Diagram 5 Compressed Transfer MPU85-267

TOSHIBA __ TMP8237A 82 ss fo sw | sw sa | \\ a i CLK JOCTR, READ EXTENDED WRITE) TRH TRH TRS {TRS mY XQ LLL es Timing Diagram 6 Ready Timing a Vee /\\-<——— rst TRSTS TOR or JOW SEE osaaes Timing Diagram7 Reset Timing ee MPU85-268

1. EXTERNAL DIMENSION VIEW (PLASTIC PACKAGE) DIP40-P-600 Unit : mm ; 3 r =) fall | | 3 . aa Ak a 1 ~ 20 Sy 50.7+0.2 F 3 3 ——_ 5-3 Toon cyt: ™ il | \\ j zt fe | = “ i 5s 1,.22TYP |freser llosor aroacam 8 2.54 270289 Note: Each pitch is 2.54mm, and all the leads are located within +0.25mm from their theoretical positions with respect to No.1 and No.40 leads. MPU85-269

1. EXAMPLE OF APPLICATION CIRCUIT The connecting method of the TMP8237A and MPU is shown in Figure 11.1. The multimode DMA controller outputs a hold request whenever valid DMA request is produced from peripheral device. When MPU answers by the hold acknowledge signal, the TMP8237A receives the contorl right of the address bus, data bus, and control bus. In the first transfer, address (the least significant 8 bits of the address bits and the most significant 8 bits on the data bus) is output. The content of the data bus is latched by the 8-bit latch (TC74HC373P) to make the address bus complete. After execution of the first transfer, that latched data is updated only when carry or borrow is produced on the least significant address byte. When one TMP8237A is used, four DMA channels are provided. [ ADDRESS BUS Ao~A15 __ As~Ais P>e OE TC74HC373P | | te Ao~Ai5 AEN Ag~A3 Ag~A7 CS. ADSTB 8BIT LATCH n BUSEN TMP8237A nm 8 HLDA HLDA e ge g a |e = rae) HOLD HQ yg E E S 8 zx Too T CLOCK ar 4 MPU RESET MEMR pb ! MEMW p | CONTROL | TOR p BUS Do~D7 fi | “SYSTEM DATA BUS osoaa9 Figure 11.1 Basic System Connection Diagram MPU85-270

Figure 11.2 shows the expansion method for number of DMA channels. It is possible to realize net 7 DMA channels by connecting the second TMP8287A to one of the DMA channels of the first TMP8237A. Two DMA chips commonly use the same 8-bit latch. Thus, any channel is used for expansion. Fy bis = Bug a7 2 a”a “ o & S | 0 2m | 2 2B < Fu 5 3 re 3 op . 5s g aie ll | | ed es > eal 258 4a tv-oyv BORNE TE || | fs 3 | Tr, < Amo 1 ® £ac-o8a ny | 5 quot a | 7 | is “ : 3 df wWaW _ VaIH | | S a) |) “~ 8 O8H | ra 3} | | oe | 5 || = | ¢ < } | w | u voy 8 O34uG i x 2 yova { ,o5 dso ww UL]! 2 J FELT iz AA | x do3p in mol 6 403 J HB 63s 4 ee ee gp 2Vobe L yi B ~ cc 8 | Po Ht _’ | ~ S| ZRRS 3 jie os 7 A 2 li lz 5 PP EPeree 3 n Po S Zz — 1 HE ] e oe 2 4 aa6 fe} is = eF5 2 = ¢ 628 & & = 5 25 4 zr < 2 Ses a Bo . a s og * MPU85-271