DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
821024 REVISION A JUNE 25, 2014 1 ©2014 Integrated Device Technology, Inc.
FEATURES
- 4 channel CODEC with on-chip digital fi lters
- Selectable A-law or μ-law companding
- Master clock frequency selection: 2.048 MHz, 4.096 MHz or
8.192 MHz
- Internal timing automatically adjusted based on MCLK and frame sync signal
- Separate PCM and master clocks
- Single PCM port with up to 8.192 MHz data rate (128 time slots)
- Transhybrid balance impedance hardware adjustable via external components
- Transmit gains hardware adjustable via external components
- Low power +5.0 V CMOS technology
- +5.0 V single power supply
- Package available: 32 pin PLCC, 44 pin TQFP FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The IDT821024 is a single-chip, four channel PCM CODEC with on- chip fi lters. The device provides analog-to-digital and digital-to-analog conversions and supports both a-law and μ−law companding. The digital fi lters in IDT821024 provides the necessary transmit and receive fi ltering for voice telephone circuit to interface with time-division multiplexed systems. All of the digital fi lters are performed in digital signal processors operating from an internal clock, which is derived from MCLK. The fi xed fi lters set the transmit and receive gain and frequency response. In the IDT821024 the PCM data is transmitted to and received from the PCM highway in time slots determined by the individual Frame Sync signals (FSR n and FSXn, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both Long and Short Frame Sync modes are available in the IDT821024. The IDT821024 can be used in digital telecommunication applications such as PBX, Central Of fi ce Switch, Digital Telephone and Integrated Voice/Data Access Unit.
821024 DATA SHEET
2 REVISION A 06/25/14
A/μ FSX4 FSR4 FSX3 FSR3 FSX2 VOUT1 CNF PDN1 PDN2 PDN3 PDN4 MCLK PCLK TSC DGND DX VCCD DR FSR1 FSX1 FSR2 IIN1 IIN2 VOUT2 VCCA IREF AGND VOUT3 IIN3 IIN4 44-Pin TQFP IIN4 VOUT4 NC NC A/μ NC FSX4 FSR4 FSX3 FSR3 FSX2 IIN1 VOUT1 NC CNF NC PDN1 PDN2 PDN3 PDN4 MCLK PCLK NC NC TSC DGND NC DX VCCD DR FSR1 FSX1 FSR2 IIN2 VOUT2 NC NC VCCA IREF AGND NC NC VOUT3 IIN3
3 QUAD NON-PROGRAMMABLE
4 REVISION A 06/25/14
PIN DESCRIPTION (cont’d)
5 QUAD NON-PROGRAMMABLE
a receive Frame Sync signal. channels to be active (power-on) or standby (power-down) separately. as PCM bandpass fi ltering and sample rate conversion. and compressed to PCM format. pulse identifi es the transmit time slot of the PCM frame for Channel N. amplifi er can drive resistive load higher than 2 KΩ. Data is received serially on DR pin with the Most Signifi cant Bit (MSB) fi rst. The receive gain of IDT821024 is fi xed and equal to 1. Figure 1. IDT821024 Transmit Gain Setting for Channel 1
6 REVISION A 06/25/14
The following descriptions about operation applies to all four channels of the IDT821024. Power-on Sequence and Master Clock Confi guration To power on the IDT821024 users should follow this sequence: 1. Apply ground; 2. Apply VCC, fi nish signal connections; 3. Set PDN1-4 pins high, thus all of the 4 channels are powered down; The master clock (MCLK) frequency of IDT821024 can be con fi gured as 2.048 MHz, 4.096 MHz or 8.192 MHz. Using the Transmit Frame Sync (FSX) inputs, the device determines the MCLK frequency and makes the necessary internal adjustments automatically. The MCLK frequency must be an integer multiple of the Frame Sync frequency. Operating Modes There are two operating modes for each transmit or receive channel: standby mode (when the channel is powered down) and normal mode (when the channel is powered on). The mode selection of each channel is done by its corresponding PDN pin. When PDNn is 1, Channel N is in standby mode; when PDNn is 0, Channel N is in normal mode. In standby mode, all circuits are powered down with the analog outputs placed in high impedance state. In normal mode, each channel of the IDT821024 is able to transmit and receive both PCM and analog information. The normal mode is used when a telephone call is in progress. Companding Law Selection An A/μ pin is provided by IDT821024 for the companding law selection. When this pin is low, μ-law is selected; when the pin is high, A-law is selected.
7 QUAD NON-PROGRAMMABLE
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Power Dissipation RECOMMENDED DC OPERATING CONDITIONS NOTE: MCLK: 2.048 MHz, 4.096 MHz or 8.192 MHz with tolerance of ± 50 ppm Digital Interface
ELECTRICAL CHARACTERISTICS
Note: Total current must not exceed absolute maximum ratings. Note: Power measurements are made at MCLK = 4.096 MHz, outputs unloaded
8 REVISION A 06/25/14
TRANSMISSION CHARACTERISTICS 0dBm0 is defi ned as 0.6832Vrms for A-law and 0.6778 Vrms for A-law, both for 600 Ω load. Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifi er is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Typical value are tested at VDD = 5V and TA = 25°C. Absolute Gain Gain Tracking Frequency Response Group Delay Note*: Minimum value in transmit and receive path.
9 QUAD NON-PROGRAMMABLE
10 REVISION A 06/25/14
11 QUAD NON-PROGRAMMABLE
Figure 2. MCLK Timing Note: Timing parameter t13 is referenced to a high-impedance state.
12 REVISION A 06/25/14
Figure 3. PCM Interface Timing for Short Frame Mode Figure 4. PCM Interface Timing for Long Frame Mode
13 QUAD NON-PROGRAMMABLE
Data Sheet Document History 01/16/2002 pgs. 4, 5 02/21/2002 pgs. 1-4, 13 09/10/2002 pg. 8 01/08/2003 pgs. 1, 13 04/03/2003 pg. 1 06/25/2014 821024PP package Product Discontinuation Notice - Last time buy expires 7/26/14, PDN CQ-13-01 Changed Datasheet format Added Contacts page
ORDERING INFORMATION
6024 Silver Creek Valley Road
San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2014. All rights reserved.