821004J

821004J RENESAS | Alldatasheet

Document overview

• Manufacturer or author: RENESAS CORPORATION
• PDF pages: 16

Technical content

NOVEMBER 2020INDUSTRIAL TEMPERATURE RANGE DSC-6807/1

FEATURES

• 4 channel CODEC with on-chip digital filters
• Selectable A-law or m-law companding
• Master clock frequency selection: 2.048 MHz, 4.096 MHz or

8.192 MHz

• Internal timing automatically adjusted based on MCLK and frame sync signal
• Separate PCM and master clocks
• Single PCM port with up to 8.192 MHz data rate (128 time slots)
• Transhybrid balance impedance hardware adjustable via external components
• Transmit gains hardware adjustable via external components
• Low power +5.0 V CMOS technology
• +5.0 V single power supply
• Package available: 32 pin PLCC FUNCTIONAL BLOCK DIAGRAM Anolog Front End CH2 Anolog Front End CH1 Anolog Front End CH3 Anolog Front End CH4 DSP PCM Interface PCM TSA 1 PCM TSA 2 PCM TSA 3 PCM TSA 4 Clock Reference Circuits Control PDN 1~ 4 A/m IIN1 VOUT1 IIN2 VOUT2 IIN3 VOUT3 IIN4 VOUT4 MCLK IREF CNF FSX1 FSR1 FSX2 FSR2 FSX3 FSR3 FSX4 FSR4 DX TSC DR PCLK VCCA AGND VCCD DGND

DESCRIPTION

The 821004J is a single-chip, four channel PCM CODEC with on-chip filters. The device provides analog-to-digital and digital-to-analog conversions and supports both a-law and µ−law companding. The digital filters in 821004J provides the necessary transmit and receive filtering for voice telephone circuit to interface with time-division multiplexed systems. All of the digital filters are performed in digital signal processors operating from an internal clock, which is derived from MCLK. The fixed filters set the transmit and receive gain and frequency response. In the 821004J the PCM data is transmitted to and received from the PCM highway in time slots determined by the individual Frame Sync signals (FSRn and FSXn, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both Long and Short Frame Sync modes are available in the 821004J. The 821004J can be used in digital telecommunication applications such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/ Data Access Unit.

INDUSTRIAL TEMPERATURE RANGE821004J QUAD NON-PROGRAMMABLE PCM CODEC PIN CONFIGURATIONS 32-Pin PLCC VOUT4 A/m FSX4 FSR4 FSX3 FSR3 FSX2 VOUT1 CNF PDN1 PDN2 PDN3 PDN4 MCLK PCLK TSC DGND DX VCCD DR FSR1 FSX1 FSR2 IIN1 IIN2 VOUT2 VCCA IREF AGND VOUT3 IIN3 IIN4

INDUSTRIAL TEMPERATURE RANGE821004J QUAD NON-PROGRAMMABLE PCM CODEC PIN DESCRIPTION Name I/O Pin Number Description AGND -- 10 Analog Ground. All ground pins should be connected to the ground plane of the circuit board. VCCA -- 8 +5 V Analog Power Supply. All power supply pins should be connected to the power plane of the circuit board. DGND -- 27 Digital Ground. All ground pins should be connected to the ground plane of the circuit board. VCCD -- 25 +5 V Digital Power Supply. All power supply pins should be connected to the power plane of the circuit board. DR I 24 Receive PCM Data Input. The PCM data for Channel 1, 2, 3 and 4 is shifted serially into DR pin by the Receive Frame Sync Signal (FSR) with MSB first. A byte of data for each channel is received every 125 µs at the PCLK rate. DX O 26 Transmit PCM Data Output. The PCM data for Channel 1, 2, 3 and 4 is shifted serially out to the DX pin by the Transmit Frame Sync Signal (FSX) with MSB first. A byte of data for each channel is transmitted every 125 µs at the PCLK rate. DX is high impedance between time slots. FSR1 FSR2 FSR3 FSR4 I Receive Frame Sync Input for Channel 1/2/3/4 This 8kHz signal pulse identifies the receive time slot for Channel N on a system’s receive PCM frame. It must be synchronized to PCLK. FSX1 FSX2 FSX3 FSX4 I Transmit Frame Sync Input for Channel 1/2/3/4 This 8 kHz signal pulse identifies the transmit time slot for Channel N on a system’s transmit PCM frame. It must be synchronized to PCLK. IREF O 9 Reference Current. The IREF output is biased at the internal reference voltage. A resistor placed from IREF to ground sets the reference current used by the analog-to-digital converter to encode the signal current present on IINn pin (n is channel number, n = 1 to 4) into digital form. VOUT1 VOUT2 VOUT3 VOUT4 O Voice Frequency Receiver Output for Channel 1/2/3/4 This is the output of receiver amplifier for Channel N. The received digital data from DR is processed and converted to an analog signal at this pin. IIN1 IIN2 IIN3 IIN4 I Voice Frequency Transmitter Input for Channel 1/2/3/4 This is the input to the gain setting amplifier in the transmit path for Channel N. The analog voice band voltage signal is applied to this pin through a resistor. This input is a virtual AC ground input, which is biased at the IREF pin. MCLK I 30 Master Clock. The Master Clock provides the clock for the DSP. It can be either 2.048 MHz or 4.096 MHz. The 821004J determines the MCLK frequency via the FSX inputs and makes the necessary internal adjustments automatically. The MCLK frequency must be an integer multiple of the FSX frequency. PCLK I 29 PCM Clock. The PCM Clock shifts out the PCM data to the DX pin and shifts in PCM data from the DR pin. The PCM clock frequency is an integer multiple of the frame sync frequency. When PCLK is connected to MCLK, the PCM clock can generate the DSP clock as well. TSC O 28 Time Slot Control. This open drain output is low active. When the PCM data is transmitted to the DX pin for any of the four channels, this pin will be pulled low. A/m I 15 A/µ-Law Selection. When this pin is low, µ-Law is selected; when this pin is high, A-Law is selected. This pin can be connected to VCCD or DGND pin directly.

INDUSTRIAL TEMPERATURE RANGE821004J QUAD NON-PROGRAMMABLE PCM CODEC Name I/O Pin Number Description PDN1 PDN2 PDN3 PDN4 I Channel 1/2/3/4 Power Down. When this pin is high, Channel N is powered down. CNF O 3 Capacitor For Noise Filter. This pin should be connected to AGND through a 0.1µF capacitor. NC -- No connection PIN DESCRIPTION (cont’d)

channels to be active (power-on) or standby (power-down) separately. as PCM bandpass filtering and sample rate conversion. and compressed to PCM format. pulse identifies the transmit time slot of the PCM frame for Channel N. amplifier can drive resistive load higher than 2 KΩ. The receive gain of 821004J is fixed and equal to 1. Figure 1. 821004J Transmit Gain Setting for Channel 1

INDUSTRIAL TEMPERATURE RANGE821004J QUAD NON-PROGRAMMABLE PCM CODEC OPERATING THE 821004J The following descriptions about operation applies to all four channels of the 821004J. Power-on Sequence and Master Clock Configuration To power on the 821004J users should follow this sequence: 1. Apply ground; 2.Apply VCC, finish signal connections; 3.Set PDN1-4 pins high, thus all of the 4 channels are powered down; The master clock (MCLK) frequency of 821004J can be configured as 2.048 MHz, 4.096 MHz or 8.192 MHz. Using the Transmit Frame Sync (FSX) inputs, the device determines the MCLK frequency and makes the necessary internal adjustments automatically. The MCLK frequency must be an integer multiple of the Frame Sync frequency. Operating Modes There are two operating modes for each transmit or receive channel: standby mode (when the channel is powered down) and normal mode (when the channel is powered on). The mode selection of each channel is done by its corresponding PDN pin. When PDNn is 1, Channel N is in standby mode; when PDNn is 0, Channel N is in normal mode. In standby mode, all circuits are powered down with the analog outputs placed in high impedance state. In normal mode, each channel of the 821004J is able to transmit and receive both PCM and analog information. The normal mode is used when a telephone call is in progress. Co mpanding Law Selection An A/µ pin is provided by 821004J for the companding law selection. When this pin is low, µ-law is selected; when the pin is high, A-law is selected.

INDUSTRIAL TEMPERATURE RANGE821004J QUAD NON-PROGRAMMABLE PCM CODEC Analog Interface ABSOLUTE MAXIMUM RATINGS NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Power Dissipation RECOMMENDED DC OPERATING CONDITIONS NOTE: MCLK: 2.048 MHz, 4.096 MHz or 8.192 MHz with tolerance of ± 50 ppm Rating Com’I & Ind’I Unit Power Supply Voltage ≤ 6.5 V Voltage on Any Pin with Respect to Ground -0.5 to 5.5 V Package Power Dissipation ≤ 600 mW Storage Temperature -65 to +150 °C Parameter Min. Typ. Max. Unit Operating Temperature -40 +85 °C Power Supply Voltage 4.75 5.25 V Digital Interface

ELECTRICAL CHARACTERISTICS

Parameter Description Min Typ Max Units Test Conditions VIL Input Low Voltage 0.8 V All digital inputs VIH Input High Voltage 2.0 V All digital inputs

0.4 V DX, TSC,IL = 14mA

0.8 V All other digital outputs,

IL = 4mA. VOL Output Low Voltage

0.2 V All digital pins, IL = 14mA

VDD-0.6 V DX, IH = -7 mA, all other outputs, IH = -4 mA VOH Output High Voltage VDD-0.2 V All digital pins, IH = -1mA II Input Current -10 10 µA Any digital inputs GND<VIN<VDD IOZ Output Current in High-impedance State -10 10 µA DX CI Input Capacitance 5 pF Note: Total current must not exceed absolute maximum ratings. Note: Power measurements are made at MCLK = 4.096 MHz, outputs unloaded Parameter Description Min Typ Max Units Test Conditions VOUT1 Output Voltage 2.25 2.4 2.6 V Alternating±zero µ-law PCM code applied to DR. VOUT2 Output Voltage Swing 3.25 V P-P RL=2000Ω RO Output Resistance 1 4 Ω 0dBm0, 1020Hz PCM code applied to DR RL Load Resistance 2000 Ω External loading IIR Analog Input Current Range ±40 µA RREF = 13kΩ IIOS Offset Current Allowed on IIN -1.6 +1.6 µA IOUT VOUT Output Current (F< 3400Hz) -5 5 mA IZ Output Leakage Current -10 10 µA Power down CL Load Capacitance 100 pF External loading Parameter Description Min Typ Max Units Test Conditions PD2 Operating Power Dissipation 1 180 240 mW All channels are active PD1 Operating Power Dissipation 1 60 90 mW Only one channel is active PD0 Standby Power Dissipation 4 10 mW All channels are powered down,with only MCLK present

INDUSTRIAL TEMPERATURE RANGE821004J QUAD NON-PROGRAMMABLE PCM CODEC TRANSMISSION CHARACTERISTICS 0dBm0 is defined as 0.6832V rms for A-law and 0.6778 Vrms for µ-law, both for 600 Ω load. Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Typical value are tested at VDD = 5V and T A = 25 °C. Absolute Gain Gain Tracking Frequency Response Group Delay Note*: Minimum value in transmit and receive path. Parameter Description Min Typ Max Units Test Conditions GTX Transmit Gain Tracking +3 dBm0 to -37 dBm0 (exclude -37 dBm0) -37 dBm0 to -50 dBm0 (exclude -50 dBm0) -50 dBm0 to -55 dBm0 -0.25 -0.50 -1.40 0.25 0.50 1.40 dB dB dB Tested by sinusoidal method, A-law or µ-law GTR Receive Gain Tracking +3 dBm0 to -40 dBm0 (exclude -40 dBm0) -40 dBm0 to -50 dBm0 (exclude -50 dBm0) -50 dBm0 to -55 dBm0 -0.10 -0.25 -0.50 0.10 0.50 0.50 dB dB dB Tested by sinusoidal method, A-law or µ-law Parameter Description Min Typ Max Units Test Conditions DXA Transmit Delay, Absolute * 340 µs DXR Transmit Delay, Relative to 1800 Hz f = 500 Hz – 600 Hz f = 600 Hz – 1000 Hz f = 1000 Hz – 2600 Hz f = 2600 Hz – 2800 Hz 280 150 280 µs µs µs µs DRA Receive Delay, Absolute * 260 µs DRR Receive Delay, Relative to 1800 Hz f = 500 Hz – 600 Hz f = 600 Hz – 1000 Hz f = 1000 Hz – 2600 Hz f = 2600 Hz – 2800 Hz 120 150 µs µs µs µs Parameter Description Min Typ Max Units Test Conditions GXA Transmit Gain, Absolute 0°C to 85°C -40°C -0.30 -0.40 0.30 0.40 dB dB Signal input of 0 dBm0, µ-law or A-law GRA Receive Gain, Absolute 0°C to 85°C -40°C -0.30 -0.40 0.30 0.40 dB dB Measured relative to 0 dBm0, µ-law or A-law, PCM input of 0 dBm0 1020 Hz, RL = 10 kΩ Parameter Description Min Typ Max Units Test Conditions GXR Transmit Gain, Relative to GXA f = 50 Hz f = 60 Hz f = 300 Hz to 3000 Hz f = 3000 Hz to 3400 Hz f = 3600 Hz f ≥ 4600 Hz -0.15 -0.4 -30 -30 0.15 0.15 -0.1 -35 dB dB dB dB dB dB GRR Receive Gain, Relative to GRA f < 300 Hz f = 300 Hz to 3000 Hz f = 3000 Hz to 3400 Hz f = 3600 Hz f ≥ 4600 Hz -0.15 -0.4 0.15 0.15 -0.2 -35 dB dB dB dB dB

INDUSTRIAL TEMPERATURE RANGE821004J QUAD NON-PROGRAMMABLE PCM CODEC Distortion Noise Parameter Description Min Typ Max Units Test Conditions STDX Transmit Signal to Total Distortion Ratio A-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 µ-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 dB dB dB dB dB dB dB dB ITU-T O.132 Sine Wave Method,Psophometric Weighted for A- law, C Message Weighted for µ-law. STDR Receive Signal to Total Distortion Ratio A-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 µ-law : Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 dB dB dB dB dB dB dB dB ITU-T O.132 Sine Wave Method,Psophometric Weighted for A - law;Sine Wave Method,C Message Weighted for µ- law; SFDX Single Frequency Distortion, Transmit -42 dBm0 200 Hz - 3400 Hz, 0 dBm0 input, output any other single frequency ≤ 3400 Hz SFDR Single Frequency Distortion, Receive -42 dBm0 200 Hz - 3400 Hz, 0 dBm0 input, output any other single frequency ≤ 3400 Hz IMD Intermodulation Distortion -42 dBm0 Transmit or receive,two frequencies in the range (300 Hz− 3400 Hz) at − 6 dBm0 Parameter Description Min Typ Max Units Test Conditions NXC Transmit Noise, C Message Weighted for µ-law 16 dBrnC0 NXP Transmit Noise, Psophometric Weighted for A-law -68 dBm0p NRC Receive Noise, C Message Weighted for µ-law 12 dBrnC0 NRP Receive Noise, Psophometric Weighted for A-law -78 dBm0p NRS Noise, Single Frequency f = 0 kHz – 100 kHz -53 dBm0 IIN = 0 A, tested at VOUT PSRX Power Supply Rejection Transmit f = 300 Hz – 3.4 kHz f = 3.4 kHz – 20 kHz dB dB VDD = 5.0 VDC + 100 mVrms PSRR Power Supply Rejection Receive f = 300 Hz – 3.4 kHz f = 3.4 kHz – 20 kHz dB dB PCM code is positive one LSB, VDD = 5.0 VDC + 100 mVrms SOS Spurious Out-of-Band Signals at VOUT Relative to Input PCM code applied:

4600 Hz – 20 kHz

20 kHz – 50 kHz -40 -30 dB dB 0 dBm0, 300 Hz – 3400 Hz input

INDUSTRIAL TEMPERATURE RANGE821004J QUAD NON-PROGRAMMABLE PCM CODEC Interchannel Crosstalk Intrachannel Crosstalk Parameter Description Min Typ Max Units Test Conditions XTX-R Transmit to Receive Crosstalk -85 -78 dB 300 Hz – 3400 Hz, 0 dBm0 signal into IIN of interfering channel. Idle PCM code into channel under test. XTR-X Receive to Transmit Crosstalk -85 -80 dB 300 Hz – 3400 Hz, 0 dBm0 PCM code into interfering channel. IIN = 0 A for channel under test. XTX-X Transmit to Transmit Crosstalk -85 -78 dB 300 Hz – 3400 Hz, 0 dBm0 signal into IIN of interfering channel. IIN = 0 A for channel under test. XTR-R Receive to Receive Crosstalk -85 -80 dB 300 Hz – 3400 Hz, 0 dBm0 PCM code into interfering channel. Idle PCM code into channel under test. Parameter Description Min Typ Max Units Test Conditions XTX-R Transmit to Receive Crosstalk -80 -70 dB 300 Hz – 3400 Hz, 0 dBm0 signal into IIN. Idle PCM code into DR. XTR-X Receive to Transmit Crosstalk -80 -70 dB 300 Hz – 3400 Hz, 0 dBm0 PCM code into DR. IIN = 0 A.

Figure 2. MCLK Timing Note: Timing parameter t13 is referenced to a high-impedance state.

Data Sheet Document History X Device Type Blank Process/ Temperature Range JG 821004J Industrial (-40 °C to +85 °C) Green Plastic Leaded Chip Carrier (PLCC, PL32) Quad Non-Programmable PCM CODEC Package

ORDERING INFORMATION

X Blank Tube Tape and Reel

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