HS-81C55RH INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Devices QML Qualified in Accordance with MIL-PRF-38535
  • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil’ QM Plan
  • Radiation Hardened EPI-CMOS - Parametrics Guaranteed 1 x 105 RAD(Si) - Transient Upset > 1 x 108 RAD(Si)/s - Latch-Up Free > 1 x 1012 RAD(Si)/s
  • Electrically Equivalent to Sandia SA 3001
  • Pin Compatible with Intel 8155/56
  • Bus Compatible with HS-80C85RH
  • Single 5V Power Supply
  • Low Standby Current 200µA Max
  • Low Operating Current 2mA/MHz
  • Completely Static Design
  • Internal Address Latches
  • Two Programmable 8-Bit I/O Ports
  • One Programmable 6-Bit I/O Port
  • Programmable 14-Bit Binary Counter/Timer
  • Multiplexed Address and Data Bus
  • Self Aligned Junction Isolated (SAJI) Process
  • Military Temperature Range -55 oC to +125oC

Description

The HS-81C55/56RH are radiation hardened RAM and I/O chips fabricated using the Intersil radiation hardened Self- Aligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices. The HS-81C55/56RH is intended for use with the HS-80C85RH radiation hardened microprocessor system. The RAM portion is designed as 2048 static cells organized as 256 x 8. A maximum post irradiation access time of 500ns allows the HS-81C55/56RH to be used with the HS-80C85RH CPU without any wait states. The HS-81C55RH requires an active low chip enable while the HS-81C56RH requires an active high chip enable. These chips are designed for operation utilizing a single 5V power supply. Functional Diagram 256 x 8 STATIC RAM A B C TIMER IO/M AD0 - AD7 CE OR CE † ALE RD WR RESET TIMER CLK TIMER OUT

8 PA0 - PA7

8 PB0 - PB7

8 PC0 - PC5

VDD (10V) GND †81C55RH = CE 81C56RH = CE

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962R9XXXX01QRC -55 oC to +125oC MIL-PRF-38535 Level Q 40 Lead SBDIP 5962R9XXXX01VRC -55 oC to +125oC MIL-PRF-38535 Level V 40 Lead SBDIP 5962R9XXXX01QXC -55 oC to +125oC MIL-PRF-38535 Level Q 42 Lead Ceramic Flatpack 5962R9XXXX01VXC -55 oC to +125oC MIL-PRF-38535 Level V 42 Lead Ceramic Flatpack 5962R9XXXX02QRC -55 oC to +125oC MIL-PRF-38535 Level Q 40 Lead SBDIP 5962R9XXXX02VRC -55 oC to +125oC MIL-PRF-38535 Level V 40 Lead SBDIP 5962R9XXXX02QXC -55 oC to +125oC MIL-PRF-38535 Level Q 42 Lead Ceramic Flatpack 5962R9XXXX02VXC -55 oC to +125oC MIL-PRF-38535 Level V 42 Lead Ceramic Flatpack HS1-81C55RH/Sample +25 oC Sample 40 Lead SBDIP HS9-81C55RH/Sample +25 oC Sample 42 Lead Ceramic Flatpack HS1-81C56RH/Sample +25 oC Sample 40 Lead SBDIP HS9-81C56RH/Sample +25 oC Sample 42 Lead Ceramic Flatpack Spec Number 518056 File Number 3039.1 March 1996

HS-81C55RH, HS-81C56RH Pinouts

40 LEAD DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)

42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

INTERSIL OUTLINE K42.A TOP VIEW TIMER IN RESET GND PC4 PC5 ALE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VDDPC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 TIMER OUT CE or CE* WR RD IO /M *81C55RH = CE 81C56RH = CE PC1 PC2 PB6 PB1 PB2 VDD PB4 PB0 PA7 PA6 PA5 NC PA4 PA3 PA2 PA1 PC0 PA0 WR ALE RESET PC5 TIMER OUT IO/M CE OR CE RD PC3 PC4 AD0 AD1 AD2 AD3 NC AD6 AD7 GND TIMER IN AD4 AD5 PB3 PB5 PB7 Spec Number 518056

HS-81C55RH, HS-81C56RH Pin Description SYMBOL TYPE NAME AND FUNCTION RESET I Reset: Pulse provided by the HS-80C85RH to initialize the system (connect to HS-80C85RH RESET OUT). Input high on this line resets the chip and initializes the three I/O ports to input mode. The width of RESET pulse should typically be two HS-80C85RH clock cycle times. AD0 - AD7 I/O Address/Data:Tri-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The 8-bit address is latched into the address latch inside the HS-81C55 and HS-81C56RH on the falling edge of ALE. The address can be either for the memory section or the I/O section depending on the IO/ M input. The 8-bit data is either written into the chip or read from the chip, depending on theWR or RD input signal. CE or CE I Chip Enable:On the HS-81C55RH, this pin isCE and is ACTIVE LOW. On the HS-81C56RH, this pin is CE and is ACTIVE HIGH. RD I Read Control:Input low on this line with the Chip Enable active enables and AD0 - AD7 buffers. If IO/ M pin is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O port or command/status registers will be read to the AD bus. WR I Write Control:Input low on this line with the Chip Enable active causes the data on the Address/Data bus to be written to the RAM or I/O ports and command/status register, depending on IO/M. ALE I Address Latch Enable:This control signal latches both the address on the AD0 - AD7 lines and the state of the Chip Enable and IO/M into the chip at the falling edge of ALE. IO/MI I/O Memory: Selects memory if low and I/O and command/status registers if high. PA0 - PA7 (8) I/O Port A:These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the command register. PB0 - PB7 (8) I/O Port B:These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the command register. PC0 - PC7 (8) I/O Port C:These 6 pins can function as either input port, output port, or as control signals for PA and PB. Programming is done through the command register. When PC0 - PC5 are used as control signals, they will provide the following: PC0 - A INTR (Port A Interrupt) PC1 - ABF (Port A Buffer Full) PC2 - A STB (Port A Strobe) PC3 - B INTR (Port B Interrupt) PC4 - B BF (Port B Buffer Full) PC5 - B STB (Port B Strobe) TIMER IN I Timer Input:Input to the counter-timer. TIMER OUT O Timer Output:This output can be either a square wave or a pulse, depending on the timer mode. VDD I Voltage:+5V. GND I Ground: Ground reference. Spec Number 518056

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: All devices are guaranteed at worst case limits and over radiation. Dynamic current is proportional to operating frequency (2mA/MHz). TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All devices guaranteed at worst case limits and over radiation.
  2. Operating supply current (IDDOP) is proportional to operating frequency.
  3. Output timings are measured with purely capacitive load.
  4. For design purposes the limits are given as shown. For compatibility with the 80C85RH microprocessor, the AC parameters are tested
  5. Parameter tested as part of the functional test. No read and record data available.
  6. At low temperature, T1 is measured down to 10ns. If the reading is less than 10ns, the parameter will read 10ns.
  7. Read and Record data available on failing data only.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS characterized upon initial design release and upon design changes which would affect these characteristics. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

Specifications HS-81C55RH, HS-81C56RH Waveforms tRV READ CE (81C55RH) OR CE (81C56RH) IO/M AD 0-7 ALE RD ADDRESS DATA VALID tAD tAL tLA tLL tLC tCC tRIDE tRD tRDF tCL WRITE CE (81C55RH) OR CE (81C56RH) IO/M AD 0-7 ALE WR ADDRESS DATA VALID tRV tAL tLA tLL tLC tCC tDW tCL tCL tWD Spec Number 518056

HS-81C55RH, HS-81C56RH Waveforms (Continued) tRDI STROBED INPUT tSS BF STR OBED INTR RD INPUT DATA FROM PORT tSBF tSI tPSS tRBE tPHS STROBED OUTPUT tWBF BF STR OBE INTR WR OUTPUT DATA TO PORT tWI tWP tSI tSBE Spec Number 518056

HS-81C55RH, HS-81C56RH Waveforms (Continued) RD INPUT DATA BUS tPR tRP BASIC INPUT BASIC INPUT RD INPUT DATA BUS tWP RELOAD COUNTER CLRLOAD COUNTER CLR TIMER OUTPUT COUNTDOWN FROM 5 TO 1 2 1 5 432 1 5 TIMER IN TIMER OUT (PULSE) TIMER OUT (SQUARE WAVE) (NOTE 1) (NOTE 1) tR tF tCYC tTL tTH tTH tTL NOTE: THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC RELOAD MODE (M, MODE BIT = 1) Spec Number 518056

HS-81C55RH, HS-81C56RH Metallization Topology DIE DIMENSIONS: 222 x 202 x 14± 1mil (Die Thickness) METALLIZATION: Type: AlSi Thickness: 11k Å ± 2kÅ GLASSIVATION: Type: SiO2 Thickness: 8k Å ± 1kÅ Metallization Mask Layout HS-81C55RH, HS-81C56RH TIMER OUT (6) IO/M (7) CE OR CE (8) AD3 (15) AD4 (16) AD5 (17) AD6 (18) (5) PC5 (4) RESET (3) TIMER IN (2) PC4 (1) PC3 (40) VDD (39) PC2 (38) PC1 (37) PC0 (36) PB7 (35)PB6 AD7 (19) GND (20) PA0 (21) PA1 (22) PA2 (23) PA3 (24) PA4 (25) PA5 (26) RD (9) WR (10) ALE (11) AD0 (12) AD1 (13) AD2 (14) (34) PB5 (33) PB4 (32) PB3 (31) PB2 (30) PB1 (29) PB0 (28) PA7 (27) PA6 Spec Number 518056

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 HS-81C55RH, HS-81C56RH Spec Number 518056 NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum lim- its of lead dimensions b and c or M shall be measured at the cen- troid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. E D b Q A C A A M (c) (b) SECTION A-A BASE LEAD FINISH METAL M e N L Ceramic Metal Seal Flatpack Packages (Flatpack) 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 11. The basic lead spacing is 0.050 inch (1.27mm) between center lines. Each lead centerline shall be located within±0.005 inch (0.13mm) of its exact longitudinal position relative to lead 1 and the highest numbered (N) lead. K42.A TOP BRAZED A - 0.100 - 2.54 - b 0.017 0.025 0.43 0.64 - b1 0.017 0.023 0.43 0.58 - c 0.007 0.013 0.18 0.33 - c1 0. 007 0.010 0.18 0.25 - D 1.045 1.075 26.54 27.31 3 E 0.630 0.650 16.00 16.51 - E1 - 0.680 - 17.27 3 E2 0.530 0.550 13.46 13.97 - e 0.050 BSC 1.27 BSC 11 k---- - L 0.320 0.350 8.13 8.89 - Q 0.045 0.065 1.14 1.65 8 S1 0.000 - 0.00 - 6 N4 2 4 2- Rev. 0 6/17/94