814S208BKILFT

ICS814S208I IDT | Alldatasheet

Document overview

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Technical content

Features

• Third generation FemtoClock® technology
• Selectable 122.88MHz or 153.6MHz output clock synthesized from a 30.72MHz fundamental mode crystal
• Eight differential LVDS clock outputs
• Differential reference clock input pair
• PLL lock indicator output
• Crystal interface designed for a 30.72MHz, parallel resonant crystal
• RMS phase jitter @ 122.88MHz, using a 30.72MHz crystal (12kHz - 20MHz): 0.650ps (typical)
• RMS phase jitter @ 153.6MHz, using a 30.72MHz crystal (12kHz - 20MHz): 0.642ps (typical)
• LVCMOS interface levels for the control input
• Full 3.3V supply voltage
• Available in Lead-free (RoHS 6) 48-lead VFQFN package
• -40°C to 85°C ambient operating temperature QLOCK QA nQA QB0 nQB0 QB1 nQB1 QB2 nQB2 QB3 nQB3 QB4 nQB4 QB5 nQB5 QB6 nQB6 QB7 nQB7 Pulldown Pulldown (2) Pulldown Pulldown Pulldown Pulldown Pulldown OSC nOE_A XTAL_IN XTAL_OUT REF_CLK nREF_CLK REF_SEL BW[1:0] BYPASS N_SEL nOE_B0 nOE_B1 nOE_B2 ÷20 ÷5, PFD LPF FemtoClock® VCO 570MHz - 640MHz Pulldown Pullup/ Pulldown 0÷20 Pulldown fREF N Block Diagram

ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER ICS814S208BKILF REVISION B OCTOBER 13, 2011 2 ©2011 Integrated Device Technology, Inc. Pin Assignment 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 GND REF_SEL BYPASS nOE_B0 BW1 BW0 VDDA GND N_SEL nOE_B1 nOE_B2 nOE_A VDD nQB7 QB7 nQB6 QB6 GND VDD nQB5 QB5 nQB4 QB4 GND GND QB0 nQB0 QB1 nQB1 VDD GND QB2 nQB2 QB3 nQB3 VDD XTAL_IN XTAL_OUT VDD REF_CLK nREF_CLK GND VDDOL QLOCK GND QA nQA VDD ICS814S208I 48-lead VFQFN 7.0mm x 7.0mm x 0.925mm, package body K Package Top View

ICS814S208BKILF REVISION B OCTOBER 13, 2011 3 ©2011 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 24, 30, 36 VDD Power Core power supply pins. following differential input levels: LVPECL, LVDS, CML. following differential input levels: LVPECL, LVDS, CML. 25, 31, 41, 48 GND Power Power supply ground. 10, 11 QA, nQA Output Differential clock output pair. LVDS interface levels. 37 nOE_A Input Pulldown Output enable input. See Table 3E for function. LVCMOS/LVTTL interface levels. Input Pulldown Output enable inputs. See Tables 3F-3H for function. LVCMOS/LVTTL interface levels. 40 N_SEL Input Pulldown Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface levels. DDA Power Analog power supply. 43, 44 BW0, BW1 Input Pulldown PLL bandwidth control pins. See Table 3D for function. LVCMOS/LVTTL interface levels. 46 BYPASS Input Pulldown PLL bypass mode select pin. See Table 3B for function. LVCMOS/LVTTL interface levels. 47 REF_SEL Input Pulldown Reference select input. See Table 3C for function. LVCMOS/LVTTL interface levels.

ICS814S208BKILF REVISION B OCTOBER 13, 2011 4 ©2011 Integrated Device Technology, Inc. Table 2. Pin Characteristics NOTE: N_SEL is an asynchronous control. 122.88MHz at the QBx outputs. NOTE: BYPASS is an asynchronous control. NOTE: REF_SEL is an asynchronous control.

1 The REF_CLK input is selected as reference clock

ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER ICS814S208BKILF REVISION B OCTOBER 13, 2011 5 ©2011 Integrated Device Technology, Inc. Table 3D. PLL Bandwidth Function Table NOTE: BW[1:0] is an asynchronous control. NOTE: With the lowest PLL bandwidth setting (BW[1:0] = 00, 240kHz), the PLL attenuates input reference jitter with spectral components above 240kHz. With the highest PLL bandwidth setting (BW[1:0] = 11, 2MHz), the PLL is not optimized for input reference jitter attenuation. Table 3E. nOE_A Output Enable Function Table NOTE: nOE_A is an asynchronous control. Table 3I. QLOCK Output Function Table NOTE: QLOCK supports 3.3V, 2.5V or 1.8V according to the voltage supplied at VDDOL. See Table 4B. Table 3F. nOE_B0 Output Enable Function Table NOTE: nOE_B0 is an asynchronous control. Table 3G. nOE_B1 Output Enable Function Table NOTE: nOE_B1 is an asynchronous control. Table 3H. nOE_B2 Output Enable Function Table NOTE: nOE_B2 is an asynchronous control. Inputs Operation BW1 BW0 PLL Bandwidth 0 (default) 0 (default) 240kHz 0 (default) 1 520kHz 1 0 (default) 1MHz 11 2 M H z Input OperationnOEA 0 (default) QA, nQA outputs are enabled

1 QA, nQA outputs are disabled (high-impedance)

0 The PLL is locked to the input reference clock

1 The PLL is not locked to the input reference clock

OperationnOE_B0 0 (default) QB[0:3], nQB[ 0:3] outputs are enabled 1 QB[0:3]. nQB[0:3] outputs are disabled (high-impedance) Input OperationnOE_B1 0 (default) QB[4:5], nQB[ 4:5] outputs are enabled

1 QB[4:5], nQB[4:5] outputs are disabled (high-impedance)

OperationnOE_B2 0 (default) QB[6:7], nQB[ 6:7] outputs are enabled

1 QB[6:7], nQB[6:7] outputs are disabled (high-impedance)

ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER ICS814S208BKILF REVISION B OCTOBER 13, 2011 6 ©2011 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functio nal operation of product at these conditions or any conditions beyond those listed in the DC Cha racteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO (LVCMOS) -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 30.5°C/W (0 mps) Storage Temperature, TSTG -65 ° C to 150 ° C NOTE: For the Power Supply Voltage Sequence Information Application Note, see page 12. Item Rating Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3V 3.465 V VDDA Analog Supply Voltage VDD – 0.22 3.3V V DD V VDDOL QLOCK Output Supply Voltage 1.6 1.8 2.0 V 2.375 2.5 2.625 V 3.135 3.3 3.465 V IDDA Analog Supply Current 22 mA IDD Power Supply Current 355 mA

ICS814S208BKILF REVISION B OCTOBER 13, 2011 7 ©2011 Integrated Device Technology, Inc. NOTE 1: Common mode input voltage is defined as VIH. Table 5. Crystal Characteristics NOTE 1: Using typical crystal parameter for ESR, CO, and CL in a 30.72MHz crystal.

ICS814S208BKILF REVISION B OCTOBER 13, 2011 8 ©2011 Integrated Device Technology, Inc. has been reached under these conditions. NOTE 1: Refer to the phase noise plots. NOTE 2: Measured from the differential input crossing point to the differential output crossing point. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.

6 Samples ±9 ±30 ps

ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER ICS814S208BKILF REVISION B OCTOBER 13, 2011 9 ©2011 Integrated Device Technology, Inc. Typical Phase Noise at 122.88MHz Typical Phase Noise at 153.6MHz 122.88MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.650ps (typical) Noise Power dBc Hz Offset Frequency (Hz) 153.6MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.642ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER ICS814S208BKILF REVISION B OCTOBER 13, 2011 10 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Bank Skew Period Jitter, RMS Differential Input Level Output Skew RMS Phase Jitter SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND VDD VDDA QBx QBy nQBx nQBy tsk(b) VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram VDD GND nREF_CLK REF_CLK V CMR Cross Points VPP nQA QA nQBy QBy tsk(o) Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power

ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER ICS814S208BKILF REVISION B OCTOBER 13, 2011 11 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Rise and Fall Time Propagation Delay Offset Voltage Setup Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup Propagation Delay Time Interval Error 10% 90% 90% 10% tR tF VOD nQA, nQBx QA, QBx tPD nQA QA nREF_CLK REF_CLK out out LVDSDC Input ➤ VOS/∆ VOS VDD nQA, nQBx QA, QBx tPW tPERIOD tPW tPERIOD odc = x 100% 100 out out LVDSDC Input VOD/∆ VOD VDD Time TIE0 TIE1 TIE2 TIEN Ideal clock edge positions TIE: Time Interval Error = min, mean and max of TIE0...N

ICS814S208BKILF REVISION B OCTOBER 13, 2011 15 ©2011 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS814S208BKILF REVISION B OCTOBER 13, 2011 18 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS814S208I. Equations and example calculations are also provided. The total power dissipation for the ICS14S208I is the sum of the core power plus the analog power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 30.5°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 48 Lead VFQFN, Forced Convection

ICS814S208BKILF REVISION B OCTOBER 13, 2011 19 ©2011 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 48-lead VFQFN

ICS814S208BKILF REVISION B OCTOBER 13, 2011 20 ©2011 Integrated Device Technology, Inc. Table 9. PackageDimensions for 48 Lead VFQFN

1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)

ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER ICS814S208BKILF REVISION B OCTOBER 13, 2011 21 ©2011 Integrated Device Technology, Inc.

Ordering Information

Table 10. Ordering Information Table NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER ICS814S208BKILF REVISION B OCTOBER 13, 2011 22 ©2011 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date B T6 8 AC Characteristics Table - added Period JItter spec for QBx, nQBx outputs at 122.88MHz. Updated LVDS Termination application note. 10/13/11

ICS814S208I Data Sheet FEMTOCLOCK® CRYSTAL-TO-LVDS 8-OUTPUT CLOCK SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. Performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informati on contained herein is provided without re presentation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of IDT’s products for any particular purpose, an im plied warranty of merchantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.

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