ICS813252I-02 IDT | Alldatasheet

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VCXO JITTER ATTENUATOR & ICS813252I-02 IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 1 CS813252CKI-02 REV. A OCTOBER 22, 2008 FEMTOCLOCK™ MULTIPLIER GENERAL DESCRIPTION The ICS813252I-02 is a member of the HiperCloc kS™ f amily of high performance clock solutions from IDT . The ICS813252I-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock™ frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range. PIN ASSIGNMENT HiPerClockS™ ICS

FEATURES

  • Two LVPECL outputs Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz
  • Two differential inputs support the following input types: LVPECL, L VDS, LVHSTL, SSTL, HCSL
  • Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz
  • Attenuates the phase jitter of the input clock by using a low- cost pullable fundamental mode VCXO crystal
  • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using exter nal loop filter connection
  • FemtoClock frequency multiplier provides low jitter, high frequency output
  • Absolute pull range: 50ppm
  • FemtoClock VCO frequency: 625MHz
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (10kHz – 20MHz): 1.3ps (maximum)
  • 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 V EE nQB QB VCCO nQA QA VEE ODASEL_0 ICS813252I-02PDSEL_2 PDSEL_1 PDSEL_0 VCC VCCA ODBSEL_1 ODBSEL_0 ODASEL_1 nCLK1 CLK1 VCC nCLK0 CLK0 XTAL_OUT XTAL_IN VCCX LF1 LF0 ISET VEE CLK_SEL VCC RESERVED VEE 32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View

IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 2 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER BLOCK DIAGRAM Charge Pump VCXO Phase Detector Output Divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2 Output Divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2 VCXO Feedback Divider ÷3125 VCXO Input Pre-Divider VCXO Jitter Attenuation PLL XTAL_INXTAL_OUT LF1LF0ISET Loop Filter ODASEL_[1:0] CLK0 PDSEL_[2:0] nCLK0 0 25MHz QB nQB ODBSEL_[1:0] FemtoClock PLL 625MHz 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 CLK1 nCLK1 CLK_SEL Pulldown Pullup QA nQA 111 = 19440 (default)

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS

521 KLCnt upnI /pulluP

820 KLCnt upnI /pulluP

IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 4 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 3A. PRE-DIVIDER FUNCTION TABLE TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE stupnI eulaVrediviD-erP 2_LESDP1 _LESDP0 _LESDP 000 1 001 3 91 01 0 6 52 011 0 342 100 5 213 10 1 0 279 110 5 2651 111 ) tluafed(04491 stupnI eulaVrediviDtuptuO 1_LESxDO0 _LESxDO 00 ) tluafed(52 01 5 10 4 11 2

IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 5 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 3C. FREQUENCY FUNCTION TABLE tupnI ycneuqerF )zHM( rediviD-erP eulaV OXCV ycneuqerF )zHM( kcolCotmeF rediviDkcabdeeF eulaV kcolcotmeF ycneuqerFOCV )zHM( rediviDtuptuO eulaV ycneuqerFtuptuO )zHM( 800.01 5 25 25 265 25 2 800.01 5 25 25 265 5 21 800.01 5 25 25 264 5 2.651 800.01 5 25 25 262 5 .213 445.13 915 25 25 265 25 2 445.13 915 25 25 265 5 21 445.13 915 25 25 264 5 2.651 445.13 915 25 25 262 5 .213 840.26 525 25 25 265 25 2 840.26 525 25 25 265 5 21 840.26 525 25 25 264 5 2.651 840.26 525 25 25 262 5 .213 44.910 3425 25 25 265 25 2 44.910 3425 25 25 265 5 21 44.910 3425 25 25 264 5 2.651 44.910 3425 25 25 262 5 .213 525 2135 25 25 265 25 2 525 2135 25 25 265 5 21 525 2135 25 25 264 5 2.651 525 2135 25 25 262 5 .213 67.770 2795 25 25 265 25 2 67.770 2795 25 25 265 5 21 67.770 2795 25 25 264 5 2.651 67.770 2795 25 25 262 5 .213 5215 26515 25 25 265 25 2 5215 26515 25 25 265 5 21 5215 26515 25 25 264 5 2.651 5215 26515 25 25 262 5 .213 25.5510 44915 25 25 265 25 2 25.5510 44915 25 25 265 5 21 25.5510 44915 25 25 264 5 2.651 25.5510 44915 25 25 262 5 .213

IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 6 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TABLE 4A. POWER SUPPL Y DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V , TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V CC egatloVylppuSeroC 531.33 .35 64.3V V ACC egatloVylppuSgolanAV CC 51.0–3 .3V CC V V OCC egatloVylppuStuptuO 531.33 .35 64.3V V XCC egatloVylppuSpmuPegrahC 531.33 .35 64.3V I EE tnerruCylppuSrewoP 532A m I ACC tnerruCylppuSgolanA 51A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI tupnIe gatloVhgiH2 V CC 3.0+V V LI egatloVwoLtupnI 3.0-8 .0V I HI tupnI tnerruChgiH ,LES_KLC ,]1:0[_LESADO ]1:0[_LESBDO V CC V= NI V564.3=0 51A µ ]2:0[LESDPV CC V= NI V564.3=5 A µ I LI tupnI tnerruCwoL ,LES_KLC ,]1:0[_LESADO ]1:0[_LESBDO V CC V,V564.3= NI V0=5 -A µ ]2:0[LESDPV CC V,V564.3= NI V0=0 51-A µ

VsadenifedsiegatlovedomnommoC:2ETON HI . TABLE 5. AC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V±5%, VEE = 0V , TA = -40°C TO 85°C

IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 8 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TYPICAL PHASE NOISE @ 125MHZ PHASE NOISE (dBc)HZ 125MHz RMS Phase Jitter (Random) 10kHz to 20MHz = 0.98ps (typical) OFFSET FREQUENCY (HZ)

IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 9 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PARAMETER MEASUREMENT INFORMATION PHASE JITTER DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx nQx LVPECL VEE -1.3V ± 0.165V VCC, VCCO, VCCX Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power OUTPUT SKEW VCCA OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD V CMR Cross Points V PP VEE nCLK0, nCLK1 VCC CLK0, CLK1 t sk(o) FOUTx FOUTy nFOUTx nFOUT y 20% 80% 80% 20% tR tF VSWING tPW tPERIOD tPW tPERIOD odc = x 100% QA, QB nQA, nQB QA, QB nQA, nQB

IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 13 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are rec- ommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal dis- tortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board design- ers simulate to guarantee compatibility across all printed circuit and clock component process variations. VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω FOUT FIN RTT = Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V 125Ω 125Ω 84Ω 84Ω Zo = 50Ω Zo = 50Ω FOUT FIN

IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 15 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (C L ). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal’s load capacitance C L characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (C TUNE If the crystal’s C L is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal’s C L is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE htdiwdnaB) zHM(ycneuqerFlatsyrCR S k( ΩΩΩΩΩ)C S )Fµ(C P )Fµ(R TES k( ΩΩΩΩΩ) )woL(zH01z HM521 210 .11 0.09 0.9 )diM(zH09z HM521 221 .01 00.01 2.2 )hgiH(zH003z HM520 861 .01 000.01 2.2 CRYSTAL CHARACTERISTICS VCXO CHARACTERISTICS TABLE lobmySr etemaraPm uminiMl acipyTm umixaMs tinU noitarepOfoedoMl atnemadnuF fN ycneuqerF5 2z HM fT ecnareloTycneuqerF0 2±m pp fS ytilibatSycneuqerF0 2±m pp egnaRerutarepmeTgnitarepO0 4-5 8C ° CL ecnaticapaCdaoL0 1F p CO ecnaticapaCtnuhS4 F p CO/C1 oitaRytiliballuP0 220 42 RSEe cnatsiseRseireStnelaviuqE0 2 leveLevirD1 W m C°52@gnigAr aeyrep3±m pp lobmySr etemaraPl acipyTt inU k OXCV niaGOXCV0 07,51V /zH C WOL_V ecnaticapaCrotcaraVwoL9 .9F p C HGIH_V ecnaticapaCrotcaraVhgiH2 .22F p the crystal specification. In either case, the absolute tuning range is reduced. The correct value of C L is dependent on the characteristics of the VCXO. The recommended C L in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows R S , C S and C P values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. LF0 LF1 ISET XTAL_IN XTAL_OUT RS CSCP RSET CTUNE CTUNE 25MHz

This section provides information on power dissipation and junction temperature for the ICS813252I-02. Equations and example calculations are also provided. The total power dissipation for the ICS813252I-02 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V , which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 235mA = 814.275mW
  • Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power _MAX (3.465V , with all outputs switching) = 814.275mW + 60mW = 874.275mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the juncti on of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction T emperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.874W * 37°C/W = 117.3°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 32 LEAD VFQFN, FORCED CONVECTION

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. L VPECL output driver circuit and termination are shown in Figure 7. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 7. θ

TABLE 8. PACKAGE DIMENSIONS dimensions are in T able 8 below.

reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. TABLE 9. ORDERING INFORMATION

IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 21 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER TEEHSYROTSIHNOISIVER veRe lbaTe gaPe gnahCfonoitpircseDe taD A9 T0 2 .rebmuNredrO/traPehtnixiferpSCIdedda-elbaTnoitamrofnIgniredrO 80/6/5

VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

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