813252CKI-02LF

ICS813252I-02 RENESAS | Alldatasheet

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Jitter Attenuator & FemtoClock Multiplier ICS813252I-02 DATA SHEET ICS813252CKI-02 REVISION A AUGUST 4, 2016 1 ©2016 Integrated Device Technology, Inc. GENERAL DESCRIPTION The ICS813252I-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The fi rst stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop fi lter components which allows confi guration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range. PIN ASSIGNMENT

FEATURES

• Two LVPECL outputs Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz
• Two differential inputs support the following input types: LVPE- CL, LVDS , LVHSTL, SSTL, HCSL
• Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz
• Attenuates the phase jitter of the input clock by using a low- cost pullable fundamental mode VCXO crystal
• VCXO PLL bandwidth can be optimiz ed for jitter attenuation and reference tracking using external loop fi lter connection
• FemtoClock frequency multiplier provides low jitter, high fre- quency output
• Absolute pull range: 50ppm
• F emtoClock VCO frequency: 625MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal (10kHz – 20MHz): 1.3ps (maxim um)
• 3.3V supply v oltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• F or functional replacement device use 813N252CKI-02LF 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 V EE nQB QB V CCO nQA QA V EE ODASEL_0 ICS813252I-02PDSEL_2 PDSEL_1 PDSEL_0 V CC VCCA ODBSEL_1 ODBSEL_0 ODASEL_1 nCLK1 CLK1 VCC nCLK0 CLK0 XTAL_OUT XTAL_IN VCCX LF1 LF0 ISET V EE CLK_SEL VCC RESERVED VEE 32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View OBSOLETE

ICS813252CKI-02 REVISION A AUGUST 4, 2016 2 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER BLOCK DIAGRAM Charge Pump VCXO Phase Detector Output Divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2 Output Divider 00 = 25 (default) 01 = 5 10 = 4 11 = 2 VCXO Feedback Divider ÷3125 VCXO Input Pre-Divider VCXO Jitter Attenuation PLL XTAL_INXTAL_OUT LF1LF0ISET Loop Filter ODASEL_[1:0] CLK0 PDSEL_[2:0] nCLK0 0 25MHz QB nQB ODBSEL_[1:0] FemtoClock PLL 625MHz 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 CLK1 nCLK1 CLK_SEL Pulldown Pullup QA nQA 111 = 19440 (default)

ICS813252CKI-02 REVISION A AUGUST 4, 2016 3 ©2016 Integrated Device Technology, Inc. TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS Loop fi lter connection node pins. LF0 is the output. LF1 is the input.

3 ISET Analog Input/

Output Charge pump current setting pin. 5 CLK_SEL Input Pulldown Input clock select. When HIGH selects CLK1/nCLK1. When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels. Power Core power supply pins. 7 RESERVED Reserved Reserved pin. Do not connect. Input Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. 19, 20 QA, nQA Output Differential Bank A clock outputs. LVPECL interface levels. Power Output power supply pin. 22, 23 QB, nQB Output Differential Bank B clock outputs. LVPECL interface levels. /2 bias voltage when left fl oating. 26 CLK1 Input Pulldown Non-inverting differential clock input. /2 bias voltage when left fl oating. 29 CLK0 Input Pulldown Non-inverting differential clock input. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. Power Power supply pin for VCXO charge pump. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

ICS813252CKI-02 REVISION A AUGUST 4, 2016 4 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER TABLE 3A. PRE-DIVIDER FUNCTION TABLE TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE Inputs Pre-Divider Value PDSEL_2 PDSEL_1 PDSEL_0 000 1 001 1 9 3 010 2 5 6 0 1 1 2430 1 0 0 3125 1 0 1 9720 1 1 0 15625 1 1 1 19440 (default) Inputs Output Divider Value ODxSEL_1 ODxSEL_0 0 0 25 (default) 01 5 10 4 11 2

ICS813252CKI-02 REVISION A AUGUST 4, 2016 5 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER TABLE 3C. FREQUENCY FUNCTION TABLE Input Frequency (MHz) Pre-Divider Value VCXO Frequency (MHz) FemtoClock Feed- back Divider Value Femtoclock VCO Frequency (MHz) Output Divider Value Output Frequency (MHz) 0.008 1 25 25 625 25 25 0.008 1 25 25 625 5 125 0.008 1 25 25 625 4 156.25 0.008 1 25 25 625 2 312.5 1.544 193 25 25 625 25 25 1.544 193 25 25 625 5 125 1.544 193 25 25 625 4 156.25 1.544 193 25 25 625 2 312.5 2.048 256 25 25 625 25 25 2.048 256 25 25 625 5 125 2.048 256 25 25 625 4 156.25 2.048 256 25 25 625 2 312.5 19.44 2430 25 25 625 25 25 19.44 2430 25 25 625 5 125 19.44 2430 25 25 625 4 156.25 19.44 2430 25 25 625 2 312.5 25 3125 25 25 625 25 25 25 3125 25 25 625 5 125 25 3125 25 25 625 4 156.25 25 3125 25 25 625 2 312.5 77.76 9720 25 25 625 25 25 77.76 9720 25 25 625 5 125 77.76 9720 25 25 625 4 156.25 77.76 9720 25 25 625 2 312.5 125 15625 25 25 625 25 25 125 15625 25 25 625 5 125 125 15625 25 25 625 4 156.25 125 15625 25 25 625 2 312.5 155.52 19440 25 25 625 25 25 155.52 19440 25 25 625 5 125 155.52 19440 25 25 625 4 156.25 155.52 19440 25 25 625 2 312.5

ICS813252CKI-02 REVISION A AUGUST 4, 2016 6 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO = V CCX = 3.3V±5%, V EE = 0V, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = V CCO = V CCX = 3.3V±5%, V EE = 0V, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I XTAL_IN 0V to V CC Other Inputs -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 37°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC – 0.15 3.3 V CC V V CCO Output Supply Voltage 3.135 3.3 3.465 V V CCX Charge Pump Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 235 mA I CCA Analog Supply Current 15 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V CC + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] V CC = V IN = 3.465V 150 µA PDSEL[0:2] V CC = V IN = 3.465V 5 µA I IL Input Low Current CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] V CC = 3.465V, V IN = 0V -5 µA PDSEL[0:2] V CC = 3.465V, V IN = 0V -150 µA

ICS813252CKI-02 REVISION A AUGUST 4, 2016 7 ©2016 Integrated Device Technology, Inc. should not be less than -0.3V. TABLE 5. AC CHARACTERISTICS, V NOTE: Characterized with outputs at the same frequency using the loop fi lter components for the mid loop bandwidth. specifi cations after thermal equilibrium has been reached under these conditions. Refer to VCXO-PLL Loop Bandwidth Selection Table. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load condtions. Measured at the output differential cross points.

ICS813252CKI-02 REVISION A AUGUST 4, 2016 8 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER TYPICAL PHASE NOISE @ 125MHZ PHASE NOISE (dBc)HZ 125MHz RMS Phase Jitter (Random) 10kHz to 20MHz = 0.98ps (typical) OFFSET FREQUENCY (HZ)

ICS813252CKI-02 REVISION A AUGUST 4, 2016 9 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER PARAMETER MEASUREMENT INFORMATION PHASE JITTER DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD

ICS813252CKI-02 REVISION A AUGUST 4, 2016 12 ©2016 Integrated Device Technology, Inc. additional protection, a 1kΩ resistor can be tied from CLK to ground. resistance is not required but can be added for additional protection. pair should either be left fl oating or terminated. FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) and the inner edges of pad pattern for the leads to avoid any shorts. achieved when an array of vias is incorporated in the land pattern. Enhance Leadfame Base Package, Amkor Technology.

ICS813252CKI-02 REVISION A AUGUST 4, 2016 13 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER TERMINATION FOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recom- mended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock com- ponent process variations. 84 84 3.3VR3 125 125 Z o = 50 Zo = 50 Input 3.3V 3.3V

ICS813252CKI-02 REVISION A AUGUST 4, 2016 14 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER SCHEMATIC EXAMPLE Figure 6 shows an example of the ICS813252I-02 application schematic. In this example, the device is operated at V CC = V CCX = V CCO = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. An optional 3-pole fi lter can also be used for additional spur reduction. It is recommended that F IGURE 6. ICS813252I-02 SCHEMATIC EXAMPLE the loop fi lter components be laid out for the 3-pole option. This will also allow the 2-pole fi lter to be used. 3.3V R17 R18 Zo = 50 Ohm Zo = 50 Ohm 0.1u SP R16 SP R19 C11 10u 125 125 125 nCLK1 0.1u VCC 0.1u C10 0.01u CLK1 R15 2.21K 125 VCCO VCC VCC VCC VCC QB CLK0 nCLK0 Logic Control Input Examples Set Logic Input to '1' Set Logic Input to '0' To Logic Input pins To Logic Input pins 0.01u C6 10u VCCX R12 10 R11 133 R14 82.5 RU2 Not Install RU1 R10 133 RD2 RD1 Not Install Zo = 50 Ohm Zo = 50 Ohm R13 82.5 VCCVCC Rs 221k 2-pole loop filter for Mid Bandwidth setting LF Cp 0.001uF ODASEL_1 ODBSEL_0 ODBSEL_1 PDSEL_0 PDSEL_1 PDSEL_2 3-pole loop filter example - (optional) XTAL_I N XTAL_OU T 0.1u 820k 220pF Cp 0.01uF Rs 200k Cs 1.0uF LFLF VCCA Optional Y-Termination nQB ICS813252I-02 LF1 LF0 ISET VEE CLK_SEL VCC RESERVED VEE PDSEL_2 PDSEL_1 PDSEL_0 VCC VCCA ODBSEL_1 ODBSEL_0 ODASEL_1 ODASEL_0 17VEE 18QA 19nQA 20VCCO 21QB 22nQB 23VEE VCCX XTAL_IN XTAL_OUT CLK0 nCLK0 VCC CLK1 nCLK1 VCC CLK_SEL LVPECL Driv er LVPECL Driv er Zo = 50 Zo = 50 Zo = 50 Zo = 50 nCLK0 CLK0 VCC VCC = VCCX = VCCO= 3.3V LF Cs 0.1uF ODASEL_0 nQA QA

ICS813252CKI-02 REVISION A AUGUST 4, 2016 15 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (C L ). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal’s load capacitance C L characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (C TUNE If the crystal’s C L is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specifi cation. If the crystal’s C L is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE Bandwidth Crystal Frequency (MHz) R S (kΩ) C S (µF) C P (µF) R SET (kΩ) 10Hz (Low) 25MHz 121 1.0 0.01 9.09 90Hz (Mid) 25MHz 221 0.1 0.001 2.21 300Hz (High) 25MHz 680 0.1 0.0001 2.21 CRYSTAL CHARACTERISTICS VCXO CHARACTERISTICS TABLE Symbol Parameter Minimum Typical Maximum Units Mode of Operation Fundamental f N Frequency 25 MHz f T Frequency Tolerance ±20 ppm f S Frequency Stability ±20 ppm Operating Temperature Range -40 85 °C C L Load Capacitance 10 pF C O Shunt Capacitance 4 pF C O Pullability Ratio 220 240 ESR Equivalent Series Resistance 20 Drive Level 1 mW Aging @ 25°C ±3 per year ppm Symbol Parameter Typical Unit k VCXO VCXO Gain 15,700 Hz/V C V_LOW Low Varactor Capacitance 9.9 pF C V_HIGH High Varactor Capacitance 22.2 pF crystal specifi cation. In either case, the absolute tuning range is reduced. The correct value of C L is dependent on the characteristics of the VCXO. The recommended C L in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows R S , C S and C P values for recommended high, mid and low loop bandwidth confi gurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop fi lter components should be kept as close as possible to the device. Loop fi lter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop fi lter or crystal components.

ICS813252CKI-02 REVISION A AUGUST 4, 2016 16 ©2016 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS813252I-02. Equations and example calculations are also provided. The total power dissipation for the ICS813252I-02 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 235mA = 814.275mW
• Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power _MAX (3.465V, with all outputs switching) = 814.275mW + 60mW = 874.275mW 2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + TA Tj = J unction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.874W * 37°C/W = 117.3°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θJA FOR 32 LEAD VFQFN, FORCED CONVECTION

ICS813252CKI-02 REVISION A AUGUST 4, 2016 17 ©2016 Integrated Device Technology, Inc.

1. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 7.

• For logic high, V OUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX ) = 0.9V
• For logic low, V OUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/R L ] * (VCCO_MAX – VOH_MAX) = [(2V – (V CCO_MAX – VOH_MAX ))/R L ] * (VCCO_MAX – VOH_MAX) = Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R L ] * (VCCO_MAX – VOL_MAX) = [(2V – (V CCO_MAX – VOL_MAX ))/R L ] * (VCCO_MAX – VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

ICS813252CKI-02 REVISION A AUGUST 4, 2016 18 ©2016 Integrated Device Technology, Inc. TABLE 7. θ

ICS813252CKI-02 REVISION A AUGUST 4, 2016 19 ©2016 Integrated Device Technology, Inc.

1. Type A: Chamfer on the paddle (near pin 1)
2. Type B: Dummy pad between pin 1 and N.
3. Type C: Mouse bite on the paddle (near pin 1)

intended to convey the actual pin count or pin layout of this device. TABLE 8. PACKAGE DIMENSIONS

ICS813252CKI-02 REVISION A AUGUST 4, 2016 20 ©2016 Integrated Device Technology, Inc. NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant. TABLE 9. ORDERING INFORMATION

ICS813252CKI-02 REVISION A AUGUST 4, 2016 21 ©2016 Integrated Device Technology, Inc. ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER REVISION HISTORY SHEET Rev Table Page Description of Change Date AC Characteristics Table - added Thermal Note. Updated “Wiring the Differential Input to Accept Single-ended Levels” application note. Updated Figure 5A & 5B, LVPECL Termination Output drawings. Updated Package Outline drawing. Deleted “ICS” prefi x from Part/Order Number. 4/13/10 A 19 Added method package drawing. Corrected typo in inside page header. from ICS1325I-02 to ICS81325I-02. 8/25/10 A Product Discontinuation Notice - PDN CQ-14-05 Features - removed reference to leaded parts Ordering Information - removed leaded devices 8/22/14 A 1 Product Discontinuation Notice to Obsolete. 8/4/16

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San Jose, CA 95138 ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK MULTIPLIER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All infor- mation in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2016. All rights reserved. www.IDT.com

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