810N322I-02 IDT | Alldatasheet
Document overview
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Technical content
Features
- Fourth generation FemtoClock® NG technology
- Two LVCMOS outputs
- Each output supports independent frequency selection at 19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz
- Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, HCSL
- Accepts input frequencies from 8kHz to 156.25MHz including 8kHz,19.44MHz, 25MHz, 62.5MHz, 77.76MHz, 125MHz, 155.52MHz and 156.25MHz
- Crystal interface designed for a 27MHz, 10pF crystal
- Attenuates the phase jitter of the input clock by using a low-cost fundamental mode crystal
- Customized settings for jitter attenuation and reference tracking using an external loop filter connection
- FemtoClock NG frequency multiplier provides low jitter, high frequency output
- Absolute pull range: ±50ppm
- Power supply noise rejection (PSNR): -55 (typical)
- FemtoClock NG VCXO frequency: 2488.32MHz
- RMS phase jitter @ 155.52MHz, using a 27MHz crystal (12kHz – 20MHz):0.624ps (typical)
- 3.3V supply voltage
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package 9 1 01 11 2 1 31 41 51 6 32 31 30 29 28 27 26 25 LF1 LF0 ISET GND CLK_ SEL VDD RESERVED VDDO QA GND ODASEL_0 PDSEL_1 PDSEL_0 VDDA ODBSEL_1 ODASEL_1 VDDX XTAL_IN XTAL_OUT VDD CLK1 nCLK1 VDD QB nc nc CLK0 nCLK0 GND GND PDSEL_2 ODBSEL_0 Pin Assignment 810N322I-02
32 Lead VFQFN
5mm x 5mm x 0.925mm package body K Package Top View Jitter Attenuator & FemtoClock NG ® Multiplier 810N322I-02 Datasheet
2©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Block Diagram Phase Detector Charge Pump A/D Control Block FemtoClockÒ NG VCO ÷NA Fractional Feedback Divider PD LF Xtal Osc. LF0 LF1 ISET QA QB ÷NB ODBSEL_[1:0] ODASEL_[1:0] 27MHz DIGITAL VCXO Pulldown Pullup/ Pulldown Pullup/ Pulldown Pulldown Pulldown Pulldown Pulldown Pullup CS RSET RS CP SELCLK _ nCLK0 CLK0 CLK1 nCLK 1 PDSEL_[2:0]
Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Input/Output Loop filter connection node pins. LF0 is the output. LF1 is the input. Input/Output Charge pump current setting pin. CLK0, nCLK0. LVCMOS / LVTTL interface levels. 6, 12, 27 V DD Power Core supply pins. 7 RESERVED Reserve Reserved pin. Input Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. 13 V DDA Power Analog supply pin. When LOW bypa ss the PLL (for testing purposes only). ODBSEL_0 Input Pulldown Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVTTL interface levels. ODASEL_0 Input Pulldown Frequency select pins for Bank A output. See Table 3B. LVCMOS/LVTTL interface levels. 19 QA Output Single-ended Bank A clock out put. LVCMOS/LVTTL interface levels. 20, 23 nc Unused No connect. 21 V DDO Power Output supply pin. 22 QB Output Single-ended Bank B clock out put. LVCMOS/LVTTL interface levels. Pulldown Inverting differential clock input. VDD/2 bias voltage when left floating. 26 CLK1 Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. VDD/2 bias voltage when left floating. 29 CLK0 Input Pulldown Non-inverting differential clock input. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 32 V DDX Power Power supply pin for VCXO charge pump.
4©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Function Tables Table 3A. Pre-Divider Selection Function Table Table 3B. Output Divider Function Table NOTE: ODxSEL denotes ODASEL or ODBSEL. Inputs Pre-Divider ValuePDSEL_2 PDSEL_1 PDSEL_0 000 1 001 1 944 010 2 500 011 6 250 100 7 776 1 0 1 12500 1 1 0 15552 1 1 1 15625 (default) Inputs Output Divider ValueODxSEL_1 ODxSEL_0 0 0 128 (default) 01 3 2 10 1 6 11 4
5©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Table 3C. Example Configurations for Selected Output and Input Frequencies NOTE: ODxSEL denotes ODASEL or ODBSEL. User Configuration and Frequencies Int ernal Divider Values and Frequencies Input Frequency (MHz) Output Frequency (MHz) PDSEL [2:0] ODxSEL [1:0] Pre Divider P Feedback Divider M Fractional Feedback Divider FemtoClock NG FemtoClock NG VCO Frequency (MHz) Output Divider Nx 0.008 622.08 000 1 128 2430 2488.32 155.52 10 16 77.76 01 32 19.44 11 128 19.44 622.08 001 1944 128 1944 2488.32 155.52 10 16 77.76 01 32 19.44 11 128 622.08 010 2500 128 1944 2488.32 155.52 10 16 77.76 01 32 19.44 11 128 62.5 622.08 011 6250 128 1944 2488.32 155.52 10 16 77.76 01 32 19.44 11 128 77.76 622.08 100 7776 128 1944 2488.32 155.52 10 16 77.76 01 32 19.44 11 128 125 622.08 101 12500 128 1944 2488.32 155.52 10 16 77.76 01 32 19.44 11 128 155.52 622.08 110 15552 128 1944 2488.32 155.52 10 16 77.76 01 32 19.44 11 128 156.25 622.08 111 15625 128 1944 2488.32 155.52 10 16 77.76 01 32 19.44 11 128
6©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VDD+ 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 33.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage PLL Mode V DD – 0.30 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V VDDX Charge Pump Supply Voltage 3.135 3.3 3.465 V IDD + IDDX Power Supply Current 220 mA IDDA Analog Supply Current V DDA = High 30 mA IDDO Output Supply Current VDDA = Low PDSEL [2:0] = 0, ODxSEL[1:0] = 1 12 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_SEL, ODASEL_[1:0], ODBSEL_[1:0] VDD = VIN = 3.465V 150 µA PDSEL_[2:0] V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK_SEL, ODASEL_[1:0], ODBSEL_[1:0] VDD = 3.465V, VIN = 0V -5 µA PDSEL_[2:0] V DD = 3.465, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 2.6 V VOL Output Low Voltage; NOTE 1 0.5 V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagram. NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined at the crosspoint. Table 5. AC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C has been reached under these conditions. NOTE: Characterized with outputs at the same frequency using the loop filter components for the 44Hz loop bandwidth. Refer to Jitter Attenuator Loop Bandwidth Selection Table. NOTE 1: Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Lock Time measured from power-up to stable output frequency.
8©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Typical Phase Noise at 155.52MHz Noise Power dBc Hz Offset Frequency (Hz)
9©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Parameter Measurement Information Output Load AC Test Circuit Output-to-Input Phase Lock Time Output Skew Output Duty Cycle/Pulse Width/Period Differential Input Level RMS Phase Jitter Output Rise/Fall Time SCOPE Qx GND 1.65V ±5% -1.65 ±5% VDD, VDDO, VDDX 1.65V ±5% VDDA Qx Qy tsk(o) VDDOX VDDOX QA, QB tPERIOD tPW tPERIOD odc = VDDO x 100% tPW nCLK[0:1] CLK[0:1] VDD GND VCMR Cross Points V PP 20% 80% 80% 20% tR tF QA, QB
13©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Jitter Attenuator External Components Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the Jitter Attenuator. In choosing a crystal, special precaution must be taken with load capacitance (CL), frequency accuracy and temperature range. The crystal’s CL characteristic determines its resonating frequency and is closely related to the center tuning of the crystal. The total external capacitance seen by the crystal when installed on a PCB is the sum of the stray board capacitance, IC package lead capacitance, internal device capacitance and any installed tuning capacitors (CTUNE). The recommended CLin the Crystal Parameter Table balances the tuning range by centering the tuning curve for a typical PCB. If the crystal CL is greater than the total external capacitance, the crystal will oscillate at a higher frequency than the specification. If the crystal CL is lower than the total external capacitance, the crystal will oscillate at a lower frequency than the specification. Tuning adjustments might be required depending on the PCB parasitics or if using a crystal with a higher CL specification. In addition, the frequency accuracy specification in the crystal characteristics table are used to calculate the APR (Absolute Pull Range). Crystal Characteristics The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS,CP and RSET values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. In addition, the digital VCXO gain (KVCXO) has been provided for additional loop filter requirements. Jitter Attenuator Characteristics Table Jitter Attenuator Loop Bandwidth Selection Table (2ND Order Loop Filter) NOTE: See Application schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET. LF0 LF1 ISET XTAL_IN XTAL_OUT R S CSCP RSET CTUNE 3.3pF CTUNE 3.3pF 27MHz Symbol Parameter Test Conditio ns Minimum Typical Maximum Units Mode of Oscillation Fundamental fN Frequency 27 MHz fT Frequency Tolerance ±20 ppm fS Frequency Stability ±20 ppm Operating Temperature Range -40 +85 0C CL Load Capacitance 10 pF CO Shunt Capacitance 4p F ESR Equivalent Se ries Resistance 40 Aging @ 25 0C First Year ±3 ppm Symbol Parameter Typical Units kVCXO VCXO Gain 2.78 kHz/V Bandwidth Crystal Frequency R S (k)C S (µF) C P (µF) R3 (k )C 3 (µF) R SET (k) 15Hz (Low) 27MHz 215 10 0.022 0 DEPOP 2.74 30Hz (Mid) 27MHz 365 2.2 0.0047 0 DEPOP 2.74 60Hz (High) 27MHz 470 1 0.0022 0 DEPOP 1.5
14©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet For applications in which there is substantial low frequency jitter in the input reference and the phase detector frequency of 8kHz or 10kHz lies in or near a jitter mask, a three pole filter is recommended. Suggested part values are in the table below. Note that the option of a three pole filter can be left open by laying out the three pole filter but setting R3 to 0 ohms and not populating C3. Refer to the application schematic for a specific example. Jitter Attenuator Loop Bandwidth Selection Table (3RD Order Loop Filter) NOTE: See Application schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. Bandwidth Crystal Frequency R S (k)C S (µF) C P (µF) R3 (k )C 3 (k)R SET (k) 15Hz (Low) 27MHz 196 10 0.022 82.5 0.010 2.74 30Hz (Mid) 27MHz 392 2.2 0.0047 165 0.0022 2.74 60Hz (High) 27MHz 432 1 0.0022 182 0.001 1.5
15©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Schematic Layout Figure 4 (next page) shows an example of 810N322I-02 application schematic. In this example, the device is operated at VDD = VDDA = VDDX = VDDO = 3.3V. The inputs are driven by a 3.3V LVPECL driver and an LVDS driver. A three pole loop filter is used for the greater reduction of 10 kHz phase detector spurs relative to that afforded by a two pole loop filter. It is recommended that the loop filter components be laid out for the 3-pole option, which will also allow a 2-pole filter to be used. The loop filter components are to be laid out on the 810N322I-02 side of the PCB directly adjacent to the LF0 and LF1 pins. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 810N322I-02 provides separate VDD, VDDA, VDDX and VDDO power supplies for each jitter attenuator to isolate any high switching noise from coupling into In order to achieve the best possible filtering, it is highly recommended that the 0.1uF capacitors on the device side of the ferrite beads be placed on the device side of the PCB as close to the power pins as possible. This is represented by the placement of these capacitors in the schematic. If space is limited, the ferrite beads, 10uf and 0.1uF capacitor connected to 3.3V can be placed on the opposite side of the PCB. If space permits, place all filter components on the device side of the board. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.
Figure 4. 810N322I-02 Application Schematic
27 MH z (10 pf )
17©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 810N322I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 810N322I-02 is the sum of the core power plus the analog power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core Output Power Dissipation Power (core) MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(220mA + 30mA) = 866.25mW Power (output) MAX = VDDO_MAX * IDDO = 3.465V *12mA = 41.58mW LVCMOS Output Power Dissipation Output Impedance R OUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 8)] = 29.871mA Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 8 * (29.871mA)2 = 7.138mW per output Total Power Dissipation on the R OUT Total Power (ROUT) = 7.138mW * 2 = 14.276mW Dynamic Power Dissipation at 622.08MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 8pF * 622.08MHz * (3.465V)2 = 59.75mW per output Total Power (622.08MHz) = 59.75mW * 2 = 119.5mW Total Power Dissipation Total Power = Power (core) + Power (output) + Total Power (622.08MH) = 866.25mW + 41.58mW + 14.276mW + 119.5mW = 1041.61mW
wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below. Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN
32 Lead VFQFN Package Outline and Package Dimensions
Table 8. Package Dimensions package dimensions are in Table 8.
- Type A: Chamfer on the paddle (near pin 1)
- Type C: Mouse bite on the paddle (near pin 1)
21©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet
Ordering Information
Table 9. Ordering Information
22©2016 Integrated Device Technology, Inc. Revision B, February 25, 2016 810N322I-02 Datasheet Revision History Sheet Rev Table Page Description of Change Date B Deleted “ICS” prefix from part number. Updated datasheet header/footer. 2/25/16
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