ICS810N252I-02 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: epieczon
- PDF pages: 22
Technical content
Features
- Fourth generation FemtoClock® NG technology
- Two single-ended LVCMOS/LVTTL outputs
- Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz
- Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, HCSL
- Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz
- Crystal interface designed for a 27MHz crystal
- Attenuates the phase jitter of the input clock by using a low-cost fundamental mode crystal
- Customized settings for jitter attenuation and reference tracking using an external loop filter connection
- FemtoClock NG frequency multiplier provides low jitter, high frequency output
- Absolute pull range: ±50ppm
- Power supply noise ratio (PSNR): -85dB
- FemtoClock NG VCO frequency: 625MHz
- RMS phase jitter @ 125MHz, using a 27MHz crystal (12kHz – 20MHz): 0.67ps (typical)
- 3.3V supply voltage
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 LF1 LF0 ISET GND CLK_SEL VDD RESERVED GND GND nc QB VDDO nc QA GND ODASEL_0 PDSEL_2 PDSEL_1 PDSEL_0 VDD VDDA ODBSEL_1 ODBSEL_0 ODASEL_1 XTAL_IN XTAL_OUT CLK0 nCLK0 VDD CLK1 nCLK1 VDDX Pin Assignment ICS810N252I-02
32 Lead VFQFN
5mm x 5mm x 0.925mm package body 3.15mm x 3.15mm ePad size K Package Top View
ICS810N252CKI-02 REVISION A MAY 31, 2013 2 ©2013 Integrated Device Technology, Inc. ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Block Diagram Phase Detector Charge Pump A/D Control Block FemtoClockÒ NG VCO ÷NA Fractional Feedback Divider PD LF Xtal Osc. LF0 LF1 ISET QA QB ÷NB ODBSEL_[1:0] ODASEL_[1:0] 27MHz DIGITAL VCXO Pulldown Pullup/ Pulldown Pullup/ Pulldown Pulldown Pulldown Pulldown Pulldown Pullup CS RSET RS CP SELCLK _ nCLK0 CLK0 CLK1 nCLK 1 PDSEL _[2:0]
ICS810N252CKI-02 REVISION A MAY 31, 2013 3 ©2013 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Input/Output Loop filter connection node pins. LF0 is the output. LF1 is the input. Input/Output Charge pump current setting pin. 4, 8, 18, 24 GND Power Power supply ground. CLK0, nCLK0. LVCMOS / LVTTL interface levels. 6, 12, 27 V DD Power Core supply pins. 7 RESERVED Reserve Reserved pin. Input Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. 13 VDDA Power Analog supply pin. ODBSEL_0 Input Pulldown Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVTTL interface levels. ODASEL_0 Input Pulldown Frequency select pins for Bank A output. See Table 3B. LVCMOS/LVTTL interface levels. 19 QA Output Single-ended Bank A clock output. LVCMOS/LVTTL interface levels. 20, 23 nc Unused No connect. DDO Power Output supply pin. 22 QB Output Single-ended Bank B clock output. LVCMOS/LVTTL interface levels. Pulldown Inverting differential clock input. VDD/2 bias voltage when left floating. 26 CLK1 Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. VDD/2 bias voltage when left floating. 29 CLK0 Input Pulldown Non-inverting differential clock input. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 32 V DDX Power Power supply pin for crystal oscillator.
ICS810N252CKI-02 REVISION A MAY 31, 2013 4 ©2013 Integrated Device Technology, Inc. Table 2. Pin Characteristics
ICS810N252CKI-02 REVISION A MAY 31, 2013 5 ©2013 Integrated Device Technology, Inc. ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Table 3C. Frequency Function Table Input Frequency (MHz) Pre-Divider Value VCXO Frequency (MHz) FemtoClock Feedback Divider Value FemtoClock VCO Frequency (MHz) Output Divider Value Output Frequency (MHz) 0.008 1 27 25 625 25 25 0.008 1 27 25 625 5 125 0.008 1 27 25 625 4 156.25 0.008 1 27 25 625 2 312.5 1.544 193 27 25 625 25 25 1.544 193 27 25 625 5 125 1.544 193 27 25 625 4 156.25 1.544 193 27 25 625 2 312.5 2.048 256 27 25 625 25 25 2.048 256 27 25 625 5 125 2.048 256 27 25 625 4 156.25 2.048 256 27 25 625 2 312.5 19.44 1944 27 25 625 25 25 19.44 1944 27 25 625 5 125 19.44 1944 27 25 625 4 156.25 19.44 1944 27 25 625 2 312.5 25 2500 27 25 625 25 25 25 2500 27 25 625 5 125 25 2500 27 25 625 4 156.25 25 2500 27 25 625 2 312.5 77.76 7776 27 25 625 25 25 77.76 7776 27 25 625 5 125 77.76 7776 27 25 625 4 156.25 77.76 7776 27 25 625 2 312.5 125 12500 27 25 625 25 25 125 12500 27 25 625 5 125 125 12500 27 25 625 4 156.25 125 12500 27 25 625 2 312.5 155.52 15552 27 25 625 25 25 155.52 15552 27 25 625 5 125 155.52 15552 27 25 625 4 156.25 155.52 15552 27 25 625 2 312.5
ICS810N252CKI-02 REVISION A MAY 31, 2013 6 ©2013 Integrated Device Technology, Inc. ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVPECL Power Supply DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagram. Item Rating Supply Voltage, VDD 3.63V Inputs, VI -0.5V to VDD+ 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 33.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage PLL Mode VDD – 0.30 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V VDDX Crystal Oscillator Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 230 mA IDDA Analog Supply Current VDDA = HIGH 30 mA IDDO Output Supply Current VDDA = LOW, PDSEL[2:0] = 000, ODxSEL[1:0] = 11 15 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_SEL, ODASEL_[1:0], ODBSEL_[1:0] VDD = VIN = 3.465V 150 µA PDSEL_[2:0] VDD = VIN = 3.465V 5 µA IIL Input Low Current CLK_SEL, ODASEL_[1:0], ODBSEL_[1:0] VDD = 3.465V, VIN = 0V -5 µA PDSEL_[2:0] VDD = 3.465, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 2.6 V VOL Output Low Voltage; NOTE 1 0.5 V
ICS810N252CKI-02 REVISION A MAY 31, 2013 7 ©2013 Integrated Device Technology, Inc. NOTE 1. Common mode voltage is defined at the crosspoint. Table 5. AC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C has been reached under these conditions. NOTE: Characterized with outputs at the same frequency using the loop filter components for the 44Hz loop bandwidth. Refer to Jitter Attenuator Loop Bandwidth Selection Table. NOTE 1: Outputs switching to same frequency. Refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Lock Time measured from power-up to stable output frequency, LOW bandwidth setting.
ICS810N252CKI-02 REVISION A MAY 31, 2013 8 ©2013 Integrated Device Technology, Inc. ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Typical Phase Noise at 125MHz Noise Power dBc Hz Offset Frequency (Hz)
ICS810N252CKI-02 REVISION A MAY 31, 2013 9 ©2013 Integrated Device Technology, Inc. ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Parameter Measurement Information 3.3V LVCMOS Output Load Test Circuit VCXO & FemtoClock PLL Lock Time Output Skew Output Duty Cycle/Pulse Width/Period Differential Input Level RMS Phase Jitter LVCMOS Output Rise/Fall Time SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% 1.65V±5% VDDA VDDX, VDDO tsk(o) VDDO VDDO Qx Qy tPERIOD tPW tPERIOD odc = VDDO x 100% tPW QA, QB nCLK[0:1] CLK[0:1] VDD GND VCMR Cross Points V PP Offset Frequencyf1 f2 Phase Noise Plot Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter = Noise Power 2 * * ƒ 1 * 20% 80% 80% 20% tR tF QA, QB
ICS810N252CKI-02 REVISION A MAY 31, 2013 12 ©2013 Integrated Device Technology, Inc. resistance is not required but can be added for additional protection. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS810N252CKI-02 REVISION A MAY 31, 2013 13 ©2013 Integrated Device Technology, Inc. ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Jitter Attenuator EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the Jitter Attenuator. In choosing a crystal, special precaution must be taken with load capacitance (C L), frequency accuracy and temperature range. The crystal’s CL characteristic determines its resonating frequency and is closely related to the center tuning of the crystal. The total external capacitance (CEXTERNAL) seen by the crystal when installed on a PCB is the sum of the stray board capacitance, IC package lead capacitance, internal device capacitance and any installed tuning capacitors (C TUNE). The recommended CLin the Crystal Parameter Table balances the tuning range by centering the tuning curve for a typical PCB. If the crystal CL is greater than the total external capacitance (CL > CEXTERNAL), the crystal will oscillate at a higher frequency than the specification. If the crystal CL is lower than the total external capacitance (CL < CEXTERNAL), the crystal will oscillate at a lower frequency than the specification. Mismatches between CL and CEXTERNAL require adjustments in CTUNE in order to center the tuning curve. In addition, the frequency accuracy specification in the crystal characteristics table are used to calculate the APR (Absolute Pull Range). It is recommended that the crystal CL is not to exceed the value stated in the Crystal Parameter Table because it can lead to a reduced APR. Crystal Characteristics The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS,CP and RSET values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. In addition, the digital VCXO gain (KVCXO) has been provided for additional loop filter requirements. Jitter Attenuator Characteristics Table Jitter Attenuator Loop Bandwidth Selection Table (2nd Order Loop Filter) NOTE: See Application Schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET. LF0 LF1 ISET XTAL_IN XTAL_OUT RS CSCP RSET CTUNE CTUNE 27MHz Symbol Parameter Test Conditions Minimum Typical Maximum Units Mode of Oscillation Fundamental fN Frequency 27 MHz fT Frequency Tolerance ±20 ppm fS Frequency Stability ±20 ppm Operating Temperature Range -40 +85 0C CL Load Capacitance 10 pF CO Shunt Capacitance 4p F ESR Equivalent Se ries Resistance 40 Drive Level 1m W Aging @ 25 0C First Y ear ±3 ppm Symbol Parameter Typical Units kVCXO VCXO Gain 2.78 kHz/V Bandwidth Crystal Frequency R S (k)C S (µF) C P (µF) R3 (k )C 3 ( µ F )R SET (k) 15Hz (Low) 27MHz 215 10 0.022 0 DEPOP 2.74 30Hz (Mid) 27MHz 432 2.2 0.0047 0 DEPOP 2.74 60Hz (High) 27MHz 470 1 0.0022 0 DEPOP 1.5
ICS810N252CKI-02 REVISION A MAY 31, 2013 14 ©2013 Integrated Device Technology, Inc. ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER For applications in which there is substantial low frequency jitter in the input reference and the phase detector frequency of 8kHz or 10kHz lies in or near a jitter mask, a three pole filter is recommended. Suggested part values are in the table below. Note that the option of a three pole filter can be left open by laying out the three pole filter but setting R3 to 0 and not populating C3. Refer to the application schematic for a specific example. Jitter Attenuator Loop Bandwidth Selection Table (3rd Order Loop Filter) NOTE: See Application Schematic to identify loop filter components RS, CS, CP, R3, C3 and RSET. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. Bandwidth Crystal Frequency R S (k)C S (µF) C P (µF) R3 (k )C 3 ( µ F )R SET (k) 15Hz (Low) 27MHz 196 10 0.022 82.5 0.010 2.74 30Hz (Mid) 27MHz 392 2.2 0.0047 165 0.0022 2.74 60Hz (High) 27MHz 432 1 0.0022 182 0.001 1.5
ICS810N252CKI-02 REVISION A MAY 31, 2013 15 ©2013 Integrated Device Technology, Inc. ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER Schematic Example Figure 4 shows an example of the ICS810N252I-02 application schematic. In this example, the device is operated at VDD= VDDA = VDDX = VDDO = 3.3V. The inputs are driven by a 3.3V LVPECL driver and an LVDS driver. A three pole loop filter is used for the greater reduction of 8kHz or 10kHz phase detector spurs relative to that afforded by a two pole loop filter. It is recommended that the loop filter components be laid out for the 3-pole option, which will also allow a 2-pole filter to be used The loop filter components are to be laid out on the ICS810N252I-02 side of the PCB directly adjacent to the LF0 and LF1 pins. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS810N252I-02 provides separate V DD, VDDA, VDDX and VDDO power supplies for each jitter attenuator to isolate any high switching noise from coupling into the internal PLLs. In order to achieve the best possible filtering, it is highly recommended that the 0.1uF capacitors on the device side of the ferrite beads be placed on the device side of the PCB as close to the power pins as possible. This is represented by the placement of these capacitors in the schematic. If space is limited, the ferrite beads, 10uF and 0.1uF capacitor connected to 3.3V can be placed on the opposite side of the PCB. If space permits, place all filter components on the device side of the board. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.
ICS810N252CKI-02 REVISION A MAY 31, 2013 16 ©2013 Integrated Device Technology, Inc. Figure 4. ICS810N252I-02 Application Schematic.
27 MHz (1 0pf)
ICS810N252CKI-02 REVISION A MAY 31, 2013 17 ©2013 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS810N252I-02. Equations and example calculations are also provided. DD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 33.1°C/W per Table 76 below. Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
ICS810N252CKI-02 REVISION A MAY 31, 2013 18 ©2013 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN
ICS810N252CKI-02 REVISION A MAY 31, 2013 19 ©2013 Integrated Device Technology, Inc. Table 8. Package Dimensions NOTE: The following package mechanical drawing is a generic package dimensions are in Table 8.
- Type A: Chamfer on the paddle (near pin 1)
- Type C: Mouse bite on the paddle (near pin 1)
ICS810N252CKI-02 REVISION A MAY 31, 2013 20 ©2013 Integrated Device Technology, Inc. ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Ordering Information
Table 9. Ordering Information
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The information contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2013. All rights reserved.
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