80C286 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • This Circuit is Processed in Accordance to MIL-STD- 883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
  • Compatible with NMOS 80286/883
  • Static CMOS Design for Low Power Operation - ICCSB = 5mA Maximum - ICCOP = 185mA Maximum (80C286-10/883) - ICCOP = 220mA Maximum (80C286-12/883)
  • Large Address Space - 16 Megabytes Physical - 1 Gigabyte Virtual per Task
  • Integrated Memory Management, Four-Level Memory Protection and Support for Virtual Memory and Operating Systems
  • Two 80C86 Upward Compatible Operating Modes - 80C286/883 Real Address Mode - Protected Virtual Address Mode
  • Compatible with 80287 Numeric Data Co-Processor March 1997

Ordering Information

PACKAGE TEMP. RANGE 10MHz 12.5MHz 16MHz 20MHz 25MHz PKG. NO. 68 Pin PGA 0 oC to +70oC - CG80C286-12 CG80C286-16 CG80C286-20 - G68.B -40oC to +85oC IG80C286-10 IG80C286-12 - - - G68.B -55oC to +125oC MG80C286-10/883 MG80C286-12/883 - - - G68.B 5962-9067801MXC 5962-9067802MXC - - - G68.B File Number 2948.1

68 LEAD PGA, COMPONENT PAD VIEW

As viewed from underside of the component when mounted on the board. P.C. BOARD VIEW As viewed from the component side of the P .C. board. 5253 13579 10 46812 1113 1416 1517 1918 2120 35 37 38 40 39 41 42 44 43 45 46 48 47 49 ERR OR NC PEA CK A22 A21 A19 A17 A15 A12 CLK RESET A10 A12 ERR OR NC INTR NMI PEREQ READ Y HLDA M/ IO NC NC B USY NC NC VSS VCC HOLD COD/ INTA LOCK D15 D14 D13 D12 D11 D10 V SS BHE NC A23 VSS A20 A18 A16 A14 VCC A11 A13 PIN 1 INDICATOR 52 53 13 579 104 68 1 2 11 13 14 16 15 17 19 18 21 20 3537 3840 3941 4244 4345 4648 4749 ERR OR NC PEA CK A22 A21 A19 A17 A15 A12 CLK RESET A10 A12 ERR OR NC INTR NMI PEREQ READ Y HLDA M/ IO NC NC B USY NC NC VSS VCC HOLD COD/ INTA LOCK D15 D14 D13 D12 D11 D10 V SS BHE NC A23 VSS A20 A18 A16 A14 V CC A11 A13 PIN 1 INDICATOR

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

  1. θJA is measured with the component mounted on an evaluation PC board in free air.

TABLE 1. 80C286/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS

  1. IBHL should be measured after lowering VIN to GND and then raising to 1.0V on the following pins: 36-51, 66, 67.
  2. IBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins: 4-6, 36-51, 66-68.
  3. ICCSB should be tested with the clock stopped in phase two of the processor clock cycle. VIN = VCC or GND, VCC = 5.5V, outputs unloaded.
  4. ISH should be measured after raising VIN to VCC and then lowering to 0V on pins 53 and 54.

TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS

  1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY . This specification is given only for testing purposes, to assure

recognition at a specific CLK edge.

  1. Delay from 1.0V on the CLK to 2.0V.

TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS

  1. Output Load: CL = 100pF .
  2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching
  3. Delay from 1.0V on the CLK to Float (no current drive) condition.

L = -6mA (VOH to Float), IL = 8mA (VOL to Float).

  1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-

acterized upon initial design and after major process and/or design changes. TABLE 4. APPLICABLE SUBGROUPS TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)

Implied. 82C284 Timing SYMBOL PARAMETER 10MHz 12.5MHz UNIT TEST CONDITIONMIN MAX MIN MAX TIMING REQUIREMENTS

11 SRD Y/SRD YEN Setup Time 15 - 15 - ns

12 SRD Y/SRD YEN Hold Time 2 - 2 - ns

13 ARD Y/ARD YEN Setup Time 5 - 5 - ns (Note 1)

14 ARD Y/ARD YEN Hold Time 30 - 25 - ns (Note 1)

19 PCLK Delay 0 20 0 16 ns C L = 75pF, IOL = 5mA,

IOH = -1mA NOTE: 1. These times are given for testing purposes to ensure a predetermined action. 82C288 Timing SYMBOL PARAMETER 10MHz 12.5MHz UNIT TEST CONDITIONMIN MAX MIN MAX TIMING REQUIREMENTS

12 CMDLY Setup Time 15 - 15 - ns

13 CMDLY Hold Time 1 - 1 - ns

16 ALE Active Delay 1 16 1 16 ns

17 ALE Inactive Delay - 19 - 19 ns

19 DT/

R Read Active Delay - 23 - 23 ns C L = 150pF

20 DEN Read Active Delay 0 21 0 21 ns I OL = 16mA Max

21 DEN Read Inactive Delay 3 23 3 21 ns I OH = -1mA Max

22 DT/ R Read Inactive Delay 5 24 5 18 ns

23 DEN Write Active Delay - 23 - 23 ns

24 DEN Write Inactive Delay 3 23 3 23 ns

29 Command Active Delay from CLK 3 21 3 21 ns C

L = 300pF

30 Command Inactive Delay from CLK 3 20 3 20 ns I OL = 32mA Max

  1. For AC testing, input rise and fall times are driven at 1ns per volt.

FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT

  1. The modified timing is due to the CMDL Y signal being active.
  2. 82C254 and 82C288 Timing Waveforms are shown for reference only, and no guarantee is inplied.

FIGURE 2. MAJOR CYCLE TIMING

  1. PEA CK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus operation

will be either a memory read at operand address or I/O read at port address 00FA(H).

  1. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x - 12AMAX -(4)MIN

to either the first or second bus operation of the processor extension data operand transfer sequence. FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY

  1. Setup time for RESET ↑may be violated with the consideration thatφ1 of the processor clock may begin one system CLK period later.
  2. Setup and hold times for RESET↓ must be met for proper operation, but RESET↓ may occur duringφ1 orφ2.
  3. The data bus is only guaranteed to be in a high impedance state at the time shown.

FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET I/O WRITE IF MEMORY TO PROC. EXT.

16 CLK PERIODS

  1. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.

external HOLD. The float starts inφ2 of TC .

  1. BHE and LOCK may start floating after the end of any TC depending on when internal 80C286 bus arbiter decides to release bus to ex-

ternal HOLD. The float starts inφ1 of TC .

  1. The minimum HOLD to HLDA time is shown. Maximum is one TH longer.
  2. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
  3. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,

Interrupts, Waits, Lock, etc.).

  1. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state

is ignored after ready is signaled via the asynchronous input. FIGURE 8. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD

NOTES: 8. Supply Voltage: VDD = 5.5V, VSS = 0.0V. 9. Input Voltage Limits: VIL (Maximum) = 0.8V, VIH (Minimum) = 2.0V 10. Component Values: RC = 1kΩ± 5%, RI = 10kΩ± 5%, RO = Two Series 2.7kΩ± 5% 11. Capacitor Values: C1 = 0.1 Microfarads 12. Oven Type and Frequency Requirements: Wakefield Oven Board f 0 = 100kHz, f3 = 12.5kHz, f4 = 6.25kHz, f5 = 3.125kHz, f7 = 781.25Hz. 13. Special Requirements: (a) ELECTROSTATIC DISCHARGE SENSITIVE. Proper Precautions Must be Used When Handling Units. (b) All Power Supplies Must be at Zero Volts When the Boards are Inserted into the Ovens. (c) When Powering Up, the Inputs Must be Held Below the VDD Voltage. (d) If an Excessive Current is Indicated at Final Inspection, Check to See if a Part is Inserted Backwards or is Latched Up. RI RI RI RI RI RI RI RI RI RI RI RI RI RI RI RI 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 35 36 34 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 RI RI RI RI RI RI RI RI RO RO RO RO RO RO GND 5.5V RO RO RO RO RO RO RO RO RO RO RO RO RO RO RC RI F VSS VDD VDD RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO 80C286/883 PGA

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com 80C286/883 Die Characteristics DIE DIMENSIONS: 286 x 283 x 19±1mils METALLIZATION: Type: Si-Al Thickness: 8k Å GLASSIVATION: Type: Nitrox Thickness: 10k Å WORST CASE CURRENT DENSITY: 2 X 105A/cm2 LEAD TEMPERATURE: (10s Soldering):≤ 300oC Metallization Mask Layout 80C286/883 Spec Number