ICL8052_V01 INTERSIL | Alldatasheet

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. . 3% Digit A/D Pair FEATURES GENERAL DESCRIPTION @ Guaranteed zero reading for 0 volts input The 8052/7101 A/D Pair, with its parallel BCD outputs, is @ Auto-zero; auto polarity ideally suited for data processing applications or interfacing : : 5pA input current typical with 3%digit Liquid Crystal Displays. No external circuitry © Single reference voltage , ° : " | © Latched parallel (full-time) BCD output for LCDs or is required to demultiplex the information. In addition, i* data busing has a “start/reset” input and “busy” output that allows easy @ True polarity at zero count for precise null detection synchronization to system requirements. The 8052/7101 © On-board clock and reference provides 4%-digit accuracy in a 3%-digit format with typica system performance like 5pA input leakage, auto-zero tc ORDERING INFORMATION 10uV with less than 1uV/°C drift and Linearity to 0.002% [Part [ Temp. Renee | —__Packose | Order Numer] asx = s - The 8052/7101 A/D pair also feat 052] O°C to 70°C | 14 pinplastic DIP | ICL8052CPD @ 8052/7101 A/D pair also features conversion rate 8052 | 0°C to 70°C | 14 pin ceramic DIP | ICL8052CDD from 10 seconds to 30 per second, making them ideally 7101] 0°C to 70°C | 40 pin plastic DIP | 1CL7101CPL suited for a wide variety of applications. 7101 | 0°C to 70°C | 40 pin ceramic DIP | ICL7101CDL a CONNECTION DIAGRAM CONNECTION DIAGRAM

8052 Analog Signal Conditioner 7101 Digital Processor

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Power Dissipation (Note 1) 500mWw Operating Temperature O°C to +70°C Storage Temperature 65°C to +150°C Lead Temperature (Soldering, 60 Sec.) 300°C

8052 ONLY 7101 ONLY

Supply Voltage £18V Source Current (Is) 100mA Oifferential Input Voltage +6V Drain Current (1p) 100mA Input Voltage (Note 2) +15V Digital Inputs 5mA Output Short Circuit Duration, vt to V~ 25V All Outputs (Note 3) Indefinite Digital Input v- to vt Note 1: Dissipation rating assumes device is mounted with all leads Note 2: For supply voltages less than :15V, the absolute maximum welded or soldered to printed circuit board in ambient input voltage is equal to the supply voltage. temperature below +70°C. For higher temperatures, derate Note 3: Short circuit may be to ground or either supply. Rating 10mW/ C applies to +70°C ambient temperature. — e 7101 ELECTRICAL CHARACTERISTICS (v* = +5.0V, V~ = -15V, Ta = +25°C unless otherwise specified) 7 - 7101 PARAMETER SYMBOL CONDITIONS UNITS. Clock Frequency fin C = 1500 pF 20 kHz 4 External Clock In UNL 1 Vin = OV 0.35 1.0 mA External Clock In fines | Vin = +5.0V | 0.35 1.0 mA Reset/Start HNL Vin =0V 08 2.0 mA Internal Counter Override linn Vin = +5.0V | 0.35 1.0 mA External Counter Input | | BCD § Vou lo, = 1.6 mA | 0.25 04 v BCD Von lon = -200 pA 2.4 | 45 Vv Outof-Range 1 Vor lon = 3.2mA 0.25 0.4 v Out-of-Range | Von lon = 400 pA 2.4 45 v Polarity, Apex, Busy, 1000 | = Vo lo, = 0.8 mA 0.25 0.4 Polarity, Apex, Busy, 1000 | Vou lon =-200uA =| 24 | 45 v Gated Ciockout {Vor io, = 0.3mA 0.25 0.4 v Gated Clockout Vou low = —200 pA 24 45 v Switches 1, 3, 4, 5,6 Rosion) 400 2 Switch 2 Rosion) 2500 2 +5.0 V Supply Current lect 15 25 mA ~15 V Supply Current L tect 3.0 5.0 mA sv enorecTion , ° P>o—o =o | wn 1 fon \\ Yo 1 = Yoo PROTECTION External Counter Input Output Internal Counter Override Start/Reset TYPICAL INPUT/OUTPUT SCHEMATICS 4-132

8052 ELECTRICAL CHARACTERISTICS (v, = #15V. Ta = +25°C unless otherwise specified) TT 8052 CHARACTERISTICS conorrions | ig] “tye | MAX UNITS OPERATIONAL AMPLIFIER Input Offset Voltage i Vem = OV 20 50 mV Input Current (either input) Vom = OV 5 50 pA Common-Mode Rejection Ratio Vom = £10V 70 90 dB Non-Linear Component of Common-Mode Vom = #2V 110 aB Rejection Ratio* Large Signal Voltage Gain Ry = 10k2 20,000 | viv Vout = +10V | Slew Rate 6 Vius Unity Gain Bandwidth 1 MHz Output Short-Circuit Current . kL 20 50 mA COMPARATOR AMPLIFIER Smali-Signal Voltage Gain Ry = 30kQ 4000 VN Positive Output Voltage Swing +12 +13 v Negative Output Voltage Swing -2.0 -2.6 v VOLTAGE REFERENCE Output Voltage ” 15 1.75 2.0 Vv Output Resistance 5 ohm: Temperature Coefficient 50 ppm + This is the only component that causes error in dual slope converter a SYSTEM ELECTRICAL CHARACTERISTICS (Va4 =415V, Vy = +5.0V, V_ = —15V, Ta = +25°C, Clock Frequency Set for 3 Reading/Sec) CHARACTERISTICS CONDITIONS UNIT [min] tvP [Max Zero Input Reading ~ Vin = 0.0V 0.000 40.000 +0.000 Digita Readir Ratiometric Reading Vin = Vret +0.998 +1.000 +1.001 Digita | | Readir Linearity over + Full Scale (error off -2V < Vin < +2V 01 1 Digita reading from best straight line) | | Count Error Rollover error (Difference in reading for = | -Vin = Vin ¥ 2V 0.1 1 Digita equal positive & negative voltage near full | Count scale) | Error Noise (P-P value not exceeded 95% Vin = OV of time) Full scale = 200.0mV 0.2 Digita Full scale = 2.000V 0.05 Coun Leakage Current into Input Vin = OV 5 30 pA Zero Reading Drift Vin = OV 1 5 uvh 0 <T,a <70°C Scale Factor Temperature Coefficient Vin = +2V 3 15 ppm? 0 <T, <70°C __ __ (ext. ref. 0 ppm/C) (1) Tested in 2° digit (2,000 count) circuit shown in Fig. 1 clock frequency 20kHz 4-133

. thus initiating the conversion sequence. charging the reference capacitor to the positive reference integrator’s slope is determined solely by the input voltage. leakage and charge injection of the FET switches, the integral of the input for a fixed time. positive and negative references track each other to 10uV . (002% typical) ity flip-flop is set, and the integrate reference period begins. to inhibit conversion (during auto-zero). Conversion is output and resets the system. Note 2: External components shown are suggested for 3 readings/sec.

1 I fe

FIGURE 1. 3% DIGIT A/D CONVERTER FUNCTIONAL DIAGRAM

7101 Digital Processor Controls In a typical application where visual readings are required

used to signal “‘new data available”.

00 The ratio of integrating resistor and capacitor is selected 1

FIGURE 2. gave excellent results. In fact, a good test for dielectr

The circuit in Figure 4 interfaces the 8052/7101 A-to-D —_—_auto-zero is sufficient to null any offsets to 10 microvolts. Conversion is initiated by activating the WRITE 1 line Delay Device). analog input to digital form, and latch the data in the 7101. on page 7 and 8. settle before retriggering a conversion. Ten milliseconds of National MM80C95 Hex CMOS Tri State Buffers. FIGURE 4. 3% DIGIT PARALLEL BCD DATA ACQUISITION SYSTEM A possible set-up and service routine for the connection is given below.

8052/7101/6100/6101 APPLICATION PROGRAM (CONT) 1222 6545 WCRA 54 /SET-UP CONTROL REGISTER A 1223 6541 WRITE? 54 /THE WRITE PULSE STARTS CONVERSION 1224 5620 JMP | CONVERT /RETURN 1240 0040 SSCRA, * 0040 MWP 1 SETHI, 1€1 SET LO 1241 0000 SCRRB, 0000 /SL1, SP1 SET LP, NEGATIVE EDGE SENSE 1242 2000 SSVV, 2000 /VECTOR ADDRESS 1243 0041 SSCRAI, 0041 /WP1 SET HI, 1E1 SET HI 0000 0000 INTRPT, 1) /ENTRY POINT FOR INTERRUPT 0001 6002 1OF /DISABLE INTERRUPT, JUMP TO VECTOR ADDRESS. 0140 0000 AD1, 0 /FIRST WORD OF DATA 0141 0000 AD2, i) /SECOND WORD OF DATA 0160 0000 TEMP), 1) /TEMPORARY STORAGE 2000 5210 VV, JMP ATOD /JUMP TO SERVICE POINT 2010 3160 ATOD, DCA TEMP1 /SAVE AC 4 2011 6540 READ1 54 /READ BCD LINES 2012 3140 DCA AD1 /AND STORE 2013 6550 READ2 54 /READ POLARITY, 1000, AND OVERRANGE 2014 7040 CMA /COMPLEMENT TO THE TRUE 2015 3141 DCA AD2 /AND STORE / -- --- ---C /ANY OTHER WORK 2020 1160 TAD TEMP1 /RESTORE AC 2021 6001 ION /RESTORE INTERRUPT 2022 5400 JMP | INTRPT /RETURN a 4-138