79C940

79C940 ROCHESTER | Alldatasheet

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79C940© 2013 Rochester Electronics, LLC. All Rights Reserved 03112013 Specification Number 79C940B-CI (A) Rev C Page 1 of 13 FINAL Publication# 16235 Rev: E Amendment/0 Issue Date: May 2000 Am79C940 Media Access Controller for Ethernet (MACE™) DISTINCTIVE CHARACTERISTICS /uni25A0Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port /uni25A0Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards /uni25A084-pin PLCC and 100-pin PQFP Packages /uni25A080-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA /uni25A0Modular architecture allows easy tuning to specific applications /uni25A0High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer /uni25A0Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: — Automatic retransmission with no FIFO reload — Automatic receive stripping and transmit padding (individually programmable) — Automatic runt packet rejection — Automatic deletion of collision frames — Automatic retransmission with no FIFO reload /uni25A0Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs /uni25A0Direct FIFO read/write access for simple interface to DMA controllers or l/O processors /uni25A0Arbitrary byte alignment and little/big endian memory interface supported /uni25A0Internal/external loopback capabilities /uni25A0External Address Detection Interface (EADI for external hardware address filtering in bridge/router applications /uni25A0JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test /uni25A0Integrated Manchester Encoder/Decoder /uni25A0Digital Attachment Interface (DAI ) allows by-passing of differential Attachment Unit Interface (AUI) /uni25A0Supports the following types of network interface: — AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU — DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU — General Purpose Serial Interface (GPSI) to external encoding/decoding scheme — Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port /uni25A0Sleep mode allows reduced power consump- tion for critical battery powered applications /uni25A05 MHz-25 MHz system clock speed /uni25A0Support for operation in industrial temperature range (–40 °C to +85°C) available in all three packages GENERAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specif- ically designed to address applications where multiple I/O peripherals are present, and a centralized or sys- tem specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an exter- nal DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architec- ture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 1 of 13 FINAL Publication# 16235 Rev: E Amendment/0 Issue Date: May 2000 Am79C940 Media Access Controller for Ethernet (MACE™) DISTINCTIVE CHARACTERISTICS /uni25A0Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port /uni25A0Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards /uni25A084-pin PLCC and 100-pin PQFP Packages /uni25A080-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA /uni25A0Modular architecture allows easy tuning to specific applications /uni25A0High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer /uni25A0Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: — Automatic retransmission with no FIFO reload — Automatic receive stripping and transmit padding (individually programmable) — Automatic runt packet rejection — Automatic deletion of collision frames — Automatic retransmission with no FIFO reload /uni25A0Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs /uni25A0Direct FIFO read/write access for simple interface to DMA controllers or l/O processors /uni25A0Arbitrary byte alignment and little/big endian memory interface supported /uni25A0Internal/external loopback capabilities /uni25A0External Address Detection Interface (EADI for external hardware address filtering in bridge/router applications /uni25A0JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test /uni25A0Integrated Manchester Encoder/Decoder /uni25A0Digital Attachment Interface (DAI ) allows by-passing of differential Attachment Unit Interface (AUI) /uni25A0Supports the following types of network interface: — AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU — DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU — General Purpose Serial Interface (GPSI) to external encoding/decoding scheme — Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port /uni25A0Sleep mode allows reduced power consump- tion for critical battery powered applications /uni25A05 MHz-25 MHz system clock speed /uni25A0Support for operation in industrial temperature range (–40 °C to +85°C) available in all three packages GENERAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specif- ically designed to address applications where multiple I/O peripherals are present, and a centralized or sys- tem specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an exter- nal DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architec- ture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 1 of 13 Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves the right to make changes without further notice to any specification herein. For complete Rochester ordering guide, please refer to page 3 Please consult factory for specific package availability

Specification Number 79C940B-CI (A) Rev C Page 2 of 13

2 Am79C940

The MACE device provides a complete Ethernet node solution with an integrated 10BASE-T transceiver, and supports up to 25-MHz system clocks. The MACE device embodies the Media Access Control (MAC) and Physical Signaling (PLS) sub-layers of the IEEE 802.3 standard, and provides an IEEE defined Attach- ment Unit Interface (AUI) for coupling to an external Medium Attachment Unit (MAU). The MACE device is compliant with 10BASE2, 10BASE5, 10BASE-T, and 10BASE-F transceivers. Additional features also enhance over-all system design. The individual transmit and receive FIFOs optimize system overhead, providing substantial latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need for an external Serial Interface Adapter (SIA) in the node system. If support for an external encoding/decoding scheme is desired, the General Purpose Serial Interface (GPSI) allows direct access to/from the MAC. In addition, the Digital Attach- ment Interface (DAI), which is a simplified electrical attachment specification, allows implementation of MAUs that do not require DC isolation between the MAU and DTE. The DAI port can also be used to indicate transmit, receive, or collision status by connecting LEDs to the port. The MACE device also provides an External Address Detection Interface (EADI) to allow external hardware address filtering in internet working applications. The Am79C940 MACE chip is offered in a Plastic Leadless Chip Carrier (84-pin PLCC), a Plastic Quad Flat Package (100-pin PQFP), and a Thin Quad Flat Package (TQFP 80-pin). There are several small func- tional and physical differences between the 80-pin TQFP and the 84-pin PLCC and 100-pin PQFP config- urations. Because of the smaller number of pins in the TQFP configuration versus the PLCC configuration, four pins are not bonded out. Though the die is identical in all three package configurations, the removal of these four pins does cause some functionality differ- ences between the TQFP and the PLCC and PQFP configurations. Depending on the application, the removal of these pins will or will not have an effect. (See section: “Pins Removed for TQFP Package and Their Effects.) With the rise of embedded networking applications op- erating in harsh environments where temperatures may exceed the normal commercial temperature (0 to +70°C) window, an industrial temperature (-40 °C to +85°C) version is available in all three packages; 84- pin PLCC, 100-pin PQFP and 80-pin TQFP. The indus- trial temperature version of the MACE Ethernet control- ler is characterized across the industrial temperature range (-40 °C to +85 °C) within the published power Thus, conformance of MACE performance over this temperature range is guaranteed by the design and characterization monitor. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 2 of 13 The MACE device provides a complete Ethernet node solution with an integrated 10BASE-T transceiver, and supports up to 25-MHz system clocks. The MACE device embodies the Media Access Control (MAC) and Physical Signaling (PLS) sub-layers of the IEEE 802.3 standard, and provides an IEEE defined Attach- ment Unit Interface (AUI) for coupling to an external Medium Attachment Unit (MAU). The MACE device is compliant with 10BASE2, 10BASE5, 10BASE-T, and 10BASE-F transceivers. Additional features also enhance over-all system design. The individual transmit and receive FIFOs optimize system overhead, providing substantial latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need for an external Serial Interface Adapter (SIA) in the node system. If support for an external encoding/decoding scheme is desired, the General Purpose Serial Interface (GPSI) allows direct access to/from the MAC. In addition, the Digital Attach- ment Interface (DAI), which is a simplified electrical attachment specification, allows implementation of MAUs that do not require DC isolation between the MAU and DTE. The DAI port can also be used to indicate transmit, receive, or collision status by connecting LEDs to the port. The MACE device also provides an External Address Detection Interface (EADI) to allow external hardware address filtering in internet working applications. The Am79C940 MACE chip is offered in a Plastic Leadless Chip Carrier (84-pin PLCC), a Plastic Quad Flat Package (100-pin PQFP), and a Thin Quad Flat Package (TQFP 80-pin). There are several small func- tional and physical differences between the 80-pin TQFP and the 84-pin PLCC and 100-pin PQFP config- urations. Because of the smaller number of pins in the TQFP configuration versus the PLCC configuration, four pins are not bonded out. Though the die is identical in all three package configurations, the removal of these four pins does cause some functionality differ- ences between the TQFP and the PLCC and PQFP configurations. Depending on the application, the removal of these pins will or will not have an effect. (See section: “Pins Removed for TQFP Package and Their Effects.) With the rise of embedded networking applications op- erating in harsh environments where temperatures may exceed the normal commercial temperature (0 to +70°C) window, an industrial temperature (-40 °C to +85°C) version is available in all three packages; 84- pin PLCC, 100-pin PQFP and 80-pin TQFP. The indus- trial temperature version of the MACE Ethernet control- ler is characterized across the industrial temperature range (-40 °C to +85 °C) within the published power Thus, conformance of MACE performance over this temperature range is guaranteed by the design and characterization monitor. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 2 of 13 FINAL Publication# 16235 Rev: E Amendment/0 Issue Date: May 2000 Am79C940 Media Access Controller for Ethernet (MACE™) DISTINCTIVE CHARACTERISTICS /uni25A0Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port /uni25A0Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards /uni25A084-pin PLCC and 100-pin PQFP Packages /uni25A080-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA /uni25A0Modular architecture allows easy tuning to specific applications /uni25A0High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer /uni25A0Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: — Automatic retransmission with no FIFO reload — Automatic receive stripping and transmit padding (individually programmable) — Automatic runt packet rejection — Automatic deletion of collision frames — Automatic retransmission with no FIFO reload /uni25A0Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs /uni25A0Direct FIFO read/write access for simple interface to DMA controllers or l/O processors /uni25A0Arbitrary byte alignment and little/big endian memory interface supported /uni25A0Internal/external loopback capabilities /uni25A0External Address Detection Interface (EADI for external hardware address filtering in bridge/router applications /uni25A0JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test /uni25A0Integrated Manchester Encoder/Decoder /uni25A0Digital Attachment Interface (DAI ) allows by-passing of differential Attachment Unit Interface (AUI) /uni25A0Supports the following types of network interface: — AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU — DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU — General Purpose Serial Interface (GPSI) to external encoding/decoding scheme — Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port /uni25A0Sleep mode allows reduced power consump- tion for critical battery powered applications /uni25A05 MHz-25 MHz system clock speed /uni25A0Support for operation in industrial temperature range (–40 °C to +85°C) available in all three packages GENERAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specif- ically designed to address applications where multiple I/O peripherals are present, and a centralized or sys- tem specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an exter- nal DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architec- ture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 1 of 13 FINAL Publication# 16235 Rev: E Amendment/0 Issue Date: May 2000 Am79C940 Media Access Controller for Ethernet (MACE™) DISTINCTIVE CHARACTERISTICS /uni25A0Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port /uni25A0Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards /uni25A084-pin PLCC and 100-pin PQFP Packages /uni25A080-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA /uni25A0Modular architecture allows easy tuning to specific applications /uni25A0High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer /uni25A0Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: — Automatic retransmission with no FIFO reload — Automatic receive stripping and transmit padding (individually programmable) — Automatic runt packet rejection — Automatic deletion of collision frames — Automatic retransmission with no FIFO reload /uni25A0Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs /uni25A0Direct FIFO read/write access for simple interface to DMA controllers or l/O processors /uni25A0Arbitrary byte alignment and little/big endian memory interface supported /uni25A0Internal/external loopback capabilities /uni25A0External Address Detection Interface (EADI for external hardware address filtering in bridge/router applications /uni25A0JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test /uni25A0Integrated Manchester Encoder/Decoder /uni25A0Digital Attachment Interface (DAI ) allows by-passing of differential Attachment Unit Interface (AUI) /uni25A0Supports the following types of network interface: — AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU — DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU — General Purpose Serial Interface (GPSI) to external encoding/decoding scheme — Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port /uni25A0Sleep mode allows reduced power consump- tion for critical battery powered applications /uni25A05 MHz-25 MHz system clock speed /uni25A0Support for operation in industrial temperature range (–40 °C to +85°C) available in all three packages GENERAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specif- ically designed to address applications where multiple I/O peripherals are present, and a centralized or sys- tem specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an exter- nal DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architec- ture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 1 of 13 The 79C940 MACE chip is offered in a Plastic

Specification Number 79C940B-CI (A) Rev C Page 3 of 13 Rochester Part Number AMD Part Number Package Temperature Am79C940B-16JC Am79C940B-16JC LDCC-84, Plastic 0° to +70°C Am79C940B-25JC Am79C940B-25JC LDCC-84, Plastic 0° to +70°C Am79C940BJC Am79C940BJC LDCC-84, Plastic 0° to +70°C Am79C940BJI Am79C940BJI LDCC-84, Plastic -40° to +85°C Am79C940BKC Am79C940BKC TPAK-100, Plastic 0° to +70°C Am79C940BKC/W Am79C940BKC/W QFP-100, Plastic 0° to +70°C Am79C940BKI Am79C940BKI TPAK-100, Plastic -40° to +85°C Am79C940BKI/W Am79C940BKI/W QFP-100, Plastic -40° to +85°C Am79C940BVC Am79C940BVC TPAK-80, Plastic 0° to +70°C Am79C940BVC/W Am79C940BVC/W TQFP-80, Plastic 0° to +70°C Am79C940BVI Am79C940BVI TPAK-80, Plastic -40° to +85°C Am79C940BVI/W Am79C940BVI/W TQFP-80, Plastic -40° to +85°C Rochester Ordering Guide *Most products can also be offered as RoHS compliant, designated by a –G suffix. Please contact factory for more information.

Specification Number 79C940B-CI (A) Rev C Page 4 of 13 Am79C940 7 CONNECTION DIAGRAMS PL 084 PLCC PACKAGE 123 8182838467894 5 80 76 777879 75 43424140 4746454437363534 393833 48 52515049 74SRDCLK EAM/R SRD SF/BD RESET SLEEP DVDD INTR TC DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DV SS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 XTAL2 AV SS XTAL1 AV DD TXD+ TXP+ TXD- TXP- AV DD RXD+ RXD- DV DD TDI DV SS TCK TMS TDO LNKST RXPOL CS R/W RXCRS RXDAT CLSN TXEN/ TXEN STDCLK DV SS TXDAT- TXDAT+ DV SS EDSEL DXCVR DV DD AVDD CI+ CI- DI+ DI- AV DD DO+ DO- AV SS DBUS10 DBUS11 DBUS12 DBUS13 DV DD DBUS14 DBUS15 DVSS EOF DTV FDS BE0 BE1 SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4 Am79C940JC MACE 16235D-2 TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 3 of 13 79C940JC MACE

Specification Number 79C940B-CI (A) Rev C Page 5 of 13

8 Am79C940

SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 4 of 13 MACE 79C940KC

Specification Number 79C940B-CI (A) Rev C Page 6 of 13 Am79C940 9 CONNECTION DIAGRAMS PQT080 TQFP PACKAGE 80 79 78 77 76 75 74 73 72 71 70 69 68 6766 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 3435 36 37 38 39 40 SRDCLK EAM/R SF/BD RESET SLEEP DVDD INTR TC DBUS0 DVSS DBUS1 DBUS2 DBUS3 DBUS4 DVSS DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 XTAL2 AVSS XTAL1 AV DD TXD+ TXP+ TXD- TXP- AVDD RXD+ RXD- DVDD TDI DVSS TCK TMS TD0 LNKST CS R/W DBUS10 DBUS11 DBUS12 DBUS13 DV DD DBUS14 DBUS15 DV SS EOF FDS BE0 BE1 SCLK TDTREQ RDTREQ ADD0 ADD1 ADD2 ADD3 ADD4 RXCRS RXDAT CLSN TXEN/ STDCLK DVSS TXDAT+ DVSS EDSEL DXCVR DVDD AVDD CI+ CI- DI+ DI- AVDD DO+ DO- AVSS MACE Am79C940VC Notes: Four pin functions available on the PLCC and PQFP packages are not available with the TQFP package. (See full data sheet for description of pins not included with the 80-pin TQFP package. In particular, see section “Pin Functions not available with the 80-pin TQFP package.”) 16235D-4 TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 5 of 13 MACE 79C940VC

Specification Number 79C940B-CI (A) Rev C Page 7 of 1390 ABSOLUTE MAXIMUM RATINGS Supply Voltage to AVSS Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Max- imum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Industrial (I) Devices VCC Supply Voltages All inputs within the range: . . AVDD – 0.5 V ≤ Vin ≤ Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS (Unless otherwise noted, parametric values are the same between Commercial devices and Industrial devices.) Parameter Symbol Parameter Description Test Conditions Min Max Unit VIL Input LOW Voltage 0.8 V VIH Input HIGH Voltage 2.0 V VILX XTAL1 Input LOW Voltage (External Clock Signal) VSS = 0.0 V –0.5 0.8 V VIHX XTAL1 Input HIGH Voltage (External Clock Signal) V SS = 0.0 V VDD– 0.8 VDD+ 0.5 V VOL Output LOW Voltage IOL = 3.2 mA 0.45 V VOH Output HIGH Voltage IOH = -0.4 mA (Note 1) 2.4 V IIL1 Input Leakage Current VDD = 5 V, VIN = 0 V (Note 2) –10 10 µA IIL2 Input Leakage Current VDD = 5 V, VIN = 0 V (Note 2) –200 200 µA IIH Input Leakage Current VDD = 5 V, VIN = 2.7 V (Note 3) –100 µA IIAXD Input Current at DI+ and DI– –1 V < VIN < AVDD + 0.5 V –500 +500 µA IIAXC Input Current at CI+ and CI– –1 V < V IN < AVDD + 0.5 V –500 +500 µA IILXN XTAL1 Input LOW Current during normal operation V IN = 0 V SLEEP = HIGH –92 (Note 9) µA IIHXN XTAL1 Input HIGH Current during normal operation V IN = 5.5 V SLEEP = HIGH (Note 10) µA IILXS XTAL1 Input LOW Current during Sleep V IN = 0 V SLEEP = LOW <10 µA IIHXS XTAL1 Input HIGH Current during Sleep V IN = 5.5 V SLEEP = LOW 410 µA IOZ Output Leakage Current 0.4 V < V OUT < VDD (Note 4) –10 10 µA VAOD Differential Output Voltage |(DO+)–(DO–)| R L = 78 Ω 630 1200 mV VAODOFF Transmit Differential Output Idle Voltage R L = 78 Ω (Note 5) –40 +40 mV TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 7 of 13

Specification Number 79C940B-CI (A) Rev C Page 8 of 13 DC CHARACTERISTICS (Continued) Parameter Symbol Parameter Description Test Conditions Min Max Unit IAODOFF Transmit Differential Output Idle Current RL = 78 Ω –1 +1 mA VAOCM DO± Common Mode Output Voltage RL = 78 Ω 2.5 AVDD V VODI DO± Differential Output Voltage Imbalance RL = 78 Ω (Note 6) –25 25 mV VATH Receive Data Differential Input Threshold R L = 78 Ω (Note 6) –35 35 mV VASQ DI± and CI± Differential Input Threshold Squelch RL = 78 Ω (Note 6) –160 –275 mV VIRDVD DI± and CI± Differential Mode Input Voltage Range 1.5 V VICM DI± and CI± Input Bias Voltage IIN= 0 mA AVDD –3.0 AV DD –0.8 V VOPD DI± Undershoot Voltage at Zero Differential on Transmit Return to Zero (ETD) (Note 5) –100 mV IDD Power Supply Current SCLK = 25 MHz XTAL1 = 20 MHz 75 mA IDDSLEEP Power Supply Current SLEEP Asserted, AWAKE = 0 RWAKE = 1 (Note 7) 100 µA IDDSLEEP Power Supply Current SLEEP Asserted, AWAKE = 1 RWAKE = 0 (Note 7) 10 mA IDDSLEEP Power Supply Current SLEEP Asserted, AWAKE = 0 RWAKE = 1 (Note 7) 20 mA Twisted Pair Interface IIRXD Input Current at RXD± AVSS< VIN < AVDD –500 500 µA RRXD RXD± Differential Input Resistance (Note 8) 10 KΩ VTIVB RXD±, RXD– Open Circuit Input Voltage (Bias) IIN= 0 mA AVDD –3.0 AV DD –1.5 V VTIDV Differential Mode Input Voltage Range (RXD±) AVDD= +5V –3.1 +3.1 V VTSQ+ RXD Positive Squelch Threshold (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz 300 520 mV

V TSQ– RXD Negative Squelch Threshold (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz –520 –300 mV

V THS+ RXD Post-Squelch Positive Threshold (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz 150 293 mV

V THS– RXD Post-Squelch Negative Threshold) (Peak) Sinusoid

5 MHz ≤ f ≤10 MHz –293 –150 mV

V LTSQ+ RXD Positive Squelch Threshold (Peak) LRT = LOW 180 312 mV VLTSQ– RXD Negative Squelch Threshold (Peak) LRT = LOW –312 –180 mV VLTHS+ RXD Post-Squelch Positive Threshold (Peak) LRT = LOW 90 156 mV TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 8 of 13

Specification Number 79C940B-CI (A) Rev C Page 9 of 13 DC CHARACTERISTICS (Continued) Notes: 1. V OH does not apply to open-drain output pins. 2. I IL1 and IIL2 applies to all input only pins except DI±, CI±, and XTAL1. IIL1 = ADD4–0, BE1–0, CS, EAM/R, FDS, RESET, RXDAT, R/W, SCLK. IIL2 = TC, TDI, TCK, TMS. 3. Specified for input only pins with internal pull-ups: TC, TDI, TCK, TMS. 4. I OZ applies to all three-state output pins and bi-directional pins. 5. Test not implemented to data sheet specification. 6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands. 7. During the activation of SLEEP –The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR, DTV, TDTREQ, RDTREQ, NTR and TDO. –The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled: DBUS15–0, EOF, SRDCLK, RXCRS, RXDAT, CLSN, TXEN, STDCLK and TXDAT+. –The following input pin has its internal pull-up and TTL level translator disabled: TC. –The following input pins have their internal TTL level translators disabled and do not have internal pull-ups: CS, FDS, R/W, ADD4-0, SCLK, BE0, BE1 and EAM/R. –The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, TXP–, DO+ and DO. –The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI. –AWAKE and RWAKE are reset to zero. IDDSLEEP , with either AWAKE set or RWAKE set, will be much higher and its value remains to be determined. 8. Parameter not tested. 9. For industrial temperature version, Max value is –150 µA. 10. For industrial temperature version, Max value is +150 µA. Parameter Symbol Parameter Description Test Conditions Min Max Unit V LTHS– RXD Post-Squelch Negative Threshold (Peak) LRT = LOW –156 –90 mV VRXDTH RXD Switching Threshold (Note 4) –35 35 mV VTXH TXD± and TXD± Output HIGH Voltage DVSS = 0V DVDD –0.6 DV DD V VTXL TXD± and TXD± Output LOW Voltage DVDD = +5V DVSS DVSS + 0.6 V VTXI TXD± and TXD± Differential Output Voltage Imbalance –40 +40 mV VTXOFF TXD± and TXD± Idle Output Voltage DVDD = +5V 40 mV RTX TXD± Differential Driver Output Impedance (Note 8) 40 Ω TXD± Differential Driver Output Impedance (Note 8) 80 Ω TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 9 of 13

Specification Number 79C940B-CI (A) Rev C Page 10 of 1393 AC CHARACTERISTICS (Unless otherwise noted, parametric values are the same between Commercial devices and Industrial devices.) Notes: 1. The following BIU timing assumes that EDSEL = 1. Therefore, these parameters are specified with respect to the falling edge of SCLK (SCLK↓). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK ↑). 2. Tested with CL set at 100 pF and derated to support the Indicated distributed capacitive Load. See the BIU output valid delay vs. Load Chart. 3. Guaranteed by design –not tested. 4. t DATD is defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead. No. Parameter Symbol Parameter Description Test Conditions Min (ns) Max (ns) Clock and Reset Timing 1t SCLK SCLK period 40 1000 2t SCLKL SCLK LOW pulse width 0.4*tSCLK 0.6*tSCLK 3t SCLKH SCLK HIGH pulse width 0.4*tSCLK 0.6*tSCLK 4t SCLKR SCLK rise time 5 5t SCLKF SCLK fall time 5 6t RST RESET pulse width 15*tSCLK 7t BT Network Bit Time (BT)=2*tX1 or tSTDC 99 101 Internal MENDEC Clock Timing 9t X1 XTAL1 period 49.995 50.005 11 t X1H XTAL1 HIGH pulse width 20 12 t X1L XTAL1 LOW pulse width 20 13 t X1R XTAL1 rise time 5 14 t X1F XTAL1 fall time 5 BIU TIMING (Note 1) 31 t ADDS Address valid setup to SCLK↓ 9 32 t ADDH Address valid hold after SCLK↓ 2 1. 33 tSLVS CS or FDS and TC, BE1–0, R/W setup to SCLK↓ 9 34 t SLVH CS or FDS and TC, BE1–0, R/W hold after SCLK↓ 2 35 t DATD Data out valid delay from SCLK↓ CL = 100 pF (Note 2) 32 36 t DATH Data out valid hold from SCLK↓ 6 37 t DTVD DTV valid delay from SCLK↓ CL = 100 pF (Note 2) 32 38 t DTVH DTV valid hold after SCLK↓ 6 39 t EOFD EOF valid delay from SCLK↓ CL = 100 pF (Note 2) 32 40 t EOFH EOF output valid hold after SCLK↓ 6 41 t CSIS CS inactive prior to SCLK↓ 9 42 t EOFS EOF input valid setup to SCLK↓ 9 43 t EOFH EOF input valid hold after SCLK↓ 2 44 t RDTD RDTREQ valid delay from SCLK↓ CL = 100 pF (Note 2) 32 45 t RDTH RDTREQ input valid hold after SCLK↓ 6 46 t TDTD TDTREQ valid delay from SCLK↓ CL = 100 pF (Note 2) 32 47 t TDTH TDTREQ input valid hold after SCLK↓ 6 48 t DATS Data in valid setup to SCLK↓ 9 49 t DATIH Data in valid setup after SCLK↓ 2 50 t DATE Data output enable delay from SCLK↓ (Note 3) 0 51 t DATD Data output disable delay from SCLK↓ (Note 3, 4) 25 TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 10 of 13

Specification Number 79C940B-CI (A) Rev C Page 12 of 13 AC CHARACTERISTICS (continued) Note: 1. Not tested but data available upon request. No. Parameter Symbol Parameter Description Test Conditions Min (ns) Max (ns) GPSI Clock Timing 17 tSTDC STDCLK period 99 101 18 tSTDCL STDCLK low pulse width See Note 1 45 19 tSTDCH STDCLK high pulse width 45 20 tSTDCR STDCLK rise time See Note 1 5 21 tSTDCF STDCLK fall time See Note 1 5 22 tSRDC SRDCLK period 85 115 23 tSRDCH SRDCLK HIGH pulse width 38 24 tSRDCL SRDCLK LOW pulse width 38 25 tSRDCR SRDCLK rise time See Note 1 5 26 tSRDCF SRDCLK fall time See Note 1 5 GPSI Timing 70 tTXEND STDCLK↑ delay to TXEN↑ (CL = 50 pF) 70 71 tTXENH TXEN hold time from STDCLK↑ (CL = 50 pF) 5 72 tTXDD STDCLK↑ delay to TXDAT+ change (CL = 50 pF) 70 73 tTXDH TXDAT+ hold time from STDCLK↑ (CL = 50 pF) 5 74 tRXDR RXDAT rise time See Note 1 8 75 tRXDF RXDAT fall time See Note 1 8 76 tRXDH RXDAT hold time (SRDCLK↑ to RXDAT change) 25 77 tRXDS RXDAT setup time (RXDAT stable to SRDCLK↑) 0 78 t CRSL RXCRS low time tSTDC + 20 79 tCLSHI CLSN high time tSTDC + 30 80 tTXH TXEN or TXDAT± hold time from CLSN↑ 32*tSTDC 96*tSTDC 81 tCRSH RXCRS hold time from SRDCLK↑ 0 EADI Feature Timing 85 tDSFBDR SRDCLK↓ delay to SF/BD↑ 20 86 tDSFBDF SRDCLK↓ delay to SF/BD↑ 20 87 tEAMRIS EAM/R invalid setup prior to SRDCLK↓ after SFD –150 88 tEAMS EAM setup to SRDCLK↓ at bit 6 of Source Address byte 1 (match packet) 89 tEAMRL EAM/R low time 200 90 tSFBDHIH SF/BD high hold from last SRDCLK↓ 100 91 t EARS EAR setup SRDCLK↓ at bit 6 of message byte 64 (reject normal packet) TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 12 of 13

Specification Number 79C940B-CI (A) Rev C Page 13 of 13 AC CHARACTERISTICS (continued) Note: 1. Not tested but data available upon request. No. Parameter Symbol Parameter Description Test Conditions Min Max IEEE 1149.1 Timing 109 t TCLK TCK Period, 50% duty cycle (+5%) 100 110 t su1 TMS setup to TCK↑ 8 111 t su2 TDI setup to TCK↑ 5 112 t hd1 TMS hold time from TCK↑ 5 113 t hd2 TDI hold time from TCK↑ 10 114 t d1 TCK↓ delay to TDO 30 115 t d2 TCK↓ delay to SYSTEM OUTPUT 35 10BASE–T Transmit Timing Min Max 125 t TETD Transmit Start of Idle 250 350 126 t TR Transmitter Rise Time (10% to 90%) 5.5 127 t TF Transmitter Fall Time (90% to 10%) 5.5 128 t TM Transmitter Rise and Fall Time Mismatch 1 129 t XMTON XMT# Asserted Delay 100 130 t XMTOFF XMT# De-asserted Delay TBD TBD 131 t PERLP Idle Signal Period 8 24 132 t PWLP Idle Link Pulse Width (Note 1) 75 120 133 t PWPLP Predistortion Idle Link Pulse Width (Note 1) 45 55 134 t JA Transmit Jabber Activation Time 20 150 135 t JR Transmit Jabber Reset Time 250 750 136 t JREC Transmit Jabber Recovery Time (Minimum Time Gap Between Transmitted Packets to Prevent Jabber Activation) 1.0 10BASE–T Receive Timing 140 t PWNRD RXD Pulse Width Not to Turn Off Internal Carrier Sense VIN > VTHS (min) 136 – 141 t PWROFF RXD Pulse Width to Turn Off VIN> VTHS (min) 200 142 t RETD Receive Start of Idle 200 143 t RCVON RCV# Asserted Delay tRON – 50 t RON – 100 144 t RCVOFF RCV# De-asserted Delay TBD TBD TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 13 of 13 Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves the right to make changes without further notice to any specification herein.

Summary

Media Access Controller for Ethernet (MACE) 84-pin PLCC and 100-pin PQFP Packages

Description