78M6610+LMU

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Energy Measurement Processor for Load Monitoring Units For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. 19-6573; Rev 0; 1/13 GENERAL DESCRIPTION The 78M6610+LMU is an energy measurement processor (EMP) for load monitoring and control of any 2-wire single- phase or 3- wire split -phase (120/180°) AC circuit. It provides flexible sensor configuration of four analog inputs and numerous host interface options for easy integration into any system architecture. The internal 24-bit processor and field upgradeable firmware performs all the necessary signal process ing, compensation, and data formatting for accurate real -time measurement. Energy accumulation, alarm monitoring, and fault detection schemes minimize the overhead requirements of the host interface and/or network . The integrated flash memory also provides for nonvolatile storage of input configurations and calibration coefficients.

APPLICATIONS

• Building Automation Systems (Commercial, Industrial)
• Inverters and Renewable Energy Systems
• Level 1 and 2 EV Charging Systems
• G rid-Friendly Appliances and Smart Plugs

FEATURES

• Four Configurable Analog Inputs for Monitoring Any Single-Phase Circuit (2/3-Wire)
• Supports Current Transformers (CT) and Resistive Shunts
• Flexible SPI, I 2C, or UART Interface Options with Configurable I/O Pins for Alarm Signaling, Address Pins, or User Control
• Nonvolatile Storage of Calibration and Configuration Parameters
• Small 24-TQFN Package and Reduced Bill of Materials
• Internal or External Oscillator Timing References
• Quick Calibration Routines Minimize Manufacturing (System) Cost Measurement Processor RAM FLASH UART SPI I2C Digital I/O Single Converter Front End MUX ADC 78M6610+LMU Voltage Sensor(s) Current Sensor(s) Host Interface Load Relay(s)

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(All voltages with respect to ground.) Supplies and Ground Pins: V3P3D, V3P3A -0.5V to +4.6V GNDD, GNDA -0.5V to +0.5V Analog Input Pins: A0, A1, A2, A3, A4, A5 -10mA to +10mA -0.5V to (V3P3 + 0.5V) Oscillator Pins: XIN, XOUT -10mA to +10mA -0.5V to +3.0V Digital Pins: IFC0, IFC1, SSB/DIR/SCL, SDO/TX/SDAO, SDI/RX/SDAI, RESET, SPCK/ADDR0, MP10, MP0, MP4, MP6/ADDR1, MP7 -30mA to +30mA, -0.5V to (V3P3D + 0.5V) Digital Pins Configured as Inputs -10mA to +10mA, -0.5V to +6V Temperatures: Operating Junction Temperature) Peak, 100ms +140°C Continuous +125°C Storage Temperature Range -45°C to +165°C Lead Temperature (soldering, 10s) +260°C Soldering Temperature (reflow) 0°C ESD Stress on All Pins ±4kV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended External Components NAME FROM TO FUNCTION VALUE UNITS XTAL XIN XOUT 20.000MHz 20.000 MHz CXS XIN GNDD Load capacitor for crystal (exact value depends on crystal specifications and parasitic capacitance of board) 18 ±10% pF CXL XOUT GNDD 18 ±10% pF Recommended Operating Conditions PARAMETER CONDITIONS MIN TYP MAX UNITS 3.3V Supply Voltage (V3P3) Normal operation 3.0 3.3 3.6 V Operating Temperature -40 – +85 °C

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Performance Specifications Note that production tests are performed at room temperature. Input Logic Levels PARAMETER CONDITIONS MIN TYP MAX UNITS Digital High-Level Input Voltage (VIH) 2 – – V Digital Low-Level Input Voltage (VIL) – – 0.8 V Output Logic Levels PARAMETER CONDITIONS MIN TYP MAX UNITS Digital High-Level Output Voltage (VOH) ILOAD = 1mA V3P3 - 0.4 – – V ILOAD = 10mA V3P3 - 0.6 – – V Digital Low-Level Output Voltage (VOL) ILOAD = 1mA 0 – 0.4 V ILOAD = 10mA – – 0.5 V Supply Current PARAMETER CONDITIONS MIN TYP MAX UNITS V3P3D and V3P3A Current (Compounded) Normal operation, V3P3 = 3.3V – 8.1 10.3 mA Crystal Oscillator PARAMETER CONDITIONS MIN TYP MAX UNITS XIN to XOUT Capacitance (Note 1) – 3 – pF Capacitance to GNDD (Note 1) XIN – 5 – pF XOUT – 5 – Note 1: Guaranteed by design; not subject to test. Internal RC Oscillator PARAMETER CONDITIONS MIN TYP MAX UNITS Nominal Frequency – 20.000 – MHz Accuracy V3P3 = 3.0V, 3.6V; temperature = -40°C to +85°C – ±1.5 – %

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ADC Converter, V3P3 Referenced LSB values do not include the 9-bit left shift at EMP input. PARAMETER CONDITIONS MIN TYP MAX UNITS Usable Input Range (VIN - V3P3) -250 – +250 mV peak THD (First 10 Harmonics) VIN = 65Hz, 64kpts FFT, Blackman-Harris window – -85 – dB Input Impedance VIN = 65Hz 30 – 90 kΩ Temperature Coefficient of Input Impedance VIN = 65Hz (Note 1) – 1.7 – Ω/°C ADC Gain Error vs. %Power Supply Variation 3 . 3 / 3 3 100 / 357106 A P V V nVNout INPK VIN = 200mVpk, 65Hz; Input Offset (VIN - V3P3) -10 +10 mV 1 Guaranteed by design; not subject to test.

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Note 1: Guaranteed by design, not subject to test. Figure 1. SPI Timing

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Note 2: Dependent on bus capacitance. Figure 2. I2C Timing

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Figure 3. QFN Package Pinout

1 A5 Analog Input (Negative) 13 SDI/RX/

2 GNDA Ground (Analog) 14 SPCK/

3 IFC0 IFC1/SPI (1 = IFC1; 0 = SPI) 15 MP0 Multipurpose Digital I/O

4 MP7 Multipurpose Digital I/O 16 MP10 Multipurpose Digital I/O

5 MP6/ADDR1 Multipurpose Digital I/O 17 IFC1 I2C/UART (1 = I2C;0 = UART)

6 SSB/DIR/

7 MP4 Multipurpose Digital I/O 19 A0 Analog Input

10 XOUT Crystal Oscillator Driver Output 22 A2 Analog Input (Positive)

11 GNDD Ground (Digital) 23 A3 Analog Input (Negative)

12 SDO/TX/

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Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “ -” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

24 TQFN T2444+4 21-0139 90-0022

Figure 4. Package Outline

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• O scillator circuits and clock management logic
• Power-on reset, watchdog timer, and reset circuitry
• High-accuracy analog front-end (AFE) with trimmed voltage reference and temperature sensor
• 24-bit energy measurement processor (EMP) with RAM and flash memory
• Serial UART, SPI, I2C interfaces and multipurpose digital I/O IC Block Diagram The following is a block diagram of the hardware resources available on the 78M6610+LMU. XTAL OSC MUX 9XIN 10XOUT FIR VREF VBIAS GEN IBIAS GEN MUX CONTROL INFO . BLOCK FLASH 4Kx16 PROGRAM MEMORY EMP CLOCK GEN UART TEMP SENSE SPCK/ADDR0 CE DATA RAM 512x24 I2C ADC CK20M SPI RC OSC CK SEL 24 b data bus TIMERS WATCH DOG program bus IO MUX TRIM BITS 21V3P3A 2 2.5v REG . 2.5v V3P3 DIVMPY TEMP LOG . GNDA SDI/RXD/SDAi SDO/TXD/SDAo SSB/DIR/SCL IFC0 IFC1 MP10 MP0 MP7 MP4 MP6/ADDR1 1 A5 V3P3D GNDD RESET

Figure 5. Block Diagram

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available to the user in the STATUS register. self biasing and therefore an external resistor should NOT be connected across the cryst al. Figure 6. Crystal Connections external clock should be connected to the XOUT pin while the XIN pin should be connected to GNDD. the XIN pin left unconnected.

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falls below the minimum operating level. in noisy environments. The reset does not occur until RESET has been held low for at least 1µs. (EMP) begins executing from address 0. simple connection diagram is shown below. Figure 7. Reset Connections

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Analog Front-End and Conversion The Analog Front-End (AFE) includes an input multiplexer, optional pre-amplifier gain stage, Delta-Sigma A/D Converter, bias current references, voltage references, temperature sensor, and several voltage fault comparators. Analog Inputs Up to four external sensors can be connected to the 78M6610+LMU. Two single-ended inputs are available for voltage sensors and two differential pairs are available for connecting current sensors. Although the current inputs are differential inputs, a common-mode voltage of less than V3P3A ±25 mV is recommended in order to utilize the available dynamic range. The full-scale signal level that can be applied to the analog input pins is V3P3A ±250mVpk. Considering a sinusoidal AC waveform, the maximum RMS voltage applied to the inputs pins is: rmsMAX = 250𝑚𝑉𝑝𝑘 = 176.78mVrms Delta-Sigma A/D Converter A second-order Delta-Sigma converter digitizes the analog inputs. The converted data is then processed through a FIR filter. Voltage Reference The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques as well as production trims to minimize errors caused by component mismatch and drift . The voltage reference is digitally compensated over temperature. Die Temperature Measurement The device includes an on-chip die temperature sensor used for digital compensation of the voltage reference. It is also used to report temperature information to the user. 24-Bit Energy Measurement Processor (EMP) The 78M6610+LMU integrates a dedicated 24-bit signal processor that performs the entire digital signal processing necessary for energy measurement, alarm generation, calibration, compensation, etc. Refer to Section 2 for a description of functionality and operations. Flash and RAM The 78M6610+LMU includes 8KB of on-chip flash memory. The flash memory primarily contains program code, but also stores calibration data and defaults for select nonvolatile configuration registers. The device also includes 1.5KB of on-chip RAM which contains the values of input and output registers and is utilized by the processor for its operations. Multipurpose DIOs There are a total of eleven digital input/outputs (DIOs) on the 78M6610+LMU de vice. Some are dedicated to serial interface communications and configuration. Others are multipurpose I/O that can be used as a simple output under user control or routed to special purpose internal signals like alarm signaling and relay control. Communication Interface The 78M6610+LMU includes three communication interfaces: UART, SPI, and I 2C. Since the I/O pins are shared, only one mode is supported at a time. Interface configuration and address pins are sampled at power-on or reset to determine which interface will be active and to set device addresses.

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measurement data, relevant calculations, alarm monitoring, I/O control, and user configurations. automatically initialized upon power on or reset. analog input pins defined as a pair of differential current inputs. Figure 8. AFE Input Multiplexer

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High Pass Filters and Offset Removal Offset registers for each analog input contain values to be subtracted from the raw ADC outputs for the purpose of removing inherent system DC offsets from any calculated power and RMS values . These registers are signed fixed point numbers with a possible range of -1.0 to 1 - LSB. They default to 0 and can be manually changed by the user or integrated offset calibration routines. Register Description S1_OFFS Current Input S1 Offset Calibration S0_OFFS Voltage Input S0 Offset Calibration S3_OFFS Current Input S3 Offset Calibration S2_OFFS Voltage Input S2 Offset Calibration Alternatively, the user can enable an integrated High Pass Filter (HPF) to dynamically update the offset registers every accumulation interval. During each accumulation interval (or low-rate cycle) the HPF calculates the median or DC average of each input. Adjustable coefficients determine what portion of the measured offset is combined with the previous offset value. HPF_COEF_x registers contain signed fixed point numbers with a usable range of 0 to 1 - LSB (0.99999), negative values are not supported. By default, they are initialized to 0.5 (0x400000) meaning the new offset value will come from one-half of the measured offset and one-half will come from the previous offset value. Setting them to 1.0 (0x7FFFFF) causes the entire measured offset to be applied to the offset register enabling lump-sum offset removal. Setting them to zero disables any dynamic update of the offset registers by the HPF. Register Description HPF_COEF_I HPF coefficient for S1 and S3 current inputs HPF_COEF_V HPF coefficient for S0 and S2 voltage inputs To allow the DC component of the load current to be included in the measurement (i.e. half-wave rectified current waveforms), the HPF_COEF_I coefficients must be set to zero. Using the offset calibration routine will automatically set the filter coefficients to zero to disable the HPF.

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The system (sensors) and the 78M6610+LMU device inherently have gain errors that can be corrected by using the gain registers. These registers can be directly accessed and modified by an external processor or automatically updated by an integrated self calibration routine. Input gain registers are signed fixed point numbers with the binary point to the left of bit 21. They are set to 1.0 by default and have a usable range of 0 to 4 - LSB, negative values are not supported. The gain equation for each input slot can be described as Sx = Sx * Sx_GAIN. Register Description S0_GAIN Voltage Input S0 Gain Calibration. S1_GAIN Current Input S1 Gain Calibration S2_GAIN Voltage Input S2 Gain Calibration. S3_GAIN Current Input S3 Gain Calibration Die Temperature Compensation The 78M6610+LMU has an on-chip temperature sensor that can be used by the signal processor for monitoring the voltage reference error and made available to the user in the TEMPC register. Setting the Temperature Compensation (TC) bit in the Command Register allows the firmware to further adjust the system gain based on measured die temperature. Die Temperature Offset is typically calibrated by the user during the calibration stage. Die temperature gain is set to a factory default value for most applications, but can be adjusted by the user. Register Description T_OFFS Die Temperature Offset Calibration. T_GAIN Die Temperature Slope Calibration. Set by factory. Voltage Reference Gain Adjustment The on-chip precision bandgap voltage reference incorporates auto-zero techniques as well as production trims to minimize errors caused by component mismatch and drift. It can be assumed that the part is trimmed at 22°C to produce a uniform voltage reference gain at that temperature. The voltage reference is digitally compensated over changes in measured die temperature using a quadratic equation.

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Phase compensation registers are used to compensate for phase errors or time delays between the voltage input source and respective current source that are introduced by the off -chip sensor circuit. The user configurable registers are signed fixed point numbers with the binary point to the left of bit 21. Values are in units of high rate (4kHz) sample delays so each integer unit of delay is 250µs with a total possible delay of ±4 samples (roughly ±20° at 60Hz). Register Description PHASECOMP1 Phase (delay) compensation for S1 input current PHASECOMP3 Phase (delay) compensation for S3 input current Example: To compensate a phase error of 277.77µs (or 6° at 60Hz) introduced by a current transformer (CT) it is necessary to enter the following: 𝑃ℎ𝑎𝑠𝑒 𝐶𝑜𝑚𝑝𝑒𝑛𝑠𝑎𝑡𝑖𝑜𝑛 = 𝑃ℎ𝑎𝑠𝑒 𝐸𝑟𝑟𝑜𝑟 𝑆𝑎𝑚𝑝𝑙𝑒 𝑅𝑎𝑡𝑒 𝑃ℎ𝑎𝑠𝑒 𝐶𝑜𝑚𝑝𝑒𝑛𝑠𝑎𝑡𝑖𝑜𝑛 = 277𝐸−6 4000 = 1.111 The value to be entered in the phase compensation register is therefore: 𝑃𝐶𝑜𝑚𝑝 = 1.111 ∗221 = 2330169 = 0x238E39

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references and uses this information to derive the voltages VA, VB, and VC as shown below. Figure 9. Voltage Input Configuration derives source voltages VA, VB, and VC by summing S0 x M0 and S2 x M2. Figure 10. Voltage Computation subtract the input, a zero (0) value does not include the input. There are four choices for every M value as shown below. This scaling is done to prevent the output register from overflowing.

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should note that results for single ended inputs are referenced to V3P3. Figure 11. Example Voltage Configurations

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configuration register can be saved in flash memory and automatically restored at power-on or reset. Figure 12. Voltage Input Flowchart

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information to derive the load currents shown below. Figure 13. Current Input Configuration by summing S1 x M1 and S3 x M3. Figure 14. Current Computation input, a zero (0) value does not include the input. There are four choices for every M value as shown below. The output registers IA and IB are automatically scaled by a factor of 0.5 if M1 and M3 are both non zero. This scaling is done to prevent the output register from overflowing.

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Figure 15. Current Configuration Examples

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configuration register can be saved in flash memory and automatically restored at power-on or reset. Figure 16. Current Input Flowchart

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Instantaneous Voltage, Current, Power, and Quadrature measurement results are updated at the sample rate of 4kS/s and are generally not useful unless accessed with a high speed interface such as SPI . The CYCLE register is a 24-bit counter that increments every high-rate sample update and resets when low- rate results are updated. Low-rate results, updated at a user configurable rate, are typically used and more suitable for most applications. The FRAME register is a counter that increments every accumulation interval . A data ready indicator in the STATUS register indicates when new data is available. The high-rate samples are averaged to produce one low-rate result (known as an accumulation interval), increasing their accuracy and repeatability. Low-rate results include RMS voltages and currents, frequency, power, energy, and power factor. The accumulation interval can be based on a fixed number of ADC samples or locked to the incoming line voltage cycles. If Line Lock is disabled, the accumulation interval defaults to a fixed time interval defined by the number of samples defined in the SAMPLES register (default of 400 samples or 0.1 seconds). When the Line-Lock bit in the Command Register is set, and a valid AC voltage signal is present, the actual accumulation interval is stretched to the next positive zero crossing of the reference line voltage after the defined number of samples has been reached. If there is not a valid AC signal present and line lock is enabled, there is a 100 sample timeout implemented that would limit the accumulation interval to SAMPLES+100. The DIVISOR register records the actual duration (number of high-rate samples) of the last low-rate interval whether or not Line-Lock is enabled. Two bits in the CONFIG register allow the user to select the reference voltage slot for deriving zero- crossing detection and line frequency. CONFIG[23:22] 00 01 10 11 Voltage reference S0 S2 S0-S2 S0+S2 Scaling Registers Most measurement data is reported in binary full-scale units with a value range of -1.0 to 1 - LSB. All full scale register readings correspond to the max analog input of 250mVpk (or 31.25mVpk with 8x gain). As an example, if 230V-peak at the input to the voltage divider gives 250mV-peak at the chip input, one would get a full scale register reading of 1 - LSB (0x7FFFFF) for instantaneous voltage. Similarly, if 30Apk at the sensor input provides 250mV-peak to the chip input, a full scale register value of 1 - LSB (0x7FFFFF) for instantaneous current would correspond to 30 amps. Full scale watts correspond to the result of full scale current and voltage so, in this example, full scale watts is 230 x 30 or 6900 watts. Nonvolatile registers (IFSCALE and VFSCALE) are provided for storing the real-world current and voltage levels that apply to the full scale register readings for any given board design. Any host application can then format the measurement results to any data format as needed. The usage of these nonvolatile scratchpad registers is user defined and their content has no effect on the internal operations of the device. Frequency data has a range of 0 to +32768Hz less one LSB (format S15.8). Temperature data has a fixed scaling with a range of -65536°C to +65536°C less one LSB (format S16.7).Energy data scaling is described in detail in section 2.10.

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The 78M6610+LMU provides integrated calibration routines to modify gain and offset coefficients. The user can set up and initiate a calibration routine through the Command Register. When in calibration mode, the line-lock bit should be set for best results. The calibration routines will write the new coefficients to the relevant registers. The user can then save the new coefficients into flash memory as defaults using the flash access command in the Command Register. See the Command Register section for more information on using commands. Voltage and Current Gain Calibration In order to calibrate the gain parameters for voltage and current channels, a reference AC signal must be applied to the channel to be calibrated. The RMS value corresponding to the applied reference signal must be entered in the relevant target register (VTARGET, ITARGET). Considering calibration is done with low-rate RMS results, the value of the target register should never be set to a value above 70.7% of full-scale. Initially, the value of the gain is set to unity for the selected channels. RMS values are then calculated on all inputs and averaged over the number of measurement cycles set by the CALCYCS register. The new gain is calculated by dividing the appropriate Target register value by the averaged measured value. The new gain is then written to the select Gain registers unless an error occurred. On a successful calibration, the command bits are cleared in the Command Register, leaving only the system setup bits. In case of a failed calibration, the bit in the Command R egister corresponding to the failed calibration is left set. Offset Calibration To calibrate offset, all signals should be removed from all analog inputs although it is possible to do the calibration in the presence of AC signals. In the command, the user also specifies which channel(s) to calibrate. Target registers are not used for Offset calibration. During the calibration process, each input is accumulated over the entire calibration interval as specified by the CALCYCS register. The result is divided by the total number of samples and written to the appropriate offset register if selected in the calibration command. Using the Offset Calibration command will set the respective HPF coefficients to zero thereby fixing the Sx_OFFS offset registers to their calibrated values. Upon completion of calibration, only the 0xCAxxxx bits of the Command Register are cleared. Die Temperature Calibration To re-calibrate the on-chip temperature sensor offset, the user must first write the known chip temperature to the T_TARGET register. Next, the user initiates the Temperature Calibration Command in the Command Register. This will update the T_OFFS offset parameter with a new offset based on the known temperature supplied by the user. The T_GAIN gain register is set by the factory and not updated with this routine. The range of the Die Temperature registers is -128 to +128 - LSB Degrees Celsius.

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measurement is also updated every low-rate interval. range from 0Hz to 128Hz - LSB. This is a single reading per device. previous accumulation interval. Figure 17. Peak Voltage Computation and then performing a square root of the result after dividing by the number of samples in the interval . Figure 18. RMS Voltage Computation

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and Crest Factor are updated every accumulation interval (n samples). This output is a capture of the largest magnitude instantaneous current load sample. Figure 19. Peak Current Computation

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and then performing a square root of the result after dividing by the number of samples in the interval . Figure 20. RMS Current Computation will report zero current and prevent the continued accumulation of energy. recent accumulation interval. They have a range of 0 to 256.

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for AC power measurement are listed in the table below. NOTE: WATT_C, VAR_C and VA_C outputs are always scaled by a factor of 0.5. compute the average active power (WATT_A, WATT_B), and the aggregate average power (WATT_C). Figure 21. Active Power Computation active power value results in a sign change, zero watts are reported.

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Figure 22. Reactive Power Computation results. Offsets applied to RMS current will affect apparent power results. Figure 23. Apparent Power Computation accumulation interval. The sign of power factor is determined by the sign of active power.

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Fundamental and Harmonic Calculations The 78M6610+LMU includes the ability to separate low-rate voltage, current, active power, and reactive power measurement results into fundamental and total harmonic components. These outputs can also be used to track individual harmonics as well as the total value excluding the selected harmonic. Register Description Time Scale SINE COSINE Instantaneous voltage of the internal waveform generator 1 sample VFUND_A VFUND_B Voltage content at specified harmonic 1 interval IFUND_A IFUND_B Current content at specified harmonic PFUND_A PFUND_B Active Power content at specified harmonic QFUND_A QFUND_B Reactive Power content at specified harmonic VHARM_A VHARM_B Voltage content not at specified harmonic IHARM_A IHARM_B Current content not at specified harmonic PHARM_A PHARM_B Active Power content not at specified harmonic QHARM_A QHARM_B Reactive Power content not at specified harmonic The HARM register is used to select the single harmonic to extract. This input register is set by default to 0x000001 selecting the first harmonic (also known as the fundamental frequency). This setting provides the user with fundamental result and the total harmonic distortion (THD) of the harmonics By setting the value in the HARM register to a higher harmonic, the fundamental result registers will contain measurement results of the selected harmonic. Likewise, by setting the value in the HARM register to a higher harmonic, the harmonics result registers will report the measurement of the remaining harmonics. As an example, for any given accumulation interval, the magnitude of measurement result IA_RMS would be the sum of IFUND_A and IHARM_A. The SINE and COSINE registers are high-rate registers updated every sample with the instantaneous value of the respective outputs from the internal Sine/Cosine generator. The referenced AC voltage frequency serves as the reference for the internal waveform generator.

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Energy calculations are included in the 78M6610+LMU to minimize the traffic on the host interface and simplify system design. Low-rate power measurement results are multiplied by the number of samples (DIVISOR) to calculate the energy in the last accumulation interval. Energy results are summed together until a user defined “bucket size” is reached. When every bucket of energy is reached, the value in the energy counter register is incremented by one. All energy counter registers are low-rate 24-bit output registers that contain values calculated over multiple accumulation intervals. Both import (positive) and export (negative) results are provided for active and reactive energy. Register Description PA_POS_CNT PB_POS_CNT Positive Active Energy Counter PA_NEG_CNT PB_NEG_CNT Negative Active Energy Counter PQA_POS_CNT PQB_POS_CNT Positive Reactive Energy Counter PQA_NEG_CNT PQB_NEG_CNT Negative Reactive Energy Counter SA_CNT SB_CNT Apparent Energy Counter Energy results are cleared upon any power down or reset and can be manually cleared by the user using the CONTROL register. The CYCLES register can be used to detect device resets (loss of energy data) or to track time between energy reads. A bit in the STATUS register also indicates when a reset has occurred. Bucket Size for Energy Counters The BUCKET register allows the user to define the unit of measure for the energy counter registers. It is an unsigned 48-bit fixed-point number with 24 bits for the integer part and 24 bits for the fractional part. High Word Low Word Bit Position 23 22 … 2 1 0 . 23 22 21 20 … 1 0 Value 223 222 … 22 21 20 2-1 2-2 2-3 2-4 … 2-23 2-24 The units should be set large enough to keep the accumulators and counters from overflowing too quickly. To increment the energy counters in watt-hours for example, the value in BUCKET should be equal to the number of seconds in an hour (3600) multiplied by the Sample Rate (4000) and divided by Full Scale Watts (VFSCALE x IFSCALE). 𝑊𝑎𝑡𝑡ℎ𝑜𝑢𝑟𝑠 (𝑊ℎ) = 3600𝑠 ∗ 4000𝑆/𝑠 𝑉𝐹𝑆𝐶𝐴𝐿𝐸 ∗𝐼𝐹𝑆𝐶𝐴𝐿𝐸 Full Scale Watts is defined by the sensors being used (see the Scaling Registers section). As an example, if the voltage sources are 400 volts-peak at full scale (VFSCALE) and the currents are 30 amps- peak at full scale (IFSCALE), then full scale watts would be 12000 watts (VFSCALE x IFSCALE). The bucket value can be saved to flash memory as the register default.

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In this example the scaling registers are set as follows: VFSCALE = 667 (667V); IFSCALE = 50 (50A) In order to set the energy bucket to one Wh: 𝐵𝑢𝑐𝑘𝑒𝑡 = 3600 ∗4000 667 ∗50 = 431.784 The value to enter in the bucket register should be set as: 𝐵𝑢𝑐𝑘𝑒𝑡 𝑅𝑒𝑔𝑖𝑠𝑡𝑒𝑟 = 431.784 ∗224 The value to set the bucket register is therefore: High word = 0x0001AF; low word = 0xC8BB4C

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The address values in MM_ADDR# can be saved to flash memory by the user as the register defaults. Figure 24. Min/Max Tracking

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Low-rate alarm conditions are determined every accumulation interval. If results for Die Temperature, AC Frequency, or RMS Voltage exceeds or drops below user configurable thresholds, then a respective alarm bit in the STATUS register is set. For RMS Current and Watts results, maximum thresholds are provided for detecting over current or over power conditions with the load. Register Description T_MAX Threshold value which Temperature must exceed to trigger alarm. T_MIN Threshold value which Temperature must drop below to trigger alarm. F_MAX Threshold value which Frequency must exceed to trigger alarm. F_MIN Threshold value which Frequency must drop below to trigger alarm. VRMS_MAX Threshold value which RMS Voltage must exceed to trigger alarm. VRMS_MIN Threshold value which RMS Voltage must drop below to trigger alarm. IRMS_MAX Threshold value which RMS current must exceed to trigger alarm. WATT_MAX Threshold value which active power must exceed to trigger alarm. Voltage Sag and Surge Detection The 78M6610+LMU implements a voltage sag and surge detection function on both VA and VB. The sag/surge detection function can generate an alarm when the line voltage drops below or exceeds the relevant programmable thresholds. The firmware calculates on a sample-by-sample basis the trailing mean square of the input voltage based on ½ line cycle interval according to the following equation: 𝑉𝑀𝑆 = 𝑓𝑙𝑖𝑛𝑒 2 × 𝑓𝑠𝑎𝑚𝑝𝑙𝑒 × 𝑣𝑛 𝑛= −𝑖𝑛𝑡( 𝑓𝑠𝑎𝑚𝑝𝑙𝑒 2×𝑓𝑙𝑖𝑛𝑒 At each sample interval the V MS value is compared to a programmable threshold contained in the VSAG and VSURGE registers. If VMS falls below or rises above the relevant thresholds, the firmware sets the relevant bits in the Alarms register. The sample count for sag detection is automatically adjusted by the firmware to maintain coverage over half of the AC line cycle. Sag and surge detection is disabled by default and can be enabled by writing a nonzero value to the VSAG/VSURGE registers. If the VSAG/VSURGE registers are set to 0, the sag/surge feature is disabled. The sag detection can be used to monitor or record the quality of the power line or utilize the sag a pin to notify external devices (for example a host microprocessor) of a pending power -down. The external device can then enter a power-down mode (for example saving data or recording the event) before a Power outage. The following figure shows a typical sag event.

38 Rev 0

Figure 25. Voltage Sag VSAG_VAL Threshold value (in RMS) which voltage must go below to trigger a Sag alarm. VSURG_VAL Threshold value which voltage must go above to trigger alarm.

39 Rev 0

The STATUS register is used to monitor the status of the device and user configurable alarms . All other registers mentioned in this section share the same bit descriptions. The STICKY register determines which alarm/status bits are sticky and which track the current status of the condition. Each alarm bit defined as sticky will (once triggered) hold its alarm status until the user clears it using the STATUS_RESET register. Any sticky bit not set will allow the respective status bit to clear when the condition clears. The STATUS_SET and the STATUS_RESET registers allow the user to force status bits on or off respectively without fear of affecting unintended bits. A bit set in the STATUS_SET register will set the respective bit in the STATUS register and a bit set in the STATUS_RESET register will clear it. STATUS_SET and STATUS_RESET are both cleared after the status bit is set or reset . The following table lists the bit mapping for all the status related registers. Bit Name Stick-able Description

23 DRDY No New low-rate results (data) ready

22 MMUPD Yes Min/Max Update occurred

21 VA_SAG Yes Voltage A Sag Condition Detected

20 VB_SAG Yes Voltage B Sag Condition Detected

19 SIGN_VA No Sign of VA

18 SIGN_VB No Sign of VB

17 OV_TEMP Yes Temperature over High Limit

16 UN_TEMP Yes Under Low Temperature Limit

15 OV_FREQ Yes Frequency over High Limit

14 UN_FREQ Yes Under Low Frequency Limit

13 OV_VRMSA Yes RMS Voltage A Over Limit

12 UN_VRMSA Yes RMS Voltage A Under Limit

11 OV_VRMSB Yes RMS Voltage B Over Limit

10 UN_VRMSB Yes RMS Voltage B Under Limit

9 VA_SURGE Yes Voltage A Surge Condition Detected

8 VB_SURGE Yes Voltage B Surge Condition Detected

7 OV_WATT1 Yes Power 1 Over Limit

6 OV_WATT2 Yes Power 2 Over Limit

5 OV_AMP1 Yes Current 1 Over Limit

4 OV_AMP2 Yes Current 2 Over Limit

3 XSTATE No Crystal status

2 RELAY1 Always Relay 1 ON

1 RELAY2 Always Relay 2 ON

0 RESET Always Set by device after any type of reset

40 Rev 0

The DIO_STATE register contains the current status of the DIOs. The user can use this register to read the state of a DIO (if configured as an input) or control the state of the DIO (if configured as an output). The DIO_DIR register sets the direction of the pins, where “1” is input and “0” is output. If a DIO defined as an input is unconnected, internal pullups will assert the respective DIO bit in the DIO_STATE register. NOTE: Some pins are used as serial interface pins and may not be capable of user control . During reset, all DIOs are configured as inputs. DIO Bit SPI UART I2C MASK Register

0 MP0 MASK0

1 SPCK ADDR0 ADDR0 –

2 SDI RXD SDAI –

3 SDO TXD SDAO –

4 MP4 MASK4

5 SSB RS485 DIR SCL –

6 MP6 ADDR1 ADDR1 MASK6

7 MP7 MASK7

8 IFC0 –

9 IFC1 –

10 MP10 MASK10

11:23 Reserved Interface configuration pins (IFC0, IFC1) and address pins (MP6/ADDR1, SPCK/ADDR0) are input pins sampled at the end of a reset to select the serial host interface and set device addresses (for I2C and UART modes). If the IFC0 pin is low, the device will operate in the SPI mode. Otherwise, the state of IFC1 and the ADDR# pins determine the operating mode and device address. These pins MUST remain configured as an input if directly connecting to GND/V3P3. Otherwise, it is recommended to use external pullup or pulldown resistors accordingly. DIO Polarity DIOs configured as outputs are by default active LOW. The logic “0” state is ON. This can be modified using the DIO_POL register using the same bit definition as the DIO_STATE register. Any corresponding bit set in the DIO_POL register will invert the same DIO output so that it becomes active high.

41 Rev 0

MP pin to be activated (default active-low).

1. Manual control of relay status using the STATUS_SET and STATUS_RESET registers .
2. Autonomous control determined by the state of other bits in the STATUS and MASK register . For

source VA would assert the RELAY1 status bit. pipeline delay of 1 sample introduced by the timers. RYB_TON Relay turn-on delay following low-to-high transition of referenced voltage. RYB_TOFF Relay turn-off delay following high-to-low transition of referenced voltage. Figure 26. Relay Timing

42 Rev 0

The Command Register is located at address 0x00. Use this register to perform specific tasks such as saving coefficients and nonvolatile register defaults into flash memory. It also allows initiation of integrated calibration routines. Value (hex) Description 00xxxx Normal operation CAxxxx Calibration commands BDxxxx Software reset ACCxxx Flash access commands Normal Operation The general settings command allows the user to enable functions such as UART auto reporting, relay operations, and Line Lock mode etc. Bit(s) Value Description 23:16 0x00 “General settings” command used during normal operation. 5 LL Line Lock 1 = lock to line cycle; 0 = independent.

4 TC Enable Die Temperature (Gain) Compensation 1 = enable; 0 = disable (Debug

Only) Calibration Command The Calibration Command starts the calibration process for the selected inputs. It is assumed that appropriate input signals are applied. When the calibration process completes, bits 23:16 are cleared along with bits associated with channels that calibrated successfully. When calibrating gain, any channels that failed will have their corresponding bit left set. When calibrating offset, the bit corresponding to the selected channels will remain set. Bit(s) Value Description 23:16 0xCA “Calibrate” Command. 14 S2 Calibrate Voltage for Sensor 2. 13 S0 Calibrate Voltage for Sensor 0. 12 S3 Calibrate Current for Sensor 3. 11 S1 Calibrate Current for Sensor 1. 10 T Calibrate Temperature. 9 O Calibrate Offset ( = 1) or Gain ( = 0). 5 LL Lock Sample Period to Line Cycle.

4 TC Enable Die Temperature (Gain) Compensation 1 = enable; 0 = disable

(debug only) NOTE: During calibration, the “line-lock” bit should be set for best results.

43 Rev 0

Use the ACC command to save to flash the calibration coefficients and defaults for nonvolatile registers. Upon reset or power-on, the values stored in flash will become new system defaults. The following table describes the ACC command bits: Bit(s) Value Description 23:12 0xACC “Access” Command. 11:8 0x2 2: Save defaults to flash memory for NV registers. 5 1 Line Lock Bit. (debug only). Control Register A CONTROL register is provided for resetting the tracked Energy and Min/Max measurement values and for clearing energy results. Control Bit Description 23:3 Reserved for future use

2 Clear Energy Accumulators and Frame Counter

1 Clear Energy Counters

0 Reset Min/Max Tracking

The CONFIG register described throughout Section 2.1 allows the user to configure which sensor (slot) inputs are used for voltage and current measurements. This section summarizes the configuration bits available to the user. The two MSBs select the reference voltage slot for deriving zero-crossing detection and line frequency. CONFIG[23:22] 00 01 10 11 Voltage reference S0 S2 S0-S2 S0+S2 The remaining bits configure which the sensor inputs are used to derive line voltages and load currents. CONFIG Bits 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Multiplier M2 M0 M2 M0 M2 M0 M3 M1 M3 M1 Source VC VB VA IB IA There are four choices for every M value as shown below. See Section 2.1 for more information. Multiplier Bits 00 01 10 11 M (multiplier) Value -1 0 1 2

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All user registers are contained in a 256-word (24-bits each) area of the on-chip RAM and can be accessed through the UART, SPI, or I2C interfaces. These registers are byte-addressable via the UART interface and word-addressable via the SPI, and I2C interfaces. These registers consist of read (output), write (input), and read/write in the case of the Command Register. Writing to reserved registers or to unspecified memory locations could result in device malfunction or unexpected results. Data Types The input and output registers have different data types, depending on their assignment and functions . The notation used indicates whether the number is signed, unsigned, or bit-mapped and the location of the binary point. INT Indicates a 24-bit integer with a range of 0 to 16777215 typically used for counters or Boolean registers with 24 independent bit values. S Indicates a signed fixed-point value. . Indicates a fixed-point number. nn Indicates the number of bits to the right of the binary point. Example: S.21 is a 24-bit signed fixed-point number with 21 fraction bits to the right of the binary point and a range of -4.0 to 4-2-21 Bit Position 23 22 21 . 20 19 18 17 … 2 1 0 Bit Multiplier Sign bit (-22) 21 20 2-1 2-2 2-3 2-4 … 2-19 2-20 2-21 Max Value 0 1 1 1 1 1 1 1 1 1 1 Min Value 1 0 0 0 0 0 0 0 0 0 0

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Use Word addresses for I2C and SPI interfaces and Byte addresses for the SSI (UART) protocol. Nonvolatile (NV) register defaults are indicated with a ‘Y’. All other registers are initialized as described in the Functional Description. Word Addr Byte Addr Register Type NV Description 0 0 COMMAND INT Y Command Register (see Command Register section) 1 3 FWDATE INT Firmware release date in hex format (0x00YMDD) 2 6 MASK0 INT Y Status bit mask for MP0 pin 3 9 MASK4 INT Y Status bit mask for MP4 pin

4 C MASK6 INT Y Status bit mask for MP6 pin

5 F MASK7 INT Y Status bit mask for MP7 pin

6 12 MASK10 INT Y Status bit mask for MP10 pin 7 15 STICKY INT Y Status bits to hold until cleared by host 8 18 SAMPLES INT Y High-Rate Samples per Low Rate (default 400) 9 1B CALCYCS INT Y Number of Calibration Cycles to Average A 1E PHASECOMP1 S.21 Y Phase compensation (+/-4 samples) for S1 input B 21 PHASECOMP3 S.21 Y Phase compensation (+/- 4 samples) for S3 input C 24 S1_GAIN S.21 Y Input S1 Gain Calibration. Positive values only D 27 S0_GAIN S.21 Y Input S0 Gain Calibration. Positive values only E 2A S3_GAIN S.21 Y Input S3 Gain Calibration. Positive values only F 2D S2_GAIN S.21 Y Input S2 Gain Calibration. Positive values only 10 30 S1_OFFS S.23 Y Input S0 Offset Calibration 11 33 S0_OFFS S.23 Y Input S1 Offset Calibration 12 36 S3_OFFS S.23 Y Input S3 Offset Calibration 13 39 S2_OFFS S.23 Y Input S2 Offset Calibration 14 3C T_GAIN S.10 Y Temperature Slope Calibration 15 3F T_OFFS S.10 Y Temperature Offset Calibration 16 42 HPF_COEF_I S.23 Y Current Input HPF Coefficient. Positive values only 17 45 HPF_COEF_V S.23 Y Voltage Input HPF Coefficient. Positive values only 18 48 VSURG_INT INT Y Voltage Surge Detect Interval 19 4B VSAG_INT INT Y Voltage Sag Detect Interval 1A 4E STATUS INT Alarm and Device Status Bits 1B 51 STATUS_SET INT Used to Set Status bits 1C 54 STATUS_RESET INT Used to Reset Status bits 1D 57 DIO_STATE INT State of DIO pins 1E 5A CYCLE INT High-Rate Sample Counter 1F 5D FRAME INT 48 bit Low-Rate Sample Number – Low word 20 60 FRAME INT 48 bit Low-Rate Sample Number – High word 21 63 DIVISOR INT Actual samples in previous low-rate period 22 66 HARM INT Harmonic Selector, default: 1 (fundamental) 23 69 DEVADDR INT Y High order address bits for I2C and UART interfaces 24 6C CONTROL INT Control (see text) 25 6F CONFIG INT Y Input Source M (gain) selectors and more 26 72 VTARGET S.23 Y Voltage Calibration Target. Positive values only 27 75 VSURG_VAL S.23 Y Voltage Surge Threshold. Positive values only 28 78 VSAG_VAL S.23 Y Voltage Sag Threshold. Positive values only

46 Rev 0

Addr Register Type NV Description 29 7B VRMS_MIN S.23 Y Voltage lower alarm limit. Positive values only 2A 7E VRMS_MAX S.23 Y Voltage upper alarm limit. Positive values only 2B 81 VA_RMS S.23 RMS Voltage for VA source 2C 84 VB_RMS S.23 RMS Voltage for VB source 2D 87 VA_FUND S.23 Fundamental Voltage for VA source 2E 8A VB_FUND S.23 Fundamental Voltage for VB source 2F 8D VA_HARM S.23 Harmonic Voltage for VA source 30 90 VB_HARM S.23 Harmonic Voltage for VB source 31 93 VC_RMS S.23 RMS Voltage for VC source 32 96 – S.23 Reserved Output 33 99 VA S.23 Instantaneous Voltage for VA source 34 9C VB S.23 Instantaneous Voltage for VB source 35 9F VQA S.23 Instantaneous Quadrature Voltage for VA source 36 A2 VQB S.23 Instantaneous Quadrature Voltage for VB source 37 A5 VC S.23 Instantaneous Voltage for VC source 38 A8 SINE S.23 Reference Sine 39 AB COSINE S.23 Reference Cosine 3A AE VA_PEAK S.23 Peak recorded voltage 3B B1 VB_PEAK S.23 Peak recorded voltage 3C B4 ITARGET S.23 Y Current Calibration Target. Positive values only 3D B7 IRMS_MIN S.23 Y RMS Current to squelch as zero. Positive values only 3E BA IA_RMS S.23 RMS Current for IA source 3F BD IB_RMS S.23 RMS Current for IB source 40 C0 IA_FUND S.23 Fundamental Current for IA source 41 C3 IB_FUND S.23 Fundamental Current for IB source 42 C6 IA_HARM S.23 Harmonic Current for IA source 43 C9 IB_HARM S.23 Harmonic Current for IB source 44 CC IA S.23 Instantaneous Current for IA source 45 CF IB S.23 Instantaneous Current for IB source 46 D2 IA_PEAK S.23 Peak recorded voltage 47 D5 IB_PEAK S.23 Peak recorded voltage 48 D8 IRMS_MAX S.23 Y Over Current alarm limit. Positive values only 49 DB IARMS_OFFS S.23 Y RMS Current offset for IA. Positive values only 4A DE IBRMS_OFFS S.23 Y RMS Current offset for IB. Positive values only 4B E1 WATT_A S.23 Active Power for source A 4C E4 WATT_B S.23 Active Power for source B 4D E7 WATT_C S.23 Total Active Power 4E EA VA_A S.23 Volt-Amperes for source A 4F ED VA_B S.23 Volt-Amperes for source B 50 F0 VA_C S.23 Total Volt-Amperes 51 F3 VAR_A S.23 Reactive Power for source A 52 F6 VAR_B S.23 Reactive Power for source B 53 F9 VAR_C S.23 Total Reactive Power 54 FC PFUND_A S.23 Fundamental Active Power for source A 55 FF PFUND_B S.23 Fundamental Active Power for source B 56 102 PHARM_A S.23 Harmonic Active Power for source A 57 105 PHARM_B S.23 Harmonic Active Power for source B

47 Rev 0

Addr Register Type NV Description 58 108 QFUND_A S.23 Fundamental Reactive Power for source A 59 10B QFUND_B S.23 Fundamental Reactive Power for source B 5A 10E QHARM_A S.23 Harmonic Reactive Power for source A 5B 111 QHARM_B S.23 Harmonic Reactive Power for source B 5C 114 PA S.23 Instantaneous Active Power for source A 5D 117 PB S.23 Instantaneous Active Power for source B 5E 11A PQA S.23 Instantaneous Reactive Power for source A 5F 11D PQB S.23 Instantaneous Reactive Power for source B 60 120 WATT_MAX S.23 Y Power alarm limit 61 123 PA_OFFS S.23 Y Active Power Offset for PA. Positive values only 62 126 QA_OFFS S.23 Y Reactive Power Offset for PQA. Positive values only 63 129 PB_OFFS S.23 Y Active Power Offset for PB. Positive values only 64 12C QB_OFFS S.23 Y Reactive Power Offset for PQB. Positive values only 65 12F PFA S.22 Source A Power Factor 66 132 PFB S.22 Source B Power Factor 67 135 PFC S.22 Total Power Factor 68 138 – INT Reserved Input 69 13B TEMPC S.10 Chip Temperature 6A 13E T_TARGET S.10 Y Temperature Calibration Target 6B 141 T_MIN S.10 Y Temperature lower alarm limit 6C 144 T_MAX S.10 Y Temperature upper alarm limit 6D 147 FREQ S.16 Line Frequency 6E 14A F_MIN S.16 Y Line Frequency lower alarm limit 6F 14D F_MAX S.16 Y Line Frequency upper alarm limit 70 150 – INT Reserved Input 71 153 MIN1 Minimum Recorded Value 1 72 156 MIN2 Minimum Recorded Value 2 73 159 MIN3 Minimum Recorded Value 3 74 15C MIN4 Minimum Recorded Value 4 75 15F MIN5 Minimum Recorded Value 5 76 162 MIN6 Minimum Recorded Value 6 77 165 MAX1 Maximum Recorded Value 1 78 168 MAX2 Maximum Recorded Value 2 79 16B MAX3 Maximum Recorded Value 3 7A 16E MAX4 Maximum Recorded Value 4 7B 171 MAX5 Maximum Recorded Value 5 7C 174 MAX6 Maximum Recorded Value 6 7D 177 MM_ADDR1 INT Y Min/Max Monitor - Word Address 1 7E 17A MM_ADDR2 INT Y Min/Max Monitor - Word Address 2 7F 17D MM_ADDR3 INT Y Min/Max Monitor - Word Address 3 80 180 MM_ADDR4 INT Y Min/Max Monitor - Word Address 4 81 183 MM_ADDR5 INT Y Min/Max Monitor - Word Address 5 82 186 MM_ADDR6 INT Y Min/Max Monitor - Word Address 6 83 189 VFSCALE INT Y (see Scaling Registers section) 84 18C IFSCALE INT Y (see Scaling Registers section) 85 18F SCRATCH1 INT Y Extra Register for storing user info 86 192 SCRATCH2 INT Y Extra Register for storing user info

48 Rev 0

Addr Register Type NV Description 87 195 SCRATCH3 INT Y Extra Register for storing user info 88 198 SCRATCH4 INT Y Extra Register for storing user info 89 19B BUCKET INT Y Energy Bucket Size – Low word 8A 19E BUCKET INT Y Energy Bucket Size – High word 8B 1A1 IA_CREST S.16 Crest Factor for IA (positive values only) 8C 1A4 IB_CREST S.16 Crest Factor for IB (positive values only) 8D 1A7 – INT Reserved Output 8E 1AA – INT Reserved Output 8F 1AD PA_POS_CNT INT Positive Active Energy Counter 90 1B0 – INT Reserved Output 91 1B3 – INT Reserved Output 92 1B6 PA_NEG_CNT INT Negative Active Energy Counter 93 1B9 – INT Reserved Output 94 1BC – INT Reserved Output 95 1BF PB_POS_CNT INT Positive Active Energy Counter 96 1C2 – INT Reserved Output 97 1C5 – INT Reserved Output 98 1C8 PB_NEG_CNT INT Negative Active Energy Counter 99 1CB – INT Reserved Output 9A 1CE – INT Reserved Output 9B 1D1 PQA_POS_CNT INT Leading Reactive Energy Counter 9C 1D4 – INT Reserved Output 9D 1D7 – INT Reserved Output 9E 1DA PQA_NEG_CNT INT Lagging Reactive Energy Counter 9F 1DD – INT Reserved Output A0 1E0 – INT Reserved Output A1 1E3 PQB_POS_CNT INT Leading Reactive Energy Counter A2 1E6 – INT Reserved Output A3 1E9 – INT Reserved Output A4 1EC PQB_NEG_CNT INT Lagging Reactive Energy Counter A5 1EF – INT Reserved Output A6 1F2 – INT Reserved Output A7 1F5 SA_CNT INT Apparent Energy Counter A8 1F8 – INT Reserved Output A9 1FB – INT Reserved Output AA 1FE SB_CNT I24 Apparent Energy Counter AB 201 RYA_TON I24 Y Relay #1 turn-on delay AC 204 RYB_TON I24 Y Relay #2 turn-on delay AD 207 RYA_TOFF INT Y Relay #1 turn-off delay AE 20A RYB_TOFF INT Y Relay #2 turn-off delay AF 20D RYA_CNT INT Delay count for relay #1 B0 210 RYB_CNT INT Delay count for relay #2 B1 213 BAUD INT Y Baud rate for UART interface B2 216 DIO_POL INT Y Polarity of DIO pins. 1 = Active High ; 0 = Active Low B3 219 DIO_DIR INT Y Direction of DIO pins. 1 = Input ; 0 = Output

49 Rev 0

• Support for single and multipoint communications
• Transmit (direction) control for an RS-485 transceiver
• E fficient use of a low bandwidth serial interface
• Data integrity checking The default configuration is 38400 baud, 8-bit, no-parity, 1 stop-bit, no flow control. The value in the BAUD register determines the baud rate to be used. Example: To select a 9600 baud rate, the user writes a decimal 9600 to the BAUD register. The new rate will not take effect immediately. It must be saved to flash and will take effect at the next reset. The maximum BAUD value is 115200. RS-485 Support The SSB/DIR/SCL pin is used to drive an RS-485 transceiver output enable or direction pin. The implemented protocol supports a full-duplex 4-wire RS-485 bus. RS-485 BUS A B ROUT REN DEN DIN78M6610+LMU SDI/RX/SDAi SSB/DIR/SCL SDO/TX/SDAo 4.7K A B RS-485 BUS

Figure 27. RS-485 Interface

50 Rev 0

1. In multipoint systems with more than 4 targets, the user must configure device address bits in the

DEVADDR register value is restored from Flash memory and the state of the address pins are acquired. Figure 28. Device Address Configuration

51 Rev 0

send a fail code. If the condition of a received packet is uncertain, no reply is sent. host to de-select all target devices. require the use of device addressing or selecting targets. of operation is shown in the following diagram. Figure 29. SSI Protocol bytes) and a 1-byte modulo-256 checksum of all packet bytes for data integrity checking. Figure 30. Master Packet Structure The payload can contain either a single command or multiple commands if the target is already selected. received least-significant-byte first.

52 Rev 0

Master Packet Command Summary Command Parameters Description 0 - 7F (invalid) 80 - 9F (not used) A0 Clear address A1 [byte-L] Set Read/Write address bits [7:0] A2 [byte-H] Set Read/Write address bits [15:8] A3 [byte-L][byte-H] Set Read/Write address bits [15:0] A4 - AF (reserved for larger address targets) B0 - BF (not used) C0 De-select Target (target will Acknowledge) C1 - CE Select target 1 to 14 (target will Acknowledge) CF [byte] Select target 0 to 255 (target will Acknowledge) D0 [data...] Write bytes set by remainder of Byte Count D1 - DF [data...] Write 1 to 15 bytes E0 [byte] Read 0 to 255 bytes E1 – EF Read 1 to 15 bytes F0 - FF (not used) Users only need to implement commands they actually need or intend to use. For example, only one address command is required – either 0xA1 for systems with 8 address bits or less or 0xA3 for systems with 9 to 16 address bits. Likewise, only one write, read, or select target command needs to be implemented. Select Target is not needed in systems with only one target.

53 Rev 0

Register Address Pointer Selection PAYLOAD 0xA3 Command Register Address (2 Bytes) Small Read Command (3 bytes) PAYLOAD 0xE3 Command Large Read Command (30 bytes) PAYLOAD 0xE0 Command 0x1E (30 bytes) Small Write Command (3 bytes) PAYLOAD 0xD3 Command 3 Bytes of Data Large Write Command (30 bytes) Byte Count PAYLOAD 0x21 (34 bytes) 0xD0 Command 30 Bytes of Data After each read or write operation, the internal address pointer is incremented to point to the address that followed the target of the previous read or write operation.

54 Rev 0

The type of slave packet depends upon the type of command from the master device and the successful execution by the slave device. Standard replies include “Acknowledge” and “Acknowledge with Data”. ACKNOWLEDGE without data ACKNOWLEDGE with data BYTE COUNT READ DATA CHECK SUM If no data is expected from the slave or there is a fail code, a single byte reply is sent. If a successfully decoded command is expected to reply with data, the slave sends a packet format similar to the master packet where the header is replaced with a Reply Code and the payload contains the read data. Reply Code Definition 0xAA Acknowledge with data 0xAB Acknowledge with data (half duplex) 0xAD Acknowledge without data. 0xB0 Negative Acknowledge (NACK). 0xBC Command not implemented. 0xBD Checksum failed. 0xBF Buffer overflow (or packet too long). - timeout - Any condition too difficult to handle with a reply. Failure to decode a host packet will cause the selected target to send a fail code (0xB0 – 0xBF) acknowledgement depending on mode of failure. Masters wishing to simplify could accept any unimplemented fail code as a Negative Acknowledge. If no target is selected or the condition of a received packet is uncertain, no reply is sent. Timeouts can also occur when data is corrupt or no target is selected. The master should implement the appropriate timeout control logic after approximately 50 byte times at the current baud rate. When a first reply byte is received, the master should check to see if it is an SSI header or an Acknowledge. If so, the timeout timer is reset, and each subsequent receive byte will also reset the timer. If no byte is received within the timeout interval, the master can expect the slave timed out and re-send a new command.

55 Rev 0

the serial data clock and latched (captured) on the rising edge. Figure 31. SPI Interface writes) is completed. NBRACC must be set to a nonzero value prior to each multiple word transaction.

56 Rev 0

The second type of transaction is dedicated to transporting data between the host and the device and is structured as follows: Byte Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1 ADDR[5:0] R/W 0

2 DATA[23:16] @ Addr

3 DATA[15:8] @ Addr

4 DATA[7:0] @ Addr

5 DATA[23:16] @ Addr + 1

6 DATA[15:8] @ Addr +1

7 DATA[7:0] @ Addr +1

… … (NbrAcc *3) DATA[7:0] @ Addr + NbrAcc (NbrAcc*3)+1 DATA[23:16] @ Addr + NbrAcc (NbrAcc*3)+2 DATA[15:8] + NbrAcc (NbrAcc*3)+3 DATA[7:0] + NbrAcc R/W: Defines the directionality of the transaction (Read = 0; Write = 1); ADDR[5:0]: Indicates the remainder of the address to access. The following are some transaction examples. Example 1: Write access of address 0x14. Byte Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1 NbrAcc[3:0] = 0x00 Addr7

= 0 Addr6 = 0 0 1

2 Addr[5:0] = 0x14 WR = 1 0

3 Data[23:16] @ 0x14

4 Data[15:8] @ 0x14

5 Data[7:0] @ 0x14

Example 2: Read access of address 0x17 and 0x18. Byte Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1 NbrAcc[3:0] = 0x01 Addr7 = 0 Addr6 =

2 Addr[5:0] = 0x17 RD = 0 0

3 Data[23:16] @ 0x17

4 Data[15:8] @ 0x17

5 Data[7:0] @ 0x17

6 Data[23:16] @ 0x18

7 Data[15:8] @ 0x18

8 Data[7:0] @ 0x18

57 Rev 0

Example 3: Noncontiguous Read accesses of address 0x17 and 0x0A.

1 NbrAcc[3:0] = 0x00 Addr7 =

2 Addr[5:0] = 0x17 RD =

6 NbrAcc[3:0] = 0x00 Addr7 =

7 Addr[5:0] = 0x0A W = 1 0

8 Data[23:16] @ 0x0A

9 Data[15:8] @ 0x0A

10 Data[7:0] @ 0x0A

by a continuously active SCK, with eight clock periods per byte. Figure 32. SPI Timing Continuous Clock placement of those gaps is strictly for the purpose of illustrating the concept. Figure 33. SPI Timing Gapped Clock

58 Rev 0

also allows for isolated configuration B. Figure 34. I2C Interface DEVADDR register value is restored from Flash memory and the state of the address pins are acquired. DEVADDR bits 23 through 5 are not used and have no effect on the device address. Figure 35. I2C Device Address

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• A data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Bus Conditions:
• Bus Not Busy (I): Both data and clock lines are HIGH indicating an Idle Condition.
• Start Data Transfer (S): A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
• Stop Data Transfer (P): A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
• Data Valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition.
• Acknowledge (A): Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (78M6610+LMU) will leave the data line HIGH to enable the master to generate the STOP condition. 1 2 7 8 9 ACK MSB Start Bit Start or Stop Bits SCL may be held low by slave to service interrupts SCL SDA ACK

Figure 36. I2C Bus Characteristics A control byte is the first byte received following the START condition from the master device. Figure 37. I2C Device Addressing

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register address will follow after it has generated an acknowledge bit (A) during the ninth clock cycle. write cycle. The example below shows a 3-byte data write (24-bit register write). Figure 38. Write Operation Single Register multiple registers written sequentially. Figure 39. Write Operation Multiple Registers

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condition to end the transfer and the 78M6610+LMU will discontinue the transmission. Figure 40. Read Operation Figure 41. Setting Read Address Figure 42. Reading Multiple Registers

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Ordering Information

PART TEMP RANGE PIN-PACKAGE TOP MARK 78M6610+LMU/B01 -40°C to +85°C 24-TQFN EMP 78M6610+LMU/B01T -40°C to +85°C 24-TQFN EMP +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Contact Information For more information about the 78M6610+LMU or other Maxim Integrated products, go to: www.maximintegrated.com/support.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in t his data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 63 © 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

Revision History

0 1/13 Initial release —