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Document overview

  • Manufacturer or author: Intersil Corporation
  • PDF pages: 6

Technical content

Features

  • 9-bit DIP switch for conveniently setting up charging current, battery thermal status, EN input, and so on.
  • Different jumpers for input source selection, USB mode selection, and the convenience of current measurement.
  • Several exposed soldering pads connected to STATUS, FAULT, TIME, EN, V2P8, IMIN and TEMP functional pins to accommodate experimental testing that need extra connections to those pins.
  • Board size 3.5x2.5 square inches for the convenience of evaluation.
  • Eight thermal vias in the thermal pad simulating the customers’ thermal enhanced environment. Pinout ISL6292 4X4 QFN TOP VIEW PART # DESCRIPTION ISL6292EVAL2 Evaluation Board for the 4x4 QFN Package Part. VIN FAULT STATUS TIME VIN VIN VBAT VBAT 16 14 13 657 8 VBAT TEMP IMIN IREF GND TOEN EN V2P8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. AN1064Application Manual July 2003
  • ISL6292EVAL2 board
  • The ISL6292 Data Sheet
  • This ISL6292EVAL2 Application Note
  • Errata (for preliminary reference only) What Is Needed The following instruments will be needed to perform testing:
  • Power supplies: 1. PS1: DC 20V/5A, 2. PS2: DC (sinks current) 20V/5A, such as Agilent 6654A
  • Electronic load: 20V/5A
  • Multimeters
  • Function generator
  • Oscilloscope
  • Cables and wires Quick Setup Guide Step 1: Switch on bit 4 and bit 7 of the Dip-switch. Leave all other bits off, see Figure 1. DO NOT APPLY POWER UNTIL STEP 6 Step 2: Connect 5V on VIN. Step 3: Connect 3.7V on VBAT. Step 4: Connect 1.2A electronic load on VBAT. Step 5: Verify that no shunts across all jumpers. Step 6: Turn on Power Supplies and electronic load. Step 7: Green LED should be on, indicating normal charging operation. Step 8: If current meter is in series with VIN, it shall read 1A as the charging current. DIP Switch Settings A 9-bit DIP switch is provided to set up voltage, current reference, end-of-charge (EOC) current, and so on. The functionality of the bits are described in Table 1. Initial Board Jumper Positioning(Refer to Figure 3) JP1 - Selects the VIN pin to be connected to either a wall adapter, or to a USB connector. If the J1 connector is being used, a shunt must be installed across ‘WALL CUBE TO VIN’, or if the J3 (USB) connector is being used, a shunt must be installed across ‘USB TO VIN’. J1, J3 and JP1 can be ignored if the power supply is connected directly to VIN test point, which is directly connected to VIN pin of the IC. A current meter, to measure the input current, can replace the shunt mentioned above. JP2 - Can connect the VBAT pin to the battery. If the J2 connector is being used, a shunt must be installed across JP2. In this case, a current meter can also replace the shunt to measure the VBAT current. JP3 - Can connect the TEMP pin to the battery. Usually no shunt is needed for JP3, as the Eval board can simulate various battery thermal conditions. Only when a battery with a attached thermistor is applied on J2 does it become necessary to install a shunt across JP3, simultaneously turning off bits 7, 8, and 9 on the DIP switch. JP4 - Selects USB modes; a shunt across IREF and V2P8 will set USB 500mA mode, a shunt across IREF and GND will set USB 100mA mode. When the charge current is programmed by the resistors connected to IREF pin, no shunt should be installed on JP4. 1 2 3 4 5 6 7 8 9 O N O F F

FIGURE 1. INITIAL DIP SWITCH SETTINGS TABLE 1. DIP SWITCH PIN DESCRIPTIONS

1 Adjustable

3 Charger

6 IMIN setting 100mA 50mA

7 TEMP normal normal All off

8 TEMP high too hot

9 TEMP low too cold

TABLE 2. JUMPER SETTINGS

FIGURE 2. CONNECTION OF INSTRUMENTS

FIGURE 3. BOARD LAYOUT INFORMATION SCHEMATIC

ISL6292EVAL2 Evaluation Board Bill Of Materials BOM FOR ISL6292EVAL2 ITEM QUANTITY REFERENCE PART DESCRIPTION PCB FOOTPRINT PART NUMBER VENDOR

11 C 1 1 µF/10V, X5R Ceramic Cap 0603 C1608X5R1A105K TDK

21 C 2 1 0 µF/6.3V Tantalum Cap 2.05x1.3x1.2 TAJR106M006 AVX 3 1 C3 15nF/16V, X7R Ceramic Cap 0402 C1005X7R1C153K TDK 41 C 4 0 . 1 µF/16V, Y5V Ceramic Cap 0402 C1005Y5V1C104ZT TDK 5 1 C5 10nF/16V, X7R Ceramic Cap 0402 C1005X7R1C103K TDK 61 C 6 1 0 µF/16V, Tantalum Cap 3.2x1.6x1.6 TAJA106M016 AVX 7 1 D1 Green LED 0805 67-1553-1-ND DigiKey 8 1 D2 Red LED 0805 67-1552-1-ND DigiKey 9 2 R1, R2 1k, 5% 0603 Various 10 1 R3 10k, 1% 0402 Various 11 2 R4, R5 160k, 1% 0402 Various 12 1 R6 160k, 1% 0805 Various 13 1 R7 80k, 1% 0805 Various 14 1 R8 160k, 1% 0805 Various 15 1 R9 5k, 1% 0805 Various 16 1 R10 500, 1% 0805 Various 17 1 R11 18k, 1% 0805 Various 18 1 J1 2.54mm Male Header, 2ckt (R/A) A23879-ND DigiKey 19 1 J2 2.54mm Male Header, 3ckt (R/A) A23880-ND DigiKey 20 2 JP1, JP4 2.54mm Male Header, 3ckt WM6403-ND DigiKey 21 2 JP2, JP3 2.54mm Male Header, 2ckt WM6402-ND DigiKey 22 1 J3 USB Receptacle, B Type 787780-1-ND DigiKey 23 1 SW1 DIP Switch, 9 POS, SMT CKN1323-ND DigiKey 24 1 U1 Single-Cell Li-ion Battery Charger 16-pin, 3x3 QFN ISL6292 Intersil 25 6 VIN, VBAT, TIME, GND1, GND2, GND3 Test Point 5002K-ND DigiKey

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com ISL6292EVAL2 Evaluation Board PCB Layout SILK LAYER INTERNAL (LAYER 2, GND) TOP (LAYER 1, SIGNAL) INTERNAL (LAYER 3, FLOATING) BOTTOM (LAYER 4, GND)