7851

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a AD7851 FUNCTIONAL BLOCK DIAGRAM AIN (+) AIN (–) CREF1 CREF2 CAL AVDD AGND AGND DVDD DGND AMODE CLKIN SLEEP CONVST BUSY SYNCSM1 SM2 DIN DOUT SCLK POLARITY CHARGE REDISTRIBUTION DAC COMP 4.096V REFERENCE AD7851 BUF T/H SAR + ADC CONTROL CALIBRATION MEMORY AND CONTROLLER SERIAL INTERFACE/CONTROL REGISTER REFIN/ REFOUT 14-Bit 333 kSPS Serial A/D Converter

FEATURES

333 kSPS Throughput Rate/ /H115502 LSB DNL—A Grade 285 kSPS Throughput Rate/ /H115501 LSB DNL—K Grade A and K Grades Guaranteed to 125/H11543C/238 kSPS Throughput Rate Pseudo-Differential Input with Two Input Ranges System and Self-Calibration with Autocalibration on Power-Up Read/Write Capability of Calibration Data Low Power: 60 mW Typ Power-Down Mode: 5 /H9262W Typ Power Consumption Flexible Serial Interface: 8051/SPI ® /QSPI™/ /H9262P Compatible 24-Lead PDIP, SOIC, and SSOP Packages

APPLICATIONS

Speech Recognition and Synthesis Spectrum Analysis DSP Servo Control Instrumentation and Control Systems High Speed Modems Automotive GENERAL DESCRIPTION The AD7851 is a high speed, 14-bit ADC that operates from a single 5 V power supply. The ADC powers up with a set of default conditions at which time it can be operated as a read-only ADC. The ADC contains self-calibration and system calibration options to ensure accurate operation over time and temperature and has a number of power-down options for low power applications. The AD7851 is capable of a 333 kHz throughput rate. The input track-and-hold acquires a signal in 0.33 µs and features a pseudo-differential sampling scheme. The AD7851 has the added advantage of two input voltage ranges (0 V to V REF and –VREF/2 to +V REF/2 centered about V REF/2). Input signal range is to V DD and the part is capable of converting full power signals to 20 MHz. CMOS construction ensures low power dissipation (60 mW typ) with power-down mode (5 µW typ). The part is available in a 24-lead, 0.3 inch-wide PDIP, a 24-lead SOIC, and a 24-lead SSOP package. PRODUCT HIGHLIGHTS 1. Single 5 V supply. 2. Operates with reference voltages from 4 V to V DD. 3. Analog input ranges from 0 V to V DD. 4. System and self-calibration including power-down mode. 5. Versatile serial I/O port. REV. B Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7851* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. DOCUMENTATION Data Sheet

• AD7851: 14-Bit 333 kSPS Serial A/D Converter Data Sheet REFERENCE MATERIALS Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC DESIGN RESOURCES
• AD7851 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints DISCUSSIONS View all AD7851 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

–2– REV. B TABLE OF CONTENTS

–3–REV. B AD7851 A Grade: fCLKIN = 7 MHz (–40/H11543C to +85/H11543C), fSAMPLE = 333 kHz; K Grade: fCLKIN = 6 MHz (0/H11543C to 85/H11543C), fSAMPLE = 285 kHz; A and K Grade: fCLKIN = 5 MHz (to 125/H11543C), fSAMPLE = 238 kHz; (AVDD = DVDD = 5.0 V /H11550 5%, REFIN/REFOUT = 4.096 V External Reference; SLEEP = Logic High; TA = TMIN to TMAX, unless otherwise noted.) Parameter Version A 1 Version K1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE Signal-to-Noise + Distortion Ratio3 (SNR) 77 78 dB min Typically SNR Is 79.5 dB. VIN = 10 kHz, Sine Wave, f SAMPLE = 333 kHz. Total Harmonic Distortion (THD) –86 –86 dB max V IN = 10 kHz, Sine Wave, f SAMPLE = 333 kHz, typically –96 dB. Peak Harmonic or Spurious Noise –87 –87 dB max V IN = 10 kHz, fSAMPLE = 333 kHz. Intermodulation Distortion (IMD) Second-Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 333 kHz. Third-Order Terms –86 –90 dB typ fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 333 kHz. Full Power Bandwidth 20 20 MHz typ @ 3 dB. DC ACCURACY Resolution 14 14 Bits Integral Nonlinearity ± 2 ± 1 LSB max Differential Nonlinearity ± 2 ± 1 LSB max Guaranteed No Missed Codes to 14 Bits Unipolar Offset Error ± 10 ± 10 LSB max Review: Adjusting the Offset Calibration Positive Full-Scale Error ± 10 ± 10 LSB max Register in the Calibration Registers section. Negative Full-Scale Error ± 10 ± 10 LSB typ Bipolar Zero Error ± 1 ± 1 LSB typ ANALOG INPUT Input Voltage Ranges 0 V to V REF 0 V to VREF V AIN(+) – AIN(–) = 0 V to VREF, AIN(–) can be biased up but AIN(+) cannot go below AIN(–). ± VREF/2 ± VREF/2 V AIN(+) – AIN(–) = –VREF/2 to +VREF/2, AIN(–) should be biased up and AIN(+) can go below AIN(–) but cannot go below 0 V. Leakage Current ± 1 ± 1 µA max Input Capacitance 20 20 pF typ REFERENCE INPUT/OUTPUT REFIN Input Voltage Range 4/V DD 4/VDD V min/max Functional from 1.2 V. Input Impedance 150 150 k Ω typ Resistor Connected to Internal Reference Node. REFOUT Output Voltage 3.696/4.496 3.696/4.496 V min/max REFOUT Temperature Coefficient 50 50 ppm/°C typ LOGIC INPUTS Input High Voltage, V INH VDD – 1.0 V DD – 1.0 V min Input Low Voltage, V INL 0.4 0.4 V max Input Current, I IN ± 10 ± 10 µA max V IN = 0 V or VDD. Input Capacitance, C IN 4 10 10 pF max LOGIC OUTPUTS Output High Voltage, V OH VDD – 0.4 V DD – 0.4 V min I SOURCE = 200 µA. Output Low Voltage, V OL 0.4 0.4 V max I SINK = 0.8 mA. Floating State Leakage Current ± 10 ± 10 µA max Floating State Output Capacitance 4 10 10 pF max Output Coding Straight (Natural) Binary Unipolar Input Range. Twos Complement Bipolar Input Range. CONVERSION RATE Conversion Time 2.78 3.25 µs max 19.5 CLKIN Cycles. Conversion + Track-and-Hold Acquisition Time 3.0 3.5 µs max 21 CLKIN Cycles Throughput Rate. SPECIFICATIONS1, 2

–4– REV. B Parameter Version A 1 Version K1 Unit Test Conditions/Comments POWER PERFORMANCE AVDD, DVDD 4.75/5.25 4.75/5.25 V min/max IDD Normal Mode4 17 17 mA max AV DD = DVDD = 4.75 V to 5.25 V. Typically 12 mA. Sleep Mode5 With External Clock On 20 20 µA typ Full Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 600 600 µA typ Partial Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. With External Clock Off 10 10 µA max Typically 1 µA. Full Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 0. 300 300 µA typ Partial Power-Down. Power management bits in control register set as PMGT1 = 1, PMGT0 = 1. Normal Mode Power Dissipation 89.25 89.25 mW max V DD = 5.25 V: Typically 63 mW; SLEEP = VDD. Sleep Mode Power Dissipation With External Clock On 105 105 µW typ V DD = 5.25 V; SLEEP = 0 V. SYSTEM CALIBRATION Offset Calibration Span 6 +0.05 × VREF/–0.05 × VREF V max/min Allowable Offset Voltage Span for Calibration. Gain Calibration Span 6 +1.025 × VREF/–0.975 × VREF V max/min Allowable Full-Scale Voltage Span for Calibratio n. NOTES 1Temperature ranges as follows: A Version, –40 °C to +125 °C; K Version, 0 °C to 125°C. 2Specifications apply after calibration. 3SNR calculation includes distortion and noise components. 4All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DVDD. No load on the digital outputs. Analog inputs at AGND. 5CLKIN at DGND when external clock off. All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DVDD. No load on the digital outputs. Analog inputs at AGND. 6The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note al so that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × VREF, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted ou t will be V REF ± 0.025 × VREF). This is explained in more detail in the Calibration section of the data sheet. Specifications subject to change without notice.

–5–REV. B AD7851 Descriptions that refer to SCLK ↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin LOW, then the opposite edge of SCLK will apply. Limit at TMIN, TMAX Parameter (A, K Versions) Unit Description fCLKIN 2 500 kHz min Master Clock Frequency

7 MHz max

3 10 MHz max Interface Modes 1, 2, 3 (External Serial Clock) fCLK IN MHz max Interface Modes 4, 5 (Internal Serial Clock) 4 100 ns min CONVST Pulse Width t2 50 ns max CONVST↓ to BUSY↑ Propagation Delay tCONVERT 3.25 µs max Conversion Time = 20 t CLKIN t3 –0.4 tSCLK ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input) ±0.4 tSCLK ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input) t4 0.6 tSCLK ns min SYNC↓ to SCLK↓ Setup Time, Interface Mode 4 Only 5 30 ns max Delay from SYNC↓ until DOUT Three-State Disabled t5A 5 30 ns max Delay from SYNC↓ until DIN Three-State Disabled 5 45 ns max Data Access Time after SCLK ↓ t7 30 ns min Data Setup Time prior to SCLK ↑ t8 20 ns min Data Valid to SCLK Hold Time 6 0.4 tSCLK ns min SCLK High Pulse Width (Interface Modes 4 and 5) t10 6 0.4 tSCLK ns min SCLK Low Pulse Width (Interface Modes 4 and 5) t11 30 ns min SCLK ↑ to SYNC↑ Hold Time (Noncontinuous SCLK) 30/0.4 tSCLK ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3 t11A 50 ns max SCLK ↑ to SYNC↑ Hold Time t12 7 50 ns max Delay from SYNC↑ until DOUT Three-State Enabled t13 90 ns max Delay from SCLK ↑ to DIN Being Configured as Output t14 8 50 ns max Delay from SCLK ↑ to DIN Being Configured as Input t15 2.5 tCLKIN ns max CAL↑ to BUSY↑ Delay t16 2.5 tCLKIN ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence tCAL 9 41.7 ms typ Full Self-Calibration Time, Master Clock Dependent (250026 tCLKIN) tCAL1 9 37.04 ms typ Internal DAC Plus System Full-Scale Calibration Time, Master Clock Dependent (222228 tCLKIN) tCAL2 9 4.63 ms typ System Offset Calibration Time, Master Clock Dependent (27798 tCLKIN) tDELAY 65 ns max Delay from CLK to SCLK NOTES 1Sample tested at 25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See Table X and timing diagrams for different interface modes and calibration. 2Mark/space ratio for the master clock input is 40/60 to 60/40. 3For Interface Modes 1, 2, 3, the SCLK maximum frequency will be 10 MHz. For Interface Modes 4 and 5, the SCLK will be an output and the frequency will be f CLKIN. 4The CONVST pulse width will only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power- Down section). 5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 6For self-clocking mode (Interface Modes 4, 5), the nominal SCLK high and low times will be 0.5 t SCLK = 0.5 tCLKIN. 7The time t 12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that t 12 as quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 8 The time t 14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the u ser can drive the DIN line knowing that a bus conflict will not occur. 9The typical time specified for the calibration times is for a master clock of 6 MHz. Specifications subject to change without notice. TIMING SPECIFICATIONS1 (AVDD = DVDD = 5.0 V /H11550 5%; fCLKIN = 6 MHz, TA = TMIN to TMAX, unless otherwise noted.)

–7–REV. B AD7851 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C, unless otherwise noted.) Operating Temperature Range θJA Thermal Impedance . . 75°C/W (SOIC), 122.28°C/W (SSOP) θJC Thermal Impedance . . . 25°C/W (SOIC), 31.25°C/W (SSOP) PINOUT FOR DIP, SOIC, AND SSOP AD7851 TOP VIEW (Not to Scale) CONVST BUSY SLEEP REFIN/REFOUT AVDD AGND CREF1 CREF2 AIN(+) AIN(–) NC AGND SYNC SCLK CLKIN DIN DOUT DGND DV DD CAL SM2 SM1 POLARITY AMODE NC = NO CONNECT ORDERING GUIDE 1 Linearity Temperature Error Throughput Throughput Package Model Range (LSB) 2 Rate (kSPS) at 125 /H11543C (kSPS) Description Options 3 AD7851AN –40 °C to +85°C ± 2 333 238 PDIP N-24 AD7851KN 0 °C to 85°C ± 1 285 238 PDIP N-24 AD7851AR –40 °C to +85°C ± 2 333 238 SOIC R-24 AD7851AR-REEL –40 °C to +85°C ± 2 333 238 SOIC R-24 AD7851ARZ3 –40°C to +85°C ± 2 333 238 SOIC R-24 AD7851ARZ-REEL3 –40°C to +85°C ± 2 333 238 SOIC R-24 AD7851KR 0 °C to 85°C ± 1 285 238 SOIC R-24 AD7851KR-REEL 0 °C to 85°C ± 1 285 238 SOIC R-24 AD7851KRZ3 0°C to 85°C ± 1 285 238 SOIC R-24 AD7851KRZ-REEL3 0°C to 85°C ± 1 285 238 SOIC R-24 AD7851ARS –40 °C to +85°C ± 2 333 238 SSOP RS-24 AD7851ARS-REEL –40 °C to +85°C ± 2 333 238 SSOP RS-24 EVAL-AD7851CB4 Evaluation Board EVAL-CONTROL BRD25 Controller Board NOTES 1Both A and K Grades are guaranteed up to 125 °C, but at a lower throughput of 238 kHz (5 MHz). 2Linearity error refers to the integral linearity error. 3Z = Pb-free part. 4This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration pu rposes. 5This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending i n the CB designators. To order a complete evaluation kit, the particular ADC evaluation board needs to be ordered, e.g., EVAL-AD7851CB, the EVAL-CONTROL BRD2, a nd a 12 V ac trans- former. See the Evaluation Board application note for more information. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7851 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Lead Temperature, Soldering NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Transient currents of up to 100 mA will not cause SCR latch-up.

–8– REV. B TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end- points of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Unadjusted Error This is the deviation of the actual code from the ideal code tak- ing all errors into account (gain, offset, integral nonlinearity, and other errors) at any point along the transfer function. Unipolar Offset Error This is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB) when operating in unipolar mode. Positive Full-Scale Error This applies to unipolar and bipolar modes and is the deviation of the last code transition from the ideal AIN(+) voltage (AIN(–) + full scale – 1.5 LSB) after the offset error has been adjusted out. Negative Full-Scale Error This applies to bipolar mode only and is the deviation of the AIN(+) voltage (AIN(–) – VREF/2 + 0.5 LSB). Bipolar Zero Error This is the deviation of the midscale transition (all 1s to all 0s) from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB). Track-and-Hold Acquisition Time The track-and-hold amplifier returns into track mode at the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ± 1/2 LSB, after the end of conversion. Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitiza- tion process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = ( 6.02 N +1.76)d B Thus, for a 14-bit converter, this is 86 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7851, it is defined as THD VVVVV V(d ) 20logB = ++++() 2 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa – fb), while the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). Testing is performed using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Power Supply Rejection Ratio (PSRR) PSRR is defined as the ratio of the power in ADC output at fre- quency f to the power of the full-scale sine wave applied to the supply voltage (VDD). The units are in LSB, % of FS per % of supply voltage, or expressed logarithmically, in dB (PSRR (dB) = 10 log (Pf/Pfs)). Full Power Bandwidth (FPBW) FPBW is that frequency at which the amplitude of the recon- structed fundamental (using FFTs and neglecting harmonics and SNR) is reduced by 3 dB for a full-scale input.

–9–REV. B AD7851 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 CONVST Convert Start. Logic input. A low-to-high transition on this input puts the track-and-hold into its hold mode and starts conversion. When this input is not used, it should be tied to DV DD. 2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL and remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed its on-chip calibration sequence. 3 SLEEP Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down, including the internal voltage reference, provided there is no conversion or calibration being performed. Calibration data is retained. A Logic 1 results in normal operation. See Power-Down section for more details.

4 REF

IN/R eference Input/Output. This pin is connected to the internal reference through a series resistor and is the REFOUT reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this appears at the pin. This pin can be overdriven by an external reference or can be taken as high as AVDD. When this pin is tied to AVDD, or when an externally applied reference approaches V DD, then the CREF1 pin should also be tied to AVDD. 5A V DD Analog Positive Supply Voltage, 5.0 V ± 5%. 6, 12 AGND Analog Ground. Ground reference for track and hold, reference, and DAC. REF1 Reference Capacitor (0.1 µF ceramic disc in parallel with a 470 nF tantalum). This external capacitor is used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND. 8C REF2 Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip reference. The capacitor should be tied between the pin and AGND. 9 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above AVDD at any time and cannot go below AIN(–) when the unipolar input range is selected. 10 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above AVDD at any time. 11 NC No Connect Pin. 13 AMODE Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range 0 to V REF (i.e., AIN(+) – AIN(–) = 0 to V REF). In this case, AIN(+) cannot go below AIN(–) and AIN(–) cannot go below AGND. A Logic 1 selects range –V REF/2 to +VREF/2 (i.e., AIN(+) – AIN(–) = –V REF /2 to +VREF/2). In this case, AIN(+) cannot go below AGND so that AIN(–) needs to be biased to +V REF/2 to allow AIN(+) to go from 0 V to +V REF V. 14 POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and Table IX for the SCLK active edges. 15 SM1 Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera- tion as described in Table X. 16 SM2 Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera- tion as described in Table X. 17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input overrides all other internal operations. If the autocalibration is not required, then this pin should be tied to a logic high. 18 DV DD Digital Supply Voltage, 5.0 V ± 5%. 19 DGND Digital Ground. Ground reference point for digital circuitry. 20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word. 21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act as an input pin or as a input and output pin depending on the serial interface mode the part is in (see Table X). 22 CLKIN Master Clock Signal for the Device (6 MHz or 7 MHz). Sets the conversion and calibration times. 23 SCLK Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin. 24 SYNC This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X ).

–11–REV. B AD7851 CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write-only register and contains 14 bits of d ata. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are describ ed below. The power-up status of all bits is 0. MSB ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1 RDSLT0 2/3 MODE CONVST CALMD CALSLT1 CALSLT0 STCAL LSB Control Register Bit Function Descriptions Bit No. Mnemonic Comment 13 ZERO These four bits must be set to 0 when writing to the control register.

12 ZERO

11 ZERO

10 ZERO

9P MGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various 8P MGT0 power-down modes (see Power-Down section for more details). 7 RDSLT1 Theses two bits determine which register is addressed for the read operations. See Table II.

6 RDSLT0

52 / 3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1, Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every write cycle. 4 CONVST Conversion Start Bit. A Logic 1 in this bit position starts a single conversion, and this bit is automati- cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration (see Calibration section). 3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III). 2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions: 1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per- 0 STCAL formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration. With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on Calibration Registers for more details). Table III. Calibration Selection CALMD CALSLT1 CALSLT0 Calibration Type 00 0 A full internal calibration is initiated where the internal DAC is calibrated followed by the internal gain error, and finally the internal offset error is calibrated out. This is the default setting. 00 1 Here the internal gain error is calibrated out followed by the internal offset error calibrated out. 01 0T his calibrates out the internal offset error only. 01 1T his calibrates out the internal gain error only. 10 0 A full system calibration is initiated here where first the internal DAC is calibrated, fol- lowed by the system gain error, and finally the system offset error is calibrated out. 10 1H ere the system gain error is calibrated out followed by the system offset error. 11 0T his calibrates out the system offset error only. 11 1T his calibrates out the system gain error only.

bits in the status register is described below. The power-up status of all bits is 0. Figure 6. Flowchart for Reading the Status Register 15 ZERO This bit is always 0. in progress. When this bit is 0, there is no conversion or calibration in progress. 13 ZERO These four bits are always 0. Interface Mode 1. This bit is reset to 0 after every read cycle. calibration is selected (see Table III).

Figure 9. Flowchart for Reading from the ter compensates for the positive offset on the analog input signal. on down to the LSB which has a weighting of 0.0006%.

1. In binary terms this is 0101 0001 1111, therefore

decrease the offset register by 0101 0001 1111. offset voltage to the analog input pins to do a system calibration. The offset compensation can take place in software. 0.975 times the reference voltage.

sive approximation converter based around a capacitor DAC. the part is buffered on-chip. able space-saving advantages over alternative solutions.

2 LEADING ZEROS

Figure 10. Typical Circuit Figure 10 shows a typical connection diagram for the AD7851.

Figure 16. AD7851 Unipolar Transfer Characteristic output transfer characteristic is shown in Figure 17. Figure 17. AD7851 Bipolar Transfer Characteristic the unipolar and bipolar ranges.

0 V to VREF

1 VIN AGND Figure 8 DGND

1Output code format is straight binary. 2Range is ± VREF/2 biased about VREF/2. Output code format is twos complement. Figure 14. 0 V to V REF Unipolar Input Configuration Figure 15. ±VREF/2 about VREF/2 Bipolar Input Configuration

Figure 22. PSRR vs. Frequency used to achieve the desired effect.

01 X Full power-down between

10 X Full power-down (SW)

11 X Partial power-down between

SW = Software selection, HW = Hardware selection. Figure 23. Typical Low Power Circuit

0.1 POWER (mW)

Figure 26. Power vs. Throughput AD7851 initiate power-down and power-up commands. ter clock. These calibration times are master-clock dependent. nal offset errors and the internal gain errors, respectively. the offset and gain calibrations.

–24– REV. B SERIAL INTERFACE SUMMARY Table IX details the five interface modes and the serial clock edges from which the data is clocked out by the AD7851 (DOUT edge) and that the data is latched in on (DIN edge). The logic level of the POLARITY pin is shown and it is clear that this reverses the edges. In Interface Modes 4 and 5 the SYNC always clocks out the first data bit and SCLK will clock out the subsequent bits. In Interface Modes 1, 2, and 3 the SYNC is gated with the SCLK and the POLARITY pin. Thus, the SYNC may clock out the MSB of data. Subsequent bits will be clocked out by the serial clock, SCLK. The conditions for the SYNC clocking out the MSB of data is as follows. With the POLARITY pin high, the falling edge of SYNC will clock out the MSB if the serial clock is low when the SYNC goes low. With the POLARITY pin low, the falling edge of SYNC will clock out the MSB if the serial clock is high when the SYNC goes low. Table IX. SCLK Active Edge for Different Interface Modes Interface POLARITY DOUT DIN Mode Pin Edge Edge 1, 2, 3 0 SCLK ↑ SCLK ↓ 1S CLK ↓ SCLK ↑ 4, 5 0 SCLK ↓ SCLK ↑ 1S CLK ↑ SCLK ↓ Resetting the Serial Interface When writing to the part via the DIN line there is the possibility of writing data into the incorrect registers, such as the test regis- ter for instance, or writing the incorrect data and corrupting the serial interface. The SYNC pin acts as a reset. Bringing the SYNC pin high resets the internal shift register. The first data bit after the next SYNC falling edge will now be the first bit of a new 16-bit transfer. It is also possible that the test register contents were altered when the interface was lost. Therefore, once the serial interface is reset, it may be necessary to write the 16-bit word 0100 0000 0000 0010 to restore the test regis- ter to its default value. Now the part and serial interface are completely reset. It is always useful to retain the ability to pro- gram the SYNC line from a port of the µController/DSP to have the ability to reset the serial interface. Table X summarizes the interface modes provided by the AD7851. It also outlines the various µP/µC to which the par- ticular interface is suited. The interface mode is determined by the serial mode selection Pins SM1 and SM2. Interface Mode 2 is the default mode. Note that Interface Mode 1 and 2 have the same combination of SM1 and SM2. Interface Mode 1 may only be set by program- ming the control register (see the Control Register section). External SCLK and SYNC signals (SYNC may be hardwired low) are required for Interfaces Modes 1, 2, and 3. In Interface Modes 4 and 5, the AD7851 generates the SCLK and SYNC. Some of the more popular µProcessors, µControllers, and the DSP machines that the AD7851 will interface to directly are mentioned here. This does not cover all µCs, µPs, and DSPs. The interface mode of the AD7851 that is mentioned here for a specific µC, µP, or DSP is only a guide and in most cases another interface mode may work just as well. A more detailed timing description on each of the interface modes follows. Table X. Interface Mode Description SM1 SM2 /H9262Processor Interface Pin Pin /H9262Controller Mode 00 8XC51 1 (2-Wire) 8XL51 DIN Is an Input/ PIC17C42 Output Pin 00 68HC11 2 (3-Wire, SPI/QSPI) 68L11 Default Mode 01 68HC16 3 (QSPI) PIC16C64 External Serial ADSP-21xx Clock, SCLK, and DSP56000 External Frame Sync, DSP56001 SYNC Are Required DSP56002 DSP56L002 TMS320C30 10 68HC16 4 (DSP Is Slave) AD7851 Generates a Noncontinuous (16 Clocks) Serial Clock, SCLK, and the Frame Sync, SYNC

11 ADSP-21xx 5 (DSP Is Slave)

DSP56000 AD7851 Generates a DSP56001 Continuous Serial DSP56002 Clock, SCLK, and the DSP56L002 Frame Sync, SYNC TMS320C20 TMS320C25 TMS320C30 TMS320C5X TMS320LC5X

CONVST pin, the user may become locked out. Figure 40. Flowchart for Setting Up and Reading from the AD7851 AD7851 has powered up (6 MHz CLK).

Figure 45. 8XC51/PIC17C42 Interface sion and there will be no need for the BUSY signal in this case. pin should be tied high and the SS line tied to the SYNC pin. and hold times of the µControllers and the AD7851. Figure 46. 68HC11 and 68HC16 Interface tied low when using the 2-wire interface mode of operation.

7 MHz /6MHz

Figure 44. Simplified Interface Diagram with DIN which only runs at 5 V. The 8XC51 is in Mode 0 operation. this would not normally be the case with the 8XC51/PIC17C42.

6 MHz CLKIN), read the conversion result data on the DIN line

–33–REV. B AD7851 Evaluating the AD7851 Performance The recommended layout for the AD7851 is outlined in the evaluation board for the AD7851. The evaluation board package includes a fully assembled and tested evaluation board, documen- tation, and software for controlling the board from the PC via the EVAL-CONTROL BOARD. The EVAL-CONTROL BOARD can be used in conjunction with the AD7851 Evaluation Board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc perfor- mance of the AD7851. The software allows the user to perform ac (Fast Fourier Trans- form) and dc (histogram of codes) tests on the AD7851. It also gives full access to all the AD7851 on-chip registers allowing for various calibration and power-down options to be programmed. AD785x Family All parts are 12 bit, 200 kSPS, 3.0 V to 5.5 V, except the AD7856 which is 14 bit, 285 kSPS, 5 V supply. AD7853 – Single-Channel Serial AD7854 – Single-Channel Parallel AD7856 – Eight-Channel Serial AD7858 – Eight-Channel Serial AD7859 – Eight-Channel Parallel APPLICATION HINTS Grounding and Layout The analog and digital supplies to the AD7851 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The part has very good immunity to noise on the power supplies as can be seen by the PSRR versus frequency graph. However, care should still be taken with regard to grounding and layout. The printed circuit board that houses the AD7851 should be designed such that the analog and digital sections are separated and confined to certain areas of the board . This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD7851 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7851. If the AD7851 is in a system where multiple devices require AGND to DGND connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the AD7851. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7851 to avoid noise coupling. The power supply lines to the AD7851 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum in parallel with 0.1 µF ca- pacitors to AGND. All digital supplies should have a 0.1 µF disc ceramic capacitor to DGND. To achieve the best from these de- coupling components, they must be placed as close as possible to the device, ideally right up against the device. In systems where a common supply voltage is used to drive both the AV DD and DVDD of the AD7851, it is recommended that the system’s AVDD supply is used. In this case, there should be a 10 Ω resistor between the AVDD pin and DVDD pin. This supply should have the recommended analog supply decoupling capacitors between the AVDD pin of the AD7851 and AGND and the recommended digital supply decoupling capacitor between the DVDD pin of the AD7851 and DGND.

–34– REV. B OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] (N-24) Dimensions shown in inches and (millimeters) 1 12 1.185 (30.01) 1.165 (29.59) 1.145 (29.08) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) SEATING PLANE 0.015 (0.38) MIN 0.180 (4.57) MAX 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) BSC 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095AG 24-Lead Standard Small Outline Package [SOIC] Wide Body (R-24) Dimensions shown in millimeters and (inches) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AD 8/H11543 0/H11543 0.75 (0.0295) 0.25 (0.0098) /H11547 45/H11543 1.27 (0.0500) 0.40 (0.0157) SEATING PLANE 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) BSC 24 13 121 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) COPLANARITY 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122)

–35–REV. B AD7851 24-Lead Shrink Small Outline Package [SSOP] (RS-24) Dimensions shown in millimeters 24 13 121 8.20 7.80 7.40 5.60 5.30 5.000.38 0.22 SEATING PLANE 0.05 MIN 0.65 BSC

2.00 MAX

1.85 1.75 1.65 0.95 0.75 0.55 0.25 0.09 8/H11543 4/H11543 0/H11543 0.10 COPLANARITY 8.50 8.20 7.90 COMPLIANT TO JEDEC STANDARDS MO-150AG

C01332–0–3/04(B) –36–

Revision History

3/04—Data Sheet changed from REV. A to REV. B. AD7851 REV. B