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TPS61381-Q1 TI | Alldatasheet

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Technical content

TPS61381-Q1 Automotive 400kHz, 40V, 15A Boost Converter with LDO Charger and Battery State of Health Detection

1 Features

• AEC-Q100 qualified for automotive applications – Device temperature grade 1: –40°C to 125°C ambient operating temperature range
• I2C programmable LDO charger – Supports charger input voltage (VOUT Pin) up to 21V, absmax up to 40V to withstand load dump – Supports multi-chemistry battery charging profile of 1-5 cell NiMH, 1-2 cell Li-Ion, LiFePO4, 1-4 cell super capacitor – Programmable charging current 50mA and 100mA – Wide battery voltage operating range 0V to 12V – Programmable charging timer up to 32h – NTC thermistor input to monitor battery temperature
• Programmable boost converter supporting 12V car battery back-up power system – Programmable output voltage range: 5V to 12V – Programmable boost average input current limit from 5A to 15A – Back-up battery (BUB) voltage in boost mode: 0.5V to 12V
• Minimum 3V for start up
• Can start up at 1V when Vout>5V – <20us automatic transition into the boost mode when 12V system voltage drops
• Backup battery State-of-Health(SOH) detection – Adjustable discharge current from 0A to 1.5A – Multi-signal analog output(AVI pin) of battery voltage, discharge current and battery temperature
• Lower quiescent current and leakage current – 20μA quiescent current in standby mode – < 1μA shutdown current – < 1μA leakage current for pins connected to the back up battery
• EMI mitigation – 400kHz fix switching frequency – Optional programmable spread spectrum
• 3mm × 4mm 25-pin package with wettable flank

2 Applications

• Emergency call(eCall)

3 Description

The TPS61381-Q1 is 400kHz, 40V, 15A automotive bi-directional boost converter/ LDO charger with battery state of health detection function designed for back-up power systems like TBOX or e-call. The converter supports absmax voltage up to 40V on VOUT pin to withstand load-dump condition and supports direct connection with 12V car battery. The TPS61381-Q1 integrates I2C configurable LDO charger supporting NiMH, Li-Ion, LiFePO4, super capacitor. TPS61381-Q1 integrates boost function that operates over 0.5V to 12V BUB voltage and 5-12V output voltage. The device applies fix frequency peak current control scheme with optional spread spectrum to minimize EMI. The boost function supports 5A-15A programmable average current limit. The TPS61381-Q1 integrates battery health detection feature which discharge the battery with a constant current and detects the voltage drop across the battery internal resistance. The TPS61381-Q1 is available in a 3mm × 4mm QFN package with wettable flank. Care must be taken when designing the PCB with TPS61381-Q1, view Section 8.4.2 for details. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TPS61381-Q1 RAV 3.0mm × 4.0mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TPS61381-Q1 VBAT Vsystem SW BOOT IL BUB TS VOUT VCC STATUS LO AVI EN_BST EN_CHGR SCL SDA COMP MCU AGNDEP Net_Tie:10-20mil trace or 0ohm resistor NT1 Vds>30V 10-30µF 0.1-1µF 0603 0-3 220-470nF 2.2µH 0.1-1µF 0603 >40V 10µFx4 >40V 100µF >40V 4.7µF R4 10k MCU_GPIO_VDD MCU_GPIO_VDD ADC GPIO GPIO GPIO GPIO GPIO 10k 12nF 100pF C10 100µF >40V AGND PGND Typical Application Circuit TPS61381-Q1 SLVSHK6 – MARCH 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

6.6 Battery State-of-Health (SOH) Detection Feature

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4 Pin Configuration and Functions

EN_CHGR IL SW VOUT Thermal Pad TS EN_BST BOOT STATUS VCC LO Figure 4-1. 24-Pin QFN with Wettable Flank Package (Top View) TERMINAL I/O DESCRIPTION NAME RAV BUB 1 I Back up battery voltage sensing pin. Connect BUB as close as possible to the battery's positive terminal for the most accurate voltage sense. COMP 2 O External compensation pin. This pin is the output of the transconductance amplifier. Connect a compensation network from the COMP pin to AGND. AVI 3 O Analog voltage output pin for battery State of Health (SOH) detection function. AVI pin can be configured to output back-up battery voltage, discharge current and back up battery temperature. The pin has internal 125k Ω pulldown resistance to AGND when AVI output is disabled. SCL 4 I Clock pin for I2C interface. SDA 5 I/O Data pin for I2C interface. AGND 6 G Signal ground pin. Connect with PGND (Low side MOSFET source) through 20mil wire or 0Ω resistor. View Section 8.4.2 for detailed GND connection. EN_CHGR 7 I Charger function enable pin. Drive this pin high / low to enable / disable the charger function. STATUS 8 O STATUS indication output pin. Open drain output for STATUS indication function. Output low when entering boost mode by default. Selectable by I2C to to output other signals. VCC 9 O Internal regulator output. Used as supply to internal control circuits. Do not connect this pin to any external loads. Connect 2.2-4.7µF capacitor from this pin to AGND LO 10 O Gate driver pin for low-side MOSFET VOUT 11, 12, 13, 14 P Boost converter output pin. www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS61381-Q1

SW 15, 16, 17 P Device switch pins and the switch node of the regulator. Connect to the low side MOSFET drain. IL 18, 19, 20, 21 P Boost converter input pin. Connect to the inductor. BOOT 22 O Power supply for the high-side MOSFET gate driver. Connect a 100nF-470nF capacitor between the SW node and BOOT. An internal diode charges the capacitor while SW node is low. EN_BST 23 I Boost function enable pin. Drive this pin high / low to enable / disable the boost function. TS 24 I Temperature qualification voltage input pin. Connect a negative temperature coefficient (NTC) thermistor directly from TS to GND (AT103-2 recommended). Charge suspends when the TS pin voltage is out of range. EP 25 G Thermal pad. Connect with AGND. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage range at terminals SW, VOUT –0.3 40 V IL –0.3 18 V BUB, EN_BST, EN_CHGR, STATUS –0.3 15 V LO, TS, AVI, SDA, SCL, VCC, COMP –0.3 6 V BOOT to SW –0.3 6 V TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(2) ±2000 V Charged-device model (CDM), per AEC Q100-011, all pins(3) ±500 V(ESD) (1) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011, corner pins(3) ±750 V (1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device. (2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VBUB Back-up battery voltage range 0.5 12 V VOUT Output voltage range Vin 20 V L Effective inductance range for 400kHz frequency 1*0.7 2.2 µH CI Effective input capacitance range, (disable BuB voltage loop) 10 µF CI Effective input capacitance range, (enable BuB voltage loop), BUB IR<100mohm 10 µF CI Effective input capacitance range, (enable BuB voltage loop), BUB IR<400mohm 5 µF CO Effective output capacitance range 30 220 µF TA Ambient temperature –40 125 °C TJ Junction temperature –40 150 °C

5.4 Thermal Information

THERMAL METRIC(1) PKG DES (16 PINS) PKG DES (16 PINS) UNIT Standard EVM(2) RθJA Junction-to-ambient thermal resistance 40.4 25.49 °C/W www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS61381-Q1

THERMAL METRIC(1) PKG DES (16 PINS) PKG DES (16 PINS) UNIT Standard EVM(2) RθJC(top) Junction-to-case (top) thermal resistance 12.0 TBD °C/W RθJB Junction-to-board thermal resistance 6.9 TBD °C/W ΨJT Junction-to-top characterization parameter 0.2 2.4 °C/W ΨJB Junction-to-board characterization parameter 6.9 13.05 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 23.6 TBD °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Measured on TPS61381QEVM-126, 4-layer, 2oz copper, 116mmx76mm PCB.

5.5 Electrical Characteristics

TJ = -40°C to 150°C, VBUB = 3.6V and VOUT = 12V(LDO charger mode), VOUT = 6.2V(boost mode). Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VBUB Back-up battery voltage range 0 13 V VBUB_UVL O Under-voltage lockout threshold VBUB rising with VOUT = 0V 2.8 V VBUB rising with VOUT>5V or VCC >4.5V, boost mode active 1 V VBUB falling with VOUT > VVOUT_UVLO, boost mode active 0.5 V VVOUT_UV LO Under-voltage lockout threshold VOUT rising 3.5 V VVOUT_UV LO_HYS VVOUT_UVLO hysteresis 300 mV IQ_BOOST _STANDBY Quiescent current into BUB pin at boost and standby mode Boost is enable, LDO is disable, SOH disable, No load, No switching, Vout_target = 6.2 V, VOUT = 10 V to 18 V, TJ up to 85°C, Vout is pre-biased. 0.01 0.1 uA Quiescent current into VOUT pin at boost and standby mode Boost is enable, LDO is disable, SOH disable, No load, No switching, Vout_target = 6.2 V, VOUT = 10 V to 18 V, TJ up to 85°C, Vout is pre-biased. 20 30 uA IQ_LDO_ST ANDBY Quiescent current into BUB pin at LDO and standby mode LDO mode enabled and boost mode disable, SOH disable, No load, No switching, No active re-charge, Vout = 12 V, VBUB > target, TJ up to 85°C 0.01 0.1 uA Quiescent current into VOUT pin at LDO and standby mode LDO mode enabled and boost mode disable, SOH disable, No load, No switching, No active re-charge, Vout = 12 V VBUB > target, TJ up to 85°C 20 30 uA ISD Shutdown current into BUB pin EN_BST=0 and EN_CHGR=0, TJ up to 85°C 0.2 1 uA Shutdown current into VOUT pin EN_BST=0 and EN_CHGR=0, TJ up to 85°C 0.2 1 uA IVOUT_LK G Leakage current into VOUT pin， Q2 leakage current VSW = VIL = 0V and VOUT = 10 V to 18 V, IC disabled, TJ up to 85°C 0.1 10 uA IIL_LKG Leakage current into IL pin, Q leakage current VSW = VOUT = 0V and VIL = 0 V to 4.8 V, IC disabled, TJ up to 85°C 0.1 10 uA VCC Internal regulator output Icc=20mA 5 5.2 5.35 V BOOST OUTPUT VOUT Output voltage setting range Programmable by I2C 5 12 V TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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TJ = -40°C to 150°C, VBUB = 3.6V and VOUT = 12V(LDO charger mode), VOUT = 6.2V(boost mode). Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT_PW M_ACY Output voltage accuracy PWM or FPWM –2.5 2.5 % VOUT_PFM _ACY PFM 1.5 % VOUT_STA NDBY Boost standby threshold Vout rising 6 % VOUT_OV P Charger and boost output over voltage protection, rising 23 V Charger and boost output over voltage protection, falling 21 V tOFF_min Min. off time Boost mode, low side 100 157 ns Duty_min _down_ mode Minimum duty at boost mode 6 11 % ILIM_boost Average current limit accuracy in boost mode ILIM_boost = 5A 4 5 6 A ILIM_boost = 10A 8 10 12 A ILIM_boost = 15A 11 15 18 A Ipeak_boost Absolute peak current limit range in boost mode ILIM_boost = 5A or 10A 15 A ILIM_boost = 15A 30 A POWER SWITCH RDS(on) High-side MOSFET on resistance VCC = 5.0V 20 mΩ RDS(on) Isolation MOSFET on resistance VCC = 5.0V 6 mΩ fSW Switching frequency 360 400 440 kHz GATE DRIVER VDRV_L Low-state voltage drop 100-mA sinking 0.08 V VDRV_H High-state voltage drop VCC – VDRV, 100-mA sourcing 0.18 V CHARGER CC/CV VBUB BUB CV setting voltage range 1.7 12 V VBUB accuracy For Li-ion and LiFePO4,TJ = -20°C ~ 85°C –1 1 % VBUB accuracy For Supercap,TJ = -20°C ~ 85°C –2 2 % ICC Charging current setting range 50 100 mA ICC accuracy 50 mA =< ICC < 100mA,TJ = -20°C ~ 85°C –20 20 % VBUB_SH ORT BUB short circuit voltage rising threshold, per cell for Li-ion battery VBUB rising,TJ = -20°C ~ 85°C 2.1 2.2 2.3 V VBUB_SH ORT BUB short circuit voltage rising threshold, per cell for LiFePO4 battery VBUB rising,TJ = -20°C ~ 85°C 1.1 1.2 1.3 V VBUB_SH ORT_HYS Hysteresis 170 mV ISHORT BUB short current 15 mA VBUB_LO WV Pre-charge to fast-charge transient threshold, per cell for Li-ion battery VBUB rising,TJ = -20°C ~ 85°C 2.7 2.8 3 V VBUB_LO WV Pre-charge to fast-charge transient threshold, per cell for LiFePO4 battery VBUB rising,TJ = -20°C ~ 85°C 1.9 2 2.1 V VBUB_LO WV_HYS Hysteresis, per cell VBUB falling 100 mV Iprecharge Precharge current ICC = 100mA 30 mA VRECHG_ HYS Battery recharge threshold, per cell for Li- ion battery VBUB falling, VBUB_CV - VBUB, TJ = -20°C ~ 85°C 50 100 200 mV www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS61381-Q1

TJ = -40°C to 150°C, VBUB = 3.6V and VOUT = 12V(LDO charger mode), VOUT = 6.2V(boost mode). Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRECHG_ HYS Battery recharge threshold, per cell for LiFePO4 battery VBUB falling, VBUB_CV - VBUB , TJ = -20°C ~ 85°C 150 200 285 mV VRECHG_ HYS Battery recharge threshold, per cell for supercap VBUB falling, VBUB_CV - VBUB, VBUB = 2.5 V, TJ = -20°C ~ 85°C 110 150 200 mV VCHG_NiM H Battery charge threshold, per cell for NiMH battery TJ = -20°C ~ 85°C 1.31 1.34 1.365 V VBUB_OVP BUB overvoltage threshold for Li-ion / LiFePO4 / Supercap Rising, As percentage of VBUB , TJ = -20°C ~ 85°C 101 104 106 % VBUB_OVP BUB overvoltage threshold, per cell for NiMH battery Rising,TJ = -20°C ~ 85°C 1.65 1.7 1.75 V tCHARGIN G Charging timer accuracy 7 8 9 hr tSAFETY Safety timer accuracy 9 10 11.5 hr tON_INTER MITTENT On time in intermittent charge 2 s tOFF_INTE RMITTENT Off time in intermittent charge 58 s BATTERY-PACK NTC MONITOR ITS_BIAS TS nominal bias current TJ = -20°C ~ 85°C 35.5 38 40 uA VCOLD Cold temperature threshold TS pin voltage rising (approx. 0°C) 0.99 1.04 1.09 V Cold temperature exit threshold TS pin voltage falling (approx. 4°C) 0.83 0.88 0.93 V VHOT Hot temperature threshold TS pin voltage falling (approx. 45°C) 176 188 200 mV Hot temperature exit threshold TS pin voltage rising (approx. 40°C) 208 220 232 mV VTS_CLAM P TS maximum voltage clamp TS pin open circuit(float) 2.3 2.6 2.9 V BATTERY HEALTH DETECTION IDISCHARG E Discharge current range 0 1.5 A Discharge current accuracy TJ = 25°C 480 500 520 mA Discharge current accuracy TJ = -20°C ~ 85°C 470 500 520 mA VDISCHAR GE_AVI Discharge current measurement voltage range 0 3.3 V Discharge current measurement voltage accuracy IDISCHARGE = 500mA, ratio=2, TJ = 25°C -3.2 3.2 % Discharge current measurement voltage accuracy IDISCHARGE = 500mA, ratio=2, TJ = -20°C ~ 85°C –4 4 % VBUB_AVI BUB voltage measurement range 0 3.3 V BUB voltage measurement accuracy VTEMP_AV I BUB temperature measurement range 0 3.3 V BUB measurement accuracy TJ = -20°C ~ 85°C -0.4 0.6 % LOGIC INTERFACE VI2C_IO IO voltage range for I2C 1.7 5.5 V VI2C_H I2C input high threshold VCC = 2.7V to 5.5V 1.2 V VI2C_L I2C input low threshold VCC = 2.7V to 5.5V 0.4 V VEN_H EN_BST and EN_CHG logic high threshold VCC = 2.7V to 5.5V 1.2 V VEN_L EN_BST and EN_CHG logic low threshold VCC = 2.7V to 5.5V 0.4 V THERMAL PROTECTION TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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TJ = -40°C to 150°C, VBUB = 3.6V and VOUT = 12V(LDO charger mode), VOUT = 6.2V(boost mode). Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TSD Thermal shutdown TJ rising 175 °C TSD_HYS Thermal shutdown hysteresis 15 °C

5.6 I2C Timing Characteristics

TJ = -40°C to 150°C, VCC = 5 V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2C TIMING fSCL SCL clock frequency 100 400 kHz tBUF Bus free time between a STOP and START condition Fast mode plus 0.5 µs tHD(STA) Hold time (repeated) START condition 260 ns tLOW Low period of the SCL clock 0.5 µs tHIGH High period of the SCL clock 260 ns tSU(STA) Setup time for a repeated START condition 260 ns tSU(DAT) Data setup time 50 ns tHD(DAT) Data hold time 0 µs tRCL Rise time of SCL signal 120 ns tRCL1 Rise time of SCL signal after a repeated START condition and after an ACK bit 120 ns tFCL Fall time of SCL signal 120 ns tRDA Rise time of SDA signal 120 ns tFDA Fall time of SDA signal 120 ns tSU(STO) Setup time of STOP condition 260 ns CB Capacitive load for SDA and SCL 200 pF www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPS61381-Q1

5.7 Typical Characteristics

O u t p u t C u r r e n t ( A ) Efficiency (%) 5 0 6 0 7 0 8 0 9 0 1 0 0 B U B = 4 . 5 V B U B = 3 . 6 V B U B = 3 V B U B = 1 . 5 V Figure 5-1. Boost Efficiency vs Output Current, VOUT = 6.2V, PFM O u t p u t C u r r e n t ( A ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 B U B = 4 . 5 V B U B = 3 . 6 V B U B = 3 V B U B = 1 . 5 V Figure 5-2. Boost Efficiency vs Output Current, VOUT = 6.2V, FPWM O u t p u t C u r r e n t ( A ) Efficiency (%) 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 B U B = 6 V B U B = 4 . 5 V B U B = 3 . 6 V B U B = 3 V B U B = 1 . 5 V Figure 5-3. Boost Efficiency vs Output Current, VOUT = 8V, PFM O u t p u t C u r r e n t ( A ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 B U B = 6 V B U B = 4 . 5 V B U B = 3 . 6 V B U B = 3 V B U B = 1 . 5 V Figure 5-4. Boost Efficiency vs Output Current, VOUT = 8V, FPWM O u t p u t C u r r e n t ( A ) Efficiency (%) 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 B U B = 6 V B U B = 4 . 5 V B U B = 3 . 6 V B U B = 3 V B U B = 1 . 5 V Figure 5-5. Boost Efficiency vs Output Current, VOUT = 10V, PFM O u t p u t C u r r e n t ( A ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 B U B = 6 V B U B = 4 . 5 V B U B = 3 . 6 V B U B = 3 V B U B = 1 . 5 V Figure 5-6. Boost Efficiency vs Output Current, VOUT = 10V, FPWM TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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V O U T V o lt a g e ( V ) Quiescent Current into VOUT (A) 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 0 2 0 3 0 4 0 5 0 T E M P = 1 2 5  C T E M P = 8 5  C T E M P = 2 5  C T E M P = 0  C T E M P = - 2 0  C T E M P = - 4 0  C Figure 5-13. Quiescent Current into VOUT vs VOUT Voltage, VBUB = 3.6V B U B V o lt a g e ( V ) Shutdown Current into BUB (nA) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 T E M P = 1 2 5  C T E M P = 8 5  C T E M P = 2 5  C T E M P = 0  C T E M P = - 2 0  C T E M P = - 4 0  C Figure 5-14. Shutdown Current into BUB vs BUB Voltage, VOUT = 12V V O U T V o lt a g e ( V ) Shutdown Current into VOUT (nA) 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0 T E M P = 1 2 5  C T E M P = 8 5  C T E M P = 2 5  C T E M P = 0  C T E M P = - 2 0  C T E M P = - 4 0  C Figure 5-15. Shutdown Current into VOUT vs VOUT Voltage, VBUB = 3.6V T e m p e r a t u r e (  C ) BUB Regulation Voltage Accuracy (%) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 Figure 5-16. Battery Regulation Voltage Accuracy vs Temperature, Icharge = 100mA T e m p e r a t u r e (  C ) Charge Current Accuracy (%) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 5 - 4 - 3 - 2 - 1 Figure 5-17. Charge Current Accuracy vs Temperature, Icharge = 100mA T e m p e r a t u r e (  C ) Pre-charge Current Accuracy (%) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 5 - 4 - 3 - 2 - 1 Figure 5-18. Precharge Current Accuracy vs Temperature TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6 Detailed Description

6.1 Overview

The TPS61381-Q1 is a bi-directional boost converter / LDO charger with battery State-of Health (SOH) detection function. The device provides an integrated power solution in back-up power system like TBOX and e-Call applications. The converter supports 40V voltage rating on VOUT pin to withstand load-dump condition and support direct connection with 12V car battery. The converter supports boost function for back up power system. The IC automaticly switch to boost mode when car battery malfunction occurs and voltage drop on the system side is detected. The TPS61381-Q1 integrates boost function that operates over a wide range of 0.5V to 13V BUB voltage and 5V to 12V programmable output voltage in boost mode.The device uses fix frequency peak current mode control scheme which provides simplified loop compensation, rapid response to load transients and inherent line voltage rejection. An error amplifier compares the feedback voltage with the internal reference voltage. The output of the error amplifier determines the peak inductor current. The IC also supports 5A-15A selectable average current limit. The TPS61381-Q1 integrates an I2C configurable constant-current / constant-voltage (CC/CV) LDO charger to charge the battery. The charger function supports 1 to 5 cell NiMH, 1 to 2 cell Li-Ion, Li-Poly, LiFePO4 and 1 to 4 cell super capacitor. The device supports battery temperature monitor function which connects TS pin to battery NTC to detect battery temperature and pauses charging when high/low temperature is detected. The TPS61381-Q1 integrates battery State-of Health (SOH) detection feature which discharge the battery with a constant current and detect the voltage drop across the battery internal resistance. By controlling back-up battery discharge current by I2C interface and output the detected BUB voltage to MCU. The MCU can calculate the internal resistance and diagnostic the battery health. An internal oscillator operates with fixed 400kHz and provide clock for the IC switching cycle. To minimize EMI, TPS61381-Q1 can dither the switching frequency at ±7% of the 400kHz switching frequency. The TPS61381-Q1 is available in a 3mm × 4mm QFN package with wettable flank. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.2 Functional Block Diagram

ISO_ON ISO Control Downmode Charge Pump VCC HS_ON VOUT VCC VCC Block Linear Driver HS Control BUB VCC UVLO Shutdown HS_ON LO AGND Vout Vref COMP Vcomp_BST CLK_SlopeSlope Compensa on- Isns R S Q Q CLK BST_LSD BST_HSD AVG Current Limit BUB Vbub_ref Gmv CV_ref CC_ref Driver Control SOH_ACTIVE SOH_DRV SOH_Iref Gmi LDO_Control AVI Output TSAVI EN_BST EN_CHGR VCC_OK Soft Start Vref SCL SDA Logic Core EN_Device Wakeup_ Vref VOUT_FB Vout_FB BUB_FB R S Q Q Standby_ Vref VOUT_FB Quit Boost Enter Boost HS_ON LS_ON ISO_ON CLK Spread Spectrum CLK CLK_Slope VCC TS 1.04V BUB_UVLO EP STATUS BUB_FB 188mV TS_FAULT ZCD BST_ACTIVE SW –Gbub –Gm –BUB UVLO BUB_UVLO BUB OVP BUB_OVP BUB_OVP VOUT UVLO VOUT_UVLO VOUT OVP VOUT_OVP Thermal Dection Thermal Shutdown VOUT_UVLO VOUT_OVP SOH OCP LDO_Control www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS61381-Q1

6.3 Feature Description

6.3.1 VCC Power Supply and UVLO Logic

An internal VCC_LDO sinks current from either BUB or VOUT pin to power VCC to 5.2V target depending on BUB and VOUT voltage and operating mode. The IC is enabled only when at least one of its EN pins is high and VCC voltage>2.8V. A ceramic capacitor is connected between the VCC pin and AGND pin to stabilize the VCC voltage and also decouple the noise on the VCC pin. The effective capacitance of this ceramic capacitor should be above 1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating higher than 6.3V is recommended. TPS61381-Q1 applies undervoltage lockout (UVLO) logic on BUB, VOUT and VCC pin depending on different operating mode. Sufficient voltage must be applied to ensure proper function of the IC. Table 6-1. UVLO Logic Operating Mode VBUB VOUT VCC Boost Mode >VBUB_UVLO >0V >2.8V Charger Mode >0V >VVOUT_UVLO >2.8V SOH Mode >0V >VVOUT_UVLO >2.8V Standby Mode >0V >VVOUT_UVLO >2.8V

6.3.2 Enable or Shutdown

TPS61381Q applies two EN pins to configure operating modes of the device. The I2C interface function can be enabled by either EN_BST pin or EN_CHGR pin. After device enabled, the device enters its operating mode depending on EN pins, I2C configuration and VOUT voltage. Check Section 6.3.3 for details about operation modes. Table 6-2. Enable or Shutdown Logic EN pins configuration I2C EN bits configuration Device State I2C Interface Device Current Consumption EN_CHGR pin = 0 AND EN_BST pin = 0 X Shutdown Disabled Register Reset <1μA(typ) EN_CHGR pin = 1 AND EN_BST pin = 0 CHGR_SOH_EN bit = 00b Standby Enabled 20μA(typ) EN_CHGR pin = 0 AND EN_BST pin = 1 CHGR_SOH_EN bit = 00b Standby Enabled 20μA(typ) EN_CHGR pin = 1 CHGR_SOH_EN bit = 01b/10b Device Active Enabled According to working condition EN_BST pin = 1 BST_EN bit = 1 Device Active Enabled According to working condition When TPS61381-Q1 is disabled by EN pin (EN_BST=0 AND EN_CHGR=0), the device is completely Shutdown. Under shutdown state, the device consumes less than 1 μA shutdown current, I2C registers are reset to default and I2C interface is disabled. When the device is disabled by EN bit (BST_EN = 0 AND CHGR_SOH_EN = 0), the device enters standby state. Current consumption under this state is 20 μA, I2C register contents are kept and I2C interface is active. During shutdown and standby state, TPS61381-Q1 supports true disconnection function and the back up battery is completely disconnected from the output. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.3.3 Device Operating Modes and Control Logic

TPS61381-Q1 supports four operating modes for its main functions: charger mode, boost mode, State-of-Health (SOH) mode and standby mode. The power structure of each modes are depicted by figures below: 12V Car Battery VBAT VOUT IL VOUT TPS61381-Q1 12V Car Battery VBAT VOUT TPS61381-Q1 12V Car Battery VBAT VOUT TPS61381-Q1 12V Car Battery VBAT VOUT TPS61381-Q1 (a) Standby Mode (c) Charger Mode (b) Boost Mode (d) SOH Mode SW LO IL VOUT SW LO IL VOUT SW LO IL VOUT SW LO Q3 Q2 Q3 Q2 Q3 Q2 Q3 Q2 Figure 6-1. TPS61381-Q1 Operating Modes TPS61381-Q1 applies AND logic on its EN pins and I2C EN bits. The boost function is enabled when EN_BST pin and BST_EN bit is both high. Charger is enabled when EN_CHGR pin is high and CHGR_SOH_EN bit is 01b. SOH is enabled when EN_CHGR pin is high and CHGR_SOH_EN bit is 10b. www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS61381-Q1

Table 6-3. Operating Modes Control Logic Boost enable: EN_BST pin AND BST_EN bit Charger/SOH enable: EN_CHGR AND CHGR_SOH_EN bit Device State Device Operation EN_BST = 0 or BST_EN = 0 EN_CHGR = 1 and CHGR_SOH_EN = 01b Pure charger Charger Active. EN_BST = 0 or BST_EN = 0 EN_CHGR = 1 and CHGR_SOH_EN = 10b Pure SOH SOH Active. EN_BST = 1 and BST_EN = 1 EN_CHGR = 0 or CHGR_SOH_EN=00b Automatic boost and standby

• Boost Active: VOUT < BST_WAKE
• Standby Active: VOUT > VOUT_STANDBY(106%VOUT_TAR GET) EN_BST = 1 and BST_EN = 1 EN_CHGR = 1 and CHGR_SOH_EN = 01b Automatic boost and charger mode
• Boost Active: VOUT < BST_WAKE
• Charger Active: VOUT > VOUT_STANDBY(106%VOUT_TAR GET) EN_BST = 1 and BST_EN = 1 EN_CHGR = 1 and CHGR_SOH_EN = 10b Automatic boost and SOH mode
• Boost Active: VOUT < BST_WAKE
• SOH Active: VOUT > VOUT_STANDBY(106%VOUT_TAR GET) TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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When multiple functions are enabled, TPS61381-Q1 monitors system voltage by VOUT pin to decide which function mode to enter. The IC stays in standby/ charger or SOH mode (depending on which function is enabled) when system voltage is sufficient and automatically transition into boost mode when car battery malfunction occurs and voltage drop on system voltage is detected. The different operation modes are shown in the Functional State Diagram. BUB EN_BST VCC CHECK VCC > VVCC-UVLO-RISING EN_CHGR DEVICE_INI = done & EN_BST = 1 & BST_EN = 1 & VOUT < BST_WAKE BOOST MODE EN_BST = 1 || EN_CHGR = 1 !Thermal Shutdown (TSD) DEVICE INI SHUT DOWN VOUT THERMAL SHUTDOWN SOH MODE DEVICE_INI = done & EN_CHGR = 1 & CHGR_SOH_EN = 10b & VOUT > BST_WAKE CHARGER MODE DEVICE_INI = done & EN_CHGR = 1 & CHGR_SOH_EN = 01b & VOUT > BST_WAKE STANDBY MODE VOUT < BST_WAKE & EN_BST = 1 & BST_EN = 1 VOUT > VBST_STANDBY & (EN_CHGR = 0 || CHGR_SOH_EN = 00b) EN_CHGR = 1 & CHGR_SOH_EN = 01b & VOUT > VBST_STANDBY EN_CHGR = 1 & CHGR_SOH_EN = 10b & VOUT > VBST_STANDBY VOUT < BST_WAKE & EN_BST = 1 & BST_EN = 1 EN_CHGR = 1 & CHGR_SOH_EN = 01b EN_CHGR = 1 & CHGR_SOH_EN = 10b EN_CHGR = 0 || CHGR_SOH_EN = 00b EN_CHGR = 0 || CHGR_SOH_EN = 00b !Thermal Shutdown (TSD) CHGR_SOH_EN = 01b CHGR_SOH_EN = 10b !Thermal Shutdown (TSD) !Thermal Shutdown (TSD) SYSTEM OVP VOUT > VOUT_OVP Rising VOUT < VOUT_OVP Falling & (EN_CHGR = 0 || CHGR_SOH_EN = 00b) VOUT > VOUT_OVP Rising VOUT < VOUT_OVP Falling & EN_CHGR = 1 & CHGR_SOH_EN = 01b VOUT > VOUT_OVP Rising VOUT < VOUT_OVP Falling & EN_CHGR = 1 & CHGR_SOH_EN = 10b !Thermal Shutdown (TSD) STANDBY MODE I2C = ON VCC = ON BOOT = GND LO = HIGH SOH MODE I2C = ON VCC = ON BOOT = HIGH LO = Regulate CHARGER MODE I2C = ON VCC = ON BOOT = HIGH LO = GND BOOST MODE I2C = ON VCC = ON BOOT = HIGH LO = Switching DEVICE INI I2C = ON VCC = ON BOOT = GND LO = GND VCC CHECK I2C = OFF VCC = ON BOOT = GND LO = GND I2C = OFF VCC = 3V BOOT = GND LO = GND SHUT DOWN VOUT < BST_WAKE & EN_BST = 1 & BST_EN = 1 VOUT < VVOUT_UVLO VOUT < VVOUT_UVLO VOUT < VVOUT_UVLO THERMAL SHUTDOWN I2C = ON VCC = ON BOOT = GND LO = GND SYSTEM OVP I2C = ON VCC = ON BOOT = GND LO = GND || : logic OR & : logic AND ! : logic NOT TSD : Thermal Shutdown : Priority 1 2 3 2 3 145 1 2 VOUT < VVOUT_UVLO !Thermal Shutdown (TSD) 2 3 Figure 6-2. Functional State Diagram www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS61381-Q1

BST_VOUT BST_Standby STANDBY_ACTIVE /CHGR_ACTIVE /SOH_ACTIVE BST_ACTIVE BST_WAKE BST_VOUT BST_Standby BST_ACTIVE VOUT VBAT VOUT VBAT STANDBY_ACTIVE /CHGR_ACTIVE /SOH_ACTIVE BST_WAKE Figure 6-3. Automatic Boost and Standby/Charger/SOH Transition Logic

6.3.4 Configured as Status Indicatior

TPS61381-Q1 supports status indication function with its STATUS pin. The STATUS pin operates as an open- drain digital output to indicate the IC status or trigger interrupt of your system MCU. TPS61381-Q1 STATUS pin supports indicating multiple items by configuring I2C register 0DH (Bit 3 to Bit 7). The pin is set to indicate BST_ACTIVE (boost active) status by default. When the device enters boost mode, the STATUS pin is pulled low to indicate a boost active status. The pin can also be configured to output charge done, thermal shutdown or TS fault signal. If multiple status items are selected, the pin output the NOR logic of all items (Pull low if any of the status is triggered). Table 6-4. STATUS Pin Indication Items Register 0DH Bit Selected Item Discription [7] INC_BST BST_ACTIVE status is included in the STATUS pin. Output low when entering boost mode. [6] INC_ABST ALRT_BST_ACTIVE status is included in the STATUS pin. Output low when boost mode has been entered since last read. [5] INC_ADN ALRT_CHGR_DONE status is included in the STATUS pin. Output low when charge done has been triggered since last read. [4] INC_TSD THRM_SD status is included in the STATUS pin. Output low when thermal shutdown protection is triggered. [3] INC_TSFAULT TS_FAULT status is included in the STATUS pin. Output low when TS pin detects cold/hot temperature over range.

6.3.5 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal switches when the IC junction temperature exceeds 175°C (typical). After thermal shutdown occurs, hysteresis prevents the device from toggling until the junction temperature drops to approximately 160°C. When the junction temperature falls below 160°C (typical), TPS61381-Q1 attempts to re-start. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.4 Charger Feature Description

TPS61381-Q1 integrates LDO charger function with complete charging strategy for mutiple types of back up battery. By setting the battery type, cell number, charging current, charging voltage and charging timer, TPS61381Q automatically applies corresponding charging strategy for the selected battery chemistry.

• Supports mutiple types of back up battery: NiMH(1S 2S 3S 4S 5S), LiFePO4(1S 2S), Li-ion(1S 2S), Super Capcitor(1S 2S 3S 4S)
• Optional charging current: 50mA to 100mA (Selectable by I2C)
• Support charger status indication by I2C interface: Register 08H (CHGR_STATUS) TPS61381-Q1 supports mutiple safety protection and monitition functions for both battery charging and system operations. Charging safety timer, back up battery overvoltage protection, charger anti-reverse protection and battery cold/hot temperature protections are applied to ensure the battery safety during charger operation. Also, TPS61381Q indicates the charger status and fault condition by CHGR_STATUS and FAULT_CONDITION registers .

6.4.1 Charger Enable

TPS61381-Q1 charger function is enabled when:

• EN_CHGR pin is high
• CHGR_SOH_EN=01b (I2C Register 0BH: CONTROL_STATUS, Bit [6:5] )
• VOUT < VOUT_OVP
• VCC > 2.8V After charger function is enabled, the IC enters charger mode when VOUT > boost wake-up threshold (Set by I2C BST_WAKE bits). When charger mode is active, TPS61381-Q1 charge the back-up battery (BUB pin). The charger only support step down operation. So if VOUT drops below 100mV+BUB Voltage, the charger turn off all power MOSFETs to protect itself. www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS61381-Q1

6.4.2 LDO Charger

TPS61381-Q1 supports LDO charger function with 50mA or 100mA charging current. In charger mode, Q 2 is regulated in saturation region to control the charging current while Q 3 is fully turned on. Please ensure VOUT voltage over 0.6V+BUB Voltage to ensure Q2 stays in saturation region. 12V Car Battery VBAT Vsystem IL VOUT TPS61381-Q1 Isense BUB Linear Driver BUB_ FB Gate Control Gmv CC_ref Gmi LDO_Control BUB_ Vref SW AGND Q3 Q2 Figure 6-4. Linear Charger Structure TPS61381Q supports multiple battery chemistry including NiMH battery, Li-ion battery, LiFePO4 battery and super capacitor. By setting I2C BUB_TYP bits (Register 04H: CHGR_SET1 bit [6:7]), TPS61381Q charges back up battery with the integrated charging profile for the selected battery type. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.4.3 NiMH Battery Charging Profile

In NiMH charging mode, TPS61381-Q1 charges batteries with a time-controlled charging profile consisting of two phases: continuous charge and intermittent charge (optional). Before initiating a NiMH charging cycle, the device checks the battery status. If back up battery voltage (VBUB) is above 1.34V*cell number (Set by I2C bit BUB_CELL, Register 05H: CHGR_SET2), the device consider back up battery as fully charged. The device does not start charging and I2C CHG_DONE bit (Register 08H: CHGR_STATUS) sets 1 to indicate that the charging cycle is done. If the initial back up battery voltage is below 1.34V×cell number, TPS61381Q enters continuous charge phase. The back up battery is charged with constant current controlled by a pre-set timer. Charging current and the duration for continuous charging phase can be programmed by I2C interface (Register 04H to 05H: BUB_CC, BUB_NIMH_TIMER). After timer is done and the continuous charge phase finishes, TPS61381-Q1 sets I2C bit CHG_DONE bit (Register 08H: CHGR_STATUS) to 1 to indicate the charging cycle is done. If the re-charge function is disabled (Set by I2C bit BUB_TER, Register 06H: CHGR_SET3), the IC stops charging after continuous charging phase is finished. User can restart charging by toggling the EN_CHGR pin or I2C CHGR_EN bit, this clears the CHGR_MODE_DONE bit and restart the continuous charge phase. CC Charge Intermittent Charge Charging Stage Register: CHGR_STATUS 0x40 0x58/0x50 CC Timer BUB_NIMH_TIMER[1:0] Charge Current: BUB_CC OVP Voltage: VBUB_OVP Battery Voltage Charge Current Disable Recharge: BUB_TER = 0 Figure 6-5. NiMH Battery Charging Profile， Re-charge Disabled www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS61381-Q1

If the re-charge is enabled (Set by I2C bit BUB_TER, Register 06H: CHGR_SET3), the device enters intermittent charging phase after continuous charging phase is finished. In this phase, the IC replenishes the natural self-discharge of NiMH by charging the battery intermittently with pulse charge cycle (2s on and 58s off). Charge Current: BUB_CC OVP Voltage: VBUB_OVP CC Charge Intermittent Charge Charging Stage Register: CHGR_STATUS 0x40 0x58/0x50 CC Timer BUB_NIMH_TIMER[1:0] Intermittent Timer 58s 2s Intermittent Timer 58s 2s Intermittent Timer 58s 2s Battery Voltage Charge Current Enable Recharge: BUB_TER = 1 Figure 6-6. NiMH Battery Charging Profile， Re-charge Enabled TPS61381-Q1 monitors the battery voltage during all charging phases, if the battery voltage is above 1.70V×cell number, the device stops charging and set I2C bit BUB_OVP (Register 0CH: FAULT_CONDITION) to 1 to indicate a overvoltage protection. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.4.4 Lithium Battery Charging Profile

In Lithium charging mode, TPS61381-Q1 charges batteries with a voltage-controlled charging profile consisting of four phases: trickle charge, pre-charge, CC charge and CV charge. When the back up battery voltage is below V BUB_SHORT threshold, the device enters trickle charge phase. In this phase, the device charges the battery by 12.5mA to ensure safety of the Lithium battery. When the battery voltage is charged to V BUB_SHORT threshold but still below V BUB_LOWV threshold , the device enters pre-charge phase. In this phase, the device charges the battery with 20% of the CC current set in I2C BUB_CC bits (Register 05H: CHGR_SET2). Lithium battery within this voltage range is considered as normal but low battery, so charging current is limited at 20% of CC current to protect battery life. If the battery voltage does not reach V BUB_LWV threshold within 30 minutes. The battery is considered damaged and internal short-circuit. The IC terminates charging and I2C bit BUB_SHORT (Register 0CH: FAULT_CONDITION) is set to 1 to indicate a battery short situation. After battery voltage reaches VBUB_LOWV threshold, the device enters CC charge phase. In this phase, the device charges the battery by CC current (Set by I2C Register 05H: CHGR_SET2, BUB_CC bits). After battery is charged to its target voltage (Set by I2C bits BUB_CV and BUB_CELL), TPS61381-Q1 enters CV charge phase. The device decrease charging current to regulate battery voltage until the charging current drops below termination threshold I TERM(Set by Register 06H: CHGR_SET3, CHG_TEM_CURRENT bit), then the device terminate charging. If configured as recharge disabled (By I2C bits BUB_TER), the device does not re-charge after terminated unless the EN_CHGR pin or CHGR_EN bit is toggled. Trickle Charge Charging Stage Register: CHGR_STATUS 0x80 Pre Charge Timer (30min) Safety Timer SAFT_TIMER ITERM ITERM Pre ChargeCC Charge CV Charge 0x40 0x20 0x18/0x10 Battery Voltage Charge Current Disable Recharge: BUB_TER = 0 IBUB_SHORT IPRE_CHG VBUB_SHORT VBUB_LOWV CV Voltage: BUB_CV CC Current: BUB_CC Figure 6-7. Lithium-based Battery Charging Profile, Re-Charge Disabled www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS61381-Q1

If configured as recharge enabled, the device pause charging temporary and automatically re-charge when BUB voltage drops below VRECHG threshold. Trickle Charge Charging Stage Register: CHGR_STATUS 0x80 Pre Charge Timer (30min) Safety Timer SAFT_TIMER ITERM Battery Voltage Charge Current Enable Recharge: BUB_TER = 1 IBUB_SHORT IPRE_CHG VBUB_SHORT VBUB_LOWV CV Voltage: BUB_CV CC Current: BUB_CC Recharge Voltage VRECHG_HYS ITERM Pre ChargeCC Charge CV Charge Safety Timer SAFT_TIMER 0x40 0x20 0x18/0x10 0x20 Figure 6-8. Lithium-based Battery Charging Profile, Re-Charge Enabled TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.4.5 Super Capacitor Charging Profile

In super capacitor charging mode, TPS61381-Q1 charges batteries with a voltage-controlled charging profile consisting of two phases:CC Charge, CV Charge. When the back up super capacitor voltage is below target voltage (Set by I2C bits BUB_CV and BUB_CELL) , the device enters CC charge phase. In this phase, the device charges the super capacitor by CC current configured by BUB_CC bits. After super capacitor is charged to its target voltage, TPS61381-Q1 enters CV charge phase. The device decrease charging current to regulate the super capacitor voltage until the current drops below a pre-set threshold, then the device terminate charging. If configured as recharge disabled (By I2C bits BUB_TER), the device does not re-charge after terminated unless the EN_CHGR pin or CHGR_EN bit is toggled. Charging Stage Register: CHGR_STATUS 0x40 Safety Timer SAFT_TIMER ITERM CC Charge CV Charge 0x20 0x18/0x10 Battery Voltage Charge Current Disable Recharge: BUB_TER = 0CV Voltage: BUB_CV CC Current: BUB_CC ITERM Figure 6-9. Supercap Charging Profile, Re-Charge Disabled www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS61381-Q1

If configured as recharge enabled, the device pause charging temporary and automatically re-charge when BUB voltage drops below VRECHG threshold. Charging Stage Register: CHGR_STATUS 0x40 Safety Timer SAFT_TIMER Battery Voltage Charge Current Enable Recharge: BUB_TER = 1CV Voltage: BUB_CV CC Current: BUB_CC Recharge Voltage VRECHG_HYS ITERM CC Charge CV Charge Safety Timer SAFT_TIMER 0x20 0x18/0x10 0x20 Figure 6-10. Supercap Charging Profile, Re-Charge Enabled TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.4.6 Battery Cold, Hot Temperature (TS Pin)

TPS61381-Q1 supports battery low, high temperature moniting function by sensing the voltage on TS pin. The negative temperature coefficient (NTC) thermistor in battery should be connected within a resistor network (Shown in Figure 6-11). TS pin sources 38uA into the resistor network and generate voltage on TS pin during charger and SOH mode. Battery charging is allowed only when the TS pin voltage stays between V COLD and V HOT thresholds (188mA~1.04V). If the battery temperature exceeds normal range and TS pin voltage becomes outside the thresholds, the device stops charging and set the TS_FAULT bit to 1 (Register 0CH: FAULT_CONDITION). Once battery temperature returns to normal range and TS pin voltage returns between threshold, charging operation resumes automatically. The temperature window can be modified by the resistance of the resistor network: R p = − 1.23 R HT − R L T + 0.73 R LT − R HT R LT − R HT + 24156 7.6 × 10 − 5 ∙ R L T − R H T − 1.704 (1) R s = 1.23 R LT − R HT + 0.73 R L T − R HT R L T − R HT + 24156 1.704 − 1.22 R L T + 0.22 R HT (2) Where RHT & RLT are the NTC resistance under your highest & lowest temperature Charger FunctionIL VOUT TPS61381-Q1 VCC 1.04V 188mV TS_FAULT Stop Charging TSRs Rp Figure 6-11. TS resistor network for modified temperature window Taking 103AT-2 as an example, the recommended resistor values for different temperature charging windows are given below: Table 6-5. Recommended Resistor Values for Different Temperature Charging Windows TEMPERATURE CHARGING WINDOW RS RP 0°C to 60°C 2.1kΩ 488 kΩ −10°C to 60°C 2.5kΩ 70 kΩ −10°C to 50°C 1.3 kΩ 74 kΩ If temperature sensing is not required in the application, connect a fixed 10-k Ω resistor from TS to GND to disable temperature sensing and protection. www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPS61381-Q1

6.4.7 Charger Protection and Fault Condition Indication

TPS61381-Q1 applies multiple fault protection function to ensure battery life and safety during charging operation. Fault conditions of the charger operation can be monitored through I2C regisiter (Register 0CH: FAULT_CONDITION). When these fault condition occurs, the device pauses charging operation and set the corresponding I2C register bit high to indicate the fault condition. Fault Item Description Fault Indication Device Behavior CHGR_RVS

• Charger reverse current protection.
• Triggered when VOUT < VBUB + 100mV. No Flag
• Pause charging
• Pause charger timer.
• Recover automatically when fault condition is removed SYSTEM_OVP
• System overvoltage protection fault.
• Triggered when VOUT >23V. Indicated by Register 0CH: FAULT_CONDITION, SYSTEM_OVP bit TS_FAULT
• Battery out of cold/hot temperature range
• Triggered when TS pin voltage >1.04V or <188mV Indicated by Register 0CH: FAULT_CONDITION, TS_FAULT bit BUB_SHORT
• Battery short-circuit fault for Li-ion/LiFePO4 battery
• Triggered when BUB voltage is still <VBUB_LOWV after 30 minutes charging
• Only availible for Li-ion and Li-FePO4 battery Indicated by Register 0CH: FAULT_CONDITION, BUB_SHORT bit
• Stop charging.
• Does not recover automatically
• Toggle EN_CHGR pin or CHGR_EN bit to reset fault status BUB_OVP
• Battery over voltage fault
• NiMH battery: Triggered when BUB voltage >1.7V per cell
• Other battery type: Triggered when BUB voltage is 4% over target voltage Indicated by Register 0CH: FAULT_CONDITION, BUB_OVP bit TIMER_FAULT
• Charger safety timer fault for Li-ion and Li-FePO4
• Triggered when charging time out of safety timer range Indicated by Register 0CH: FAULT_CONDITION, TIMER_FAULT bit THRM_SD
• Thermal shutdown
• Triggered when junction temperature >175°C Indicated by Register 0CH: FAULT_CONDITION, THRM_SD bit
• Pause charging.
• Reset charger timer
• Recover automatically when fault condition is removed TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.5 Boost Feature Description

The TPS61381-Q1 integrates synchronous boost converter with load disconnect function. The boost function supports input voltage from 0.5V to 13V and output voltage up to 12V with 5-15A programmable average input current limit. The boost function operates with fixed 400kHz switching frequency with optional spread spectrum to achieve EMI performance for automotive applications.

6.5.1 Enable and Start up

TPS61381-Q1 enable its boost function EN_BST pin is high and I2C BST_EN bit is both 1. After boost function is enabled, the TPS61381-Q1 keeps monitoring VOUT voltage and enters boost mode when VOUT drops below wake up voltage threshold. When entering boost mode, TPS61381-Q1 checkes its BUB pin voltage for undervoltage lockout (UVLO) boosting only when BUB voltage is over UVLO threshold. TPS61381-Q1 applies 30us start-up time to ensure its boost can start up quickly when power interruption of your system is detected. So the boost start up current can be up to its input current limit (default 15A). Set I2C current limit to 5A before enable boost if you need a smaller start up current and slower start up. www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPS61381-Q1

6.5.1.1 Automatic Transition into Boost Mode

For back-up power application, TPS61381-Q1 detects system voltage with VOUT pin (Connected to your system power rail) and automatically transition into boost mode when a power interruption of your system is detected. Taking automatic boost and standby mode as an example, the device works in standby mode when Vout is normal. When the power failure occurs and Vout drops below than min{V BST_WAKEUP(Set by I2C bits BST_WAKE), VBST_STANDBY (BST_VOUT ×106%)}, the device enters boost mode to maintain the output voltage. When the 12V main battery recovers and Vout rises higher than VBST_STANDBY, the device enter standby mode. The VBST_WAKEUP is configured to BST_VOUT ×103% (BST_WAKE = 111b) by default to achieve smaller voltage drop during transition into boost mode. But TPS61381-Q1 also allows configuring V BST_WAKEUP lower than boost output voltage to avoid entering boost mode at temporary voltage drop like cold crank conditions. User can decide to choose higher V BST_WAKEUP for smaller voltage drop or choose lower V BST_WAKEUP to avoid entering boost mode at cold crank condition and improve back up battery life. Operating Mode Register: CONTROL_STATUS 0x81 12V Battery Normal Voltage: Boost Vout: Standby Mode Boost Mode 0x98/0x88 0x91/0x81 Diode Vf VBST_STANDBY: VBST_WAKEUP: Standby Mode 106% Boost Vout 12V Battery Voltage (VBAT) System Voltage (VOUT) Figure 6-12. Case1: VBST_WAKEUP > BST_VOUT Operating Mode Register: CONTROL_STATUS 0x81 12V Battery Normal Voltage: Boost Vout: Standby Mode Boost Mode 0x98/0x88 0x91/0x81 VBST_STANDBY: VBST_WAKEUP: Standby Mode Diode Vf 106% Boost Vout 12V Battery Voltage (VBAT) System Voltage (VOUT) Figure 6-13. Case2: VBST_WAKEUP < BST_VOUT TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.5.1.2 Manual Transition into Boost Mode

TPS61381Q also supports manual transition into boost mode by controlling external EN pins. Manual transition by EN pins allows user to shutdown the IC when 12V battery voltage is normal and saves quiescent current. But external voltage detection circuit and MCU are required to control EN pins. The device requires 50us(t EN_delay1) delay time to initialize its internal circuit from shutdown mode. After initialized, the device takes about 20μs(tEN_delay2) delay time from standby mode to boost mode. For back up power applications, TI suggests setting up two threshold to enable our device. Use the V Pre-WAKEUP threshold to control EN_CHGR pin and initialize the deivce in advance. And use the V BST_EN threshold to control EN_BST pin. This EN sequence can reduce the delay time entering boost mode (Only tEN_delay2). Operating Mode EN Pin Signal: 12V Battery Normal Voltage: Boost Vout: Shutdown Mode Boost Mode VPre_ENABLE: VBST_EN: Diode Vf 12V Battery Voltage (VBAT) System Voltage (VOUT) tEN_Delay_1 tEN_Delay_2 EN_CHGR EN_BST Inductor Current (IL) Figure 6-14. Manual Transition into Boost Mode www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPS61381-Q1

6.5.2 Down Mode

The TPS61381-Q1 enters down mode when BUB voltage is higher than output voltage during boost mode. During downmode TPS61381-Q1 high-side and low-side FETs works the same way as in boost operation, while the isolation FET Q 3 is regulated in saturation region during high side on phase. This allows the device to regulate its output voltage at target value even when VBUB > VOUT. With its Q3 operates in saturation region, downmode generates a lot of loss and heat compared to normal boost operation. Therefore current limit threshold is reduced in downmode to avoid overheating. When BUB-VOUT is over 8V, the peak inductor current is limited to 2.33A. When BUB-VOUT is between 4-8V, the peak current limit is 2.95A. When BUB-VOUT is between 0-4V, the peak current limit is 4.41A. Also, because of the high loss and low efficiency, this mode is only for start up and output short protection. Please avoid V BUB > V OUT condition during normal operation.

6.5.3 Output Short- to-Ground Protection

TPS61381-Q1 applies optional output short protection to protect the IC from damage during output short-circuit condition. The short circuit protection is disabled by default and can be enabled by I2C SCP_EN bits. If the output short occurred and the output voltage is pulled below the BUB voltage, the device enters short circuit protection operation in which downmode is applied to control inductor current. For system safety, TI recommends enabling short circuit protection function. After SCP_EN bit is enabled and short circuit protection is triggered, TPS61381-Q1 applies peak current limit to protect the IC from overheating. When BUB-VOUT is over 8V, the peak inductor current is limited to 2.33A. When BUB-VOUT is between 4-8V, the peak current limit is 2.95A. When BUB-VOUT is between 0-4V, the peak current limit is 4.41A. TPS61381-Q1 applies hiccup control for short circuit protection to avoid overheating in downmode, the device keeps switching for 2ms, stopping for 65ms and repeats this cycle to reduce the average current and power consumption.

6.5.4 Boost Control Loop

TPS61381-Q1 applies fix-frequency peak current control scheme, the internal oscillator supports 400kHz switching frequency. The TPS61381-Q1 operates with fixed-frequency pulse width modulation (PWM) from medium to heavy load. At the beginning of each switching cycle, the low-side N-MOSFET switch is turned on. The inductor current ramps up to a peak current that is determined by the output of the internal error amplifier (V EA). Once the switching peak current triggers the output of the EA, the low-side N-MOSFET is turned off and the high-side N-MOSFET is turned on after a short dead time. The high-side N-MOSFET switch is not turned off until the next cycle as determined by the internal oscillator. The low-side switch turns on again after a short dead time and the switching cycle is repeated.

6.5.5 Current Limit Operation

TPS61381-Q1 implements both peak current and average inductor current limit function to protect the device from overload and back up battery from over-discharging. The average current limit can be programmed by I2C BST_ILIM bits. Besides the average current limit, peak current limit protection is applied to protect the device against overcurrent conditions. In boost operation, the peak current limit threshold is determined by average current limit. With the average current limit set to 5A or 10A, the peak current is limited to 15A, otherwise the peak current is limited to 30A. The peak current limit can enable or disable by I2C BST_ILIM_EN bit. In downmode operation, the peak current limit is reduced depending on VOUT and BUB voltage to avoid IC overheating. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.5.6 Functional Modes at Light Load

In light load condition, the TPS61381-Q1 can work in either auto PFM or forced PWM (FPWM) mode to meet different application requirements. Auto PFM mode decreases switching frequency under light load. This strategy reduces switching loss and improves higher efficiency at light load condition. FPWM mode force the converter to keep switching with fixed frequency under light load. FPWM improves EMI performance and reduces output ripple, but sacrifices light load efficiency compared to PFM mode. TPS61381-Q1 is configured to auto PFM mode by default. Write I2C BST_PFM bit (Register 01H, BOOST_SET1) as 1 to switch to FPWM mode. Care must be taken for back up power applications, FPWM allows reverse current into back up battery when VOUT is higher than boost output target. Reverse current into BUB is usually not favorable for the back up battery. So TI recommend PFM mode during transition into boost mode.

6.5.6.1 Auto PFM Mode

The TPS61381-Q1 can apply auto PFM operation to improve efficiency at light load. Auto PFM mode is applied by enabling the PFM function in the internal register. When the TPS61381-Q1 operates at light load condition, the output of the internal error amplifier decreases to make the inductor peak current down and deliver less power to the load. When the inductor current decreases to I CLAMP_LOW (peak current approximately 4A), the output voltage of the error amplifier is clamped by the internal circuit and does not further reduce. If the load current reduces further, the inductor current is clamped and V OUT will increase. When the output voltage hits the PFM reference voltage (101.5% Vout_target), the device pauses switching. The load is supplied by the output capacitor, and the output voltage declines. When the output voltage falls below 100.5% Vout_target, the device starts switching again to ramp up the output voltage. Heavy Load Light Load Tipping Load PWM PFM Inductor Current Load Current Output Voltage VOUT_TARGET 101.5% VOUT_TARGET 100.5% VOUT_TARGET ICLAMP_LOW Figure 6-15. PWM and PFM operation www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPS61381-Q1

6.5.6.2 Forced PWM Mode

TPS61381-Q1 can also apply force PWM (FPWM) operation to reduce output ripple and improve EMI performance. In the FPWM mode, the TPS61381-Q1 keeps the switching frequency constant in light load condition. When the load current decreases, the output of the internal error amplifier decreases as well to keep the inductor current down and deliver less power from input to output. When the output current further reduces, the current through the inductor decreases to zero during the off-time. The high-side MOSFET is not turned off even if the current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs to zero. The power flow is from output side to input side. The efficiency is low in this mode. But with the fixed switching frequency, there is no audible noise and other problems which might be caused by low switching frequency in light load condition. Heavy Load Light Load Medium Load PWM Inductor Current Load Current Output Voltage VOUT_TARGET Figure 6-16. PWM and PFM operation

6.5.7 Duty Cycle Limitation

TPS61381-Q1 triggers maximum duty cycle limitation when the low-side MOS off time is about 100ns. When VBUB is too low and the max duty cycle is met, the device clampes its duty and output voltage can not be regulated. So the avilable Vin range is limited by: V BU B < 1 − D mi n V O U T (3) V BU B > t OF F mi n V OU T f s w (4)

6.5.8 BUB Voltage Loop

The TPS61381-Q1 applies BUB voltage loop to protect back up battery with high internal impedance. like batteries at low battery, cold temperature or the end of its life. This function allows the battery to output its maximum power and maitain its voltage over boost UVLO threshold when the battery has high internal resistance and cannot output enough power for the output. This function is enabled by I2C BST_VINLOOP_EN bits and the input target voltage is programmed by BST_VINLOOP bits. When the BUB voltage is higher than input target voltage, the BUB voltage loop is not activated. When the BUB voltage is lower than input target voltage, the BUB voltage loop takes over the controlling loop and try decreasing its inductor current to maintain its input voltage. So by allowing the V OUT to drop below VOUT_TARGET, TPS61381-Q1 turns to control its input voltage by which the battery can match its output impedence with internal impedence and output its maximum power. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.5.9 Spread Spectrum

TPS61381-Q1 implements optional switching frequency dithering for boost function to improve the EMI performance. The device uses a triangle jitter to spread the switching frequency by ±7% . The modulation frequency of the spread spectrum is optional programmable by I2C BST_SS bits. Table 6-6. Spread Spectrum and Optional Modulation Frequency BST_SS Bits Spread Spectrum Modulation Frequency

00 No Spread Spectrum No Spread Spectrum

01 ±7% Spread Spectrum 6.5 kHz 10 ±7% Spread Spectrum 3.2 kHz 11 ±7% Spread Spectrum 1.6 kHz

6.6 Battery State-of-Health (SOH) Detection Feature Description

The battery state-of-health (SOH) detection function allows TPS61381-Q1 to detect the internal resistance of the backup battery (BUB). When the EN_CHGR pin is high and CHGR_SOH_EN=10b, the SOH function is enabled. After enabled, the device enters SOH mode when VOUT> wake up voltage. In SOH mode, the backup battery is discharged by a constant current programmed by I2C SOH_I bits. During the test, the TPS61381-Q1 AVI pin can be configured to output the backup battery’s voltage, discharge current and the battery temperature with the ratio selected by I2C. Connect AVI pin to your MCU ADC to acquire and calculate internal resistance. The ISO FET Q3 is turned on during SOH mode. So TI suggests the output voltage is higher than BUB voltage during SOH operation to avoid inrush current through high side body diode. www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TPS61381-Q1

6.6.1 SOH Mode Operation

During SOH mode, the TPS61381-Q1 fully turns on its isolation MOSFET Q3 and regulate the gate voltage of the low-side MOSFET Q2 with LO pin. In this way, low side MOSFET operates in saturation area and discharge the back up battery by constant current. TI recommend 500mA discharge current to achieve best accuracy. By sensing the battery open voltage, voltage with discharge current and discharge current, the battery internal resistance Rbatcan be given by: R bat = V o p en − V di s c ℎ g I d i s c ℎ g (5) where:

• Vopen is the battery voltage without discharge current
• Vdischg is the battery voltage with discharge current
• Idischg is the discharge current According to the recommendation from battery manufacturer , it is recommened to discharge battery with 500mA Idischg for 500ms and then read Vdischg 12V Car Battery VBAT Vsystem IL VOUT TPS61381-Q1 –LO Iref_SOH Isense SW BUB AVI Output BUB sense AVI ADC MCU Q3 Q2 Figure 6-17. Typical Operation of SOH TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.6.2 Multi-Signal Output in AVI Pin

The AVI pin can output three optional signals, battery voltage, battery discharge current and battery temperature. The output item is selected by I2C SOH_AVI_EN bits. So MCU can use one ADC channel to read all signal and help ADC resource can be saved. The AVI pin voltage is limited to <3.3V to protect MCU ADC pin. The ratio from measured item to AVI output can be selected by I2C AVI_I_RATIO or AVI_V_RATIO bits. TI recommend AVI_I_RATIO = 2 with 500mA discharge current to achieve best accuracy 12V Car Battery VBAT Vsystem IL VOUT TPS61381-Q1 BUB AVI Output BUB sense AVI ADC MCU SOH_AVI_EN SW VCC Rs Rp Isense TS sense I2C Block SCL SDA GPIO GPIO Q3 Q2 Figure 6-18. AVI pin connection

6.6.3 Calculate Impedance of BUB

Steps below gives an example on how to calculate the internal impedance of the back up battery with your system MCU :

• Set SOH discharge current to 0A (Register 0x09: SOH_SET1, SOH_I bits)
• Set AVI pin ratio to the backup battery voltage as 1 (Register 0x10: SOH_SET2, SOH_V_RATIO bits)
• Set AVI pin ratio to the discharge current as 2 (Register 0x10: SOH_SET2, SOH_I_RATIO bits)
• Select AVI pin output as battery voltage (Register 0x10: SOH_SET2, SOH_AVI_EN bits)
• Enable SOH function (Register 0x0B: CONTROL_STATUS, CHGR_SOH_EN bits)
• Wait for about 1ms for AVI output voltage to stabilize.
• Read the back-up battery voltage at AVI pin with the MCU ADC (VBUB1)
• Set SOH discharge current to 500mA (Register 0x09: SOH_SET1, SOH_I bits)
• Discharge for 500ms (Depending on battery characteristic, NiMH usually requires 500ms).
• Read the back-up battery voltage at AVI pin with the MCU ADC (VBUB2)
• Select AVI pin output as discharge current (Register 0x10: SOH_SET2, SOH_AVI_EN bits)
• Wait for about 1ms for AVI output voltage to stabilize.
• Read the discharge current at AVI pin with the MCU ADC (IBUB2) MCU can use below equation to calculate the internal impedance of the back-up battery and detect the battery state of health. R BU B = V BU B 1 − V B U B 2 / I BU B (6) www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TPS61381-Q1

6.7 I2C Serial Interface

The TPS61381-Q1 uses I2C interface for flexible converter parameter programming. I2C is a bi-directional 2-wire serial interface. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). I 2C devices can be considered as masters or slaves when performing data transfers. A master is the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave. The TPS61381-Q1 operates as a slave device with address 31h. Receiving control inputs from the master device like a microcontroller or a digital signal processor reads and writes the internal registers 00h through 0Eh. The I2C interface of the TPS61381-Q1 supports both standard mode (up to 100 kbit/s) and fast mode plus (up to 400 kbit/s). Both SDA and SCL must be connected to the positive supply voltage through current sources or pullup resistors. When the bus is free, both lines are in high voltage.

6.7.1 Data Validity

The data on the SDA line must be stable during the high level period of the clock. The high level or low level state of the data line can only change when the clock signal on the SCL line is low level. One clock pulse is generated for each data bit transferred. Data line stable Data valid Change of data allowed SDA SCL Figure 6-19. I2C Data Validity

6.7.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A high level to low level transition on the SDA line while SCL is at high level defines a START condition. A low level to high level transition on the SDA line when the SCL is at high level defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition. START (S) SDA SCL STOP (P) Figure 6-20. I2C START and STOP Conditions TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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6.7.3 Byte Format

Every byte on the SDA line must be eight bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL. 1 2 7 8 9 1 2 8 9 S or Sr P or Sr START or Repeated START STOP or Repeated START MSB Acknowledgement signal from slave Acknowledgement signal from receiver SCL SDA Figure 6-21. Byte Format

6.7.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line to low level and it remains stable low level during the high level period of this clock pulse. The Not Acknowledge signal is when SDA remains high level during the 9 th clock pulse. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

6.7.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is seven bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). 1 - 7 8 9 S START SCL SDA 1 - 7 8 9 1 - 7 8 9 ADDRESS R/W ACK DATA ACK DATA ACK P STOP Figure 6-22. Slave Address and Data Direction www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TPS61381-Q1

6.7.6 Single Read and Write

The images below show the single-byte write and single-byte read format of the I2C communication. S 0 ACKSlave Address Register Address ACK Data to Address ACK P 1 7 1 1 8 1 8 1 1 Figure 6-23. Single-byte Write S 0 ACKSlave Address Register Address ACK Data from Address NACK P 1 7 1 1 8 1 8 1 1 S 1 ACKSlave Address 1 7 1 1 From master to slave From slave to master Figure 6-24. Single-byte Read If the register address is not defined, the TPS61381-Q1 sends back NACK and goes back to the idle state.

6.7.7 Multi-Read and Multi-Write

The TPS61381-Q1 supports multi-read and multi-write. S 0 ACKSlave Address Register Address ACK 1 7 1 1 8 1 Data to Address ACK 8 1 P Data to Address + 1 ACK 8 1 Data to Address + N ACK 8 1 Figure 6-25. Multi-byte Write S 0 ACKSlave Address Register Address ACK Data from Address ACK 1 7 1 1 8 1 8 1 S 1 ACKSlave Address 1 7 1 1 Data from Address + 1 ACK 8 1 Data from Address + N NACK 8 1 P Figure 6-26. Multi-byte Read TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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7 Register Maps

Table 7-1 lists the memory-mapped registers for the device registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations, and the register contents should not be modified. Table 7-1. Device Registers Address Register Name Type Description Section 00H CHIP_ID R DIE_TYPE provides information on the chip and silicon revision 01H BOOST_SET1 R/W Boost set1: frequency, PFM or FPWM, spread spectrum, short protection, output discharge 02H BOOST_SET2 R/W Boost set2: Vout, current limit 03H BOOST_SET3 R/W Boost set2: BUB voltage loop, boost wake up threshold. 04H CHGR_SET1 R/W Charger set1: battery type, CV voltage, NiMH timer. 05H CHGR_SET2 R/W Charger set2: cell number, CC current 06H CHGR_SET3 R/W Charger set3: termination current 07H CHGR_SET4 R/W Charger set4: safety timer 08H CHGR_STATUS R Charger status: pre-charge, CC phase, CV phase, charge done, 09H SOH_SET1 R/W SOH set1: discharge current 0AH SOH_SET2 R/W SOH set2: AVI pin to current ratio, AVI pin to voltage ratio, AVI output selection. 0BH CONTROL_STATUS R/W or R Control status: Boost enable, charger or SOH enable, boost active, charger active, SOH active, standby active. 0CH FAULT_CONDITION R Fault flag: Vout OVP, battery is OVP, thermal shutdown signal, short, out of safety time and out of temperature and device thermal shutdown 0DH STATUS_PIN_SET R/W STATUS pin output selection: including boost, charger done and thermal shutdown 0EH SW_RST W Software reset: resets the entire part to its original default conditions www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TPS61381-Q1

7.1 Register 00H: CHIP_ID

Figure 7-1. CHIP_ID 7 6 5 4 3 2 1 0 CHIP_ID R-00001100b Table 7-2. CHIP_ID Register Field Descriptions Bit Field Type Reset Description [7:0] CHIP_ID R 0x0C Provides information on the chip and silicon version. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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7.2 Register 01H: BOOST_SET1

Figure 7-2. BOOST_SET1 7 6 5 4 3 2 1 0 Reserved BST_PFM BST_PFM BST_SCP Reserved R/W-0b R/W-0b R/W-01b R/W-0b R/W-000b Table 7-3. BOOST_SET1 Register Field Descriptions Bit Field Type Reset Description [7] Reserved R 0 Reserved [6] BST_PFM R/W 0 0 = PFM, auto PFM at light load 1 = FPWM, force PWM at light load TI recommend PFM for bi-directional application. [5:4] BST_SS R/W 01b 00b = no spread spectrum 01b = 6.5 kHz modulation frequency 10b = 3.2 kHz modulation frequency 11b = 1.6 kHz modulation frequency [3] BST_SCP R/W 0 0 = Boost output short circuit protection disabled 1 = Boost output short circuit protection enabled TI recommend enabling short circuit protection for system safety. [2:0] Reserved R 000b Reserved www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: TPS61381-Q1

7.3 Register 02H: BOOST_SET2

Figure 7-3. BOOST_SET2 7 6 5 4 3 2 1 0 BST_VOUT Reserved BST_ILIM BST_ILIM_EN R/W-0011b R-0b R/W-10b R-1b Table 7-4. BOOST_SET2 Register Field Descriptions Bit Field Type Reset Description [7:4] BST_VOUT R/W 0011b Set output target voltage 0000b=5V 0001b=5.5V 0010b=6V 0011b=6.2V 0100b=6.5V 0101b=6.8V 0110b=7.1V 0111b=7.5V 1000b=8V 1001b=8.5V 1010b=9V 1011b=9.5V 1100b=10V 1101b=10.5V 1110b=11V 1111b=12V [3] Reserved R 0 Reserved [2:1] BST_ILIM R/W 10b Boost average current limit 00b=5A 01b=10A 10b=15A [0] BST_ILIM_EN R/W 1 0=disable boost peak current limit 1=enable boost peak current limit If average current=5A or 10A, the peak current limit is 15A; otherwise the peak current limit is 30A. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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7.4 Register 03H: BOOST_SET3

Figure 7-4. BOOST_SET3 7 6 5 4 3 2 1 0 BST_VINLOOP BST_VINLOOP _EN BST_WAKE Reserved R/W-10b R/W-0b R/W-111b R-00b Figure 7-5. BOOST_SET3 Register Field Descriptions Bit Field Type Reset Description [7:6] BST_VINLOOP R/W 10b Set input voltage regulation voltage 00b=1V 01b=1.2V 10b=1.5V 11b=2V [5] BST_VINLOOP_EN R/W 0 0=disable input voltage loop 1=enable input voltage loop [4:2] BST_WAKE R/W 111b Set boost automatically wake-up threshold, VOUT falling 000b=4.5V 001b=5V 010b=5.5V 011b=6V 100b=6.5V 101b= 7.5V 110b=8V 111b=Vout_target+3% [1:0] Reserved R 00b Reserved www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: TPS61381-Q1

7.5 Register 04H: CHGR_SET1

Figure 7-6. CHGR_SET1 7 6 5 4 3 2 1 0 BUB_TYP BST_VINLOOP_EN BST_WAKE R/W-00b R/W-0000b R/W-00b Figure 7-7. CHGR_SET1 Register Field Descriptions Bit Field Type Reset Description [7:6] BUB_TYP R/W 00b Set the back-up battery charging strategy 00b=Li-ion charging profile, precharge+CC+CV 01b=LiFePO4 charging profile, precharge+CC+CV 10b=NiMH charging profile, CC + timer 11b=Super capacitor charging profile, CC+CV [5:2] BUB_CV R/W 0000b Set CV voltage 0000b=1.7V (supercap) 0001b=2.0V (supercap) 0010b=2.2V (supercap) 0011b=2.4V (supercap) 0100b=2.5V (supercap) 0101b=2.7V (supercap) 0110b=3.0V (supercap) 0111b=3.5V (LiFePO4) 1000b=3.6V (LiFePO4) 1001b=3.7V (LiFePO4) 1010b=3.8V (Li-ion) 1011b=3.9V (Li-ion) 1100b=4.05V (Li-ion) 1101b=4.10V (Li-ion) 1110b=4.20V (Li-ion) 1111b=4.35V (Li-ion) Note: this register is inactive for NiMH battery. [1:0] BUB_NIMH_TIMER R/W 00b Set the NiMH battery charging time 00b=4h 01b=8h 10b=16h 11b=32h TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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7.6 Register 05H: CHGR_SET2

Figure 7-8. CHGR_SET2 7 6 5 4 3 2 1 0 BUB_CELL Reserved BUB_CC R/W-000b R-000b R/W-00b Figure 7-9. CHGR_SET2 Register Field Descriptions Bit Field Type Reset Description [7:5] BUB_CELL R/W 000b The number cell of back-up battery Li-ion supports up to 2s, NiMH support up to 5s Supercap support up to 4s 000b=1 001b=2 010b=3 011b=4 100b=5 [4:2] Reserved R 000b Reserved [1:0] BUB_CC R/W 00b Set CC current 00b=50mA 01b=100mA www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: TPS61381-Q1

7.7 Register 06H: CHGR_SET3

Figure 7-10. CHGR_SET3 7 6 5 4 3 2 1 0 Reserved BUB_TER CHG_TEM_CU RRENT Reserved R-00000b R/W-0b R/W-0b R-0b Figure 7-11. CHGR_SET3 Register Field Descriptions Bit Field Type Reset Description [7:3] Reserved R 00000b Reserved [2] BUB_TER R/W 0 After fully charged, re-charge or not. For NiMH battery, enable intermittent charging For Li-ion, LiFePO4 or super capacitor battery, start recharge when battery voltage is lower than recharge voltage. 0=disable re-charge 1=enable re-charge [1] CHG_TEM_CURRENT R/W 0 0= 10% * Icc 1=20% * Icc Note: this bit is active for Li-ion, LiFePO4 and super capacitor. [0] Reserved R 0 Reserved TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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7.8 Register 07H: CHGR_SET4

Figure 7-12. CHGR_SET4 7 6 5 4 3 2 1 0 SAFT_TIMER_ EN SAFT_TIMER CHG_TEM_CURRENT R/W-1b R/W-1b R-00000b Figure 7-13. CHGR_SET4 Register Field Descriptions Bit Field Type Reset Description [7] SAFT_TIMER_EN R/W 1 0=disable the safety time of Li-ion charger 1= enable the safety time of Li-ion charger [6] SAFT_TIMER R/W 1 0=5hr 0=10hr [5:0] Reserved R 00000b Reserved www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: TPS61381-Q1

7.9 Register 08H: CHGR_STATUS

Figure 7-14. CHGR_STATUS 7 6 5 4 3 2 1 0 CHGR_MODE_ PRE CHGR_MODE_ CC CHGR_MODE_ CV CHGR_MODE_ DONE ALRT_CHGR_ MODE_DO NE Reserved R-0b R-0b R-0b R-0b R-0b R-000b Figure 7-15. CHGR_STATUS Register Field Descriptions Bit Field Type Reset Description [7] CHGR_MODE_PRE R 0 Read only that provides information on the charger operation mode 0=Charger is not operating in pre-charge stage 1=Charger is operating in pre-charge stage [6] CHGR_MODE_CC R 0 Read only that provides information on the charger operation mode 0=Charger is not operating in CC stage 1=Charger is operating in CC stage [5] CHGR_MODE_CV R 0 Read only that provides information on the charger operation mode 0=Charger is not operating in CV stage 1=Charger is operating in CV stage [4] CHGR_MODE_DONE R 0 Read only that provides information on the charger operation mode 0= Charge done not triggered. 1= Charge done triggered. [3] ALRT_CHGR_MODE_DO NE R 0 Read only that provides information on the charger operation mode. 0= charging is no done since the last read 1=charging is done since the last read Latch after set, clear-on-read [2:0] Reserved R 000b Reserved TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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7.10 Register 09H: SOH_SET1

Figure 7-16. SOH_SET1 7 6 5 4 3 2 1 0 SOH_I Reserved R/W-000b R-00000b Figure 7-17. SOH_SET1 Register Field Descriptions Bit Field Type Reset Description [7:5] SOH_I R/W 000b Set SOH discharge current 000b=0A 001b=100mA (Recommend AVI_I_RATIO=2) 010b=200mA (Recommend AVI_I_RATIO=2) 011b=300mA (Recommend AVI_I_RATIO=2) 100b=500mA (Recommend AVI_I_RATIO=2) 101b=800mA (Recommend AVI_I_RATIO=2) 110b=1A (Recommend AVI_I_RATIO=2) 111b=1.5A (Recommend AVI_I_RATIO=1) [4:0] Reserved R 00000b Reserved www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: TPS61381-Q1

7.11 Register 0AH: SOH_SET2

Figure 7-18. SOH_SET2 7 6 5 4 3 2 1 0 AVI_I_RATIO AVI_V_RATIO Reserved SOH_AVI_EN R/W-01b R/W-10b R-00b R/W-00b Figure 7-19. SOH_SET2 Register Field Descriptions Bit Field Type Reset Description [7:6] AVI_I_RATIO R/W 01b AVI pin ratio to the discharge current. The voltage of AVI pin = AVI_I_RATIO × discharge current 00b=1/2 01b=1 10b=2 [5:4] AVI_V_RATIO R/W 10b AVI pin ratio to the back-up battery voltage. The voltage of AVI pin = AVI_V_RATIO × back-up battery voltage 00b=1/4 (Recommended for 2S Lithium, 3-4S super capacitor) 01b=1/2(Recommended for 1S Lithium, 2-4S NiMH, 2S super capacitor) 10b=1 (Recommended for 1S NiMH, 1S super capacitor) [3:2] Reserved R 00b Reserved [1:0] SOH_AVI_EN R/W 00b Enable AVI pin output and choose I, V or T output signal 00b=disable AVI pin output, internal 125kΩ pulldown to AGND. 01b=Enable back-up battery voltage output 10b=Enable discharge current output 11b=Enable battery temperature output TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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7.12 Register 0BH: CONTROL_STATUS

Figure 7-20. CONTROL_STATUS 7 6 5 4 3 2 1 0 BST_EN CHGR_SOH_EN ALRT_BST_AC TIVE BST_ACTIVE CHGR_ACTIVE SOH_ACTIVE STANDBY_ACT IVE R/W-1b R/W-00b R-0b R-0b R-0b R-0b R-0b Figure 7-21. CONTROL_STATUS Register Field Descriptions Bit Field Type Reset Description [7] BST_EN R/W 1 0=disable boost function 1= enable boost function [6:5] CHGR_SOH_EN R/W 00b 00b=disable charger and SOH function 01b= enable charger function 10b=enable SOH function [4] ALRT_BST_ACTIVE R 0 Read only. Provides information about the system operating mode 0= boost mode has not been activated since the last read 1= boost mode has been activated since the last read Latch after set, clear-on-read [3] BST_ACTIVE R 0 Read only. Provides information about the system operating mode 0= boost mode is not active 1= boost mode is active [2] CHGR_ACTIVE R 0 Read only. Provides information about the system operation mode 0=charger mode is not active 1= charger mode is active [1] SOH_ACTIVE R 0 Read only. Provides information about the system operation mode 0=SOH mode is not active 1= SOH mode is active [0] STANDBY_ACTIVE R 0 Read only. Provides information about the system operation mode 0=standby mode is not active 1= standby mode is active www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: TPS61381-Q1

7.13 Register 0CH: FAULT_CONDITION

Figure 7-22. FAULT_CONDITION 7 6 5 4 3 2 1 0 SYSTEM_OVP TS_FAULT BUB_SHORT TIMER_FAULT BUB_OVP THRM_SD Reserved R-0b R-0b R-0b R-0b R-0b R-0b R-00b Figure 7-23. FAULT_CONDITION Register Field Descriptions Bit Field Type Reset Description [7] SYSTEM_OVP R 0 0=No overvoltage on VOUT pin 1=Overvoltage on VOUT pin [6] TS_FAULT R 0 0= TS pin voltage is within cold/hot temperature threshold 1= TS pin voltage is out of cold/hot temperature threshold [5] BUB_SHORT R 0 0= No short circuit on Li-ion/LiFePO4 battery 1= Short circuit on Li-ion/LiFePO4 battery Note: this bit only active for Li-ion/LiFePO4 battery [4] TIMER_FAULT R 0 0= Within safety time 1= Out of safety time [3] BUB_OVP R 0 0= No overvoltage on battery 1= Overvoltage on battery [2] THRM_SD R 0 0=no thermal shutdown 1= thermal shutdown (Tj > 175degC) [1:0] Reserved R 00b Reserved TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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7.14 Register 0DH: STATUS_PIN_SET

Figure 7-24. STATUS_PIN_SET 7 6 5 4 3 2 1 0 INC_BST INC_ABST INC_ADN INC_TSD INC_TSFAULT Reserved R-1b R-0b R-0b R-0b R-0b R-000b Figure 7-25. STATUS_PIN_SET Register Field Descriptions Bit Field Type Reset Description [7] INC_BST R/W 1 0= BST_ACTIVE status is not included in the STATUS pin output, STATUS pin pulls low when entering boost mode 1= BST_ACTIVE status is included in the STATUS pin output Check Section 7.12 for discriptions of BST_ACTIVE signal [6] INC_ABST R/W 0 0= ALRT_BST_ACTIVE status is not included in the STATUS pin output, STATUS pin pulls low when boost mode is entered since last read 1= ALRT_BST_ACTIVE status is included in the STATUS pin output Check Section 7.12 for discriptions of ALRT_BST_ACTIVE signal [5] INC_ADN R/W 0 0= ALRT_CHGR_MODE_DONE status is not included in the STATUS pin output, STATUS pin pulls low when charger operation is done since last read 1= ALRT_CHGR_MODE_DONE status is included in the STATUS pin output Check Section 7.9 for discriptions of ALRT_CHGR_MODE_DONE signal [4] INC_TSD R/W 0 0= THRM_SD status is not included in the STATUS pin output, STATUS pin pulls low when thermal shutdown is triggered 1= THRM_SD status is included in the STATUS pin output Check Section 7.13 for discriptions of THRM_SD signal [3] INC_TSFAULT R/W 0 0= TS_FAULT status is not included in the STATUS pin output, STATUS pin pulls low when TS_FAULT is triggered 1= TS_FAULT status is included in the STATUS pin output Check Section 7.13 for discriptions of TS_FAULT signal [2:0] Reserved R 000b Reserved www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: TPS61381-Q1

7.15 Register 0EH: SW_RST

SW_RST (software reset) is a write-only register/command that resets the entire part to its original default conditions at the end of the I2C SW_RST transaction (i.e., the data-byte ACK). Execution only occurs if DIN[7:0]=0x00. The effect of a SW_RST is identical to power-cycling the part. TPS61381-Q1 also support hardware reset, when the two EN pins are both low(EN_BST=0 AND EN_CHGR=0), the entire registers are reset to its original default conditions. Figure 7-26. SW_RST 7 6 5 4 3 2 1 0 CHIP_ID W-00000000b Table 7-5. SW_RST Register Field Descriptions Bit Field Type Reset Description [7:0] SW_RST W 00000000b resets the entire part to its original default conditions TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

TPS61381-Q1 is a bi-directional boost converter with CC/CV charger and battery health detection function. The device provides an integrated power solution in back-up power system, like T-box and e-call applications. The following design procedure can be used to design TBOX system with TPS61381-Q1.

8.2 Typical Application

Figure 8-1 shows a typical application circuit for the TPS61381-Q1. This device is designed to charge BUB when VBAT is normal when VBAT is normal and boost BUB energy to Vsystem when VBAT is disconnected. TPS61381-Q1 VBAT Vsystem SW BOOT IL BUB TS VOUT VCC STATUS LO AVI EN_BST EN_CHGR SCL SDA COMP MCU AGNDEP Net_Tie:10-20mil trace or 0ohm resistor NT1 Vds>30V 10-30µF 0.1-1µF 0603 0-3 220-470nF 2.2µH 0.1-1µF 0603 >40V 10µFx4 >40V 100µF >40V 4.7µF R4 10k MCU_GPIO_VDD MCU_GPIO_VDD ADC GPIO GPIO GPIO GPIO GPIO 10k 12nF 100pF C10 100µF >40V AGND PGND Figure 8-1. Typical TBOX Application www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: TPS61381-Q1

8.2.1 Design Requirements

The following table provides the parameters for our detailed design procedure example: Table 8-1. Design Requirements PARAMETERS VALUES Car Battery Input Voltage: Typical: 6~18V, load damp: up to 40V Back-up Battery 3s NiMH Back-up Battery Voltage: 3 ~ 4.5V Charging Current: 100mA Charging Time 8h Battery Health Detection Current: 500mA Boost Output Voltage: 6.2V Boost Output Current: 4A Mode Selection Automatic Charger and Boost Mode Voltage Drop during Mode Transient <=200mV

8.2.2 Detailed Design Procedure

8.2.2.1 Selecting the External MOSFET

TPS61381-Q1 requires an external MOSFET (Q1) as its boost low side switch and SOH discharge switch. The external MOSFET is selected depending on its thermal performance, VDS voltage and Id current.

• TPS61381-Q1 supports only n-channel MOSFET as Q1.
• Recommend Qgd< 5nC. Qgd should not exceed 10nC at most.
• Vplateau<4V.
• Rdson low as possible. Recommend Rdson less than 15mohm at most
• The drain-source breakdown voltage, V(BR)DSS >= 30V
• The continuous drain current should be larger than the maximum peak current in the boost mode: I peak = I O U T 1 − D ⋅ e f f + V BU B ⋅ D

2 L ⋅ f sw (7)

• IOUT is the maximum load current in boost mode.
• D is the duty cycle of boost operation
• eff is the boost mode efficiency
• L is the boost inductance
• fsw is the switching frequency in boost mode
• VBUB is the input voltage on BUB pin TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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8.2.2.2 Inductor Selection

A boost converter normally requires two main passive components for storing energy during power conversion: an inductor and an output capacitor. The inductor affects the steady state efficiency (including the ripple and efficiency), transient behavior, and loop stability, which makes the inductor the most critical component in application. When selecting the inductor and the inductance, the other important parameters are:

• The maximum current rating (RMS and peak current should be considered)
• The series resistance
• Operating temperature The TPS61381-Q1 has built-in slope compensation to avoid subharmonic oscillation associated with current mode control. If the inductor value is too low and makes the inductor peak-to-peak ripple higher than 2 A, the slew rate of its slope compensation may not be adequate, and the loop can be unstable. Therefore, it is recommended to make the peak-to-peak current ripple between 1.2A to 2 A when selecting the inductor. The inductance can be calculated by: L = V B UB 1 − V B U B ⋅ e f f V OU T Δ I L ⋅ f s w (8) So, TI suggests 2.2μH for 400kHz switching frequency. The current flowing through the inductor is the inductor ripple current plus the average input current. During power up, load faults, or transient load conditions, the inductor current can increase above the peak inductor current calculated. Inductor values can have ±20%, or even ±30%, tolerance with no current bias. When the inductor current approaches the saturation level, the inductance can decrease 20% to 35% from the value at 0-A bias current, depending on how the inductor vendor defines saturation. When selecting an inductor, make sure the rated current, especially the saturation current, is larger than its peak current during the operation. The inductor peak current varies as a function of the load, switching frequency, and input and output voltages. The peak current can be calculated by: I peak = I O U T 1 − D ⋅ e f f + V BU B ⋅ D

2 L ⋅ f sw (9)

Select the inductor with a saturation current rating higher than the maximum inductor current. where

• Ipeak is the peak current of the inductor
• IOUT is the output current
• D is the duty cycle
• eff is the efficiency
• VBUB is the input voltage
• L is the inductance
• ƒSW is the switching frequency The heat rating current (RMS) is can be calculated with: I L RMS = I B U B 2 + Δ I L 2 / 12 (10) www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: TPS61381-Q1

• ILRMS is the RMS current of the inductor
• IBUB is the input current of the inductor
• ΔIL is the ripple current of the inductor It is important that the peak current does not exceed the inductor saturation current and the RMS current is not over the temperature-related rating current of the inductors. For a given physical inductor size, increasing inductance usually results in an inductor with lower saturation current. The total losses of the coil consists of the DC resistance (DCR) loss and the following frequency- dependent loss:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect) For a certain inductor, the larger current ripple (smaller inductor) generates the higher DC and also the frequency-dependent loss. An inductor with lower DCR is basically recommended for higher efficiency. However, it is usually a tradeoff between the loss and foot print. Table 8-2 lists some recommended inductors. In this application example, the Coilcraft inductor XGL6060-222 is selected for its small size, high saturation current, and small DCR. Table 8-2. Recommended Inductors for the TPS61381-Q1 PART NUMBER L (µH) DCR TYPICAL(mΩ) SATURATION CURRENT (A) HEAT RATING CURRENT (A) SIZE (L × W × H) VENDOR(1) B82464D6222M000 2.2 9 11.8 (10% Drop) 13.85 (30% Drop) 6 (ΔT 40K) 10.4 × 10.4 × 6.3 TDK (1) See the Third-Party Products disclaimer

8.2.2.3 Capacitor in Back-Up Battery Side

The capacitance in the back-up battery side affects BUB loop stability. The effective capacitance should be between 5μF to 10 μF BUB loop functions needs to be applied. If BUB loop function is not required, then the capacitance in BUB side can be big without limit. Care must be taken when evaluating a ceramic capacitor’s effective capacitance. For ceramic capacitors, the derating under dc bias voltage, aging, and ac signal should be taken into consideration. Taking Murata GCM21BR71C475KA73K as an example, the capacitor's effective capacitance reduces by 56% when 8V DC voltage is applied. If back up battery is connected to the IC through long cable, TI recommend adding extra 100-200uF electrolytic capacitors on BUB side. This capacitor helps supress LC ringing caused by parasite inductance on back up battery cable. Note that the electrolytic capacitor cannot replace ceramic capacitor and 5 μF to 10 μF ceramic capacitor still needs to be placed near the IC. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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8.2.2.4 Selecting the Output Capacitor

Main consideration for designing the output capacitor is the requirements for the output voltage drop when main battery fails and the device transition into boost mode. The minimum Cout can be calculated by: C ou t > I ou t max × 20 us Δ V o ut max (11) Where

• COUT is the output capacitance
• IOUTMAX is the maximum output current
• ΔVOUTMAX is the maximum output voltage drop allowed when transition into boost mode 20us is the maximum transition time for the device to enter boost mode and start switching The output ripple voltage another factor that affects the Cout selection. Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by C ou t > I ou t max × V o ut − V BU B f s w × Δ V × V o u t (12) Where
• IOUT is the output current
• VOUT is the output DC voltage
• VBUB is the back up battery voltage
• ΔV is the output voltage ripple required
• fswis the switching frequency Typically, a combination of ceramic capacitors and bulk electrolytic capacitors is needed to provide low ESR, high ripple current, and small output voltage ripple. Ceramic capacitors has DC-bias derating that significantly reduce the effective capacitance when a DC-voltage is applied. So please check the DC-bias curve at Boost Vout target voltage when calculating the capacitance. Electrolytic capacitors has large ESR and the ESR of electrolytic capacitor can increase by over 10 times under low temperature condition and seriously affect loop stability. So please make sure low temperature ESR is considered when calculating loop stability. Poly-hybrid capacitors usually has smaller ESR under low temperature and is therefore more recommended. Based on the application requirement, this application choose 100uF electrolytic capacitor with four 10uF ceramic capacitors in parallel. www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: TPS61381-Q1

8.2.2.5 Loop Stability and Compensation Design

The TPS61381-Q1 requires external compensation, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external compensation network, comprised of resistor R5, and ceramic capacitors C8 and C9, is connected to the COMP pin. Compensation parameter need to be calculated case by case. Following section gives an example about how to calculate the compensation network parameters with the selected inductor and output capacitor. TPS61381-Q1 VBAT Vsystem SW BOOT IL BUB TS VOUT VCC STATUS LO AVI EN_BST EN_CHGR SCL SDA COMP AGNDEP Net_Tie:10-20mil trace or 0ohm resistor NT1 Vds>25V 30-100µF 0.1-1µF 0603 0-3 220-470nF 2.2µH 0.1-1µF 0603 >40V 10µFx4 >40V 100µF >40V 4.7µF R4 10k MCU_GPIO_VDD ADC GPIO GPIO GPIO GPIO GPIO 10k 12nF 100pF C10 100µF >40V AGND PGND Compensation Parameter Figure 8-2. TPS61381-Q1 Compensation Design TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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8.2.2.5.1 Small Signal Analysis

The TPS61381-Q1 uses the fixed frequency peak current mode control with an internal adaptive slope compensation to avoid subharmonic oscillation. With the inductor current information sensed, the small-signal model of the power stage reduces from a two-pole system, created by L and C OUT, to a single-pole system, created by ROUT and COUT. The single-pole system is easily used with the loop compensation. The image below shows the equivalent small signal elements of a boost converter. RESR FB RUP VOUT RCOMP VREF GEA COUTVOUT ROUT ISENSE Slope Comp L CIN VIN R SQ Q Q RSENSE REA RDOWN Q CCOMP CHF Figure 8-3. TPS61381-Q1 Control Equivalent Circuitry Model The small signal of power stage can be given by: K PS s = R ou t 1 − D

2 R s en s e ×

2 π × f zE SR 1 − s 2 π × f zRHP 1 + s 2 π × f p PS (13) where

• D is the duty cycle
• Rout is the output load resistance
• Rsense is the equivalent internal current sense resistor, which is typically 6mΩ The single pole of the power stage can be given by: f p PS = 2 2 π × C ou t × R ou t (14) where
• Cout is the output capacitance. For a boost converter having multiple identical output capacitors in parallel, simply combine the capacitors with the equivalent capacitance The zero created by the ESR of the output capacitor can be given by: f z ESR = 1 2 π × C o u t × R ES R (15) where
• RESR is the equivalent resistance in series of the output capacitor The right-hand plane zero can be given by: www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: TPS61381-Q1

f zR HP = R o u t 1 − D 2 2 π × L (16) where

• D is the duty cycle
• Rout is the output load resistor
• L is the inductance Equation 17 shows the equation for feedback resistor network and the compensation network. H CO MP s = G c o mp × R E A × R u p + R d ow n R do w n × 1 + s 2 π × f zC OMP s 1 + s 2 π × f p CO MP 1 1 + s 2 π × f p C OMP 2 (17) where
• GCOMP is the gain of the error amplifier, typically GEA = 24uS
• REA is the output impedance of the error amplifier, typically REA = 5 MΩ
• ƒpCOMP1, ƒpCOMP2 is the pole's frequency of the compensation
• fzCOMP is the zero’s frequency of the compensation network ƒpCOMP1 can be given by: f p CO MP 1 = 1 2 π × R E A × C C OMP (18) where
• CCOMP is the compensation capacitor ƒpCOMP2 can be given by: f p CO MP 2 = 1 2 π × R C OMP × C HF (19) where
• CHF is the high frequency bypass capacitor on COMP pin
• RCOMP is the resistor of the compensation network ƒzCOMP can be given by: f z CO MP = 1 2 π × R C OMP × C C OMP (20) where
• CCOMP is the zero capacitor compensation
• RCOMP is the resistor of the compensation network

8.2.2.5.2 Loop Compensation Design

With the previous analysis on small signal models, we can calculate the compensation network parameters with the given inductor and output capacitor parameters. This section gives an example on calculating loop compensation. 1. Set the Crossover Frequency, ƒC . The first step is to set the loop crossover frequency, ƒC. The higher the crossover frequency, the faster the loop response is. It is generally accepted that the loop gain crosses over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒzRHP. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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1. Set the Compensation Resistance, RCOMP . For a well compensated boost system, the fC is determined by RCOMP. For a properly designed boost system, ƒzCOMP should be placed below ƒC to ensure phase margin. And for common RCOMP range, RCOMP should be far smaller than the amplifier output resistance REA, which makes RCOMP | | REA ~ = RCOMP. Therefore, in the equation below, the initial gain RCOMP × GCOMP × KFB is determined by RCOMP. Therefore the fc can be calculated by the equation that the close loop total gain T(s) = KPS(s) + HCOMP(s) is zero at ƒC. H CO MP = 20 l g G CO MP × R CO MP × R d ow n R up + R d o wn = − K PS f c (21) where

• KPS is the gain of the power stage
• GEA is the transconductance of the amplifier, the typical value of GEA = 24 µS 3. Set the Compensation Zero capacitor, CCOMP . The compensation zero should be placed at the power stage pole fpPS to compensate the phase drop near fpPS. Set ƒZ = ƒP, the CCOMP can be calculated . C CO MP = R o u t × C o u t

2 R C OMP (22)

1. Set the Compensation Pole Capacitor, CHF . The compensation pole should be placed to elimiate the ESR zero produced by RESR and Cout. Set ƒpCOMP2 = ƒzESR, and get: C HF = R E SR × C o ut R C OMP (23) 5. Check Phase Margin and Gain Margin The calculated compensation parameters does not always ensure stability. Especially when the Cout has big ESR which bring fzESR into bandwidth. TI provide excel calculation tool which generates bode plot after all compensation parameters are selected. So please check the bode plot for stability after step 1-4. TI recommend Phase margin > 60deg and gain margin > 10db. Reduce desired fc and re-calculate compensation in step1-4 if the margin does not meet requirement. Bandwidth Phase Margin Gain Margin Check Stability Figure 8-4. Evaluate Loop Stability www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: TPS61381-Q1

8.2.3 Application Curves

Vout (6.2V o set) 100mV/div IL 2A/div Time Scale: 2µs/div VBUB = 3.6V VOUT = 6.2V IOUT = 4A Figure 8-5. Boost Switching at Heavy Load SW 5V/div Vout (6.2V o set) 100mV/div IL 2A/div Time Scale: 100µs/div VBUB = 3.6V VOUT = 6.2V IOUT = 100mA Figure 8-6. Boost Switching at Light Load Vout (6.2V o set) 500mV/div Iout 2A/div Time Scale: 400µs/div VBUB = 3.6V VOUT = 6.2V IOUT = 10mA to 4A Figure 8-7. Load Transient at Boost Mode IL 2A/div Vout (6.2V o set) 500mV/div Iout 2A/div Time Scale: 10ms/div VBUB = 3.6V VOUT = 6.2V IOUT = 10mA to 4A Figure 8-8. Load Sweep at Boost Mode BUB 2V/div IL 5A/div Time Scale: 10ms/div Vout (6.2V o set) 200mV/div VBUB = 2.5V to 4V VOUT = 6.2V IOUT = 2A Figure 8-9. Line Transient at Boost Mode BUB 2V/div IL 5A/div Time Scale: 10ms/div Vout (6.2V o set) 200mV/div VBUB = 2.5V to 4V VOUT = 6.2V IOUT = 2A Figure 8-10. Line Sweep at Boost Mode SW 5V/div IL 5A/div Time Scale: 20µs/div Vout 5V/div VBUB = 3.6V VOUT = 6.2V Figure 8-11. Boost Output Short Protection SW 2V/div IL 5A/div Time Scale: 20ms/div Vout 2V/div VBUB = 3.6V VOUT = 6.2V Figure 8-12. Boost Output Short Hiccup TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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Time Scale: 20ms/div VBAT 10V/div Vout 10V/div VBAT = 12V to 40V VBUB = 3.6V IOUT = 0A Figure 8-21. 12V Battery Load Dump Time Scale: 20ms/div VBAT 2V/div Vout 2V/div SW 5V/div IL 5A/div VBUB = 3.6V VOUT = 6.2V IOUT = 2A Figure 8-22. 12V Battery Cold Crank TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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8.3 Power Supply Recommendations

The characteristics of the input supply must be capable of delivering the required input current to the loaded regulator. The average input current can be estimated with the following equation. I BU B = V o ut × I ou t V BU B × η (24) where

• η is the efficiency If the regulator is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR ceramic input capacitors, can result in LC resonant circuit. This can result in overvoltage transients at the input to the regulator or tripping UVLO. Consider that the supply voltage can dip when a load transient is applied to the output depending on the parasitic resistance and inductance of the harness and characteristics of the supply. If the application is operating close to the minimum input voltage, this dip can cause the regulator to momentarily shut down and reset. The best way to solve these kinds of issues is to reduce the distance from the input supply to the regulator. Additionally, use an aluminum input capacitor in parallel with the ceramics. The moderate ESR of this type of capacitor helps damp the input resonant circuit and reduce any overshoots or undershoots. A value in the range of 47µF to 100µF is usually sufficient to provide input damping and help hold the input voltage steady during large load transients.

8.4 Layout

8.4.1 Layout Guidelines

The PCB layout of any DC-DC converter is critical to the excellent performance of the design. Bad PCB layout generates extral noise and therefore disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly in some preliminary tests, bad PCB layout still affects reliability and increases risk under mass production. Furthermore, the EMI performance of the regulator is dependent on the PCB layout to a great extent. In a boost converter, the most EMI-critical PCB feature is the loop formed by the output capacitor and low side MOSFET ground. This loop carries discontinuous currents with high di/dt which generates high voltage spikes on layout parasitic inductance. Excessive transient voltages can disrupt the proper operation of the converter, affect EMI and even damage the MOSFET. In order to reduce parasitic inductance on layout, ceramic Cout need to be placed as close to Vout pin as possible (within 1mm) and low side MOSFET Q1 should be placed as close to SW pin as possible. TI also recommend a smaller Cout (100nF-1uF, 0603 package) closest to the Vout pin to bypass the high frequency noise. Avoid connecting this smaller Cout through vias. Besides Cout loop, GND connection is also very important to avoid switching noise form affecting the IC. There are risks that the IC internal circuit get out of control or even damage if AGND is not connected correctly. Make sure that there’s a separate AGND from PGND and connect VCC, COMP , AGND pin, thermal pad to AGND. AGND need to be connected to PGND by single point (net-tie, 0ohm resistor or 10-20mil width trace). The net-tie should be connected by a seprate, short trace between low side MOSFET source (PGND) and AGND pad of VCC capacitor. View Section 8.4.2 for detailed routing eaxmple on GND connection. Place the VCC capacitor close to the VCC pin and AGND pin: This capacitor must be routed with short, wide traces to the VCC pin and AGND pin. Make layer 2 of the PCB a ground plane: This plane operates as a noise shield and as a heat dissipation path. Using layer 2 as GND plane reduces the enclosed area of the Cout loop and reduces parasitic inductance. Provide wide polygon pour for IL, SW, VOUT, and PGND(Low side MOSFET source): These paths must be as wide and direct as possible to reduce any voltage drops on the input or output paths of the converter to maximize efficiency. www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: TPS61381-Q1

Provide enough copper plane for proper heat sinking: Enough copper area must be applied to ensure low R θJA under heavy load and high temperature. Apply at least 4-layer board with two-ounce copper the top and bottom PCB layers. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes. Note that the package of this device dissipates heat through all pins. Wide traces can be used for all pins except where noise considerations dictate minimization of area

8.4.2 Layout Example

According to the previous analysis on GND connection. The net-tie between AGND and PGND should be connected between source of the low side MOSFET and AGND pad of VCC capacitor. Driver current return path is cut out from PGND copper and routed seprately in pararllel with the gate trace as differential pairs so that their mutual inductance can eliminate parasite inductance. Also, VCC Cap should be placed closed to the IC as possible. LO VCC Cap Seprate Trace VCC Cap PGND AGND Top Layer Bottom Layer Bottom Trace Top Trace MOSFET Source AGND Pad AGND Pad Seprate Trace Net-Tie Figure 8-23. GND Connection Layout Example TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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D G S BUB IL SW VOUT PGNDPGND AGND Figure 8-24. TPS61381Q typical layout top layer www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: TPS61381-Q1

D G S PGND Figure 8-25. TPS61381Q typical layout top bottom TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Performing Accurate PFM Mode Efficiency Measurements Application Report
• Texas Instruments, Accurately Measuring Efficiency of Ultra-low-IQ Devices Technical Brief
• Texas Instruments, IQ: What it is, What it isn’t, and How to Use it Techanical Brief

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES March 2024 * Initial release www.ti.com TPS61381-Q1 SLVSHK6 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: TPS61381-Q1

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPS61381-Q1 SLVSHK6 – MARCH 2025 www.ti.com

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS61381QRAVRQ1 Active Production WQFN-FCRLF (RAV) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 S61381Q TPS61381QRAVRQ1.A Active Production WQFN-FCRLF (RAV) | 24 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 S61381Q (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Apr-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS61381QRAVRQ1 WQFN- FCRLF Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Apr-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS61381QRAVRQ1 WQFN-FCRLF RAV 24 3000 346.0 346.0 33.0 Pack Materials-Page 2

A A www.ti.com PACKAGE OUTLINE 3.1 2.9 4.1 3.9 0.8 0.6 1.5 .000 PKG 0 0.5 0.5 1.5 0.737 0.05 1.225 0.1 2X 1.25 .000 PKG 0 2X 0.75 2X 0.25 2X 0.25 2X 0.75 2X 1.25 0.488 0.05 3X 0.125 0.05 0.819 0.1 1.5 0.5 0.5 1.5 26X 0.3 0.2 2X 0.625 0.05 0.875 0.05 0.625 0.05 0.625 0.05 0.875 0.05 1.35 0.05 1.35 0.05 0.01 0.00

0.1 MIN

11X 0.5 0.3 (0.18) TYP (0.125) TYP (0.1) (0.2) (0.125) TYP 2X (0.625) 2X (0.375) (0.375) 3X (1.375) 3X (1.25) (0.65) (0.525) (0.75) WQFN-FCRLF - 0.8 mm max heightRAV0024A PLASTIC QUAD FLATPACK - NO LEAD 4229510/D 04/2025 0.08 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE

0.1 C A B

0.05 C 2024 PIN 1 ID (45 X 0.212) SCALE 3.500 A-A40.000 SECTION A-A TYPICAL AB C

www.ti.com EXAMPLE BOARD LAYOUT .000 PKG 0 .000 PKG 0

0.05 MAX

0.05 MIN

( ) 1.5 ( ) 1 ( ) 0.5 ( ) 0.5 ( ) 1 ( ) 1.5 ( ) 0.737 ( ) 1.9 4X ( ) 2.2 4X ( ) 2.2 ( ) 0.875 ( ) 0.625 ( ) 0.625 ( ) 0.875 2X ( ) 2.2 2X ( ) 2.2 ( ) 1.7 ( ) 1.25 2X ( ) 0.75 ( ) 0.488 2X ( ) 0.25 2X ( ) 0.25 2X ( ) 0.625 7X ( ) 1.7 ( ) 1.5 ( ) 1 ( ) 0.5 ( ) 0.5 ( ) 1 ( ) 1.5 3X ( ) 0.125 2X ( ) 0.625 4X ( ) 1.375 ( ) 1.875 ( ) 1.875 2X ( ) 0.75 2X ( ) 1.25 (1.225) (0.819) 15X (0.25) 11X (0.6) 11X (0.25) ( ) 1.35 ( ) 1.35 ( ) 1.9 (R0.05) TYP (R0.05) TYP WQFN-FCRLF - 0.8 mm max heightRAV0024A PLASTIC QUAD FLATPACK - NO LEAD 4229510/D 04/2025 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. LAND PATTERN EXAMPLE SCALE: 20X (45 X 0.212) 8 12 METAL UNDER SOLDER MASK TYP SOLDER MASK OPENING TYP METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED SOLDER MASK DETAILS METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN ( ) 1.9 .000 PKG 0 ( ) TYP 1.7 .000 PKG 0 ( ) 1.9 ( ) 1.5 ( ) 1 ( ) 0.5 ( ) 0.5 ( ) 1 ( ) 1.5 6X ( ) 2.2 6X ( ) 2.2 ( ) 0.387 ( ) 1.087 ( ) 2.013 ( ) 1.5 ( ) 1 ( ) 0.5 ( ) 0.5 ( ) 1 ( ) 1.5 ( ) 2.013 ( ) 1.9 ( ) 1.263 ( ) 1.11 ( ) 0.355 ( ) 0.355 ( ) 1.11 ( ) 1.263 ( ) TYP 1.7 ( ) 1.4 2X ( ) 1.25 2X ( ) 0.75 2X ( ) 0.25 2X ( ) 0.488 2X ( ) 0.25 ( ) TYP 1.7 2X ( ) 0.75 2X ( ) 1.25 2X ( ) 0.82 2X ( ) 0.575 2X ( ) 0.29 2X (0.725) 2X (0.42) 2X (0.85) 2X (0.51) 4X (0.375) 7X (0.5) 11X (0.6) 26X (0.25) (0.8) 2X (0.5) 2X (0.36) 2X (0.3) (R0.05) TYP WQFN-FCRLF - 0.8 mm max heightRAV0024A PLASTIC QUAD FLATPACK - NO LEAD 4229510/D 04/2025 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE FUSED PAD 11 - 14 & 18-20: 62% FUSED PAD 15-17: 68% PAD 25: 79% 8 12 METAL UNDER SOLDER MASK TYP SOLDER MASK OPENING TYP (45 X 0.209)

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