784218AY

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Technical content

Datasheet sections

• 5.1 Port Pins
• 5.2 Non-Port Pins
• 5.3 Pin I/O Circuits and Recommended Connections of Unused Pins
• 6.1 Memory Space
• 6.2 CPU Registers
• 6.2.1 General-purpose registers
• 6.2.2 Control registers
• 6.2.3 Special function registers (SFRs)
• 7.1 Ports
• 7.2 Clock Generator
• 7.3 Real-Time Output Port
• 7.4 Timer/Event Counter
• 7.5 A/D Converter
• 7.6 D/A Converter
• 7.7 Serial Interface
• 7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)
• 7.7.2 Clocked serial interface (CSI)
• 7.8 Clock Output Function
• 7.9 Buzzer Output Function
• 7.10 Edge Detection Function
• 7.11 Watch Timer
• 7.12 Watchdog Timer
• 8.1 Interrupt Sources
• 8.2 Vectored Interrupt
• 8.3 Context Switching
• 8.4 Macro Service
• 8.5 Application Example of Macro Service

µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 16-BIT SINGLE-CHIP MICROCONTROLLERS Document No. U14121EJ2V0DS00 (2nd edition) Date Published August 2000 N CP(K) Printed in Japan DATA SHEET

DESCRIPTION

The µPD784214A, 784215A, 784216A, 784217A, and 784218A are products of the µPD784216A/784218A Subseries in the 78K/IV Series. Besides a high-speed and high perform ance C PU, these controllers have R OM, RAM, I/O ports, 8-bit resolution A/D and D /A converters, tim ers, serial interfaces, a real-tim e output port, interrupt functions, and various other peripheral hardware. The µPD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are based on the µPD784216Y/784218Y Subseries with the addition of a multimaster-supporting I 2C bus interface. The µPD78F4218A and 78F4218AY, products with a flash memory instead of the internal R OM of m ask R OM versions, and various development tools are also available. Detailed function descriptions are provided in the follow ing user’s manuals. Be sure to read them before designing. µµPD784216A, 784216AY Subseries User’s Manual Hardware: U13570E µµPD784218A, 784218AY Subseries User’s Manual Hardware: U12970E 78K/IV Series User’s Manual Instructions: U10905E

FEATURES

• 78K/IV Series • Supply voltage: V DD = 1.8 to 5.5 V
• Standby function• Inherits peripheral functions of µPD78078, 78078Y Subseries HALT/STOP/IDLE mode
• Minimum instruction execution time 160 ns In low-power consumption mode: HALT/IDLE mode (with subsystem clock) (@fXX = 12.5 MHz operation with main system clock) • Clock division function 61 µs • Watch timer: 1 channel (@fXT = 32.768 kHz operation with subsystem clock) • Watchdog timer: 1 channel
• I/O port: 86 pins • Clock output function
• Tim er/event counter:
• 16-bit timer/event counter × 1 unit Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
• 8-bit timer/event counter × 6 units • Buzzer output function
• Serial interface: 3 channels Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
• UART/IOE (3-wire serial I/O): 2 channels • A/D converter: 8-bit resolution × 8 channels
• CSI (3-wire serial I/O, I2C bus supporting multimaster Note): 2 channels
• D/A converter: 8-bit resolution × 2 channels Note µPD784216AY/784218AY Subseries only

APPLICATIONS

Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment Unless otherwise specified, r eferences in this document to the µµPD784218A, 784218A Y r efer to the µµPD784214A, 784215A , 784216A , 784217A , 784218A , 784214A Y, 784215A Y, 784216AY, 784217AY, and 784218AY. The mark shows major revised points. 2000 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Data Sheet U14121EJ2V0DS002 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

ORDERING INFORMATION

Part Number Package Internal ROM (Bytes) Internal RAM (Bytes) µPD784214AGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

96 K 3,584

µPD784214AGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) µPD784215AGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

128 K 5,120

µPD784215AGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) µPD784216AGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

128 K 8,192

µPD784216AGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) µPD784217AGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

192 K 12,800

µPD784217AGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) µPD784218AGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)

256 K 12,800

µPD784218AGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) µPD784214AYGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784214AYGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) µPD784215AYGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784215AYGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) µPD784216AYGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784216AYGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) µPD784217AYGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784217AYGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) µPD784218AYGC-××× -8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD784218AYGF-××× -3BA 100-pin plastic QFP (14 × 20 mm) Remark ××× indicates ROM code suffix.

Data Sheet U14121EJ2V0DS00 3 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 78K/IV SERIES LINEUP PD784026 PD784956A PD784908 PD784915 PD784928 PD784928Y PD784046 PD784054 PD784216A PD784216AY PD784038 PD784038Y PD784225Y PD784225 PD784218AY PD784218A Enhanced A/D converter, 16-bit timer, and power management Enhanced internal memory capacity Pin-compatible with the PD784026 Supports I 2C bus Supports multimaster I2C bus 80-pin, ROM correction added Supports multimaster I2C bus Enhanced internal memory capacity, ROM correction added 100-pin, enhanced I/O and internal memory capacity On-chip 10-bit A/D converter For DC inverter control On-chip IEBus TM controller Software servo control On-chip analog circuit for VCRs Enhanced timer Supports multimaster I 2C bus Enhanced functions of the PD784915 Standard models ASSP models Supports multimaster I2C bus : Products in mass-production : Products under development µ µ PD784976A On-chip VFD controller/driver µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ PD784938A Enhanced functions of the PD784908, enhanced internal memory capacity, ROM correction added. µ µ PD784967µ Enhanced functions of the PD784938A, enhanced I/O and internal memory capacity. µ

Data Sheet U14121EJ2V0DS004 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY OVERVIEW OF FUNCTIONS (1/2) Part Number Item µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY Number of basic instructions (mnemonics) 113 General-purpose registers 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) Minimum instruction execution time • 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@f XX = 12.5 MHz operation with main system clock)

• 61 µs (@fXT = 32.768 kHz operation with subsystem clock) ROM 96 KB 128 KB 192 KB 256 KBInternal memory RAM 3,584 bytes 5,120 bytes 8,192 bytes 12,800 bytes Memory space 1 MB with program and data spaces combined Total 86 CMOS input 8 CMOS I/O 72 I/O ports N-ch open-drain I/O 6 Pins with pull-up resistor 70 LED direct drive output 22 Pins with additional functions Note 1 Middle-voltage pin 6 Real-time output port 4 bits × 2 or 8 bits × 1 Timer/event counter: Timer counter × 1 Pulse output (16-bit) Capture/compare register × 2 • PPG output
• Square wave output
• One-shot pulse output Timer/event counter 1: Timer counter × 1 Pulse output (8-bit) Com pare register × 1 • PWM output
• Square wave output Timer/event counter 2: Timer counter × 1 Pulse output (8-bit) Com pare register × 1 • PWM output
• Square wave output Timer/event counter 5: Timer counter × 1 Pulse output (8-bit) Com pare register × 1 • PWM output
• Square wave output Timer/event counter 6: Timer counter × 1 Pulse output (8-bit) Com pare register × 1 • PWM output
• Square wave output Timer/event counter 7: Timer counter × 1 Pulse output (8-bit) Com pare register × 1 • PWM output
• Square wave output Timer/event counter Timer/event counter 8: Timer counter × 1 Pulse output (8-bit) Com pare register × 1 • PWM output
• Square wave output Serial interface • UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O, multimaster supporting I 2C busNote 2): 1 channel A/D converter 8-bit resolution × 8 channels D/A converter 8-bit resolution × 2 channels Notes 1. Pins with additional functions are included with the I/O pins. 2. µPD784216AY/784218AY Subseries only

Data Sheet U14121EJ2V0DS00 5 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY OVERVIEW OF FUNCTIONS (2/2) Part Number Item µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY Clock output Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT Buzzer output Selectable from fXX/210, fXX/211, fXX/212, fXX/213 Watch timer 1 channel Watchdog timer 1 channel Standby • HA LT/STOP/IDLE modes

• In low power consumption mode (with sub system clock): HALT/IDLE modes Hardware sources 29 (internal: 20, external: 9) Software sources BRK instruction, BRKCS instruction, operand error Non-maskable Internal: 1, external: 1 Interrupt Maskable Internal: 19, external: 8
• 4 programmable priority levels
• 3 service modes: Vectored interrupt/macro service/context switching Supply voltage VDD = 1.8 to 5.5 V Package 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm)

Data Sheet U14121EJ2V0DS00 7 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Data Sheet U14121EJ2V0DS008 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 1. DIFFERENCES AMONG MODELS IN µµPD784216A, 784216AY/784218A, 784218AY SUBSERIES The only difference am ong the µPD784214A, 784215A, 784216A, 784217A, and 784218A lies in the internal memory capacity. The µPD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are m odels with the addition of an I2C bus control function. The µPD78F4216A, 78F4216AY, 78F4218A, and 78F4218AY are provided w ith a 128 KB/256 KB flash memory instead of the mask ROM of the above models. These differences are summarized in Table 1-1. Table 1-1. Differences Among Models in µPD784216A, 784216AY/784218A, 784218AY Subseries Part Number Item µPD784214A, µPD784214AY µPD784215A, µPD784215AY µPD784216A, µPD784216AY µPD784217A, µPD784217AY µPD784218A, µPD784218AY µPD78F4216A, µPD78F4216AY µPD78F4218A, µPD78F4218AY Internal ROM 96 KB (Mask ROM)

128 KB (Mask ROM) 192 KB

(Mask ROM) 256 KB (Mask ROM) 128 KB (Flash memory) 256 KB (Flash memory) Internal RAM 3,584 bytes 5,120 bytes 8,192 bytes 12,800 bytes 5,120 bytes 12,800 bytes Internal memory size switching register (IMS) Not provided Provided Note ROM correction Not provided Provided Not provided Provided External access status function Not provided Provided Not provided Provided Supply voltage VDD = 1.8 to 5.5 V VDD = 1.9 to 5.5 V Electrical specifications Recommended soldering conditions Refer to the data sheet for each device. EXA pin Not provided Provided Not provided Provided TEST pin Provided Not provided VPP pin Not provided Provided Note The internal flash memory capacity and internal R AM capacity can be changed using the internal m emory size switching register (IMS). Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set w ith the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version.

Data Sheet U14121EJ2V0DS00 9 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 2. MAJOR DIFFERENCES FROM µPD78078Y SUBSERIES Series Name Item µPD784216A, 784216AY/784218A, 784218AY Subseries µPD78078Y Subseries CPU 16-bit CPU 8-bit CPU With main system clock 160 ns (@12.5 MHz operation) 400 ns (@5.0 MHz operation)Minimum instruction execution time With subsystem clock 61 µs (@32.768 kHz operation) 122 µs (@32.768 kHz operation) Memory space 1 MB 64 KB Total 86 88 CMOS input 8 2 CMOS I/O 72 78 I/O ports N-ch open-drain I/O 6 8 Pins with pull-up resistor 70 86 LED direct drive output 22 16 Pins with additional functions Note 1 Middle-voltage pin 6 8 Timer/counter • 16-bit timer/event counter × 1 unit

• 8-bit timer/event counter × 6 units
• 16-bit timer/event counter × 1 unit
• 8-bit timer/event counter × 4 units Serial interface • UART/IOE (3-wire serial I/O) × 2 channels
• CSI (3-wire serial I/O, multimaster supporting I2C busNote 2) × 1 channel
• UART/IOE (3-wire serial I/O) × 1 channel
• CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus) × 1 channel
• CSI (3-wire serial I/O, 3-wire serial I/O with automatic transmit/receive function) × 1 channel NMI pin Provided Not provided Macro service Provided Not provided Context switching Provided Not provided Interrupts Programmable priority 4 levels Not provided Standby function • HA LT/STOP/IDLE modes
• In low power consumption mode: HALT/IDLE modes HALT/STOP modes Package • 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
• 100-pin ceramic WQFN (14 × 20 mm) (µPD78P078Y only) Notes 1. Pins with additional functions are included with the I/O pins. 2. µPD784216AY/784218AY Subseries only

Data Sheet U14121EJ2V0DS0010 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 3. PIN CONFIGURATION (TOP VIEW)

• 100-pin plastic LQFP (fine pitch) (14 ×× 14 mm) µPD784214AGC-××× -8EU, µµPD784215AGC-××× -8EU, µµPD784216AGC-××× -8EU, µPD784217AGC-×××× -8EU, µPD784218AGC-××× -8EU, µµPD784214AYGC-××× -8EU, µµPD784215AYGC-××× -8EU, µPD784216AYGC-××× -8EU, µµPD784217AYGC-××× -8EU, µµPD784218AYGC-××× -8EU 100 76 P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 V DD V SS XT2 XT1 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 AV DDNote 2 AVREF0 P10/ANI0 P62/A18 P61/A17 P60/A16 V SS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P84/A4 P83/A3 P95 P94 P93 P92 P91 P90 TEST Note 1 P37/EXANote 5 P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103/TI8/TO8 P102/TI7/TO7 P101/TI6/TO6 P100/TI5/TO5 V DD P67/ASTB P66/WAIT P65/WR P64/RD P63/A19 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AV SSNote 3 P130/ANO0 P131/ANO1 AV REF1 P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note 4 P26/SO0 P27/SCK0/SCL0Note 4 P80/A0 P81/A1 P82/A2 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 26 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 Notes 1. Connect the TEST pin to V SS directly or via a pull-dow n resistor. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ . 2. Connect the AV DD pin to VDD. 3. Connect the AV SS pin to VSS. 4. The SCL0 and SDA0 pins are available in µPD784216AY/784218AY Subseries products only. 5. The EXA pin is available in µPD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00 11 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

• 100-pin plastic QFP (14 ×× 20 mm) µµPD784214AGF-×××× -3BA, µPD784215AGF-××× -3BA, µPD784216AGF- ×××× -3BA, µµPD784217AGF-××× -3BA, µµPD784218AGF-×××× -3BA, µPD784214AYGF-××× -3BA, µPD784215AYGF- ×××× -3BA, µµPD784216AYGF-×××× -3BA, µPD784217AYGF-××× -3BA, µPD784218AYGF- ×××× -3BA 100 VSS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 P84/A4 P83/A3 P82/A2 P81/A1 P80/A0 P27/SCK0/SCL0 Note 4 P26/SO0 P25/SI0/SDA0 Note 4 P24/BUZ P23/PCL P22/ASCK1/SCK1 P21/TxD1/SO1 P20/RxD1/SI1 P72/ASCK2/SCK2 P71/TxD2/SO2 P70/RxD2/SI2 AV REF1 P131/ANO1 P130/ANO0 AV SSNote 3 P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AV REF0 AVDDNote 2 P60/A16 P61/A17 P62/A18 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB V DD P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/TI00 P36/TI01 P37/EXA Note 5 TESTNote 1 P90 P91 P92 P93 P94 P95 P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 V DD V SS XT2 XT1 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 31 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Notes 1. Connect the TEST pin to V SS directly or via a pull-dow n resistor. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ . 2. Connect the AV DD pin to VDD. 3. Connect the AV SS pin to VSS. 4. The SCL0 and SDA0 pins are available in µPD784216AY/784218AY Subseries products only. 5. The EXA pin is available in µPD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS0012 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY A0 to A19: Address Bus P120 to P127: Port 12 AD0 to AD7: Address/Data Bus P130, P131: Port 13 ANI0 to ANI7: Analog Input PCL: Programmable Clock ANO0, ANO1: Analog Output RD: Read Strobe ASCK1, ASCK2: Asynchronous Serial Clock RESET: Reset ASTB: Address Strobe RTP0 to RTP7: Real-time Output Port AVDD: Analog Power Supply RxD1, RxD2: Receive Data AVREF0, AVREF1: Analog Reference Voltage SCK0 to SCK2: Serial Clock AVSS: Analog Ground SCL0Note 1: Serial Clock BUZ: Buzzer Clock SDA0Note 1: Serial Data EXANote 2: External Access Status Output SI0 to SI2: Serial Input INTP0 to INTP6: Interrupt from Peripherals SO0 to SO2: Serial Output NMI: Non-maskable Interrupt TEST: Test P00 to P06: Port 0 TI00, TI01, P10 to P17: Port 1 TI1, TI2, TI5 to TI8: Timer Input P20 to P27: Port 2 TO0 to TO2, TO5 to TO8: Timer Output P30 to P37: Port 3 TxD1, TxD2: Transmit Data P40 to P47: Port 4 VDD: Power Supply P50 to P57: Port 5 VSS: Ground P60 to P67: Port 6 WAIT: Wait P70 to P72: Port 7 WR: Write Strobe P80 to P87: Port 8 X1, X2: Crystal (Main System Clock) P90 to P95: Port 9 XT1, XT2: Crystal (Subsystem Clock) P100 to P103: Port 10 Notes 1. The SCL0 and SDA0 pins are available in µPD784216AY/784218AY Subseries products only. 2. The EXA pin is available in µPD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00 13 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 4. BLOCK DIAGRAM INTP2/NMI INTP0, INTP1, INTP3 to INTP6 Programmable interrupt controller Real-time output port Timer/event counter 7 (8 bits) Timer/event counter 6 (8 bits) Timer/event counter 5 (8 bits) Timer/event counter 2 (8 bits) Timer/event counter 1 (8 bits) Timer/event counter (16 bits) Watch timer Timer/event counter 8 (8 bits) Watchdog timer TI00 TI01 TO0 TI1 TO1 TI2 TO2 TI5/TO5 TI6/TO6 TI7/TO7 TI8/TO8 NMI/INTP2 RTP0 to RTP7 Clock output control A/D converter AVDD AVSS PCL BUZ AVREF0 ANI0 to ANI7 D/A converter ANO0 AVSS P03/INTP3 AVREF1 ANO1 78K/IV CPU Core ROM RAM Baud-rate generator RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0/SDA0 SO0 SCK0/SCL0 Bus I/F UART/IOE1 RD ASTB WR WAIT A0 to A7 AD0 to AD7 A8 to A15 A16 to A19 Port 1 P10 to P17 Port 0 P00 to P06 Port 2 P20 to P27 Port 3 P30 to P37 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P60 to P67 Port 7 P70 to P72 Port 8 P80 to P87 Port 9 P90 to P95 Port 10 P100 to P103 Port 12 P120 to P127 Port 13 P130, P131 Buzzer output System control RESET XT2 XT1 VSS VDD TEST Clocked serial interface Note 1 Baud-rate generator UART/IOE2 EXANote 2 Notes 1. This function supports the I C bus interface and is available in µPD784216AY/784218AY Subseries products only. 2. The EXA pin is available in µPD784218A, 784218AY Subseries products only. Remark The internal ROM and RAM capacities differ depending on the product.

Data Sheet U14121EJ2V0DS0014 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 5. PIN FUNCTIONS

5.1 Port Pins (1/2)

Pin Name I/O Alternate Function Function P00 INTP0 P01 INTP1 P02 INTP2/NMI P03 INTP3 P04 INTP4 P05 INTP5 P06 I/O INTP6 Port 0 (P0):

• 7-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. P10 to P17 Input ANI0 to ANI7 Port 1 (P1):
• 8-bit input only port P20 RxD1/SI1 P21 TxD1/SO1 P22 ASCK1/SCK1 P23 PCL P24 BUZ P25 SI0/SDA0Note 1 P26 SO0 P27 I/O SCK0/SCL0Note 1 Port 2 (P2):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. P30 TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 TI00 P36 TI01 P37 I/O EXANote 2 Port 3 (P3):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. P40 to P47 I/O AD0 to AD7 Port 4 (P4):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• All pins set in input mode can be connected to on-chip pull-up resistors by means of software.
• LEDs can be driven directly. P50 to P57 I/O A8 to A15 Port 5 (P5):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• All pins set in input mode can be connected to on-chip pull-up resistors by means of software.
• LEDs can be driven directly. Notes 1. This function is available in µPD784216AY/784218AY Subseries products only. 2. This function is available in µPD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00 15 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

5.1 Port Pins (2/2)

Pin Name I/O Alternate Function Function P60 A16 P61 A17 P62 A18 P63 A19 P64 RD P65 WR P66 WAIT P67 I/O ASTB Port 6 (P6):

• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• All pins set in input mode can be connected to on-chip pull-up resistors by means of software. P70 RxD2/SI2 P71 TxD2/SO2 P72 I/O ASCK2/SCK2 Port 7 (P7):
• 3-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. P80 to P87 I/O A0 to A7 Port 8 (P8):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software.
• The interrupt control flag (KRIF) is set to 1 when a falling edge is detected at a pin of this port. P90 to P95 I/O − Port 9 (P9):
• N-ch open-drain middle-voltage I/O port
• 6-bit I/O port
• Input/output can be specified in 1-bit units.
• LEDs can be driven directly. P100 TI5/TO5 P101 TI6/TO6 P102 TI7/TO7 P103 I/O TI8/TO8 Port 10 (P10):
• 4-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. P120 to P127 I/O RTP0 to RTP7 Port 12 (P12):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, use of an on-chip pull-up resistor can be specified in 1-bit units by means of software. P130, P131 I/O ANO0, ANO1 Port 13 (P13):
• 2-bit I/O port
• Input/output can be specified in 1-bit units.

Data Sheet U14121EJ2V0DS0016 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

5.2 Non-Port Pins (1/2)

Pin Name I/O Alternate Function Function TI00 P35 External count clock input to 16-bit timer counter TI01 P36 Capture trigger signal input to capture/compare register 00 TI1 P33 External count clock input to 8-bit timer counter 1 TI2 P34 External count clock input to 8-bit timer counter 2 TI5 P100/TO5 External count clock input to 8-bit timer counter 5 TI6 P101/TO6 External count clock input to 8-bit timer counter 6 TI7 P102/TO7 External count clock input to 8-bit timer counter 7 TI8 Input P103/TO8 External count clock input to 8-bit timer counter 8 TO0 P30 16-bit timer output (shared by 14-bit PWM output) TO1 P31 TO2 P32 TO5 P100/TI5 TO6 P101/TI6 TO7 P102/TI7 TO8 Output P103/TI8 8-bit timer output (shared by 8-bit PWM output) RxD1 P20/SI1 Serial data input (UART1) RxD2 Input P70/SI2 Serial data input (UART2) TxD1 P21/SO1 Serial data output (UART1) TxD2 Output P71/SO2 Serial data output (UART2) ASCK1 P22/SCK1 Baud rate clock input (UART1) ASCK2 Input P72/SCK2 Baud rate clock input (UART2) SI0 P25/SDA0Note Serial data input (3-wire serial I/O 0) SI1 P20/RxD1 Serial data input (3-wire serial I/O 1) SI2 Input P70/RxD2 Serial data input (3-wire serial I/O 2) SO0 P26 Serial data output (3-wire serial I/O 0) SO1 P21/TxD1 Serial data output (3-wire serial I/O 1) SO2 Output P71/TxD2 Serial data output (3-wire serial I/O 2) SDA0 P25/SI0 Serial data input/output (I2C bus) SCK0 P27/SCL0Note Serial clock input/output (3-wire serial I/O 0) SCK1 P22/ASCK1 Serial clock input/output (3-wire serial I/O 1) SCK2 P72/ASCK2 Serial clock input/output (3-wire serial I/O 2) SCL0 I/O P27/SCK0 Serial clock input/output (I 2C bus) NMI P02/INTP2 Non-maskable interrupt request input INTP0 P00 INTP1 P01 INTP2 P02/NMI INTP3 P03 INTP4 P04 INTP5 P05 INTP6 Input P06 External interrupt request input Note This function is available in µPD784216AY/784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00 17 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

5.2 Non-Port Pins (2/2)

Pin Name I/O Alternate Function Function PCL Output P23 Clock output (for trimming main system clock and subsystem clock) BUZ Output P24 Buzzer output RTP0 to RTP7 Output P120 to P127 Real-time output port that outputs data in synchronization with trigger AD0 to AD7 I/O P40 to P47 Lower address/data bus for expanding memory externally A0 to A7 P80 to P87 Lower address bus for expanding memory externally A8 to A15 P50 to P57 Middle address bus for expanding memory externally A16 to A19 Output P60 to P63 Higher address bus for expanding memory externally RD P64 Strobe signal output for reading from external memory WR Output P65 Strobe signal output for writing to external memory WAIT Input P66 Wait insertion at external memory access ASTB Output P67 Strobe output that externally latches address information output to ports 4 through 6 and 8 to access external memory EXANote Output P37 Status signal output at external memory access RESET Input − System reset input X1 Input X2 − − Connecting crystal resonator for main system clock oscillation XT1 Input XT2 − − Connecting crystal resonator for subsystem clock oscillation ANI0 to ANI7 Input P10 to P17 A/D converter analog input ANO0, ANO1 Output P130, P131 D/A converter analog output AVREF0 A/D converter reference voltage input AVREF1 D/A converter reference voltage input AVDD A/D converter positive power supply. Connect to VDD. AVSS GND for A/D converter and D/A converter. Connect to VSS. VDD Positive power supply VSS GND TEST Connect this pin to VSS directly or via a pull-down resistor. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ (this pin is for IC test). Note This function is available in µPD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS0018 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

5.3 Pin I/O Circuits and Recommended Connections of Unused Pins

The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 5-1. For each type of input/output circuit, refer to Figure 5-1. Table 5-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins (1/2) Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 to P06/INTP6 8-N I/O Input: Independently connect to V SS via a resistor Output: Leave open P10/ANI0 to P17/ANI7 9 Input Connect to V SS or VDD P20/RxD1/SI1 10-K P21/TxD1/SO1 10-L P22/ASCK1/SCK1 10-K P23/PCL P24/BUZ 10-L P25/SI0/SDA0Note 1 10-K P26/SO0 10-L P27/SCK0/SCL0Note 1 10-K P30/TO0 to P32/TO2 12-E P33/TI1, P34/TI2 8-N P35/TI00, P36/TI01 10-M P37/EXANote 2 12-E P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB 5-A P70/RxD2/SI2 8-N P71/TxD2/SO2 10-M P72/ASCK2/SCK2 8-N P80/A0 to P87/A7 12-E P90 to P95 13-D P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 8-N P120/RTP0 to P127/RTP7 12-E P130/ANO0, P131/ANO1 12-F I/O Input: Independently connect to V SS via a resistor Output: Leav e open Notes 1. This function is available in µPD784216AY/784218AY Subseries products only. 2. This function is available in µPD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00 19 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 5-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins (2/2) Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins RESET 2-G − XT1 Input Connect to VSS XT2 Leave open AVREF0 Connect to VSS AVREF1 AVDD Connect to VDD AVSS Connect to VSS TEST Connect this pin to VSS directly or via a pull-down resistor. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ . Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided).

Data Sheet U14121EJ2V0DS0020 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 5-1. Types of Pin I/O Circuits (1/2) IN Pullup enable Data Output disable Input enable V DD P-ch VDD P-ch IN/OUT N-ch Pullup enable Data Output disable V DD P-ch VDD P-ch IN/OUT N-ch Pullup enable Data Open drain Output disable VDD P-ch VDD P-ch IN/OUT N-ch Pullup enable Data Open drain Output disable Output disable VDD P-ch VDD VSS P-ch IN/OUT N-ch Pullup enable Data VDD P-ch VDD VSS P-ch IN/OUT N-ch Pullup enable Data Output disable Input enable V DD P-ch VDD P-ch IN/OUT N-ch P-ch N-ch IN Comparator P-ch N-ch Input enable Type 2-G Type 5-A Type 8-N Type 9 (Threshold voltage) Analog output voltage Type 12-E Type 10-M Type 10-L Type 10-K Schmitt-triggered input with hysteresis characteristics

Data Sheet U14121EJ2V0DS00 21 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 5-1. Types of Pin I/O Circuits (2/2) Data Output disable Middle-voltage input buffer IN/OUT N-ch P-ch VDD RD Data Analog output voltage Type 12-F Type 13-D Type 16 Output disable P-ch IN/OUT VDD VSS VSS N-ch Input enable P-ch N-ch P-ch Feedback cut-off XT1 XT2

Data Sheet U14121EJ2V0DS0022 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 6. CPU ARCHITECTURE

6.1 Memory Space

A memory space of 1 M B can be accessed. M apping of the internal data area (special function registers and internal RAM) can be specified by the LO CATION instruction. The LO CATION instruction must always be executed after reset cancellation, and must not be used more than once. (1) When LOCATION 0H instruction is executed

• Internal memory The internal data area and internal ROM area are mapped as follows. Part Number Internal Data Area Internal ROM Area µPD784214A, µPD784214AY 0F100H to 0FFFFH 00000H to 0F0FFH 10000H to 17FFFH µPD784215A, µPD784215AY 0EB00H to 0FFFFH 00000H to 0EAFFH 10000H to 1FFFFH µPD784216A, µPD784216AY 0DF00H to 0FFFFH 00000H to 0DEFFH 10000H to 1FFFFH µPD784217A, µPD784217AY 00000H to 0CCFFH 10000H to 2FFFFH µPD784218A, µPD784218AY 0CD00H to 0FFFFH 00000H to 0CCFFH 10000H to 3FFFFH Caution The following areas that overlap the internal data area of the internal RO M cannot be used when the LOCATION 0H instruction is executed. Part Number Unusable Area µPD784214A, µPD784214AY 0F100H to 0FFFFH (3,840 bytes) µPD784215A, µPD784215AY 0EB00H to 0FFFFH (5,376 bytes) µPD784216A, µPD784216AY 0DF00H to 0FFFFH (8,448 bytes) µPD784217A, µPD784217AY µPD784218A, µPD784218AY 0CD00H to 0FFFFH (13,056 bytes)
• • Exter nal memor y The external memory is accessed in external memory expansion mode.

Data Sheet U14121EJ2V0DS00 23 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) When LOCATION 0FH instruction is executed

• Inter nal memory The internal data area and internal ROM area are mapped as follows. Part Number Internal Data Area Internal ROM Area µPD784214A, µPD784214AY FF100H to FFFFFH 00000H to 17FFFH µPD784215A, µPD784215AY FEB00H to FFFFFH 00000H to 1FFFFH µPD784216A, µPD784216AY FDF00H to FFFFFH 00000H to 1FFFFH µPD784217A, µPD784217AY 00000H to 2FFFFH µPD784218A, µPD784218AY FCD00H to FFFFFH 00000H to 3FFFFH
• Exter nal memor y The external memory is accessed in external memory expansion mode.

Data Sheet U14121EJ2V0DS0024 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 6-1. Memory Map of µµPD784214A, 784214AY Internal ROM (61,696 bytes) (256 bytes) Special function registers (SFR) Internal RAM (3,584 bytes) External memory Note 1 (928 KB) Note 1 General-purpose registers (128 bytes) Macro service control word area (54 bytes) Data area (512 bytes) Program/data area (3,072 bytes) CALLF entry area (2 KB) Program/data area Note 3 CALLT table area (64 bytes) Vector table area (64 bytes) Internal RAM (3,584 bytes) External memory Note 1 (980,736 bytes) (256 bytes) Internal ROM (96 KB) On execution of LOCATION 0H instruction Special function registers (SFR) Note 1 On execution of LOCATION 0FH instruction H F F F F F H 0 0 0 0 1 H F F F F 0 H F D F F 0 H 0 D F F 0 H 0 0 F F 0 H F F E F 0 H 0 0 1 F 0 H F F 0 F 0 H 0 0 0 0 0 H F F E F 0 H 0 8 E F 0 H F 7 E F 0 H B 3 E F 0 H 0 0 D F 0 H F F C F 0 H 6 0 E F 0 H 0 0 1 F 0 H F F F 7 1 H 0 0 0 1 0 H F F F 0 0 H 0 0 8 0 0 H F F 7 0 0 H 0 8 0 0 0 H F 7 0 0 0 H 0 4 0 0 0 H F 3 0 0 0 H 0 0 0 0 0 H F F E F F H 0 8 E F F H F 7 E F F H B 3 E F F H 6 0 E F F H 0 0 D F F H F F C F F H 0 0 1 F F H 0 0 0 0 0 H F F F 7 1 H 0 0 0 8 1 H F F 0 F F H 0 0 1 F F H F F F F F H F D F F F H 0 D F F F H 0 0 F F F H F F E F F Note 4 Note 4 Note 2 H F F F 7 1 H 0 0 0 8 1 H F F F 7 1 Internal ROM (32,768 bytes) H F F 0 F 0 H 0 0 0 0 1 Notes 1. Accessed in external memory expansion mode. 2. This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Data Sheet U14121EJ2V0DS00 25 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 6-2. Memory Map of µµ µµPD784215A, 784215AY Internal ROM (60,160 bytes) (256 bytes) Special function registers (SFR) Internal RAM (5,120 bytes) External memory Note 1 (896 KB) Note 1 General-purpose registers (128 bytes) Macro service control word area (54 bytes) Data area (512 bytes) Program/data area (4,608 bytes) CALLF entry area (2 KB) Program/data area Note 3 CALLT table area (64 bytes) Vector table area (64 bytes) Internal RAM (5,120 bytes) External memory Note 1 (912,128 bytes) (256 bytes) Internal ROM (128 KB) On execution of LOCATION 0H instruction Special function registers (SFR) Note 1 On execution of LOCATION 0FH instruction H F F F F F H 0 0 0 0 1 H F F F F 0 H F D F F 0 H 0 D F F 0 H 0 0 F F 0 H F F E F 0 H 0 0 B E 0 H F F A E 0 H 0 0 0 0 0 H F F E F 0 H 0 8 E F 0 H F 7 E F 0 H B 3 E F 0 H 0 0 D F 0 H F F C F 0 H 6 0 E F 0 H 0 0 B E 0 H 0 0 0 1 0 H F F F 0 0 H 0 0 8 0 0 H F F 7 0 0 H 0 8 0 0 0 H F 7 0 0 0 H 0 4 0 0 0 H F 3 0 0 0 H 0 0 0 0 0 H F F E F F H 0 8 E F F H F 7 E F F H B 3 E F F H 6 0 E F F H 0 0 D F F H F F C F F H 0 0 B E F H 0 0 0 0 0 H F F F F 1 H 0 0 0 0 2 H F F A E F H 0 0 B E F H F F F F F H F D F F F H 0 D F F F H 0 0 F F F H F F E F F Note 4 Note 4 H F F F F 1 Internal ROM (65,536 bytes) H 0 0 0 0 2 H F F F F 1 H F F F F 1 Note 2 H F F A E 0 H 0 0 0 0 1 Notes 1. Accessed in external memory expansion mode. 2. This 5,376-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 125,696 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Data Sheet U14121EJ2V0DS0026 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 6-3. Memory Map of µµPD784216A, 784216AY Internal ROM (57,088 bytes) (256 bytes) Special function registers (SFR) Internal RAM (8,192 bytes) External memory Note 1 (896 KB) Note 1 General-purpose registers (128 bytes) Macro service control word area (54 bytes) Data area (512 bytes) Program/data area (7,680 bytes) CALLF entry area (2 KB) Program/data area Note 3 CALLT table area (64 bytes) Vector table area (64 bytes) Internal RAM (8,192 bytes) External memory Note 1 (909,056 bytes) (256 bytes) Internal ROM (128 KB) On execution of LOCATION 0H instruction Special function registers (SFR) Note 1 On execution of LOCATION 0FH instruction H F F F F F H 0 0 0 0 1 H F F F F 0 H F D F F 0 H 0 D F F 0 H 0 0 F F 0 H F F E F 0 H 0 0 F D 0 H F F E D 0 H 0 0 0 0 0 H F F E F 0 H 0 8 E F 0 H F 7 E F 0 H B 3 E F 0 H 0 0 D F 0 H F F C F 0 H 6 0 E F 0 H 0 0 F D 0 H 0 0 0 1 0 H F F F 0 0 H 0 0 8 0 0 H F F 7 0 0 H 0 8 0 0 0 H F 7 0 0 0 H 0 4 0 0 0 H F 3 0 0 0 H 0 0 0 0 0 H F F E F F H 0 8 E F F H F 7 E F F H B 3 E F F H 6 0 E F F H 0 0 D F F H F F C F F H 0 0 F D F H 0 0 0 0 0 H F F F F 1 H 0 0 0 0 2 H F F E D F H 0 0 F D F H F F F F F H F D F F F H 0 D F F F H 0 0 F F F H F F E F F Note 4 Note 4 H 0 0 0 0 2 H F F F F 1 H F F F F 1 Internal ROM (65,536 bytes) H F F F F 1 Note 2 H F F E D 0 H 0 0 0 0 1 Notes 1. Accessed in external memory expansion mode. 2. This 8,448-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 122,624 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Data Sheet U14121EJ2V0DS00 27 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 6- 4. Memory Map of µµ µµPD784217A, 784217AY Notes 1. Accessed in external memory expansion mode. 2. This 13,056-byte area can be used as internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 183,552 bytes, on execution of LOCATION 0FH instruction: 196,608 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. Internal ROM (52,480 bytes) (256 bytes) Special function registers (SFR) Internal RAM (12,800 bytes) External memory Note 1 (928 KB) Note 1 General-purpose registers (128 bytes) Macro service control word area (54 bytes) Data area (512 bytes) Program/data area (12,288 bytes) CALLF entry area (2 KB) Program/data area Note 3 CALLT table area (64 bytes) Vector table area (64 bytes) Internal RAM (12,800 bytes) External memory Note 1 (838,912 bytes) (256 bytes) Internal ROM (192 KB) On execution of LOCATION 0H instruction Special function registers (SFR) Note 1 On execution of LOCATION 0FH instruction H F F F F F H 0 0 0 0 1 H F F F F 0 H F D F F 0 H 0 D F F 0 H 0 0 F F 0 H F F E F 0 H 0 0 D C 0 H F F C C 0 H 0 0 0 0 0 H F F E F 0 H 0 8 E F 0 H F 7 E F 0 H B 3 E F 0 H 0 0 D F 0 H F F C F 0 H 6 0 E F 0 H 0 0 D C 0 H F F F F 2 H 0 0 0 1 0 H F F F 0 0 H 0 0 8 0 0 H F F 7 0 0 H 0 8 0 0 0 H F 7 0 0 0 H 0 4 0 0 0 H F 3 0 0 0 H 0 0 0 0 0 H F F E F F H 0 8 E F F H F 7 E F F H B 3 E F F H 6 0 E F F H 0 0 D F F H F F C F F H 0 0 D C F H 0 0 0 0 0 H F F F F 2 H 0 0 0 0 3 H F F C C F H 0 0 D C F H F F F F F H F D F F F H 0 D F F F H 0 0 F F F H F F E F F Note 4 Note 4 Note 2 H F F F 7 1 H 0 0 0 8 1 H F F F 7 1 Internal ROM (32,768 bytes) H F F 0 F 0 H 0 0 0 0 1

Data Sheet U14121EJ2V0DS0028 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 6-5. Memory Map of µµPD784218A, 784218AY Notes 1. Accessed in external memory expansion mode. 2. This 13,056-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0H instruction: 249,088 bytes, on execution of LOCATION 0FH instruction: 262,144 bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. Internal ROM (52,480 bytes) (256 bytes) Special function registers (SFR) Internal RAM (12,800 bytes) External memory Note 1 (768 KB) Note 1 General-purpose registers (128 bytes) Macro service control word area (54 bytes) Data area (512 bytes) Program/data area (12,288 bytes) CALLF entry area (2 KB) Program/data area Note 3 CALLT table area (64 bytes) Vector table area (64 bytes) Internal RAM (12,800 bytes) External memory Note 1 (773,376 bytes) (256 bytes) Internal ROM (256 KB) On execution of LOCATION 0H instruction Special function registers (SFR) Note 1 On execution of LOCATION 0FH instruction H F F F F F H 0 0 0 0 1 H F F F F 0 H F D F F 0 H 0 D F F 0 H 0 0 F F 0 H F F E F 0 H 0 0 D C 0 H F F C C 0 H 0 0 0 0 0 H F F E F 0 H 0 8 E F 0 H F 7 E F 0 H B 3 E F 0 H 0 0 D F 0 H F F C F 0 H 6 0 E F 0 H 0 0 D C 0 H 0 0 0 1 0 H F F F 0 0 H 0 0 8 0 0 H F F 7 0 0 H 0 8 0 0 0 H F 7 0 0 0 H 0 4 0 0 0 H F 3 0 0 0 H 0 0 0 0 0 H F F E F F H 0 8 E F F H F 7 E F F H B 3 E F F H 6 0 E F F H 0 0 D F F H F F C F F H 0 0 D C F H 0 0 0 0 0 H F F F F 3 H 0 0 0 0 4 H F F C C F H 0 0 D C F H F F F F F H F D F F F H 0 D F F F H 0 0 F F F H F F E F F Note 4 Note 4 H F F F F 3 Internal ROM (196,608 bytes) H 0 0 0 0 4 H F F F F 3 H F F F F 3 Note 2 H F F C C 0 H 0 0 0 0 1

Data Sheet U14121EJ2V0DS0 29 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

6.2 CPU Registers

6.2.1 General-purpose registers

Sixteen 8-bit general-purpose registers are available. Tw o 8-bit registers can also be used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in com bination with an 8-bit register for address expansion as 24- bit address specification registers. Eight banks of these register sets are available and can be selected by using software or the context switching function. The general-purpose registers except the V, U, T, and W registers for address expansion are m apped to the internal RAM. Figure 6-6. General-Purpose Register Format Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series. A (R1) B (R3) R11 D (R13) H (R15) V U T W VVP (RG4) UUP (RG5) TDE (RG6) WHL (RG7) X (R0) C (R2) R10 E (R12) L (R14) AX (RP0) BC (RP1) RP2 RP3 VP (RP4) UP (RP5) DE (RP6) HL (RP7) Names in parentheses indicate absolute names. 8 banks

Data Sheet U14121EJ2V0DS0030 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

6.2.2 Control registers

(1) Program counter (PC) The program counter is a 20-bit register w hose contents are automatically updated when the program is executed. Figure 6-7. Format of Program Counter (PC) (2) Program status word (PSW) This register holds the statuses of the C PU. Its contents are autom atically updated w hen the program is executed. Figure 6-8. Format of Program Status Word (PSW) Note This flag is provided to m aintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when the software for the 78K/III Series is used. (3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to w rite 0 to the higher 4 bits of this pointer. Figure 6-9. Format of Stack Pointer (SP) 19 0 PC 15 14 13 12 11 10 9 8 UF RBS2 RBS1 RBS0 – – – –PSWH 76543210 S Z RSS Note AC IE P/V 0 CYPSWL PSW 23 0 SP 0 0 0 0

Data Sheet U14121EJ2V0DS00 31 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

6.2.3 Special function registers (SFRs)

The special function registers, such as the m ode registers and control registers of the internal peripheral hardware, are registers to w hich special functions are assigned. These registers are mapped to the 256-byte space of addresses 0FF00H to 0FFFFHNote. Note On execution of the LO CATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH instruction. Caution Do not access an address in this area to w hich no SFR is assigned. If such an address is accessed by mistake, the µµPD784218A may enter a deadlocked state. This deadlock state can be cleared only by inputting the RESET signal. Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows. (RA78K4). It can be used as an sfr variable by means of the #pragma sfr command in the C compiler (CC78K4). R/W: Read/write R: R ead-only W: Write-only SFRs that can be m anipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction.

Data Sheet U14121EJ2V0DS0032 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 6-1. Special Function Register (SFR) List (1/4) Bit Units for ManipulationAddressNote 1 Special Function Register (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

0FF00H Port 0 P0 R/W √√− 0FF01H Port 1 P1 R √√− 0FF02H Port 2 P2 √√− 0FF03H Port 3 P3 √√− 0FF04H Port 4 P4 √√− 0FF05H Port 5 P5 √√− 0FF06H Port 6 P6 √√− 0FF07H Port 7 P7 √√− 0FF08H Port 8 P8 √√− 0FF09H Port 9 P9 √√− 0FF0AH Port 10 P10 √√− 0FF0CH Port 12 P12 √√− 0FF0DH Port 13 P13 R/W √√− 00HNote 2 0FF10H 0FF11H 16-bit timer counter TM0 R −−√ 0FF12H 0FF13H Capture/compare register 00 (16-bit timer/event counter) CR00 −−√ 0FF14H 0FF15H Capture/compare register 01 (16-bit timer/event counter) CR01 −−√ 0000H0FF16H Capture/compare control register 0 CRC0 √√− 0FF18H 16-bit timer mode control register TMC0 √√− 0FF1AH 16-bit timer output control register TOC0 √√− 0FF1CH Prescaler mode register 0 PRM0 √√− 00H 0FF20H Port 0 mode register PM0 √√− 0FF22H Port 2 mode register PM2 √√− 0FF23H Port 3 mode register PM3 √√− 0FF24H Port 4 mode register PM4 √√− 0FF25H Port 5 mode register PM5 √√− 0FF26H Port 6 mode register PM6 √√− 0FF27H Port 7 mode register PM7 √√− 0FF28H Port 8 mode register PM8 √√− 0FF29H Port 9 mode register PM9 √√− 0FF2AH Port 10 mode register PM10 √√− 0FF2CH Port 12 mode register PM12 √√− 0FF2DH Port 13 mode register PM13 R/W √√− FFH Notes 1. When the LO CATION 0H instruction is executed. Add "F0000H " to this value w hen the LO CATION 0FH instruction is executed. 2. Because each port is initialized to input mode after reset, "00H" is not actually read. The output latch is initialized to "0".

Data Sheet U14121EJ2V0DS00 33 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 6-1. Special Function Register (SFR) List (2/4) Bit Units for ManipulationAddressNote Special Function Register (SFR) Name Symbol R/W 0FF30H Pull-up resistor option register 0 PU0 √√− 0FF32H Pull-up resistor option register 2 PU2 √√− 0FF33H Pull-up resistor option register 3 PU3 √√− 0FF37H Pull-up resistor option register 7 PU7 √√− 0FF38H Pull-up resistor option register 8 PU8 √√− 0FF3AH Pull-up resistor option register 10 PU10 √√− 0FF3CH Pull-up resistor option register 12 PU12 √√− 0FF40H Clock output control register CKS √√− 0FF42H Port function control register PF2 √√− 0FF4EH Pull-up resistor option register PUO R/W √√− 00H 0FF50H 8-bit timer counter 1 TM1 −√ 0FF51H 8-bit timer counter 2 TM2 TM1W R 0FF52H Compare register 10 (8-bit timer/event counter 1) CR10 −√ 0FF53H Compare register 20 (8-bit timer/event counter 2) CR20 CR1W 0FF54H 8-bit timer mode control register 1 TMC1 √√ 0FF55H 8-bit timer mode control register 2 TMC2 TMC1W 0FF56H Prescaler mode register 1 PRM1 √√ 0FF57H Prescaler mode register 2 PRM2 PRM1W R/W 0FF60H 8-bit timer counter 5 TM5 −√ 0FF61H 8-bit timer counter 6 TM6 TM5W 0FF62H 8-bit timer counter 7 TM7 −√ 0FF63H 8-bit timer counter 8 TM8 TM7W R 0FF64H Compare register 50 (8-bit timer/event counter 5) CR50 −√ 0FF65H Compare register 60 (8-bit timer/event counter 6) CR60 CR5W 0FF66H Compare register 70 (8-bit timer/event counter 7) CR70 −√ 0FF67H Compare register 80 (8-bit timer/event counter 8) CR80 CR7W 0FF68H 8-bit timer mode control register 5 TMC5 √√ 0FF69H 8-bit timer mode control register 6 TMC6 TMC5W 0FF6AH 8-bit timer mode control register 7 TMC7 √√ 0FF6BH 8-bit timer mode control register 8 TMC8 TMC7W 0FF6CH Prescaler mode register 5 PRM5 √√ 0FF6DH Prescaler mode register 6 PRM6 PRM5W 0FF6EH Prescaler mode register 7 PRM7 √√ 0FF6FH Prescaler mode register 8 PRM8 PRM7W 0000H 0FF70H Asynchronous serial interface mode register 1 ASIM1 √√− 0FF71H Asynchronous serial interface mode register 2 ASIM2 R/W √√− 0FF72H Asynchronous serial interface status register 1 ASIS1 √√− 0FF73H Asynchronous serial interface status register 2 ASIS2 R √√− 00H Note When the LOCATION 0H instruction is executed. Add "F0000H " to this value w hen the LO CATION 0FH instruction is executed.

Data Sheet U14121EJ2V0DS0034 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 6-1. Special Function Register (SFR) List (3/4) Bit Units for ManipulationAddressNote 1 Special Function Register (SFR) Name Symbol R/W Transmit shift register 1 TXS1 W −√−0FF74H Receive buffer register 1 RXB1 R −√− Transmit shift register 2 TXS2 W −√−0FF75H Receive buffer register 2 RXB2 R −√− FFH 0FF76H Baud rate generator control register 1 BRGC1 √√− 0FF77H Baud rate generator control register 2 BRGC2 √√− 0FF7AH Oscillation mode select register CC √√− 0FF80H A/D converter mode register ADM √√− 0FF81H A/D converter input select register ADIS R/W √√− 00H 0FF83H A/D conversion result register ADCR R −√− Undefined 0FF84H D/A conversion value setting register 0 DACS0 √√− 0FF85H D/A conversion value setting register 1 DACS1 √√− 0FF86H D/A converter mode register 0 DAM0 √√− 0FF87H D/A converter mode register 1 DAM1 √√− 0FF8CH External bus type select register EBTS √√− 0FF90H Serial operation mode register 0 CSIM0 √√− 0FF91H Serial operation mode register 1 CSIM1 √√− 0FF92H Serial operation mode register 2 CSIM2 √√− 0FF94H Serial I/O shift register 0 SIO0 −√− 0FF95H Serial I/O shift register 1 SIO1 −√− 0FF96H Serial I/O shift register 2 SIO2 −√− 0FF98H Real-time output buffer register L RTBL −√− 0FF99H Real-time output buffer register H RTBH −√− 0FF9AH Real-time output port mode register RTPM √√− 0FF9BH Real-time output port control register RTPC √√− 0FF9CH Watch timer mode control register WTM √√− 0FFA0H External interrupt rising edge enable register EGP0 √√− 0FFA2H External interrupt falling edge enable register EGN0 R/W √√− 0FFA8H In-service priority register ISPR R √√− 0FFA9H Interrupt select control register SNMI √√− 00H 0FFAAH Interrupt mode control register IMC √√− 80H 0FFACH Interrupt mask flag register 0L MK0L √√ 0FFADH Interrupt mask flag register 0H MK0H MK0 0FFAEH Interrupt mask flag register 1L MK1L √√ 0FFAFH Interrupt mask flag register 1H MK1H MK1 FFFFH 0FFB0H I2C bus control registerNote 2 IICC0 √√− 0FFB2H Prescaler mode register for serial clock SPRM0 √√− 0FFB4H Slave address register SVA0 R/W √√− 00H Notes 1. When the LO CATION 0H instruction is executed. Add "F0000H " to this value w hen the LO CATION 0FH instruction is executed. 2. µPD784216AY/784218AY Subseries only

Data Sheet U14121EJ2V0DS00 35 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 6-1. Special Function Register (SFR) List (4/4) Bit Units for ManipulationAddressNote 1 Special Function Register (SFR) Name Symbol R/W 0FFB6H I2C bus status registerNote 2 IICS0 R √√− 0FFB8H Serial shift register IIC0 √√− 00H 0FFC0H Standby control register STBC −√− 30H 0FFC2H Watchdog timer mode register WDM −√− 00H 0FFC4H Memory expansion mode register MM √√− 20H 0FFC7H Programmable wait control register 1 PWC1 R/W √√− AAH 0FFCEH Clock status register PCS R √√− 32H 0FFCFH Oscillation stabilization time specification register OSTS √√− 00H 0FFD0H to 0FFDFH External SFR area − √√− − 0FFE0H Interrupt control register (INTWDTM) WDTIC √√− 0FFE1H Interrupt control register (INTP0) PIC0 √√− 0FFE2H Interrupt control register (INTP1) PIC1 √√− 0FFE3H Interrupt control register (INTP2) PIC2 √√− 0FFE4H Interrupt control register (INTP3) PIC3 √√− 0FFE5H Interrupt control register (INTP4) PIC4 √√− 0FFE6H Interrupt control register (INTP5) PIC5 √√− 0FFE7H Interrupt control register (INTP6) PIC6 √√− 0FFE8H Interrupt control register (INTIIC0/INTCSI0) CSIIC0 √√− 0FFE9H Interrupt control register (INTSER1) SERIC1 √√− 0FFEAH Interrupt control register (INTSR1/INTCSI1) SRIC1 √√− 0FFEBH Interrupt control register (INTST1) STIC1 √√− 0FFECH Interrupt control register (INTSER2) SERIC2 √√− 0FFEDH Interrupt control register (INTSR2/INTCSI2) SRIC2 √√− 0FFEEH Interrupt control register (INTST2) STIC2 √√− 0FFEFH Interrupt control register (INTTM3) TMIC3 √√− 0FFF0H Interrupt control register (INTTM00) TMIC00 √√− 0FFF1H Interrupt control register (INTTM01) TMIC01 √√− 0FFF2H Interrupt control register (INTTM1) TMIC1 √√− 0FFF3H Interrupt control register (INTTM2) TMIC2 √√− 0FFF4H Interrupt control register (INTAD) ADIC √√− 0FFF5H Interrupt control register (INTTM5) TMIC5 √√− 0FFF6H Interrupt control register (INTTM6) TMIC6 √√− 0FFF7H Interrupt control register (INTTM7) TMIC7 √√− 0FFF8H Interrupt control register (INTTM8) TMIC8 √√− 0FFF9H Interrupt control register (INTWT) WTIC √√− 0FFFAH Interrupt control register (INTKR) KRIC R/W √√− 43H Notes 1. When the LO CATION 0H instruction is executed. Add "F0000H " to this value w hen the LO CATION 0FH instruction is executed. 2. µPD784216AY/784218AY Subseries only

Data Sheet U14121EJ2V0DS0036 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 7. PERIPHERAL HARDWARE FUNCTIONS

7.1 Ports

The ports shown in Figure 7-1 are provided to m ake various control operations possible. Table 7-1 show s the function of each port. Ports 0, 2 through 8, 10, and 12 can be connected to on-chip pull-up resistors by m eans of software when in input mode. Figure 7-1. Port Configuration ìí î Port 7 ì ï ï í ï ï î Port 0 ì ï ï í ï ï î Port 2 ì ï ï í ï ï î Port 3 ì ï ï í ï ï î Port 4 ì ï ï í ï ï î Port 5 ì ï ï í ï ï î Port 6 Port 1 P70 P72 ì ï ï í ï ï î Pprt 8 P80 P87 ì ï ï í ï ï î Port 12 P120 P127 ìï ï í ï ï î Port 9 P90 P95 ì í î Port 10 P100 P103 ì í î Port 13 P130 P131 P00 P06 P10 to P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67

Data Sheet U14121EJ2V0DS00 37 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 7-1. Port Functions Port Name Pin Name Function Specification of Pull-up Resistor Connection by Software Port 0 P00 to P06 • Input/output can be specified in 1-bit units Can be specified in 1-bit units Port 1 P10 to P17 • I nput port − Port 2 P20 to P27 • Input/output can be specified in 1-bit units Can be specified in 1-bit units Port 3 P30 to P37 • Input/output can be specified in 1-bit units Can be specified in 1-bit units Port 4 P40 to P47 • Input/output can be specified in 1-bit units

• LEDs can be driven directly Can be specified in 1-port units Port 5 P50 to P57 • Input/output can be specified in 1-bit units
• LEDs can be driven directly Can be specified in 1-port units Port 6 P60 to P67 • Input/output can be specified in 1-bit units Can be specified in 1-port units Port 7 P70 to P72 • Input/output can be specified in 1-bit units Can be specified in 1-bit units Port 8 P80 to P87 • Input/output can be specified in 1-bit units Can be specified in 1-bit units Port 9 P90 to P95 • N-ch open-drain I/O port
• Input/output can be specified in 1-bit units
• LEDs can be driven directly Port 10 P100 to P103 • Input/output can be specified in 1-bit units Can be specified in 1-bit units Port 12 P120 to P127 • Input/output can be specified in 1-bit units Can be specified in 1-bit units Port 13 P130, P131 • Input/output can be specified in 1-bit units −

7.2 Clock Generator

An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider. If high-speed operation is not necessary, the internal operating frequency can be low ered by the frequency divider to reduce the current consumption. Figure 7-2. Block Diagram of Clock Generator XT2 XT1 STOP or bit 2 (MCK) of the standby control register (STBC) is set to 1 when the subclock is selected as the CPU clock Main system clock oscillator Subsystem clock oscillator f XT Watch timer, clock output function Clock to peripheral hardware CPU clock CPU) Frequency divider IDLE controller Prescaler Prescaler STOP, IDLE controller HALT controller fX fX fXX fXX fXX fXX Selector Selector Internal system clock CLK)

Data Sheet U14121EJ2V0DS00 39 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.3 Real-Time Output Port

The real-time output function is to transfer data set in advance to the real-tim e output buffer register to the output latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device. The pins that output the data to the external device constitute a port called a real-tim e output port. Because the real-time output port can output signals without jitter, it is ideal for controlling a stepper motor. Figure 7-5. Block Diagram of Real-Time Output Port Internal bus RTPOE BYTE EXTR Output trigger Controller Real-time output port control register (RTPC) Real-time output port mode register (RTPM) Real-time output port output latch High-order 4 bits of real-time output buffer register (RTBH) Low-order 4 bits of real-time output buffer register (RTBL) INTP2TRG INTTM1 INTTM2 Port 12 output latch P12n/RTPn pin output (n = 0 to 7) P127/ P120/ RTPOE bit

Data Sheet U14121EJ2V0DS0040 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.4 Timer/Event Counter

One unit of 16-bit timer/event counter and six 8-bit timer/event counters are provided. Because a total of eight interrupt requests are supported, these tim er/event counters can be used as eight timer/counters. Table 7-2. Operations of Timers Name Item 16-Bit Timer/ Event Counter 8-Bit Timer/ Event Counter 1 8-Bit Timer/ Event Counter 2 8-Bit Timer/ Event Counter 5 8-Bit Timer/ Event Counter 6 8-Bit Timer/ Event Counter 7 8-Bit Timer/ Event Counter 8 16 bits √ √√√ Interval timer 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 chOperation mode Timer output 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch Pulse width measurement 2 inputs −−−−−− Function Number of interrupt requests 2 1 1 1 1 1 1

Data Sheet U14121EJ2V0DS00 41 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 7-6. Block Diagram of Timer/Event Counters 16-bit timer/event counter 8-bit timer/event counter 1, 5, 7 Remarks 1. n = 1, 5, 7 2. OVF: Overflow flag 8-bit timer/event counter 2, 6, 8 Remarks 1. n = 2, 6, 8 2. OVF: Overflow flag fXX/4 fXX/16 INTTM3 TI01 TI00 Edge detector Edge detector 16-bit timer counter (TM0) 16-bit capture/compare register 00 (CR00) 16-bit capture/compare register 01 (CR01) Clear INTTM00 INTTM01 TO0 SelectorSelector Output controller fXX/29 fXX/27 fXX/25 fXX/24 fXX/23 fXX/22 TIn 8-bit timer counter n (TMn) 8-bit compare register n0 (CRn0) Clear OVF INTTMn + 1 INTTMn TOn Edge detector Output controller Selector Selector fXX/29 fXX/27 fXX/25 fXX/24 fXX/23 fXX/22 TIn TMn – 1 8-bit timer counter n (TMn) 8-bit compare register n0 (CRn0) Clear OVF INTTMn TOn Edge detector Output controller Selector

Data Sheet U14121EJ2V0DS0042 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.5 A/D Converter

An A/D converter converts an analog signal input into a digital signal. This m icrocontroller is provided with an A/D converter with a resolution of 8 bits and eight channels (ANI0 to ANI7). This A/D converter is of successive approximation type and the result of conversion is stored in an 8-bit A/D conversion result register (ADCR). The A/D converter can be started in the following two ways:

• Hardware start Conversion is started by trigger input (P03).
• Software start Conversion is started by setting the A/D converter mode register (ADM). One analog input channel is selected from ANI0 to ANI7 for A/D conversion. When A/D conversion is started by means of hardware start, conversion is stopped after it has been com pleted. When conversion is started by means of software start, A/D conversion is repeatedly executed. Each tim e conversion has been com pleted, an interrupt request (INTAD) is generated. Figure 7-7. Block Diagram of A/D Converter ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Sample & hold circuit Series resistor string Voltage comparator Successive approximation register (SAR) A/D conversion result register (ADCR) ControllerEdge detector INTP3/P03 INTAD INTP3 AVSS AVREF0 AVDD Internal bus Selector Tap selector Edge detector

Data Sheet U14121EJ2V0DS00 43 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.6 D/A Converter

A D /A converter converts a digital signal input into an analog signal. This m icrocontroller is provided w ith a voltage output type D/A converter with a resolution of 8 bits and two channels. The conversion method is of R-2R resistor ladder type. D/A conversion is started by setting D ACE0 of D /A converter m ode register 0 (D AM0) and DACE1 of D/A converter mode register 1 (DAM1). The D/A converter operates in the following two modes:

• N ormal mode The converter outputs an analog voltage immediately after it has completed D/A conversion.
• Real-time output mode The converter outputs an analog voltage in synchronization w ith an output trigger after it has com pleted D/A conversion. Figure 7-8. Block Diagram of D/A Converter AVREF1 AVSS DACS0 2R R R Selector ANO0 DACS1 2R R R Selector ANO1

Data Sheet U14121EJ2V0DS0044 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.7 Serial Interface

Three independent serial interface channels are provided.

• Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2
• Clocked serial interface (CSI) × 1
• 3-wire serial I/O (IOE)
• I 2C bus interface (I2C) (µPD784216AY/784218AY Subseries only) Therefore, com munication w ith an external system and local com munication within the system can be simultaneously executed (refer to Figure 7-9). Figure 7-9. Example of Serial Interface (a) UART + I2C (b) [UART] [UART] RS-232-C driver/receiver RxD1 TxD1 RS-232-C driver/receiver Port RxD2 TxD2 Port SDA0 SCL0 [I2C] VDD VDD SDA SCL SDA SCL LCD PD4711Aµ PD4711Aµ PD784218AY (master)µ PD780078Y (slave)µ PD780308Y (slave)µ (b) UART + 3-wire serial I/O PD784218AY (master)µ RS-232-C driver/receiver [UART] Port RxD2 TxD2 PD753106 (slave)µ SI SO SCK Port INT [3-wire serial I/O] Note SO1 SI1 SCK1 INTPm Port PD4711Aµ Note H andshake line

Data Sheet U14121EJ2V0DS00 45 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)

Two channels of serial interfaces for w hich an asynchronous serial interface mode and a 3-wire serial I/O mode can be selected are provided. (1) Asynchronous serial interface mode In this mode, data of 1 byte following the start bit is transmitted or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conform ing to the MIDI standard (31.25 kbps) can also be obtained. Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode Internal bus Receive buffer register 1, 2 (RXB1, RXB2) Receive shift register 1, 2 (RX1, RX2) Transmit shift register 1, 2 (TXS1, TXS2) Receive control parity check Transmit control parity addition 5-bit counter × 2 transmit/ receive clock generation RxD1, RxD2 TxD1, TxD2 ASCK1, ASCK2 Baud rate generator INTSR1, INTSR2 INTST1, INTST2 Selector fXX to fXX/25

Data Sheet U14121EJ2V0DS0046 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) 3-wire serial I/O mode In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to com municate with a device having a conventional clocked serial interface. Basically, communication is established by using three lines: serial clocks (SCK1 and SCK2), serial data inputs (SI1 and SI2), and serial data outputs (SO1 and SO 2). To connect tw o or m ore devices, a handshake line is necessary. Figure 7-11. Block Diagram in 3-Wire Serial I/O Mode Internal bus Interrupt generator Selector Serial clock counter Serial clock controller Serial I/O shift register 1, 2 (SIO1, SIO2)SI1, SI2 SO1, SO2 SCK1, SCK2 INTCSI1, INTCSI2 TO2 fXX/8 fXX/16

Data Sheet U14121EJ2V0DS00 47 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.7.2 Clocked serial interface (CSI)

In this m ode, the m aster device starts transfer by m aking the serial clock active and transfers 1-byte data in synchronization with this clock. (1) 3-wire serial I/O mode This mode is to communicate with devices having a conventional clocked serial interface. Basically, communication is established in this mode w ith three lines: serial clock (SC K0) serial data input (SI0), and serial data output (SO0) lines. Generally, a handshake line is necessary to check the reception status. Figure 7-12. Block Diagram in 3-Wire Serial I/O Mode SI0 SO0 SCK0 INTCSI0 TO2 fXX/8 fXX/16 Internal bus Interrupt generator Selector Serial clock counter Serial clock controller Serial I/O shift register 0 (SIO0)

Data Sheet U14121EJ2V0DS0048 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) I 2C bus (Inter IC) bus mode (supporting multimaster) (µµPD784216AY/784218AY Subseries only) This mode is for communication with devices conforming to the I 2C bus format. This mode is for transferring 8-bit data betw een two or m ore devices by using tw o lines: serial clock (SC L0) and serial data bus (SDA0) lines. During transmission, a “start condition”, “data”, and “stop condition” can be output onto the serial data bus. During reception, these data are automatically detected by hardware. Figure 7-13. Block Diagram of I 2C Bus Mode Internal bus Direction controller Slave address register (SVA0) 8 8 SDA0 SCL0 Serial I/O shift register 0 (SIO0) Output latch Wake-up controller Start condition/acknowledge detector Stop condition detector Serial clock counter Serial clock controller Acknowledge generator Interrupt generator Selector INTIIC0 TO2/18 to TO2/68 fXX/24 to fXX/178

Data Sheet U14121EJ2V0DS00 49 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.8 Clock Output Function

Clocks of the following frequencies can be output as clock output. (@12.5 MHz operation with main system clock)

• 32.768 kHz (@32.768 kHz operation with subsystem clock) Figure 7-14. Block Diagram of Clock Output Function

7.9 Buzzer Output Function

Clocks of the following frequencies can be output as buzzer output. Figure 7-15. Block Diagram of Buzzer Output Function fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXT Synchronization circuit Output controller PCL Selector fXX/210 fXX/211 fXX/212 fXX/213 Output controller BUZ Selector

Data Sheet U14121EJ2V0DS0050 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.10 Edge Detection Function

The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 to INTP6) are used not only to input interrupt requests but also to input trigger signals to the internal hardw are units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. M oreover, a noise elimination function is also provided to prevent erroneous detection due to noise. Pin Name Detectable Edge Noise Elimination NMI By analog delay INTP0 to INTP6 Either or both of rising and falling edges

7.11 Watch Timer

The watch timer has the following functions:

• Watch timer
• Interval timer The watch timer and interval timer functions can be used at the same time. (1) Watch timer The watch timer sets the WTIF flag of the interrupt control register (WTIC) at tim e intervals of 0.5 seconds by using the 32.768 kHz subsystem clock. (2) Interval timer The interval timer generates an interrupt request (INTTM3) at predetermined time intervals. Figure 7-16. Block Diagram of Watch Timer fXX/27 Prescaler fXT fW fW fW fW fW fW fW 5-bit counter fW fW 214 INTWT INTTM3 To 16-bit timer/counter Selector Selector Selector Selector

Data Sheet U14121EJ2V0DS00 51 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.12 Watchdog Timer

A watchdog timer is provided to detect a C PU runaw ay. This w atchdog tim er generates a non-m askable or maskable interrupt unless it is cleared by softw are within a specified interval tim e. O nce enabled to operate, the watchdog timer cannot be stopped by softw are. Whether the interrupt by the w atchdog timer or the interrupt input from the NMI pin takes precedence can be specified. Figure 7-17. Block Diagram of Watchdog Timer Note Write “+” to bit 7 (RUN) of the watchdog timer (WDM) Remark f CLK: Internal system clock (fXX to fXX/8) fCLK/221 fCLK/220 fCLK/219 fCLK/217 fCLK INTWDTHALT IDLE STOP RUN Note Timer Selector

Data Sheet U14121EJ2V0DS0052 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 8. INTERRUPT FUNCTIONS The three types of interrupt request servicing shown in Table 8-1 can be selected by program. Table 8-1. Servicing of Interrupt Request Servicing Mode Entity of Servicing Servicing Contents of PC and PSW Vectored interrupt Branches and executes servicing routine (servicing is arbitrary) Saves to and restores from stack Context switching Software Automatically switches register bank, branches and executes servicing routine (servicing is arbitrary) Saves to or restores from fixed area in register bank Macro service Firmware Executes data transfer between memory and I/O (servicing is fixed) Retained

8.1 Interrupt Sources

Table 8-2 shows the interrupt sources available. As show n, interrupts are generated by 29 types of sources, execution of the BRK instruction, BRKCS instruction, or an operand error. The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and so that w hich of the tw o or m ore interrupts that sim ultaneously occur should be serviced first can be determined. When the macro service function is used, however, nesting always proceeds. The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same priority, are simultaneously generated (refer to Table 8-2). Table 8-2. Interrupt Sources (1/2) SourceType Default Priority Name Trigger Internal/ External Macro Service BRK instruction Instruction execution BRKCS instruction Instruction execution Software − Operand error If result of exclusive OR between operands byte and byte is not FFH when “MOV STBC, #byte” instruction, “MOV WDM, #byte” instruction, or LOCATION instruction is executed −−NMI Pin input edge detection ExternalNon-maskable − INTWDT Overflow of watchdog timer Internal 0 (highest) INTWDTM Overflow of watchdog timer Internal 1I NTP0 2I NTP1 3I NTP2 4I NTP3 5I NTP4 6I NTP5 7I NTP6 Pin input edge detection External INTIIC0 End of I2C bus transfer by CSI08 INTCSI0 End of 3-wire transfer by CSI0 Maskable

9 INTSER1 Occurrence of UART reception error in ASI1

Data Sheet U14121EJ2V0DS00 53 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 8-2. Interrupt Sources (2/2) SourceType Default Priority Name Trigger Internal/ External Macro Service INTSR1 End of UART reception by ASI110 INTCSI1 End of 3-wire transfer by CSI1

11 INTST1 End of UART transmission by ASI1

12 INTSER2 Occurrence of UART reception error in ASI2

INTSR2 End of UART reception by ASI213 INTCSI2 End of 3-wire transfer by CSI2

14 INTST2 End of UART transmission by ASI2

15 INTTM3 Reference time interval signal from watch timer

16 INTTM00 Signal indicating match between 16-bit timer

counter and capture/compare register (CR00)

17 INTTM01 Signal indicating match between 16-bit timer

counter and capture/compare register (CR01)

18 INTTM1 Occurrence of match signal of 8-bit timer/event

19 INTTM2 Occurrence of match signal of 8-bit timer/event

20 INTAD End of conversion by A/D converter

21 INTTM5 Occurrence of match signal of 8-bit timer/event

22 INTTM6 Occurrence of match signal of 8-bit timer/event

23 INTTM7 Occurrence of match signal of 8-bit timer/event

24 INTTM8 Occurrence of match signal of 8-bit timer/event

25 INTWT Overflow of watch timer

26 (lowest) INTKR Detection of falling edge of port 8 External Remarks 1. ASI: Asynchronous Serial Interface CSI: Clocked Serial Interface 2. There are two interrupt sources for the watchdog timer: non-maskable interrupts (INTWDT) and maskable interrupts (INTWDTM). Either one (but not both) should be selected for actual use.

Data Sheet U14121EJ2V0DS0054 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

8.2 Vectored Interrupt

Execution branches to a servicing routine by using the m emory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. So that the CPU performs interrupt servicing, the following operations are performed:

• On branching: Saves the status of the CPU (contents of PC and PSW) to stack
• On returning: Restores the status of the CPU (contents of PC and PSW) from stack To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH. Table 8-3. Vector Table Address Interrupt Source Vector Table Address Interrupt Source Vector Table Address BRK instruction 003EH INTST1 001CH TRAP0 (operand error) 003CH INTSER2 001EH NMI 0002H INSR2 INTWDT (non-maskable) 0004H INTCSI2 0020H INTWDTM (maskable) 0006H INTST2 0022H INTP0 0008H INTTM3 0024H INTP1 000AH INTTM00 0026H INTP2 000CH INTTM01 0028H INTP3 000EH INTTM1 002AH INTP4 0010H INTTM2 002CH INTP5 0012H INTAD 002EH INTP6 0014H INTTM5 0030H INTIIC0 INTTM6 0032H INTCSI0 0016H INTTM7 0034H INTSER1 0018H INTTM8 0036H INTSR1 INTWT 0038H INTCSI1 001AH INTKR 003AH

Data Sheet U14121EJ2V0DS00 55 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

8.3 Context Switching

When an interrupt request is generated or w hen the BR KCS instruction is executed, a predetermined register bank is selected by hardw are. Context switching is a function that branches execution to a vector address stored in advance in the register bank, w hile at the sam e time stacking the current contents of the program counter (PC) and program status word (PSW) to the register bank. The branch address is in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Is Generated Register bank n (n = 0 to 7) 0000B <7> Transfer PC19-16 PC15-0 <6> Exchange <5> Save <2> Save Temporary register <1> Save PSW V U T W A B D H X C E L VP UP <3> Switching of register bank (RBS0 to RBS2 ‹ n) Register bank (0 to 7) (Bits 8 to 11 of temporary register) <4> RSS ‹ 0 IE ‹ 0

Data Sheet U14121EJ2V0DS0056 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

8.4 Macro Service

This function is to transfer data betw een memory and a special function register (SFR) without intervention by the CPU. A m acro service controller accesses the m emory and SFR in the sam e transfer cycle and directly transfers data without loading it. Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds. Figure 8-2. Macro Service CPU Memory SFR Macro service controller Read Write Write Read Internal bus

Data Sheet U14121EJ2V0DS00 57 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

8.5 Application Example of Macro Service

(1) Serial interface transmission Each time macro service requests INTST1 and INTST2 are generated, the next transm it data is transferred from memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the transmit data storage buffer has becom e em pty), vectored interrupt requests IN TST1 and IN TST2 are generated. (2) Serial interface reception Each time macro service requests INTSR1 and IN TSR2 are generated, the receive data is transferred from RXB1 and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt requests INTSR1 and INTSR2 are generated. Transmit data storage buffer (memory) Data n Data n – 1 Data 1 Data 2 Internal bus Transmit shift register TXS1, TXS2 (SFR) Transmit control TxD1, TxD2 INTST1, INTST2 Receive data storage buffer (memory) Data n Data n – 1 Data 1 Data 2 Internal bus Receive shift register RXB1, RXB2 (SFR) Receive control INTSR1, INTSR2 RxD1, RxD2 Receive buffer register

Data Sheet U14121EJ2V0DS0058 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 9. LOCAL BUS INTERFACE The local bus interface can connect an external m emory or I/O (m emory m apped I/O ) and support a m emory space of 1 MB (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface (a) Multiplexed bus mode (b) Separate bus mode m PD784218A RD WR A8 to A19 ASTB AD0 to AD7 VDD Address latch LE Q0 to Q7 D0 to D7 OE SRAM CS OE WE I/O1 to I/O8 A0 to A19 Data bus Address bus VDD Address bus SRAM Data busOE WE A0 to A19 CS I/O1 to I/O8 mPD784218A RD WR A0 to A19 AD0 to AD7

Data Sheet U14121EJ2V0DS00 59 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

9.1 Memory Expansion

External program memory and data memory can be connected in two stages: 256 KB and 1 MB. To connect the external memory, ports 4 through 6 and port 8 are used. The external memory can be connected in the following two modes:

• M ultiplexed bus mode: The external memory is connected by using a tim e-division address/data bus. The number of ports used w hen the external m emory is connected can be reduced in this mode.
• Separate bus mode: The external memory is connected by using an address bus and data bus independent of each other. Because an external latch circuit is not necessary, this mode is useful for reducing the number of components and mounting area on the printed wiring board.

9.2 Programmable Wait

Wait state(s) can be inserted to the memory space (00000H to FFFFFH) while the RD and WR signals are active. In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address decode time.

Data Sheet U14121EJ2V0DS0060 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 10. STANDBY FUNCTION This function is to reduce the power consumption of the chip, and can be used in the following modes:

• HALT mode: Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power consumption.
• IDLE mode: Stops the entire system except for the oscillator, which continues operating. The power consumption in this m ode is close to that in the STOP mode. However, the tim e required to restore the norm al program operation from this mode is almost the same as that from the HALT mode.
• STOP mode: Stops the m ain system clock and thereby stops all the internal operations of the chip. C onsequently, the pow er consum ption is minimized with only leakage current flowing.
• Low power consumption mode: The main system clock is stopped and the subsystem clock is used as the system clock. The C PU can operate on the subsystem clock to reduce the current consumption.
• Low power consumption HALT mode: This is a standby function in the low pow er consum ption m ode and stops the operation clock of the CPU, to reduce the pow er consumption of the entire system.
• Low power consumption IDLE mode: This is a standby function in the low pow er consum ption m ode and stops the entire system except the oscillator, to reduce the pow er consumption of the entire system. These modes are programmable. The macro service can be started from the H ALT m ode or low pow er consum ption H ALT m ode. After m acro service processing is executed, the system returns to the HALT mode again. The transition of the standby status is shown in Figure 10-1.

Data Sheet U14121EJ2V0DS00 61 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Figure 10-1. Standby Function State Transitions Notes 1. Only unmasked interrupt requests 2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87) Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby (HALT mode/STOP mode/IDLE mode). Wait for stable oscillation Normal operation (Main system clock operation) Macro service HALT (Standby) IDLE (Standby) Low power consumption mode (Subsystem clock operation) Low power consumption HALT mode (Standby) Low power consumption IDLE mode (Standby) STOP (Standby) RESET input Macro service request One-time processing ends Macro service ends Macro service request One-time processing ends Interrupt request RESET input HALT set IDLE set RESET input NMI, INTP0 to INTP6 input, INTWT,key return interrupt Note 2 NMI, INTP0 to INTP6 input, INTWT, key return interrupt Note 2 STOP set Low power consumption IDLE mode set RESET input Low power consumption mode setReturn to normal operation NMI, INTP0 to INTP6 input, INTWT, key return interrupt Note 2 Low power consumption HALT mode set RESET input Interrupt requestNote 1 Interrupt request for masked interrupt Interrupt request for masked interrupt Interrupt request for masked interrupt Interrupt request for masked interrupt Interrupt request for masked interrupt RESET input RESET input Macro service Macro service request Macro service request One-time processing ends Macro service ends One-time processing ends

Data Sheet U14121EJ2V0DS00 63 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 12. INSTRUCTION SET (1) 8-bit instructions (instructions in parentheses are combinations realized by describing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MUL U, DIVUW, INC, DEC, ROR, ROL , RORC, ROLC, SHR, SHL , ROR4 , ROL 4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC Table 12-1. Instruction List by 8-Bit Addressing Second Operand First Operand #byte A r saddr saddr' sfr !addr16 !!addr24 mem [saddrp] [%saddrg] PSWL PSWH [WHL+] [WHL−] n None Note 2 A (MOV) ADD Note 1 (MOV) (XCH) (ADD) Note 1 MOV XCH (ADD) Note 1 (MOV) Note 6 (XCH) Note 6 (ADD) Notes 1, 6 MOV (XCH) (ADD) Note 1 (MOV) (XCH) ADD Note 1 MOV XCH ADD Note 1 MOV (MOV) (XCH) (ADD) Note 1 r MOV ADD Note 1 (MOV) (XCH) (ADD) Note 1 MOV XCH ADD Note 1 MOV XCH ADD Note 1 MOV XCH ADD Note 1 MOV XCH ROR Note 3 MULU DIVUW INC DEC saddr MOV ADD Note 1 (MOV) Note 6 (ADD) Note 1 MOV ADD Note 1 MOV XCH ADD Note 1 INC DEC DBNZ sfr MOV ADD Note 1 MOV (ADD) Note 1 MOV ADD Note 1 PUSH POP !addr16 !!addr24 MOV (MOV) ADD Note 1 MOV mem [saddrp] [%saddrg] MOV ADD Note 1 mem3 ROR4 ROL4 PSWL PSWH MOV MOV B, C DBNZ STBC, WDM MOV [TDE+] [TDE−] (MOV) Note 6 (ADD) Note 1 MOVM Note 4 MOVBK Note 5 Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR. 4. The operands of XC HM, C MPME, C MPMNE, C MPMNC, and C MPMC are the sam e as that of MOVM. 5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK. 6. The code length of some instructions having saddr2 as saddr in this combination is short.

Data Sheet U14121EJ2V0DS0064 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) 16-bit instructions (instructions in parentheses are combinations realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CM PW, M ULUW, M ULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instruction List by 16-Bit Addressing Second Operand First Operand #word AX rp rp' saddrp saddrp' sfrp !addr16 !!addr24 mem [saddrp] [%saddrg] [WHL+] byte n None Note 2 AX (MOVW) ADDW Note 1 (MOVW) (XCHW) (ADD) Note 1 (MOVW) (XCHW) (ADDW) Note 1 (MOVW) Note 3 (XCHW) Note 3 (ADDW) Notes 1, 3 MOVW (XCHW) (ADDW) Note 1 (MOVW) XCHW MOVW XCHW (MOVW) (XCHW) rp MOVW ADDW Note 1 (MOVW) (XCHW) (ADDW) Note 1 MOVW XCHW ADDW Note 1 MOVW XCHW ADDW Note 1 MOVW XCHW ADDW Note 1 MOVW SHRW SHLW MULU Note 4 INCW DECW saddrp MOVW ADDW Note 1 (MOVW) Note 3 (ADDW) Note 1 MOVW ADDW Note 1 MOVW XCHW ADDW Note 1 INCW DECW sfrp MOVW ADDW Note 1 MOVW (ADDW) Note 1 MOVW ADDW Note 1 PUSH POP !addr16 !!addr24 MOVW (MOVW) MOVW MOVTBLW mem [saddrp] [%saddrg] MOVW PSW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] (MOVW) SACW byte MACW MACSW Notes 1. The operands of SUBW and CMPW are the same as that of ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The code length of some instructions having saddrp2 as saddrp in this combination is short. 4. The operands of MULUW and DIVUX are the same as that of MULW.

Data Sheet U14121EJ2V0DS00 65 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (3) 24-bit instructions (instructions in parentheses are combinations realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instruction List by 24-Bit Addressing Second Operand First Operand #imm24 WHL rg rg' saddrg !!addr24 mem1 [%saddrg] SP None Note WHL (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) ADDG SUBG (MOVG) MOVG MOVG MOVG rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg (MOVG) MOVG !!addr24 (MOVG) MOVG mem1 MOVG [%saddrg] MOVG SP MOVG MOVG INCG DECG Note Either the second operand is not used, or the second operand is not an operand address.

Data Sheet U14121EJ2V0DS0066 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 12-4. Instruction List by Bit Manipulation Instruction Addressing Second Operand First Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit /saddr.bit /sfr. bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit None Note CY MOV1 AND1 OR1 XOR1 AND1 OR1 NOT1 SET1 CLR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BF BT BTCLR BFSET Note Either the second operand is not used, or the second operand is not an operand address.

Data Sheet U14121EJ2V0DS00 67 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (5) Call and return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 12-5. Instruction List by Call and Return/Branch Instruction Addressing Operand of Instruction Address $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None Basic instruction BC Note BR CALL BR CALL BR RETCS RETCSB CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLF BRKCS BRK RET RETI RETB Compound instruction BF BT BTCLR BFSET DBNZ Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO , BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as that of BC. (6) O ther instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS

Data Sheet U14121EJ2V0DS0068 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 13. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Symbol Conditions Ratings Unit VDD −0.3 to +6.5 V AVDD −0.3 to VDD + 0.3 V AVSS −0.3 to VSS + 0.3 V AVREF0 A/D converter reference voltage input −0.3 to VDD + 0.3 V Supply voltage AVREF1 D/A converter reference voltage input −0.3 to VDD + 0.3 V VI1 Other than P90 to P95 −0.3 to VDD + 0.3 VInput voltage VI2 P90 to P95 N-ch open drain −0.3 to +12 V Analog input voltage V AN Analog input pin AVSS − 0.3 to AVREF0 + 0.3 V Output voltage VO −0.3 to VDD + 0.3 V Per pin 15 mA Total of P2, P4 to P8 75 mA Total of P0, P3, P9, P10, P12, P13 75 mA Output current, low I OL Total of all pins 100 mA Per pin −10 mAOutput current, high I OH Total of all pins −50 mA Operating ambient temperature TA −40 to +85 °C Storage temperature T stg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at w hich the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.

Data Sheet U14121EJ2V0DS00 69 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Operating Conditions

• Operating ambient temperature (T A): −40 to +85°C
• Power supply voltage and clock cycle time: See Figure 13-1
• Power supply voltage with subsystem clock operation: V DD = 1.8 to 5.5 V Figure 13-1. Power Supply Voltage and Clock Cycle Time (CPU Clock Frequency: f CPU) Capacitance (TA = 25°°C, VDD = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Other than Port 9 15 pFInput capacitance CI Port 9 20 pF Other than Port 9 15 pFOutput capacitance C O Port 9 20 pF Other than Port 9 15 pFI/O capacitance CIO f = 1 MHz Unmeasured pins returned to 0 V. Port 9 20 pF 8,000 10,000 500 400 300 320 160 200 100 0123 1.8 2.7 4.5 5.5 Supply voltage [V] 456 Clock cycle time tCYK [ns] Guaranteed operating range

Data Sheet U14121EJ2V0DS0070 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Main System Clock Oscillator Characteristics (TA = −−40 to +85°C) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 2 12.5 2.7 V ≤ VDD < 4.5 V 2 6.25 2.0 V ≤ VDD < 2.7 V 2 3.125 Ceramic resonator or crystal resonator X2 X1 V SS Oscillation frequency 1.8 V ≤ VDD < 2.0 V 2 2 MHz 4.5 V ≤ VDD ≤ 5.5 V 2 12.5 2.7 V ≤ VDD < 4.5 V 2 6.25 2.0 V ≤ VDD < 2.7 V 2 3.125 X1 input frequency (fX) 1.8 V ≤ VDD < 2.0 V 2 2 MHz X1 input high-/low- level width (t WXH, tWXL) 15 250 ns 4.5 V ≤ VDD ≤ 5.5 V 0 5 2.7 V ≤ VDD < 4.5 V 0 10 2.0 V ≤ VDD < 2.7 V 0 20 External clock X2 X1 PD74HCU04m X1 input rising/falling time (t XR, tXF) 1.8 V ≤ VDD < 2.0 V 0 30 ns Cautions 1. When using the main system clock oscillator, wire as follow s in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• • Keep the wiring length as short as possible.
• • Do not cross the wiring with other signal lines.
• • Do not route the wiring near a signal line through which a high fluctuating current flows.
• • Always make the ground point of the oscillator capacitor the same potential as V SS.
• • Do not ground the capacitor to a ground pattern through which a high current flows.
• • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be sw itched back to the main system clock after the oscillation stabilization time is secured by the program. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U14121EJ2V0DS00 71 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Subsystem Clock Oscillator Characteristics (TA = −40 to +85°°C) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillation frequency (fXT) 32 32.768 35 kHz 4.5 V ≤ VDD ≤ 5.5 V 1.2 2 Crystal resonator VSS XT2 XT1 Oscillation stabilization timeNote 1.8 V ≤ VDD < 4.5 V 10 s XT1 input frequency (fXT) 32 35 kHzExternal clock XT2 XT1 PD74HCU04m XT1 input high-/low- level width (t XTH, tXTL) 14.3 15.6 µs Note Time required to stabilize oscillation after applying supply voltage (V DD). Cautions 1. When using the subsystem clock oscillator, w ire as follow s in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• • Do not route the wiring near a signal line through which a high fluctuating current flows.
• • Always make the ground point of the oscillator capacitor the same potential as V SS.
• • Do not ground the capacitor to a ground pattern through which a high current flows.
• • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U14121EJ2V0DS0072 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY DC Characteristics (TA = −−40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (1/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.2 V ≤ VDD ≤ 5.5 V 0 0.3VDDVIL1 Note 1 1.8 V ≤ VDD < 2.2 V 0 0.2VDD V 2.2 V ≤ VDD ≤ 5.5 V 0 0.2VDDVIL2 P00 to P06, P20, P22, P33, P34, P70, P72, P100 to P103, RESET

1.8 V ≤ V

DD < 2.2 V 0 0.15VDD V 2.2 V ≤ VDD ≤ 5.5 V 0 0.3VDDVIL3 P90 to P95 (N-ch open drain) 1.8 V ≤ V DD < 2.2 V 0 0.2VDD V 2.2 V ≤ VDD ≤ 5.5 V 0 0.3VDDVIL4 P10 to P17, P130, P131 1.8 V ≤ VDD < 2.2 V 0 0.2VDD V 2.2 V ≤ VDD ≤ 5.5 V 0 0.2VDDVIL5 X1, X2, XT1, XT2 1.8 V ≤ VDD < 2.2 V 0 0.1VDD V 2.2 V ≤ VDD ≤ 5.5 V 0 0.3VDD Input voltage, low VIL6 P25, P27 1.8 V ≤ VDD < 2.2 V 0 0.2VDD V 2.2 V ≤ VDD ≤ 5.5 V 0.7V DD VDDVIH1 Note 1 1.8 V ≤ VDD < 2.2 V 0.8V DD VDD V 2.2 V ≤ VDD ≤ 5.5 V 0.8V DD VDDVIH2 P00 to P06, P20, P22, P33, P34, P70, P72, P100 to P103, RESET DD < 2.2 V 0.85V DD VDD V 2.2 V ≤ VDD ≤ 5.5 V 0.7V DD 12VIH3 P90 to P95 (N-ch open drain) 1.8 V ≤ V DD < 2.2 V 0.8V DD VDD V 2.2 V ≤ VDD ≤ 5.5 V 0.7V DD VDDVIH4 P10 to P17, P130, P131 1.8 V ≤ VDD < 2.2 V 0.8V DD VDD V 2.2 V ≤ VDD ≤ 5.5 V 0.8V DD VDDVIH5 X1, X2, XT1, XT2 1.8 V ≤ VDD < 2.2 V 0.85V DD VDD V 2.2 V ≤ VDD ≤ 5.5 V 0.7V DD VDD Input voltage, high VIH6 P25, P27 1.8 V ≤ VDD < 2.2 V 0.8V DD VDD V For pins other than P40 to P47, P50 to P57, P90 to P95 I OL = 1.6 mA Note 1 4.5 V ≤ VDD ≤ 5.5 V 0.4 V P40 to P47, P50 to P57 I OL = 8 mA Note 2 4.5 V ≤ VDD ≤ 5.5 V 1.0 V VOL1 P90 to P95 IOL = 15 mA Note 2 4.5 V ≤ VDD ≤ 5.5 V 0.8 2.0 V Output voltage, low VOL2 IOL = 400 µA Note 2 0.5 V IOH = −1 mA Note 2 4.5 V ≤ VDD ≤ 5.5 V V DD − 1.0 VOutput voltage, high VOH1 IOL = −100 µA Note 2 VDD − 0.5 V ILIL1 Except X1, X2, XT1 XT2 −3 µAInput leakage current, low ILIL2 VIN = 0 V X1, X2, XT1, XT2 −20 µA ILIH1 Except X1, X2, XT1 XT2 µA ILIH2 VIN = VDD X1, X2, XT1, XT2 20 µA Input leakage current, high ILIH3 VIN = 12 V (N-ch open drain) P90 to P95 20 µA Output leakage current, low I LOL1 VOUT = 0 V −3 µA Output leakage current, high I LOH1 VOUT = VDD 3 µA Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87, P120 to P127 2. Per pin

Data Sheet U14121EJ2V0DS00 73 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY DC Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (2/3) (1) µPD784214A, 784215A, 784216A, 784214AY, 784215AY, 784216AY Parameter Symbol Conditions MIN. TYP. MAX. Unit fXX = 12.5 MHz, VDD = 5.0 V ±10% 11 40 mA fXX = 6 MHz, VDD = 3.0 V ±10% 3 17 mA IDD1 Operation mode fXX = 2 MHz, VDD = 2.0 V ±10% 1 8 mA fXX = 12.5 MHz, VDD = 5.0 V ±10% 5 20 mA fXX = 6 MHz, VDD = 3.0 V ±10% 2 8 mA IDD2 HALT mode fXX = 2 MHz, VDD = 2.0 V ±10% 0.3 3.5 mA fXX = 12.5 MHz, VDD = 5.0 V ±10% 1 2.5 mA fXX = 6 MHz, VDD = 3.0 V ±10% 0.4 1.3 mA IDD3 IDLE mode fXX = 2 MHz, VDD = 2.0 V ±10% 0.2 0.9 mA fXX = 32 kHz, VDD = 5.0 V ±10% 80 200 µA fXX = 32 kHz, VDD = 3.0 V ±10% 60 110 µA IDD4 Operation modeNote fXX = 32 kHz, VDD = 2.0 V ±10% 30 100 µA fXX = 32 kHz, VDD = 5.0 V ±10% 60 160 µA fXX = 32 kHz, VDD = 3.0 V ±10% 20 80 µA IDD5 HALT mode Note fXX = 32 kHz, VDD = 2.0 V ±10% 10 70 µA fXX = 32 kHz, VDD = 5.0 V ±10% 50 150 µA fXX = 32 kHz, VDD = 3.0 V ±10% 15 70 µA Supply current IDD6 IDLE mode Note fXX = 32 kHz, VDD = 2.0 V ±10% 5 60 µA Data retention voltage V DDDR HALT, IDLE modes 1.8 5.5 V VDD = 2.0 V ±10% 2 10 µAData retention current I DDDR STOP mode VDD = 5.0 V ±10% 10 50 µA Pull-up resistor RL VIN = 0 V 10 30 100 k Ω Note When main system clock is stopped and subsystem clock is operating. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.

Data Sheet U14121EJ2V0DS0074 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY DC Characteristics (TA = −−40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (3/3) (2) µPD784217A, 784218A, 784217AY, 784218AY Parameter Symbol Conditions MIN. TYP. MAX. Unit fXX = 12.5 MHz, VDD = 5.0 V ±10% 11 40 mA fXX = 6 MHz, VDD = 3.0 V ±10% 4 17 mA IDD1 Operation mode fXX = 2 MHz, VDD = 2.0 V ±10% 1 8 mA fXX = 12.5 MHz, VDD = 5.0 V ±10% 6 20 mA fXX = 6 MHz, VDD = 3.0 V ±10% 2 8 mA IDD2 HALT mode fXX = 2 MHz, VDD = 2.0 V ±10% 0.4 3.5 mA fXX = 12.5 MHz, VDD = 5.0 V ±10% 1 2.5 mA fXX = 6 MHz, VDD = 3.0 V ±10% 0.4 1.3 mA IDD3 IDLE mode fXX = 2 MHz, VDD = 2.0 V ±10% 0.2 0.9 mA fXX = 32 kHz, VDD = 5.0 V ±10% 80 200 µA fXX = 32 kHz, VDD = 3.0 V ±10% 60 110 µA IDD4 Operation modeNote fXX = 32 kHz, VDD = 2.0 V ±10% 30 100 µA fXX = 32 kHz, VDD = 5.0 V ±10% 60 160 µA fXX = 32 kHz, VDD = 3.0 V ±10% 20 80 µA IDD5 HALT mode Note fXX = 32 kHz, VDD = 2.0 V ±10% 10 70 µA fXX = 32 kHz, VDD = 5.0 V ±10% 50 150 µA fXX = 32 kHz, VDD = 3.0 V ±10% 15 70 µA Supply current IDD6 IDLE mode Note fXX = 32 kHz, VDD = 2.0 V ±10% 5 60 µA Data retention voltage V DDDR HALT, IDLE modes 1.8 5.5 V VDD = 2.0 V ±10% 2 10 µAData retention current I DDDR STOP mode VDD = 5.0 V ±10% 10 50 µA Pull-up resistor RL VIN = 0 V 10 30 100 k Ω Note When main system clock is stopped and subsystem clock is operating. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.

Data Sheet U14121EJ2V0DS00 75 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY AC Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 80 ns 2.7 V ≤ VDD < 4.5 V 160 ns 2.0 V ≤ VDD < 2.7 V 320 ns Cycle time tCYK 1.8 V ≤ VDD < 2.0 V 500 ns Address setup time (to ASTB↓)t SAST VDD = 5.0 V ±10% 0.5T − 19 ns VDD = 3.0 V ±10% 0.5T − 24 ns Address hold time (from ASTB↓)t HSTLA VDD = 2.0 V ±10% 0.5T − 34 ns ASTB high-level width tWSTH VDD = 2.0 V ±10% (0.5 + a)T − 110 ns VDD = 5.0 V ±10% 0.5T − 14 ns VDD = 3.0 V ±10% 0.5T − 14 ns Address hold time (from RD↑)t HRA VDD = 2.0 V ±10% 0.5T − 14 ns VDD = 5.0 V ±10% (1 + a)T − 24 ns VDD = 3.0 V ±10% (1 + a)T − 35 ns Delay time from address to RD↓ tDAR VDD = 2.0 V ±10% (1 + a)T − 80 ns VDD = 5.0 V ±10% 0 ns VDD = 3.0 V ±10% 0 ns Address float time (from RD↓)t FAR VDD = 2.0 V ±10% 0 ns Data input time from address t DAID VDD = 2.0 V ±10% (2.5 + a + n)T − 120 ns VDD = 5.0 V ±10% (2 + n)T − 35 ns VDD = 3.0 V ±10% (2 + n)T − 50 ns Data input time from ASTB↓ tDSTID VDD = 2.0 V ±10% (2 + n)T − 80 ns Data input time from RD↓ tDRID VDD = 5.0 V ±10% 0.5T − 9n s VDD = 3.0 V ±10% 0.5T − 9n s Delay time from ASTB↓ to RD↓ tDSTR VDD = 2.0 V ±10% 0.5T − 20 ns VDD = 5.0 V ±10% 0 ns VDD = 3.0 V ±10% 0 ns Data hold time (from RD↑)t HRID VDD = 2.0 V ±10% 0 ns Remark T: t CYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of waits (n ≥ 0)

Data Sheet U14121EJ2V0DS0076 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY AC Characteristics (1) Read/write operation (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD = 5.0 V ±10% 0.5T − 2n s VDD = 3.0 V ±10% 0.5T − 12 ns Address active time from RD↑ tDRA VDD = 2.0 V ±10% 0.5T − 35 ns VDD = 5.0 V ±10% 0.5T − 9n s VDD = 3.0 V ±10% 0.5T − 9n s Delay time from RD↑ to ASTB↑ tDRST VDD = 2.0 V ±10% 0.5T − 40 ns RD low-level width tWRL VDD = 5.0 V ±10% (1 + a)T − 24 ns VDD = 3.0 V ±10% (1 + a)T − 34 ns Delay time from address to WR↓ tDAW VDD = 2.0 V ±10% (1 + a)T − 70 ns VDD = 5.0 V ±10% 0.5T − 14 ns VDD = 3.0 V ±10% 0.5T − 14 ns Address hold time (from WR↑)t HRD VDD = 2.0 V ±10% 0.5T − 14 ns VDD = 5.0 V ±10% 0.5T + 15 ns VDD = 3.0 V ±10% 0.5T + 30 ns Delay time from ASTB ↓ t o dat a output tDSTOD VDD = 2.0 V ±10% 0.5T + 240 ns VDD = 5.0 V ±10% 0.5T − 30 ns VDD = 3.0 V ±10% 0.5T − 30 ns Delay time fr om W R↓ t o dat a output tDWOD VDD = 2.0 V ±10% 0.5T − 30 ns VDD = 5.0 V ±10% 0.5T − 9n s VDD = 3.0 V ±10% 0.5T − 9n s Delay time from ASTB↓ to WR↓ tDSTW VDD = 2.0 V ±10% 0.5T − 20 ns Data setup time (to WR↑)t SODWR VDD = 5.0 V ±10% 0.5T − 14 ns VDD = 3.0 V ±10% 0.5T − 14 ns Data hold time (from WR↑)t HWOD VDD = 2.0 V ±10% 0.5T − 50 ns VDD = 5.0 V ±10% 0.5T − 9n s VDD = 3.0 V ±10% 0.5T − 9n s Delay time from WR↑ to ASTB↑ tDWST VDD = 2.0 V ±10% 0.5T − 30 ns WR low-level width tWWL Remark T: t CYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0)

Data Sheet U14121EJ2V0DS00 77 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY AC Characteristics (2) External wait timing Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD = 5.0 V ±10% (2 + a)T − 40 ns VDD = 3.0 V ±10% (2 + a)T − 60 ns Input time from address to WAIT↓ tDAWT VDD = 2.0 V ±10% (2 + a)T − 300 ns VDD = 5.0 V ±10% 1.5T − 40 ns VDD = 3.0 V ±10% 1.5T − 60 ns Input time from ASTB↓ to WAIT↓ tDSTWT VDD = 2.0 V ±10% 1.5T − 260 ns Hold time from ASTB↓ to WAIT tHSTWT Delay time from ASTB↓ to WAIT↑ tDSTWTH VDD = 5.0 V ±10% T − 40 ns VDD = 3.0 V ±10% T − 60 ns Input time from RD↓ to WAIT↓ tDRWTL VDD = 2.0 V ±10% T − 70 ns VDD = 5.0 V ±10% nT + 5n s VDD = 3.0 V ±10% nT + 10 ns Hold time from RD↓ to WAIT↓ tHRWT VDD = 2.0 V ±10% nT + 30 ns VDD = 5.0 V ±10% (1 + n)T − 40 ns VDD = 3.0 V ±10% (1 + n)T − 60 ns Delay time from RD↓ to WAIT↑ tDRWTH VDD = 2.0 V ±10% (1 + n)T − 90 ns VDD = 5.0 V ±10% 0.5T − 5n s VDD = 3.0 V ±10% 0.5T − 10 ns Data input time from WAIT↑ tDWTID VDD = 2.0 V ±10% 0.5T − 30 ns VDD = 5.0 V ±10% 0.5T ns VDD = 3.0 V ±10% 0.5T ns Delay time from WAIT↑ to RD↑ tDWTR VDD = 2.0 V ±10% 0.5T + 5n s VDD = 5.0 V ±10% 0.5T ns VDD = 3.0 V ±10% 0.5T ns Delay time from WAIT↑ to WR↑ tDWTW VDD = 2.0 V ±10% 0.5T + 5n s VDD = 5.0 V ±10% T − 40 ns VDD = 3.0 V ±10% T − 60 ns Input time from WR↓ to WAIT↓ tDWWTL VDD = 2.0 V ±10% T − 90 ns VDD = 5.0 V ±10% nT + 5n s VDD = 3.0 V ±10% nT + 10 ns Hold time from WR↓ to WAIT tHWWT VDD = 2.0 V ±10% nT + 30 ns VDD = 5.0 V ±10% (1 + n)T − 40 ns VDD = 3.0 V ±10% (1 + n)T − 60 ns Delay time from WR↓ to WAIT↑ tDWWTH VDD = 2.0 V ±10% (1 + n)T − 90 ns Remark T: t CYK = 1/fXX (fXX: main system clock frequency) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0)

Data Sheet U14121EJ2V0DS0078 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Serial Operation (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (a) 3-wire serial I/O mode (SCK: Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.7 V ≤ VDD ≤ 5.5 V 800 nsSCK cycle time tKCY1 3,200 ns 2.7 V ≤ VDD ≤ 5.5 V 350 nsSCK high-/low-level width t KH1, tKL1 1,500 ns 2.7 V ≤ VDD ≤ 5.5 V 10 nsSI setup time (to SCK↑)t SIK1 30 ns SI hold time (from SCK↑)t KSI1 40 ns SO output delay time (from SCK↓) tKSO1 30 ns (b) 3-wire serial I/O mode (SCK: External clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.7 V ≤ VDD ≤ 5.5 V 800 nsSCK cycle time tKCY2 3,200 ns 2.7 V ≤ VDD ≤ 5.5 V 400 nsSCK high-/low-level width tKH2 tKL2 1,600 ns 2.7 V ≤ VDD ≤ 5.5 V 10 nsSI setup time (to SCK↑)t SIK2 30 ns SI hold time (from SCK↑)t KSI2 40 ns SO output delay time (from SCK↓) t KSO2 30 ns (c) UART mode Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 417 ns 2.7 V ≤ VDD < 4.5 V 833 ns ASCK cycle time tKCY3 1,667 ns 4.5 V ≤ VDD ≤ 5.5 V 208 ns 2.7 V ≤ VDD < 4.5 V 416 ns ASCK high-/low-level width t KH3 tKL3 833 ns

Data Sheet U14121EJ2V0DS00 79 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (d) I2C bus mode Standard Mode High-Speed ModeParameter Symbol MIN. MAX. MIN. MAX. Unit SCL0 clock frequency fCLK 0 100 0 400 kHz Bus free time (between stop and start conditions) tBUF 4.7 − 1.3 − µs Hold timeNote1 tHD : STA 4.0 − 0.6 − µs Low-level width of SCL0 clock t LOW 4.7 − 1.3 − µs High-level width of SCL0 clock t HIGH 4.0 − 0.6 − µs Setup time of start/restart conditions t SU : STA 4.7 − 0.6 − µs When using CBUS- compatible master 5.0 −−− µsData hold time When using I 2C bus tHD : DAT 0Note 2 − 0Note 2 0.9Note 3 µs Data setup time tSU : DAT 250 − 100Note 4 − ns Rise time of SDA0 and SCL0 signals t R − 1,000 20 + 0.1Cb Note 5 300 ns Fall time of SDA0 and SCL0 signals t F − 300 20 + 0.1Cb Note 5 300 ns Setup time of stop condition t SU : STO 4.0 − 0.6 − µs Pulse width of spike restricted by input filter t SP −− 05 0 n s Load capacitance of each bus line Cb − 400 − 400 pF Notes 1. For the start condition, the first clock pulse is generated after the hold time. 2. To fill the undefined area of the SC L0 falling edge, it is necessary for the device to provide an internal SDA0 signal (on VIHmin.) with at least 300 ns of hold time. 3. If the device does not extend the SC L0 signal low-level hold time (t LOW), only the m aximum data hold time tHD : DAT needs to be satisfied. 4. The high-speed m ode I 2C bus can be used in a standard m ode I 2C bus system . In this case, the conditions described below must be satisfied.

• If the device does not extend the SCL0 signal low-level hold time t SU : DAT ≥ 250 ns
• If the device extends the SCL0 signal low-level hold time Be sure to transmit the data bit to the SD A0 line before the SCL0 line is released (tRmax. + tSU : DAT = 1,000 + 250 = 1,250 ns by standard mode I2C bus specification) 5. Cb: Total capacitance per bus line (unit: pF)

Data Sheet U14121EJ2V0DS0080 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Other Operations (TA = −−40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit NMI high-/low-level width tWNIL tWNIH 10 µs INTP input high-/low-level width t WITL tWITH INTP0 to INTP6 100 ns RESET high-/low-level width tWRSL tWRSH 10 µs Clock Output Operation (TA = −−40 to +85°° °°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit PCL cycle time tCYCL 4.5 V ≤ VDD ≤ 5.5 V, nT 80 31,250 ns PCL high-/low-level width tCLL tCLH 4.5 V ≤ VDD ≤ 5.5 V, 0.5T − 10 30 15,615 ns 4.5 V ≤ VDD ≤ 5.5 V 5 ns 2.7 V ≤ VDD < 4.5 V 10 ns PCL rise/fall time tCLR tCLF 1.8 V ≤ VDD < 2.7 V 20 ns Remark T: t CYK = 1/fXX (fXX: Main system clock frequency) n: Divided frequency ratio set by software in the CPU

• When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128
• When using the subsystem clock: n = 1

Data Sheet U14121EJ2V0DS00 81 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY A/D Converter Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 888 b i t s 2.7 V ≤ VDD ≤ 5.5 V

2.2 V ≤ AVREF0 ≤ VDD

±1.2 %FSROverall errorNotes 1, 2 1.8 V ≤ VDD < 2.7 V

1.8 V ≤ AVREF0 ≤ VDD

±1.6 %FSR Conversion time tCONV 14 144 µs Sampling time tSAMP 24/fXX µs Analog input voltage VIAN AVSS AVREF0 V Reference voltage AVREF0 1.8 AVDD V Resistance between AVREF0 and AVSS RAVREF0 When not A/D converting 40 kΩ Notes 1. Quantization error (±1/2 LSB) is not included. 2. Overall error is indicated as a ratio to the full-scale value. Remark f XX : Main system clock frequency D/A Converter Characteristics (TA = −40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 888 B i t s R = 10 MΩ , 2.0 V ≤ AVREF1 ≤ VDD, 2.0 V ≤ VDD ≤ 5.5 V ±0.6 %FSROverall errorNotes 1, 2 R = 10 MΩ , 1.8 V ≤ AVREF1 ≤ VDD, 1.8 V ≤ VDD ≤ 2.0 V ±1.2 %FSR 4.5 V ≤ AVREF1 ≤ 5.5 V 10 µs 2.7 V ≤ AVREF1 < 4.5 V 15 µs Settling time Load conditions: C = 30 pF 1.8 V ≤ AVREF1 < 2.7 V 20 µs Output resistance RO DACS0, 1 = 55H 8 kΩ Reference voltage AVREF1 1.8 VDD V AVREF1 current AIREF1 For only 1 channel 2.5 mA Notes 1. Quantization error (±1/2 LSB) is not included. 2. Overall error is indicated as a ratio to the full-scale value.

Data Sheet U14121EJ2V0DS0082 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Data Retention Characteristics (TA = −−40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage VDDDR STOP mode 1.8 5.5 V VDDDR = 5.0 V ±10% 10 50 µAData retention current IDDDR VDDDR = 2.0 V ±10% 2 10 µA VDD rise time tRVD 200 µs VDD fall time tFVD 200 µs VDD hold time (from STOP mode setting) tHVD 0m s STOP release signal input time t DREL 0m s Crystal resonator 30 msOscillation stabilization wait time t WAIT Ceramic resonator 5 ms Low-level input voltage VIL 00 .1VDDDR V High-level input voltage VIH RESET, P00/INTP0 to P06/INTP6 0.9VDDDR VDDDR V AC Timing Test Points 0.8VDD or 1.8 V 0.8 V 0.8VDD or 1.8 V 0.8 V Test points VDD - 1 V 0.45 V

Data Sheet U14121EJ2V0DS00 83 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Timing Waveforms (1) Read operations Remark The signal is output from pins A0 to A7 when P80 to P87 are unused. (CLK) A8 to A19 (Output) ASTB (Output) RD (Output) WAIT (Input) AD0 to AD7 (Input/output) tCYK Higher address Hi-Z Hi-Z Hi-Z Higher address A0 to A7 (Output) Lower address Lower address Data (Input)Lower address (Output) Lower address (Output) tDAID tHRA tSAST tWSTH tDSTR tDRST tDAR tDRID tWRL tDRWTH tDSTWT tDSTWTH tHSTWT tHRWT tDAWT tDWTR tHSTLA tFAR tDWTID tDRWTL tHRID tDRAtDSTID

Data Sheet U14121EJ2V0DS0084 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (2) Write operation Remark The signal is output from pins A0 to A7 when P80 to P87 are unused. (CLK) A8 to A19 (Output) ASTB (Output) WAIT (Input) AD0 to AD7 (Output) tCYK tDAID tHWA tSAST tWSTH tDSTW tDWST tDAW tDWOD tWWL tDWWTH tDSTWT tDSTWTH tHSTWT tHWWT tDAWT tDWTW tHSTLA tFAR tDWTID tDWWTL tHWOD tDAWtDSTOD tSODWR Hi-Z Hi-Z Hi-Z WR (Output) Higher address Higher address A0 to A7 (Output) Lower address Lower address Data (Output)Lower address (Output) Lower address (Output)

Data Sheet U14121EJ2V0DS00 85 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Serial Operation (1) 3-wire serial I/O mode (2) UART mode (3) I 2C bus mode (µPD784216AY/784218AY Subseries only) SCK SI/SO tKCY1, 2 tKL1, 2 tKH1, 2 tKSO1, 2 tSIK1, 2 tKSI1, 2 ASCK tKCY3 tKH3 tKL3 SCL0 SDA0 tR tHD : DAT tHD : STA tBUF tHIGH tSU : DAT tF tSU : STA tHD : STA tSP tSU : STO Stop condition Start condition Restart condition Stop condition

Data Sheet U14121EJ2V0DS0086 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Clock Output Timing Interrupt Input Timing Reset Input Timing CLKOUT tCLH tCLL tCYCL tCLFtCLR NMI INTP0 to INTP6 tWNIH tWNIL tWITH tWITL RESET tWRSH tWRSL

Data Sheet U14121EJ2V0DS00 87 µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Clock Timing Data Retention Characteristics tWXH tWXL 1/fX tXFtXR XT1 tXTH tXTL 1/fXT VDD RESET NMI (Cleared by falling edge) NMI (Cleared by rising edge) tHVD tFVD tRVD tDREL VDDDR STOP mode setting tWAIT

Data Sheet U14121EJ2V0DS0088 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 14. PACKAGE DRAWINGS Remark The external dimensions and material of the ES version are the same as those of the mass-produced version. 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 16.00– 0.20 14.00– 0.20 0.50 (T.P.) 1.00 J 16.00– 0.20 K C 14.00 –0.20 I 0.08 1.00– 0.20 L 0.50– 0.20 F 1.00 N P Q 0.08 1.40– 0.05 0.10– 0.05 S100GC-50-8EU, 8EA-2 S 1.60 MAX. H 0.22 +0.05 -0.04 M 0.17 +0.03 -0.07 R3 °+7° -3° 1 25 100 75 51 S S N J detail of lead end C D A B R K M L P I S Q G F MH

Data Sheet U14121EJ2V0DS00 89 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Remark The external dimensions and material of the ES version are the same as those of the mass-produced version. 81 50 1001 100-PIN PLASTIC QFP (14x20) HI J detail of lead end M Q R K M L P S S N G F NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 23.6– 0.4 20.0– 0.2 0.30– 0.10 0.6 H 17.6– 0.4 I C 14.0– 0.2 0.15 J 0.65 (T.P.) K 1.8– 0.2 L 0.8– 0.2 F 0.8 P100GF-65-3BA1-4 N P Q 0.10 2.7– 0.1 0.1– 0.1 R5 °–5° S 3.0 MAX. M 0.15 +0.10 -0.05 C D A B S

Data Sheet U14121EJ2V0DS0090 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY 15. RECOMMENDED SOLDERING CONDITIONS The µPD784218A should be soldered and mounted under the following recommended conditions. For the details of the recom mended soldering conditions, refer to the docum ent Semiconductor Device M ounting Technology Manual (C10535E). For soldering m ethods and conditions other than those recom mended below , contact your N EC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions (1/2) (1) µµPD784214AGC-××× -8EU:100-pin plastic LQFP(fine pitch) (14 × 14 mm) µPD784215AGC-××× -8EU:100-pin plastic LQFP(fine pitch) (14 ×× 14 mm) µPD784216AGC-××× -8EU:100-pin plastic LQFP(fine pitch) (14 ×× 14 mm) µµPD784217AGC-×××××× -8EU: 100-pin plastic LQFP (fine pitch) (14 ×× 14 mm) µµPD784218AGC-×××××× ×××××× -8EU: 100-pin plastic LQFP (fine pitch) (14 ×× 14 mm) µµ µµPD784214AYGC-×××××× -8EU:100-pin plastic LQFP(fine pitch) (14 ×× 14 mm) µµPD784215AYGC-×××××× -8EU:100-pin plastic LQFP(fine pitch) (14 ×× ×× 14 mm) µµPD784216AYGC-×××××× -8EU:100-pin plastic LQFP(fine pitch) (14 ×× ×× 14 mm) µµPD784217AYGC-×××××× -8EU: 100-pin plastic LQFP (fine pitch) (14 ×× 14 mm) µPD784218AYGC-×××××× -8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less, Exposure limit: 7 days Note (after that, prebake at 125°C for 10 hours) IR35-107-2 Count: Two times or less, Exposure limit: 7 days Note (after that, prebake at 125°C for 10 hours) VP15-107-2 Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per pin row) − Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14121EJ2V0DS00 91 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Table 15-1. Surface Mounting Type Soldering Conditions (2/2) (2) µPD784214AGF-××× -3BA:100-pin plastic QFP(14 × 20 mm) µµPD784215AGF-××× -3BA:100-pin plastic QFP(14 × 20 mm) µµPD784216AGF-××× -3BA:100-pin plastic QFP(14 × 20 mm) µµPD784217AGF-××× -3BA: 100-pin plastic QFP (14 × 20 mm) µPD784218AGF-××× -3BA: 100-pin plastic QFP (14 × 20 mm) µPD784214AYGF-×××××× -3BA:100-pin plastic QFP(14 × 20 mm) µµPD784215AYGF-××× -3BA:100-pin plastic QFP(14 × 20 mm) µµPD784216AYGF-××× -3BA:100-pin plastic QFP(14 × 20 mm) µµPD784217AYGF-××× -3BA: 100-pin plastic QFP (14 × 20 mm) µPD784218AYGF-××× -3BA: 100-pin plastic QFP (14 × 20 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less IR35-00-2 Count: Two times or less VP15-00-2 Wave soldering Solder bath temperature: 260 °C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per pin row) − Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14121EJ2V0DS0092 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD784218A. Also refer to (5) Cautions on using development tools. (1) Language processing software RA78K4 Assembler package common to 78K/IV Series CC78K4 C compiler package common to 78K/IV Series DF784218 Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries CC78K4-L C compiler library source file common to 78K/IV Series (2) Flash memory writing tools Flashpro II (Model number: FL-PR2), Flashpro III (Model number: FL-PR3, PG-FP3) Dedicated flash programmer for microcontroller incorporating flash memory FA-100GF Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Connection must be performed in accordance with the target product. FA-100GC Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must be performed in accordance with the target product. Flashpro II controller, Flashpro III controller Control program that runs on a personal computer and is attached to Flashpro II, Flashpro III. Operates on Windows TM 95, etc. (3) Debugging tools

• When IE-78K4-NS in-circuit emulator is used IE-78K4-NS In-circuit emulator common to 78K/IV Series IE-70000-MC-PS-B Power supply unit for IE-78K4-NS IE-70000-98-IF-C Interface adapter required when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) IE-70000-CD-IF-A PC card and cable when PC-9800 series notebook PC is used as host machine (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter required when using IBM PC/ATTM compatibles as host machine (ISA bus supported) IE-70000-PCI-IF Interface adapter required when using PC that incorporates PCI bus as host machine IE-784225-NS-EM1 Emulation board to emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries NP-100GF Emulation probe for 100-pin plastic QFP (GF-3BA type) NP-100GC Emulation probe for 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) TGC-100SDW Conversion adapter to connect the NP-100GC and a target system board on which a 100-pin plastic LQFP (GC-8EU type) can be mounted ID78K4-NS Integrated debugger for IE-78K4-NS SM78K4 System simulator common to 78K/IV Series DF784218 Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries

Data Sheet U14121EJ2V0DS00 93 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

• When IE-784000-R in-circ uit emulator is used IE-784000-R In-circuit emulator common to 78K/IV Series IE-70000-98-IF-C Interface adapter required when PC-9800 series PC (except notebook type) is used as host machine (C bus supported) IE-70000-PC-IF-C Interface adapter required when using IBM PC/AT and compatibles as host machine (ISA bus supported) IE-70000-PCI-IF Interface adapter required when using PC that incorporates PCI bus as host machine IE-78000-R-SV3 Interface adapter and cable required when EWS is used as host machine IE-784225-NS-EM1 Emulation board to emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries IE-784000-R-EM Emulation board common to 78K/IV Series IE-78K4-R-EX3 Emulation probe conversion board required when using IE-784225-NS-EM1 on IE-784000-R. EP-784218GF-R Emulation probe for 100-pin plastic QFP (GF-3BA type) EP-78064GC-R Emulation probe for 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) TGC-100SDW Conversion adapter to connect the EP-78064GC-R and a target system board on which a 100-pin plastic LQFP (GC-8EU type) can be mounted ID78K4 Integrated debugger for IE-784000-R SM78K4 System simulator common to 78K/IV Series DF784218 Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries (4) Real-time OS RX78K/IV Real-time OS for 78K/IV Series MX78K4 OS for 78K/IV Series

Data Sheet U14121EJ2V0DS0094 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY (5) Cautions on using development tools

• The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218.
• The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218.
• The FL-PR 2, FL-PR 3, FA-100G F, FA-100G C, N P-100GF, and NP-100GC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813).
• The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (TEL: +81-3-3820-7112) Osaka Electronic Division (TEL: +81-6-6244-6672)
• For third party developm ent tools, see the Single-C hip Microcontroller Development Tool Selection Guide (U11069E).
• The host machine and OS suitable for each software are as follows: PC EWSHost Machine [OS] Software PC-9800 series [Windows] IBM PC/AT and compatibles [Japanese/English Windows] HP9000 Series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM] RA78K4 √Note √ CC78K4 √Note √ ID78K4-NS √− ID78K4 √√ SM78K4 √− RX78K/IV √Note √ MX78K4 √Note √ Note DOS-based software

Data Sheet U14121EJ2V0DS00 95 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY APPENDIX B. RELATED DOCUMENTS Documents related to devices Document No.Document Name English Japanese µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Data Sheet This document U14121J µPD78F4216A, 78F4216AY, 78F4218A, 78F4218AY Data Sheet To be prepared To be prepared µPD784216A, 784216AY Subseries User’s Manual Hardware U13570E U13570J µPD784218A, 784218AY Subseries User’s Manual Hardware U12970E U12970J 78K/IV Series User’s Manual Instructions U10905E U10905J 78K/IV Series Instruction Table − U10594J 78K/IV Series Instruction Set − U10595J 78K/IV Series Application Note Software Basics − U10095J Documents related to development tools (user’s manuals) Document No.Document Name English Japanese Language U11162E U11162JRA78K4 Assembler Package Operation U11334E U11334J RA78K Structured Assembler Preprocessor U11743E U11743J Language U11571E U11571JCC78K4 C Compiler Operation U11572E U11572J IE-78K4-NS U13356E U13356J IE-784000-R U12903E U12903J IE-784218-R-EM1 U12155E U12155J IE-784225-NS-EM1 U13742E U13742J EP-78064 EEU-1469 EEU-934 SM78K4 System Simulator Windows Based Reference U10093E U10093J SM78K Series System Simulator External Part User Open Interface Specifications U10092E U10092J ID78K4-NS Integrated Debugger PC Based Reference U12796E U12796J ID78K4 Integrated Debugger Windows Based Reference U10440E U10440J ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS based Reference U11960E U11960J Caution The related documents listed above are subject to change w ithout notice. Be sure to use the latest version of each document for designing.

Data Sheet U14121EJ2V0DS0096 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Documents related to embedded software (user’s manuals) Document No.Document Name English Japanese Fundamental U10603E U10603J Installation U10604E U10604J 78K/IV Series Real-Time OS Debugger − U10364J 78K/IV Series OS MX78K4 Fundamental − U11779J Other documents Document No.Document Name English Japanese SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E C11892J Guide to Microcomputer-Related Products by Third Party − U11416J Caution The related documents listed above are subject to change w ithout notice. Be sure to use the latest version of each document for designing.

Data Sheet U14121EJ2V0DS00 97 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

Data Sheet U14121EJ2V0DS0098 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 NEC Electronics (France) S.A. Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Singapore Pte. Ltd. United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7

Data Sheet U14121EJ2V0DS00 99 µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY IEBus is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.

µµPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY The related docum ents indicated in this publication m ay include prelim inary versions. However, preliminary versions are not marked as such. Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. M8E 00. 4 The information in this document is current as of August, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility o f customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC' s willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.