AD7811 AD | Alldatasheet
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD7811/AD7812 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 2.7 V to 5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs
FEATURES
10-Bit ADC with 2.3 /H9262s Conversion Time The AD7811 has Four Single-Ended Inputs that Can Be Configured as Three Pseudo Differential Inputs with Respect to a Common, or as Two Inde- pendent Pseudo Differential Channels The AD7812 has Eight Single-Ended Inputs that Can Be Configured as Seven Pseudo Differential Inputs with Respect to a Common, or as Four Independent Pseudo Differential Channels Onboard Track and Hold Onboard Reference 2.5 V /H11550 2.5% Operating Supply Range: 2.7 V to 5.5 V Specifications at 2.7 V–3.6 V and 5 V /H11550 10% DSP-/Microcontroller-Compatible Serial Interface High Speed Sampling and Automatic Power-Down Modes Sharing of the Serial Bus in Multipackage Applications Input Signal Range: 0 V to V REF Reference Input Range: 1.2 V to V DD GENERAL DESCRIPTION The AD7811 and AD7812 are high speed, low power, 10-bit A/D converters that operate from a single 2.7 V to 5.5 V supply. The devices contain a 2.3 µs successive approximation A/D converter, an on-chip track/hold amplifier, a 2.5 V on-chip refer- ence and a high speed serial interface that is compatible with the serial interfaces of most DSPs (Digital Signal Processors) and microcontrollers. The user also has the option of using an exter- nal reference by connecting it to the V REF pin and setting the EXTREF bit in the control register. The V REF pin may be tied to VDD. At slower throughput rates the power-down mode may be used to automatically power down between conversions. The control registers of the AD7811 and AD7812 allow the input channels to be configured as single-ended or pseudo differential. The control register also features a software convert start and a software power-down. Two of these devices can share the same serial bus and may be individually addressed in a multipackage application by hardwiring the device address pin. The AD7811 is available in a small, 16-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a 16-lead 0.15" wide, Small Outline IC (SOIC) and in a 16-lead, Thin Shrink Small Out- line Package (TSSOP). The AD7812 is available in a sm all, 20-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a 20-lead, Small Outline IC (SOIC) and in a 20-lead, Thin Shrink Small Outline Package (TSSOP). PRODUCT HIGHLIGHTS 1. Low Power, Single Supply Operation Both the AD7811 and AD7812 operate from a single 2.7 V to 5.5 V supply and typically consume only 10 mW of power. The power dissipation can be significantly reduced at lower throughput rates by using the automatic power- down mode e.g., 315 µW @ 10 kSPS, V DD = 3 V—see Power vs. Throughput. 2. 4-/8-Channel, 10-Bit ADC The AD7811 and AD7812 have four and eight single-ended input channels respectively. These inputs can be configured as pseudo differential inputs by using the Control Register. 3. On-chip 2.5 V ( ±2.5%) reference circuit that is powered down when using an external reference. 4. Hardware and Software Control The AD7811 and AD7812 provide for both hardware and software control of Convert Start and Power-Down. FUNCTIONAL BLOCK DIAGRAMS REV.B CHARGE REDISTRIBUTION DAC CLOCK OSC AD7811 CONVST AGND VDD/3 COMP REFIN VDD DOUT DGND VIN1 VIN2 VIN3 VIN4 DIN RFS TFS SCLK BUF CONTROL LOGIC MUX CREF SERIAL PORT 1.23V REF CHARGE REDISTRIBUTION DAC CLOCK OSC AD7812 AGNDREFIN VDD DOUT DGND DIN RFS TFS SCLK BUF CONTROL LOGIC MUX CREF SERIAL PORT VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 CONVST VDD/3 COMP 1.23V REF
–2– REV. B AD7811/AD7812–SPECIFICATIONS Parameter Y Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE f IN = 30 kHz Any Channel, f SAMPLE = 350 kHz Signal to (Noise + Distortion) Ratio 1 58 dB min V REF Internal or External Total Harmonic Distortion (THD) 1 –66 dB max Peak Harmonic or Spurious Noise 1 –80 dB typ Intermodulation Distortion 1, 2 fa = 29 kHz, fb = 30 kHz Second Order Terms –67 dB max Third Order Terms –67 dB max Channel-to-Channel Isolation 1, 2 –80 dB typ f IN = 20 kHz DC ACCURACY Any Channel Resolution 10 Bits Minimum Resolution for Which No Missing Codes are Guaranteed 10 Bits Relative Accuracy1 ±1 LSB max Differential Nonlinearity 1 ±1 LSB max Gain Error1 ±2 LSB max Gain Error Match1 ±0.75 LSB max Offset Error1 ±2 LSB max Offset Error Match1 ±0.75 LSB max ANALOG INPUT Input Voltage Range 0 V min VREF V max Input Leakage Current 2 ±1 µA max Input Capacitance2 20 pF max REFERENCE INPUTS2 VREF Input Voltage Range 1.2 V min VDD V max Input Leakage Current ±3 µA max Input Capacitance 20 pF max ON-CHIP REFERENCE Nominal 2.5 V Reference Error ±2.5 % max Temperature Coefficient 50 ppm/ °C typ LOGIC INPUTS2 VINH, Input High Voltage 2.4 V min V DD = 5 V ± 10% VINL, Input Low Voltage 0.8 V max V DD = 5 V ± 10% VINH, Input High Voltage 2 V min V DD = 3 V ± 10% VINL, Input Low Voltage 0.4 V max V DD = 3 V ± 10% Input Current, IIN ±1 µA max Typically 10 nA, V IN = 0 V to VDD Input Capacitance, C IN 8 pF max LOGIC OUTPUTS Output High Voltage, V OH ISOURCE = 200 µA 4V m i n V DD = 5 V ± 10%
2.4 V min V DD = 3 V ± 10%
Output Low Voltage, V OL ISINK = 200 µA
0.4 V max
High Impedance Leakage Current ±1 µA max High Impedance Capacitance 15 pF max CONVERSION RATE Conversion time 2.3 µs max Track/Hold Acquisition Time 1 200 ns max (VDD = 2.7 V to 3.6 V, VDD = 5 V /H11550 10%, GND = 0 V, VREF = VDD [EXT]. All specifications –40 /H11543C to +105/H11543C unless otherwise noted.)
5.5 V max
2Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice. 1Sample tested to ensure compliance. time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. Figure 1. Load Circuit for Digital Output Timing Specifications
–4– REV. B ABSOLUTE MAXIMUM RATINGS * Digital Input Voltage to DGND (CONVST, SCLK, RFS, TFS, Digital Output Voltage to DGND ( DOUT) Analog Inputs ORDERING GUIDE Linearity Package Package Model Error Descriptions Options AD7811YN ±1 LSB 16-Lead Plastic DIP N-16 AD7811YR ±1 LSB 16-Lead Small Outline IC (SOIC) R-16A AD7811YRU ±1 LSB 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD7812YN ±1 LSB 20-Lead Plastic DIP N-20 AD7812YR ±1 LSB 20-Lead Small Outline IC (SOIC) R-20A AD7812YRU ±1 LSB 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20 Lead Temperature, Soldering Lead Temperature, Soldering *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7811/AD7812 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE
–5–REV. B PIN FUNCTION DESCRIPTIONS Pin(s) Pin(s) AD7811 AD7812 Mnemonic Description 11 V REF An external reference input can be applied here. When using an external precision reference or VDD the EXTREF bit in the control register must be set to logic one. The external reference input range is 1.2 V to V DD. 22 C REF Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise performance of the on-chip reference. 3, 5–7 3, 5–11 V IN1–VIN4(8) Analog Inputs. The analog input range is 0 V to V REF. 4 4 AGND Analog Ground. Ground reference for track/hold, comparator, on-chip reference and DAC. conjunction with the package address bit in the control register this input allows two devices to share the same serial bus. For example a twelve channel solution can be achieved by using the AD7811 and the AD7812 on the same serial bus. 9 13 DGND Digital Ground. Ground reference for digital circuitry. 10 14 TFS Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new control byte should be shifted in on the next 10 falling edges of SCLK. 11 15 RFS Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in the serial interface. It is used to provide compatibility with DSPs which use a continuous serial clock and framing signal. In multipackage applications the RFS Pin can also be used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a rising edge on this input. The counter is reset at the end of a serial read operation. 12 16 DOUT Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial clock. The output enters a High impedance condition on the rising edge of the 11th SCLK pulse. 13 17 DIN Serial Data Input. The control byte is read in at this input. In order to complete a serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are shifted in—see Serial Interface section. 14 18 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK. 15 19 CONVST Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold Mode on the falling edge of this signal and a conversion is initiated. The state of this pin at the end of conversion also determines whether the part is powered down or not. See operating modes section of this data sheet. 16 20 V DD Positive Supply Voltage 2.7 V to 5.5 V. PIN CONFIGURATIONS DIP/SOIC/TSSOP TOP VIEW (Not to Scale) AD7811 VREF DIN SCLK CONVST VDD CREF VIN1 AGND TFS RFS DOUTVIN2 VIN3 VIN4 A0 DGND TOP VIEW (Not to Scale) AD7812 VREF DIN SCLK VDD CREF VIN1 AGND TFS RFS DOUTV IN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 DGND CONVST
–6– REV. B TERMINOLOGY Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distor- tion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion ) = (6.02N + 1.76) dB Thus for a 10-bit converter, this is 62 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7811 and AD7812 it is defined as: THD (dB) = 20 log 2 +V3 2 +V4 2 +V5 2 +V6 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f S/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The AD7811 and AD7812 are tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the inter- modulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full- scale 20 kHz sine wave signal to all nonselected input channels and determining how much that signal is attenuated in the selected channel. The figure given is the worst case across all four or eight channels for the AD7811 and AD7812 respectively. Relative Accuracy Relative accuracy, or endpoint nonlinearity, is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (0000 . . . 000) Offset Error Match This is the difference in Offset Error between any two channels. Gain Error This is the deviation of the last code transition (1111 . . . 110) offset error has been adjusted out. Gain Error Match This is the difference in Gain Error between any two channels. Track/Hold Acquisition Time Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ± 1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected V IN input of the AD7811 or AD7812. It means that the user must wait for the duration of the track/hold acquisi- tion time after the end of conversion or after a channel change/ step input change to V IN before starting another conversion, to ensure that the part operates to specification.
–7–REV. B Control Register (AD7811) The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7811 receives a falli ng edge on its TFS pin. The AD7811 will maintain the same configuration until a new control byte is written to the part. The contr ol register can be written to at the same time data is being read. This latter feature enhances throughput rates when software con trol is being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros ; therefore, when the supplies are connected, the AD7811 is powered down by default. Control Register AD7811 9 0 X* 0A1 DP0 DPV 4NI / DNGA /FFID LGS 1HC0 HC TSVNOC FERTXE *This is a don’t care bit. A0 This is the package address bit. It is used in conjunction with the package address pin to allow two AD7811s to share the same serial bus. The AD7811 can also share the same serial bus with the AD7812. When a control word is written to the control register of the AD7811 the control word is ignored if the package address bit in the con- trol byte does not match how the package address pin is hardwired. Only the serial port of the device that received the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus on the next serial read. When the part powers up this bit is set to 0. PD1, PD0 These bits allow the AD7811 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the power-down mode when the AD7811 enters a power-down at the end of a conversion. There are two power-down modes—Full Power-Down and Partial Power-Down. See Power-Down Options section of this data sheet. PD1 PD0 Description 0 0 Full Power-Down of the AD7811 0 1 Partial Power-Down at the End of Conversion 1 0 Full Power-Down at the End of Conversion 1 1 Power-Up the AD7811 VIN4/AGND The DIF/SGL bit in the control register must be set to 0 to use this option otherwise this bit is ignored. Setting VIN4/AGND to 0 configures the analog inputs of the AD7811 as four single-ended analog inputs referenced to analog ground (AGND). By setting this bit to 1 the input channels V IN1 to VIN3 are configured as three pseudo- differential channels with respect to V IN4—see Table I. DIF/SGL This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0 the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to VIN4 as explained above. Setting this bit to 1 configures the analog input channels as two pseudo differential pairs VIN1/VIN2 and VIN3/VIN4—see Table I. CH1, CH0 These bits are used in conjunction with V IN4/AGND and DIF/SGL to select an analog input channel. The table shows how the various channel selections are made—see Table I. CONVST Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initiated in the same serial write. The bit is reset after the end of a conversion. EXTREF This bit must be set to a logic one if the user wishes to use an external reference or use V DD as the reference. When the external reference is selected the on chip reference circuitry powers down.
–8– REV. B Control Register (AD7812) The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7812 receives a falli ng edge on its TFS pin. The AD7812 will maintain the same configuration until a new control byte is written to the part. The cont rol register can be written to at the same time data is being read. This latter feature enhances throughput rates when software con trol is being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros ; therefore, when the supplies are connected, the AD7812 is powered down by default. Control Register AD7812 9 0 0A1 DP0 DPV 8NI / DNGA /FFID LGS 2HC1 HC0 HC TSVNOC FERTXE A0 This is the package address bit. It is used in conjunction with the package address pin to allow two AD7812s to share the same serial bus. The AD7812 can also share the same serial bus with the AD7811. When a control word is written to the control register of the AD7812 the control word is ignored if the package address bit in the con- trol byte does not match how the package address pin is hardwired. Only the serial port of the device which received the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus on the next serial read. When the part powers up this bit is set to 0. PD1, PD0 These bits allow the AD7812 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the power-down mode when the AD7812 enters a power-down at the end of a conversion. There are two power-down modes—Full Power-Down and Partial Power-Down. See Power-Down section of this data sheet. PD1 PD0 Description 0 0 Full Power-Down of the AD7812 0 1 Partial Power-Down at the End of Conversion 1 0 Full Power-Down at the End of Conversion 1 1 Power-Up the AD7812 VIN8/AGND The DIF/SGL bit in the control register must be set to 0 in order to use this option otherwise this bit is ignored. Setting V IN8/AGND to 0 configures the analog inputs of the AD7812 as eight single-ended analog inputs referenced to analog ground (AGND). By setting this bit to 1 the input channels V IN1 to V IN7 are configured as seven pseudo differential channels with respect to V IN8—see Table II. DIF/SGL This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0 the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to VIN8 as explained above. Setting this bit to 1 configures the analog input channels as four pseudo differential pairs VIN1/VIN2, VIN3/VIN4, VIN5/VIN6 and VIN7/VIN8—see Table II. CH2, CH1, CH0 T hese bits are used in conjunction with V IN8/AGND and DIF/SGL to select an analog input channel. Table II shows how the various channel selections are made. CONVST Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initi- ated in the same write operation. The bit is reset after the end of a conversion. EXTREF This bit must be set to a logic one if the user wishes to use an external reference or use V DD as the reference. When the external reference is selected the on-chip reference circuitry powers down and the current consumption is reduced by about 1 mA.
–9–REV. B Table I. AD7811 Channel Configurations VIN4/AGND DIF/SGL CH1 CH0 Description 000 0 V IN1 Single-Ended with Respect to AGND 000 1 V IN2 Single-Ended with Respect to AGND 001 0 V IN3 Single-Ended with Respect to AGND 001 1 V IN4 Single-Ended with Respect to AGND 100 0 V IN1 Pseudo Differential with Respect to V IN4 100 1 V IN2 Pseudo Differential with Respect to V IN4 101 0 V IN3 Pseudo Differential with Respect to V IN4 X1 0 0 V IN1(+) Pseudo Differential with Respect to V IN2(–) X1 0 1 V IN3(+) Pseudo Differential with Respect to V IN4(–) X 1 1 0 Internal Test. SAR Input Equal to V REF/2 X 1 1 1 Internal Test. SAR Input Equal to V REF Table II. AD7812 Channel Configurations VIN8/AGND DIF/SGL CH2 CH1 CH0 Description 0 0 000 V IN1 Single-Ended with Respect to AGND 0 0 001 V IN2 Single-Ended with Respect to AGND 0 0 010 V IN3 Single-Ended with Respect to AGND 0 0 011 V IN4 Single-Ended with Respect to AGND 0 0 100 V IN5 Single-Ended with Respect to AGND 0 0 101 V IN6 Single-Ended with Respect to AGND 0 0 110 V IN7 Single-Ended with Respect to AGND 0 0 111 V IN8 Single-Ended with Respect to AGND 1 0 000 V IN1 Pseudo Differential with Respect to V IN8 1 0 001 V IN2 Pseudo Differential with Respect to V IN8 1 0 010 V IN3 Pseudo Differential with Respect to V IN8 1 0 011 V IN4 Pseudo Differential with Respect to V IN8 1 0 100 V IN5 Pseudo Differential with Respect to V IN8 1 0 101 V IN6 Pseudo Differential with Respect to V IN8 1 0 110 V IN7 Pseudo Differential with Respect to V IN8 X 1 000 V IN1(+) Pseudo Differential with Respect to V IN2(–) X 1 001 V IN3(+) Pseudo Differential with Respect to V IN4(–) X 1 010 V IN5(+) Pseudo Differential with Respect to V IN6(–) X 1 011 V IN7(+) Pseudo Differential with Respect to V IN8(–) X 1 1 0 0 Internal Test. SAR Input Equal to V REF/2 X 1 1 0 1 Internal Test. SAR Input Equal to V REF
Figure 11. Automatic Power-Down Figure 12. AD7811/AD7812 Power vs. Throughput
2048 POINT FFT
Figure 13. AD7811/AD7812 SNR of the AD7812 can be evaluated. Figure 14. Evaluation Quick Setup
- When power is first connected to the device it is in a powered
- The CONVST signal is first pulsed to enable the serial port
- Next, a 16-bit serial read/write operation is carried out. By
- It is necessary to wait approximately 1.5 µs before pulsing
- Approximately 2.3 µs after the falling edge of CONVST, i.e.,
justified in the 16-bit serial register (MSB clocked out first).
- By idling the CONVST signal high or low it is possible to
operate the AD7812 in Mode 1 and Mode 2 respectively.
6040 HEX
4040 HEX
Figure 15. Read/Write Sequence for AD7812 serial shift register and the state of the CONVST signal checked. leaving the CONVST signal low until the end of the conversion. performance is required—see Power vs. Throughput section. Figure 16. Mode 1 Operation Timing Diagram
–18– REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-Lead Small Outline Package (SOIC) (R-16A) 16 9 0.3937 (10.00) 0.3859 (9.80) 0.2550 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (5.80) PIN 1 SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) BSC 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 16-Lead Thin Shrink Outline Package (TSSOP) (RU-16) 16 9 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50)
–19–REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic DIP (N-20) 11 0 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-Lead Small Outline Package (SOIC) (R-20A) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 20 11 101 0.5118 (13.00) 0.4961 (12.60) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) PIN 1 20-Lead Thin Shrink Outline Package (TSSOP) (RU-20) 20 11 101 0.260 (6.60) 0.252 (6.40) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) C01312a–0–10/00 (rev. B) PRINTED IN U.S.A.