7736

7733 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER

7700 FAMILY / 7700 SERIES

7733 Group

7735 Group

7736 Group

User’s Manual

keep safety first in your circuit designs ! l Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials l These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. l Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. l Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. l If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. l Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

This manual describes the hardware of the Mitsubishi CMOS 16-bit microcomputers 7733/7735/7736 Group. After reading this manual, the user will be able to understand the functions, so that the capabilities of the microcomputers can fully be utilized. For details concerning the software for the 7733/7735/ 7736 Group, refer to the 7700 Family Software Manual.

I BEFORE USING THIS MANUAL 1. INTRODUCTION This manual consists of the following: PART 1: 7733 Group, PART 2: 7735 Group, and PART 3: 7736 Group. The peripheral functions are common to all of these groups, but the external bus mode differs according to the group, as follows:

• 7733 Group: external bus mode A is assigned.
• 7735 Group: external bus mode B is assigned.
• 7736 Group: external bus mode A or B is selectable. In parts 2 and 3, only the differences occurring between the 7735/7736 Group and the 7733 Group are described. Also, the chapter, section, table and figure numbers are the same as those in part 1 and the differences are described by the section. PART 1: 7733 Group l Chapter 1. OVERVIEW through Chapter 17. APPLICATIONS The common functions of the 7733 Group microcomputers are described. The M37733MHBXXXFP is used as a typical microcomputer in this group to describe all common functions. l Chapter 18. LOW VOLTAGE VERSION Read this chapter when using the microcomputers with the electrical characteristics indicated by “L.” (See page 1-2 in part 1.) Ex.: M37733MH LXXXHP The differences between the M37733MHLXXXHP, which is a typical low voltage version of the 7733 Group, and the M37733MHBXXXFP are described. l Chapter 19. BUILT-IN PROM VERSION Read this chapter when using the microcomputers with the memory type indicated by “E.” (See page 1-2 in part 1.) Ex.: M37733 EHBXXXFP The differences between the M37733EHBXXXFP, which is a typical built-in PROM version of the 7733 Group, and the M37733MHBXXXFP are described. l Chapter 20. EXTERNAL ROM VERSION Read this chapter when using the microcomputers with the memory type indicated by “S.” (See page 1-2 in part 1.) Ex.: M37733 S4BFP The differences between the M37733S4BFP, which is a typical external ROM version of the 7733 Group, and the M37733MHBXXXFP are described. l APPENDIX Practical information for using the 7733 Group is described . PART 2: 7735 Group, PART 3: 7736 Group Refer to the table on the next page.

Refer to part 1: CHAPTER 1. OVERVIEW CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) CHAPTER 3. PROGRAMMABLE I/O PORTS CHAPTER 4. INTERRUPTS CHAPTER 5. KEY INPUT INTERRUPTS CHAPTER 6. TIMER A CHAPTER 7. TIMER B CHAPTER 8. SERIAL I/O CHAPTER 9. A-D CONVERTER CHAPTER 10. WATCHDOG TIMER CHAPTER 11. STOP AND WAIT MODES CHAPTER 12. CONNECTING EXTERNAL DEVICES CHAPTER 13. RESET CHAPTER 14. CLOCK GENERATING CIRCUIT CHAPTER 15. ELECTRICAL CHARACTERISTICS CHAPTER 16. STANDARD CHARACTERISTICS CHAPTER 17. APPLICATIONS CHAPTER 18. LOW VOLTAGE VERSION CHAPTER 19. BUILT-IN PROM VERSION CHAPTER 20. EXTERNAL ROM VERSION APPENDIX PART 2 (Note 1) Refer to part 2: Refer to part 1: Refer to part 2: Note 1: In part 2 and 3, when there is no reference provided about the part, refer to the corresponding chapter/section in that part. 2 : When referring to the chapters and sections listed below, use the following guide: External bus mode A: refer to part 1, External bus mode B: refer to part 2.

• Chapter 11. STOP AND WAIT MODES
• Chapter 12. CONNECTING EXTERNAL DEVICES”
• Chapter 15. ELECTRICAL CHARACTERISTICS” (electrical characteristics related to the external bus mode)
• Paragraph 17.1 Memory expansion
• Chapter 18. LOW VOLTAGE VERSION (electrical characteristics related to the external bus mode)
• Paragraph 18.6 Applications PART 1

Refer to part 1: Refer to part 2: PART 3 (Note 1) Refer to part 1: Refer to part 3: (Note 2) Refer to part 3: Refer to part 3:

1. NOTES l For product expansion information, refer to the latest catalog and data book, or contact the appropriate office, as listed in “CONTACT ADDRESSES FOR FURTHER INFORMATION” on the last page. l Always refer to the latest data book for electrical characteristics. l This manual does not include the forms listed below. When necessary, copy the corresponding page of the latest data book, or contact the appropriate office, as listed in “CONTACT ADDRESSES FOR FURTHER INFORMATION”:

• MASK ROM ORDER CONFIRMATION FORM
• PROM ORDER CONFIRMATION FORM
• MARK SPECIFICATION FORM l For details concerning development support tools, refer to the latest data book of development support tools. l For details concerning software, refer to the 7700 Family Software Manual.

1. REGISTER STRUCTURE Below is the structure diagram for all registers. XXX register (address XX16) b1 b0b2b3b4b5b6b7 ] 1 ] 2 ]3 1 : ... 1 : ... The value is “0” at reading. 0 : ... 1 : ... Fix this bit to “0.” 7 to 5 Not implemented. RW WO RO RW RW Bit Bit name This bit is ignored in ... mode. Functions At reset RW ... flag Undefined Undefined Blank : Set to “0” or “1” according to the usage. 0 : Set to “0” at writing. 1 : Set to “1” at writing. 5 : Ignored depending on the mode or state. It may be “0” or “1.” : Not implemented. 0 : “0” immediately after reset. 1 : “1” immediately after reset. Undefined : Undefined immediately after reset. RW : It is possible to read the bit state at reading. The written value becomes valid. R O : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be “0” or “1.” W O : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading] is indicated in the “Function” or “Note” column, the bit is always “0” at reading.(See to ]4 above.) — : It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading] is indicated in the “Function” or “Note” column, the bit is always “0” at reading.(See to ]4 above.) The written value becomes invalid. Accordingly, the written value may be “0” or “1.”

7733 Group User’s Manual i

CHAPTER 1. OVERVIEW CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) CHAPTER 3. PROGRAMMABLE I/O PORTS

7733 Group User’s Manual

CHAPTER 4. INTERRUPTS 4.3.3 Interrupt priority level selection bits and Processor interrupt priority level (IPL).. 4-8

4.7 How interrupts are processed (from acceptance of interrupt request until

____ ____ ____ CHAPTER 5. KEY INPUT INTERRUPT FUNCTION CHAPTER 6. TIMER A

7733 Group User’s Manual iii

CHAPTER 7. TIMER B 7.5 Pulse period/Pulse width measurement mode (Bits 1 and 0 of timer Bi mode register = “102”) ...7-25 CHAPTER 8. SERIAL I/O

CHAPTER 9. A-D CONVERTER CHAPTER 10. WATCHDOG TIMER

7733 Group User’s Manual v

CHAPTER 11. STOP AND WAIT MODES

11.3.2 Stop mode terminating operation by interrupt request occurrence (when using watchdog timer)11-9

11.3.3 Stop mode terminating operation by interrupt request occurrence (when not

CHAPTER 12. CONNECTING EXTERNAL DEVICES ____ CHAPTER 13. RESET

CHAPTER 14. CLOCK GENERATING CIRCUIT CHAPTER 15. ELECTRICAL CHARACTERISTICS CHAPTER 16. STANDARD CHARACTERISTICS

16.1.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3, P40 to P43, P54 to P57,

CHAPTER 17. APPLICATIONS

7733 Group User’s Manual vii

CHAPTER 18. LOW VOLTAGE VERSION

18.5.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3, P40 to P43, P54 to P57,

18.5.2 Programmable I/O port (CMOS output) standard characteristics: P44 to P47 and P50 to P53. .18-28 CHAPTER 19. BUILT-IN PROM VERSION CHAPTER 20. EXTERNAL ROM VERSION

7735 Group User’s Manual ix

CHAPTER 1. OVERVIEW CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) CHAPTER 3. PROGRAMMABLE I/O PORTS CHAPTER 4. INTERRUPTS ____ CHAPTER 5. KEY INPUT INTERRUPT FUNCTION

7735 Group User’s Manual

x CHAPTER 6. TIMER A

6.6 Pulse width modulation (PWM) mode (Bits 1 and 0 of timer Ai mode

CHAPTER 7. TIMER B

7.4 Event counter mode (Bits 1 and 0 of timer Bi mode register = “012”) 7-17 in part 1

7.5 Pulse period/Pulse width measurement mode (Bits 1 and 0 of timer Bi

CHAPTER 8. SERIAL I/O CHAPTER 9. A-D CONVERTER CHAPTER 10. WATCHDOG TIMER CHAPTER 11. STOP AND WAIT MODES

7735 Group User’s Manual xi

CHAPTER 12. CONNECTING EXTERNAL DEVICES CHAPTER 13. RESET CHAPTER 14. CLOCK GENERATING CIRCUIT CHAPTER 15. ELECTRICAL CHARACTERISTICS CHAPTER 16. STANDARD CHARACTERISTICS

CHAPTER 17. APPLICATIONS CHAPTER 18. LOW VOLTAGE VERSION CHAPTER 19. BUILT-IN PROM VERSION CHAPTER 20. EXTERNAL ROM VERSION

7735 Group User’s Manual xiii

7736 Group User’s Manual

CHAPTER 1. OVERVIEW CHAPTER 2. CENTRAL PROCESSING UNIT (CPU)

2.2 Bus interface unit

2.3 Accessible area

CHAPTER 3. PROGRAMMABLE I/O PORTS CHAPTER 4. INTERRUPTS

4.7 How interrupts are processed (from acceptance of interrupt request

____

7736 Group User’s Manual xv

CHAPTER 5. KEY INPUT INTERRUPT FUNCTION CHAPTER 6. TIMER A CHAPTER 7. TIMER B CHAPTER 8. SERIAL I/O CHAPTER 9. A-D CONVERTER

CHAPTER 10. WATCHDOG TIMER CHAPTER 11. STOP AND WAIT MODES

11.1 Overview

11.2 Clock generating circuit

11.3 Stop mode

11.4 Wait mode

CHAPTER 12. CONNECTING EXTERNAL DEVICES

12.1 Signals required for accessing external devices

12.2 Software wait

12.3 Ready function

12.4 Hold function

CHAPTER 13. RESET CHAPTER 14. CLOCK GENERATING CIRCUIT

7736 Group User’s Manual xvii

CHAPTER 15. ELECTRICAL CHARACTERISTICS

15.6 Ready and Hold

15.8 Memory expansion mode and Microprocessor mode : with no wait

15.9 Memory expansion mode and Microprocessor mode : with wa it 1

15.10 Memory expansion mode and Microprocessor mode : with w ait 0

CHAPTER 16. STANDARD CHARACTERISTICS

16.1.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3,

16.1.2 Programmable I/O port (CMOS output) standard characteristics: P44 to P47

CHAPTER 17. APPLICATIONS

17.1 Memory expansion

CHAPTER 18. LOW VOLTAGE VERSION

18.4.6 Ready and Hold

18.4.8 Memory expansion mode and microprocessor mode : with no wait

18.4.9 Memory expansion mode and microprocessor mode : with wait 1

18.4.10 Memory expansion mode and microprocessor mode : with wait 0

18.5.1 Programmable I/O port (CMOS output) standard characteristics : Ports P0 to P3,

18.5.2 Programmable I/O port (CMOS output) standard characteristics : Ports P44 to P47

CHAPTER 19. BUILT-IN PROM VERSION APPENDIX GLOSSARY

CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) CHAPTER 3 PROGRAMMABLE I/O PORTS CHAPTER 4 INTERRUPTS CHAPTER 5 KEY INPUT INTERRUPT FUNCTION CHAPTER 6 TIMER A CHAPTER 7 TIMER B CHAPTER 8 SERIAL I/O CHAPTER 9 A-D CONVERTER CHAPTER 10 WATCHDOG TIMER CHAPTER 11 STOP AND WAIT MODES CHAPTER 12 CONNECTING EXTERNAL DEVICES CHAPTER 13 RESET CHAPTER 14 CLOCK GENERATING CIRCUIT CHAPTER 15 ELECTRICAL CHARACTERISTICS CHAPTER 16 STANDARD CHARACTERISTICS CHAPTER 17 APPLICATIONS CHAPTER 18 LOW VOLTAGE VERSION CHAPTER 19 BUILT-IN PROM VERSION CHAPTER 20 EXTERNAL ROM VERSION APPENDIX

7733 Group User’s Manual2

The 7733 Group is described in part 1. For the 7735 Group, refer to part “2. 7735 Group.” In part 2, the differences between the 7735 Group and the 7733 Group are mainly described. For the 7736 Group, refer to part “3. 7736 Group.” In part 3, the differences between the 7736 Group and the 7733 Group are mainly described.

1.1 Performance overview

1.2 Pin configuration

1.3 Pin description

1.4 Block diagram

1-2 7733 Group User’s Manual The 7733 Group is a 16-bit single-chip microcomputer designed with high-performance CMOS silicon gate technology. It is housed in an 80-pin plastic molded flat package. This single-chip microcomputer has a large 16-Mbyte accessible space, three instruction queue buffers, and two data buffers for high-speed instruction execution. The CPU is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. This microcomputer is suitable for communication and office equipment controllers. h About details concerning each microcomputer’s development state of the 7733 Group, inquire “CONTACT ADDRESSES FOR FURTHER INFORMATION” described last. h Functional codes of the 7733 Group are described below. M 3 77 33 M H B XXX FP Represents Mitsubishi integrated prefix Represents uses and operating temperature range Represents circuit type and family name Represents group name 2-digit numerals (Running number) Represents memory type M:Mask ROM E:EPROM S:External ROM Represents memory size 1-digit alphanumeric Represents electrical characteristics Represents ROM’s contents 3-digit numerals Package type FP: Molded plastic flat package GP: Molded plastic flat package HP: Molded fine-pitch plastic flat package SP: Molded plastic SDIP FS: Ceramic flat package

7733 Group User’s Manual 1-3

Ports P0–P2, P4–P8 Port P3 Timers A0–A4 Timers B0–B2 UART0–UART2 Main-clock oscillation circuit Sub-clock oscillation circuit Input/Output withstand voltage Output current Items Number of basic instructions The minimum instruction execution time Main-clock frequency f(X IN) Sub-clock frequency f(XCIN) Memory size Programmable I/O ports Multifunction timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuits Power source voltage Power consumption in single-chip mode Port input/output characteristics Memory expansion Operating temperature range Device structure Package Table 1.1.1 lists the M37733MHBXXXFP’s performance overview. Table 1.1.1 M37733MHBXXXFP’s performance overview Performance 103 160 ns (When f(X IN) = 25 MHz and the main clock is the system clock) 25 MHz (Max.) (Note 3) 32.768 kHz (Typ.)

124 Kbytes

(UART or clock synchronous serial I/O) 5 3 (10-bit successive approximation method) 5 1 (8 channels) 12 bits 5 1 3 external, 16 internal (By software, one of interrupt priority levels 0 to 7 can be set for each interrupt) Built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator.) Built-in (externally connected to a quartz-crystal oscillator)

5 V ± 10% (When the main clock is the system clock)

2.7 V to 5.5 V (When the sub clock is the system clock) 47.5 mW (When f(X IN) = 25 MHz, VCC = 5 V, and the main clock is the system clock, Typ.) 250 µW (When f(XCIN) = 32 kHz, VCC = 5 V, the sub clock is the system clock, and the main clock is stopped, Typ.) 5 V 5 mA Possible (Maximum of 16 Mbytes) –20 °C to +85 °C High-performance CMOS silicon gate process 80-pin plastic molded QFP Notes 1: All of the 7733 Group microcomputers are the same except for package type, memory type, memory size, and electrical characteristics. 2: For the low voltage version, refer to chapter “18. LOW VOLTAGE VERSION.” 3: When the main clock division selection bit = “1,” the maximum value of f(XIN) = 12.5 MHz.

1-4 7733 Group User’s Manual Figure 1.2.1 shows the M37733MHBXXXFP pin configuration. Note: For the low voltage version, refer to chapter “18. LOW VOLTAGE VERSION.” Fig. 1.2.1 M37733MHBXXXFP pin configuration (Top view) 25 2726 28 3429 30 31 32 33 35 36 37 38 39 40 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 0/HOLDBYTECNV SS RESET X IN X OUT E V SS 3/HLDA 2/ALE 1/BHE 0/R/W 7/A 6/A 5/A 4/A 4/AN 4/R XD 5/AN 5/AD TRG XD 6/AN 6/X COUT 7/AN 7/X CIN V SS AV SS V REF AV CC V CC 0/CTS 0/RTS 0/CLKS 1/CLK 2/R XD 0/CLKS 3/T XD P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 80 79 78 77 76 75 74 73 72 71 69 68 67 66 6570 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 P22/A18/D2 P23/A19/D3 M37733MHBXXXFP 24P41/RDY P47 P46 P45 P44 P43 P42/ f1 1/AN 2/AN 2/CTS 3/AN 3/CLK Outline 80P6N-A

7733 Group User’s Manual 1-5

EPROM mode is described in section “19.1 EPROM mode.” Table 1.3.1 Pin description (1) Input/Output Input Input Input Output Output Input Input Name Power source input CNV SS Reset input Clock input Clock output Enable output External data bus width selection input Analog power source input Reference voltage input Note: In the low voltage version, it is 2.7 V to 5.5 V. Pin V CC , VSS CNV SS RESET X IN X OUT E BYTE AV CC AV SS V REF Functions To pin VCC , apply 5 V±10% (Note) (When the main clock is the system clock) or 2.7 V to 5.5 V (When the sub clock is the system clock). To pin VSS , apply 0 V. This pin switches the processor mode. [Single-chip Mode] [Memory Expansion Mode] Connect to pin V SS . [Microprocessor Mode] Connect to pin V CC . The microcomputer is reset when “L” level is input to this pin. Pins X IN and X OUT are the I/O pins of the clock generating circuit, respectively. Connect these pins via a ceramic resonator or a quartz-crystal oscillator. When an external clock is used, the clock should be input to pin X IN, and pin XOUT should be left open. This pin outputs signal E. When E’s level is “L,” the microcomputer reads data and instruction codes or writes data. Also, output of signal E can be stopped by software. [Single-chip Mode] Connect to pin VSS . [Memory Expansion Mode] [Microprocessor Mode] Input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. A 16-bit width is selected when the level is “L,” and an 8-bit width is selected when the level is “H.” Power source input for the A-D converter. Connect to pin V CC . Power source input for the A-D converter. Connect to pin V SS . This is the reference voltage input pin for the A-D converter.

1-6 7733 Group User’s Manual Table 1.3.2 Pin description (2) Input/Output I/O Output I/O I/O I/O Output Functions [Single-chip Mode] P0 is an 8-bit CMOS I/O port and has an I/O direction register. Each pin can be programmed for input or output. [Memory Expansion Mode] [Microprocessor Mode] Address’s low-order 8 bits (A 0–A 7) are output. [Single-chip Mode] P1 is an 8-bit I/O port with the same function as port P0. [Memory Expansion Mode] [Microprocessor Mode] l When the external data bus width = 8 bits (Pin BYTE is at “H” level) Address’s middle-order 8 bits (A 8–A 15) are output. l When the external data bus width = 16 bits (Pin BYTE is at “L” level) Input/Output of data (D 8–D 15) and output of address’s middle-order 8 bits (A8–A 15) are performed with the time sharing method. [Single-chip Mode] P2 is an 8-bit I/O port with the same function as port P0. [Memory Expansion Mode] [Microprocessor Mode] Input/Output of data (D 0–D 7) and output of address’s high-order 8 bits (A16–A 23) are performed with the time sharing method. [Single-chip Mode] P3 is a 4-bit I/O port with the same function as port P0. [Memory Expansion Mode] [Microprocessor Mode] These pins respectively output signals R/W , BHE , ALE, and HLDA . l Signal R/W This signal indicates the data bus state. When this signal level is “H,” a data bus is in the read state. When this signal level is “L,” a data bus is in the write state. ____ l Signal BHE This signal’s level is “L” when the microcomputer accesses an odd address. l Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. l Signal HLDA This signal informs the external whether this microcomputer enters the Hold state or not. In Hold state, pin HLDA outputs “L” level. Name I/O port P0 I/O port P1 I/O port P2 I/O port P3 Pin P0 0–P0 7 A 0–A 7 P1 0–P1 7 A 8/D8– A 15/D15 P2 0–P2 7 A 16/D0– A 23/D7 P3 0–P3 3 R/W , ____ BHE , ALE, HLDA

7733 Group User’s Manual 1-7

[Single-chip Mode] P4 is an 8-bit I/O port with the same function as port P0. P4 2 can also be programmed as the clock φ1 output pin. (Refer to chapter “14. CLOCK GENERATING CIRCUIT.”) [Memory Expansion Mode] P4 0 functions as pin HOLD , and P41 as pin RDY . The microcomputer is in Hold state while pin HOLD ’s ____ input level is “L” and is in Ready state while pin RDY ’s input level is “L.” 2–P4 7 function as I/O ports with the same function as port P0. P42 can also be programmed as the clock φ1 output pin. (Refer to chapter “14. CLOCK GENERATING CIRCUIT.” ) [Microprocessor Mode] P4 0 functions as pin HOLD , P41 as pin RDY , and P42 as the clock φ1 output pin. (Refer to “[Memory Expansion Mode].” ) P43–P4 7 function as I/O ports with the same function as port P0. P5 is an 8-bit I/O port with the same function as port P0 and can be programmed as I/O pins for timers A0– A3 and input pins (KI0–KI3) for the key input interrupt. P6 is an 8-bit I/O port with the same function as port P0 and can be programmed as I/O pins for timer A4, external interrupt input pins, and input pins for timers B0–B2. P6 7 also functions as an output pin for the sub clock (φSUB ). P7 is an 8-bit I/O port with the same function as port P0 and can be programmed as analog input pins for the A-D converter. P7 6 and P77 can be programmed as I/O pins (XCOUT , XCIN ) for the sub-clock (32 kHz) oscillation circuit. When using P76 and P7 7 as pins X COUT and XCIN , connect a quartz-crystal oscillator between them. When inputting an external clock, input the clock from pin X CIN . P72–P7 5 also function as UART2’s I/O pins. P8 is an 8-bit I/O port with the same function as port P0 and can be programmed as serial I/O’s I/O pins. Input/Output I/O Input Input I/O Input Input Output I/O I/O I/O I/O I/O Pin 0–P4 7 HOLD , ____ RDY , P4 2–P4 7 HOLD , ____ RDY , φ1, P4 3–P4 7 P5 0–P5 7 P6 0–P6 7 P7 0–P7 7 P8 0–P8 7 Name I/O port P4 I/O port P5 I/O port P6 I/O port P7 I/O port P8 Table 1.3.3 Pin description (3)

1-8 7733 Group User’s Manual

1.3.1 Examples of handling unused pins

The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user’s application. (1) In single-chip mode Table 1.3.4 Examples of handling unused pins in single-chip mode Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). Leave this pin open. Connect this pin to pin Vcc. Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 2: This is applied when an external clock is input to pin XIN. Pins P0–P8 E X OUT (Note 2) AVcc AVss, VREF , BYTE P0–P8 AVss VREF BYTE M37733MHBXXXFP Vss AVcc E XOUT Left open n When setting ports to input mode VCC P0–P8 AVss VREF BYTE M37733MHBXXXFP Vss AVcc E XOUT Left open n When setting ports to output mode Left open Vcc Fig. 1.3.1 Examples of handling unused pins in single-chip mode

7733 Group User’s Manual 1-9

(2) In memory expansion mode Table 1.3.5 Examples of handling unused pins in memory expansion mode Pins P4 2–P4 7, P5–P8 ____ BHE (Note 3) ALE (Note 4) HLDA X OUT (Note 6) HOLD , RDY AVcc AVss, VREF Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1, 2, and 7). Leave this pin open. (Note 5) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: This is applied when “H” level is input to pin BYTE. 4: This is applied when “H” level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: this pin functions as an input port from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. 7: Set pin P42/φ1 as pin P42. (Clock φ1 output is disabled.) And then, for this pin, do the same handling as that for pins P43 to P47 and P5 to P8. P42–P47, P5–P8 AVss VREF HOLD RDY Left open M37733MHBXXXFP HLDA Vcc Vss AVcc XOUT n When setting ports to input mode Left open P42–P47, P5–P8 AVs s VREF Left open Vss AVcc XOUT n When setting ports to output mode Left open Left open Vcc M37733MHBXXXFP BHE ALE HOLD RDY BHE ALE HLDA Fig. 1.3.2 Examples of handling unused pins in memory expansion mode

1-10 7733 Group User’s Manual (3) In microprocessor mode Table 1.3.6 Examples of handling unused pins in microprocessor mode Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1 and 2). Leave this pin open. (Note 5) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: This is applied when “H” level is input to pin BYTE. 4: This is applied when “H” level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: this pin functions as an input port from reset until the processor mode is switched to the microprocessor mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. Pins P4 3–P4 7, P5–P8 ____ BHE (Note 3) ALE (Note 4) HLDA , φ1 X OUT (Note 6) HOLD , RDY AVcc AVss, VREF P43–P47, P5–P8 AVss VREF HOLD RDY Left open M37733MHBXXXFP HLDA Vcc Vss AVcc XOUT n When setting ports to input mode Left open P43–P47, P5–P8 AVss VREF Left open Vss AVcc XOUT n When setting ports to output mode Left open Left open Vcc M37733MHBXXXFP BHE ALE HOLD RDY BHE ALE HLDA f1 f1 Fig. 1.3.3 Examples of handling unused pins in microprocessor mode

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Figure 1.4.1 shows the M37733MHBXXXFP block diagram. Fig.1.4.1 M37733MHBXXXFP block diagram

1-12 7733 Group User’s Manual MEMO

(CPU)

2.1 Central processing unit

2.4 Memory allocation

2.5 Processor modes

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The CPU of the 7733 Group has ten registers as shown in Figure 2.1.1. Each of these registers is described below. Fig. 2.1.1 CPU registers structure b0b7b8b15 AH AL b0b7b8b15 BH BL b0b7b8b15 XH XL b0b7b8b15 YH YL b0b7b8b15 SH SL b0b7b8b15 b7 b0 b8b23 b16 b15 b7 b0 PC H PC LPG b0b7 DT b0b7b8b15 b0b1b2b3b4b5b6b7b8b10

00000 C ZIDxmVNIPL

Accumulator A (A) Accumulator B (B) Index register X (X) Index register Y (Y) Stack pointer (S) Data bank register (DT) Program counter (PC) Program bank register (PG) Direct page register (DPR) Processor status register (PS) Processor interrupt priority level Carry flag Zero flag Interrupt disable flag Index register length flag Decimal mode flag Data length flag Overflow flag Negative flag DPR LDPR H PS LPS H b9b15

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2.1.1 Accumulator (Acc)

Accumulators A and B are available. (1) Accumulator A (A) Data processing such as calculation, data transfer, or data input/output is executed mainly through accumulator A. It consists of 16 bits and its low-order 8 bits can also be used separately. The data length flag (m), which is a part of the processor status register, specifies whether accumulator A is used as a 16-bit register or an 8-bit register. When the data length is 8 bits wide, only the low-order 8 bits of accumulator A are used and the contents of the high-order 8 bits is unchanged. (2) Accumulator B (B) Accumulator B has the same function as accumulator A and can be used instead of accumulator A. Note that, except for some instructions, the use of accumulator B requires more instruction bytes and execution cycles than that of accumulator A. Accumulator B consists of 16 bits and is also affected by the data length flag (m) just as for accumulator A.

2.1.2 Index register X (X)

Index register X consists of 16 bits and its low-order 8 bits can also be used separately. The index register length flag (x), which is a part of the processor status register, specifies whether index register X is used as a 16-bit register or an 8-bit register. When the index register length is 8 bits wide, only the low-order 8 bits of index register X are used and the contents of the high-order 8 bits is unchanged. In an addressing mode where index register X is used as an index register, the address obtained by adding the contents of index register X to the operand is accessed. In execution of a block transfer instruction (MVP or MVN) , the contents of index register X is the low-order 16 bits of the source address and the third byte of the instruction is the high-order 8 bits of the address. h Refer to “7700 Family Software Manual” for addressing modes.

2.1.3 Index register Y (Y)

Index register Y has the same function as index register X. Index register Y consists of 16 bits and is also affected by the index register length flag (x) just as for index register X. In execution of a block transfer instruction (MVP or MVN) , the contents of index register Y is the low-order 16 bits of the destination address and the second byte of the instruction is the high-order 8 bits of the address.

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2.1.4 Stack pointer (S)

The stack pointer (S) consists of 16 bits and is used for an interrupt, a subroutine call, or execution of an addressing mode where a stack is used. The contents of S indicates a store address for a register and so on during an interrupt or a subroutine call (stack area). The stack area is set in bank 0 16. (Refer to section “2.1.6 Program bank register (PG).”) When an interrupt request is accepted, the microcomputer stores the contents of the program bank register (PG) into an address indicated by the contents of S and decrements the contents of S by 1. Then the microcomputer stores the contents of the program counter (PC) and the processor status register (PS). After acceptance of an interrupt request, the contents of S becomes [S] – 5. ([S] is the initial address that the stack pointer (S) indicates when an interrupt request is accepted.) (Refer to Figure 2.1.2.) After processing in an interrupt routine is finished, processing for return to the original routine is performed as follows. When the RTI instruction is executed, the contents of registers which were stored in the stack area are restored into the original registers. (The contents are restored PS, PC, and PG in that order.) The contents of S is also returned to the state before acceptance of an interrupt request. During a subroutine call, the same processing as for an interrupt is performed. The contents of PS, however, are not automatically stored. (The contents of PG may not be stored. This depends on the addressing mode.) During an interrupt or a subroutine call, registers other than the above registers are not automatically stored. Therefore, be sure to store necessary registers by software. The contents of S is undefined at reset. Therefore, be sure to initialize S at the start of a program. Furthermore, a stack area changes according to subroutine’s nesting or acceptance of multiple interrupts’ requests. Therefore, give careful consideration to subroutine’s nesting depth not to destroy the necessary data. h Refer to “7700 Family Software Manual” for addressing modes. Fig. 2.1.2 Stored registers in stack area h [S] is the initial address that the stack pointer (S) indicates when an interrupt request is accepted. S’s contents is “[S] – 5” after all of the above registers are pushed. Address [S] – 4 [S] – 3 [S] – 2 [S] – 1 [S] Processor status register’s low-order byte (PSL) Stack area [S] – 5 Processor status register’s high-order byte (PSH ) Program counter’s low-order byte (PCL) Program counter’s high-order byte (PCH ) Program bank register (PG)

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2.1.5 Program counter (PC)

The program counter consists of 16 bits. This counter indicates the low-order 16 bits of a store address, which consists of 24 bits, of an instruction to be executed next, in other words an instruction which is read from an instruction queue buffer. At reset, value “FF16” is set to the high-order byte (PCH ) of the program counter and value “FE16” is set to the low-order byte (PCL) of the counter. And then, immediately after reset, the contents of the reset’s vector addresses (addresses FFFE16, FFFF16) are set to the counter. Figure 2.1.3 shows the program counter and the program bank register. Fig. 2.1.3 Program counter and program bank register

2.1.6 Program bank register (PG)

The program bank register consists of 8 bits. (Refer to Figure 2.1.3.) This register indicates the high-order 8 bits of a store address, which consists of 24 bits, of an instruction to be executed next, in other words an instruction which is read from an instruction queue buffer. These 8 bits indicate “bank.” The contents of the program bank register is automatically incremented by 1 when a carry occurs in the following cases:

• When a certain value is added to the contents of the program counter
• When the displacement is added to the program counter by executing a branch instruction and others The contents of the program bank register is automatically decremented by 1 when a borrow occurs in the following case:
• When a certain value is subtracted from the contents of the program counter Therefore, when normally programming, it is not necessary to give consideration to bank boundaries. At reset, this register is cleared to “00 16.” PC H PC L b7 b0 b15 b8 b7 b0 (b16) PG (b23)

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2.1.7 Data bank register (DT)

The data bank register consists of 8 bits. In an addressing mode where the data bank register is used, the contents of this register is processed as the high-order 8 bits (bank) of an address to be accessed, which consists of 24 bits. When setting a certain value to this register, execute the LDT instruction. At reset, this register is cleared to “00 16.” h Addressing modes where the data bank register is used are listed below: Direct • indirect Direct • indexed X • indirect Direct • indirect • indexed Y Absolute Absolute • bit Absolute • indexed X Absolute • indexed Y Absolute • bit • relative Stack pointer • relative • indirect • indexed Y

2.1.8 Direct page register (DPR)

The direct page register consists of 16 bits. The contents of this register specifies a direct page area to bank 0 16 or an area which extends banks 016 and 116. The direct page area can be accessed with two bytes (Note ) by using the direct page addressing mode. The contents of the direct page register indicates the base address (the lowest address) of a direct page area which is extended to 256 bytes above this address. Values from 0000 16 to FFFF16 can be set to the direct page register. When a certain value equal to or more than “FF0116” is set to the direct page register, the direct page area is specified to an area which extends banks 016 and 116. When the contents of low-order 8 bits of the direct page register is cleared to “0016,” the number of cycles required to generate the address to be accessed is decremented by 1. Therefore, efficient access is possible. At reset, this register is cleared to “000016.” Figure 2.1.4 shows a setting example of direct page areas. Note: For the DIV and MPY instructions, the direct page area is accessed with 3 bytes. When accumulator B is used, for each instruction, the number of instruction bytes is incremented by 1. h Addressing modes where the direct page register is used are listed below: Direct Direct • bit Direct • indexed X Direct • indexed Y Direct • indirect Direct • indexed X • indirect Direct • indirect • indexed Y Direct • indirect long Direct • indirect long • indexed Y Direct • bit • relative

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Fig. 2.1.4 Setting example of direct page area /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Bank 016 Bank 116 016 FF16 22216 When DPR = 000016 When DPR = 012316 12316 FF1016 1000F16 Notes 1: When the low-order 8 bits of DPR = “0016,” the number of cycles required to generate the address to be accessed is decremented by 1. When DPR = “FF0116” or more, the direct page area is specified to the area which extends banks 016 and 116. 016 FFFF 16 1000016 When DPR = FF1016

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2.1.9 Processor status register (PS)

The processor status register consists of 11 bits. Figure 2.1.5 shows the structure of the processor status register. b15 b8 b7 b0 b1b2b3b4b5b6b14 b9 b10b11b12b13 Processor status register (PS)0N C ZIDxmV0 IPL 000 Note: “0” is always read from bits 11 to 15. Fig. 2.1.5 Structure of processor status register (1) Bit 0: Carry flag (C) This flag retains a carry or borrow which occur in the Arithmetic Logic unit (ALU) during an arithmetic or logic operation. This flag is also affected by a shift or rotate instruction. When the BCC or BCS instruction is executed, the program branches according to this flag’s state. When setting this flag to “1,” execute the SEC or SEP instruction; when clearing this flag to “0,” execute the CLC or CLP instruction. (2) Bit 1: Zero flag (Z) This flag is set to “1” when the result of an arithmetic operation or data transfer is “0” and cleared to “0” when otherwise. When the BNE or BEQ instruction is executed, the program branches according to this flag’s state. This flag is ignored for an addition and subtraction instructions (the ADC and the SBC instructions) in the decimal mode. When setting this flag to “1,” execute the SEP instruction; when clearing this flag to “0,” execute the CLP instruction. (3) Bit 2: Interrupt disable flag (I) This flag disables all maskable interrupts, in other words interrupts other than watchdog timer, the BRK instruction, and zero division interrupts. Interrupts are disabled when this flag is “1.” When an interrupt request is accepted, this flag is automatically set to “1” and disables multiple interrupts. When setting this flag to “1,” execute the SEI or SEP instruction; when clearing this flag to “0,” execute the CLI or CLP instruction. At reset, this flag is set to “1.” (4) Bit 3: Decimal mode flag (D) This flag determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic is performed when this flag is “0.” When it is “1,” decimal arithmetic is performed. At this time, each word is processed as 2- or 4-digit decimal data. (The digit’s number is determined by the data length flag (m)). Decimal adjust is automatically performed. (Note that a decimal operation is enabled only in execution of the ADC or SBC instruction.) When setting this flag to “1,” execute the SEP instruction; when clearing this flag to “0,” execute the CLP instruction. At reset, this flag is cleared to “0.”

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(5) Bit 4: Index register length flag (x) This flag determines whether index register X or index register Y is used as a 16-bit register or an 8-bit register. The register is used as a 16-bit register when this flag is “0” and as an 8-bit register when this flag is “1.” When setting this flag to “1,” execute the SEP instruction; when clearing this flag to “0,” execute the CLP instruction. At reset, this flag is cleared to “0.” Note: When data is transferred between registers which are different in bit length, the data is transferred with the bit length of the destination register. But this is not applied to the case where the TXA , TYA , TXB , or TYB instruction is executed. Refer to “7700 Family Software Manual” for details. (6) Bit 5: Data length flag (m) This flag determines whether data is used as 16-bit data or 8-bit data. Data is used as 16-bit data when this flag is “0” and as 8-bit data when this flag is “1.” When setting this flag to “1,” execute the SEM or SEP instruction; when clearing this flag to “0,” execute the CLM or CLP instruction. At reset, this flag is cleared to “0.” Note: When data is transferred between registers which are different in bit length, the data is transferred with the data length of the destination register. But this is not applied to the case where the TXA , TYA , TXB , or TYB instruction is executed. Refer to “7700 Family Software Manual” for details. (7) Bit 6: Overflow flag (V) This flag is valid when addition or subtraction is executed for each word which is processed as signed binary data. If the data length flag (m) is “0,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range between –32768 and +32767 and cleared to “0” in the other cases. If the data length flag (m) is “1,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range between –128 and +127 and cleared to “0” in the other cases. Also, the overflow flag is set to “1” when the length of the division result obtained by the DIV instruction is longer than that of a register where the result is to be stored. When the BVC or BVS instruction is executed, the program branches according to this flag’s state. This flag is ignored in the decimal mode. When setting this flag to “1,” execute the SEP instruction; when clearing this flag to “0,” execute the CLV or CLP instruction. (8) Bit 7: Negative flag (N) This flag is set to “1” when the result of an arithmetic operation or data transfer is negative. (Bit 15 of the result is “1” when the data length flag (m) is “0,” or bit 7 of the result is “1” when the data length flag (m) is “1.”) It is cleared to “0” in the other cases. When the BPL or BMI instruction is executed, the program branches according to this flag’s state. This flag is ignored in the decimal mode. When setting this flag to “1,” execute the SEP instruction; when clearing this flag to “0,” execute the CLP instruction. (9) Bits 8 to 10: Processor interrupt priority level (IPL) These bits can specify one of levels 0 to 7 as the processor interrupt priority level. An interrupt is enabled when its interrupt priority level, which is set in the interrupt control register, is higher than IPL. When the interrupt request is accepted, the contents of IPL is stored into the stack area and the interrupt priority level of the accepted interrupt is set in IPL. No instruction can directly set or clear each of these bits. When changing these bits, store a desired processor interrupt priority level into the stack area. And then, change the contents of the processor status register by executing the PUL or PLP instruction. At reset, the contents of IPL is cleared to “000 2.”

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The microcomputer has a bus interface unit (BIU) between the central processing unit (CPU) and memory • I/O unit. The BIU’s function and operation are described below. When connecting external devices, refer to chapter “12. CONNECTING EXTERNAL DEVICES,” also.

2.2.1 Overview

Transfer operation between the CPU and memory • I/O unit is always performed via the BIU. À The BIU reads an instruction from the memory before the CPU executes it. \` When the CPU reads data from the memory • /O unit, the CPU informs the BIU of the address where the data resides. The BIU reads the data from the address and pass it to the CPU. ´ When the CPU writes data to the memory • I/O unit, the CPU informs the BIU of the address where the data resides. The BIU writes the data to the address. ˆ In order to realize operations À to ´ , the BIU inputs and outputs bus control signals and controls the buses. Figure 2.2.1 shows the buses and bus interface unit (BIU).

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Fig. 2.2.1 Buses and bus interface unit (BIU) M37733MHBXXXFP Internal bus D to D Central processing unit (CPU) SFR : Special Function Register Notes 1: CPU bus, internal bus, and external bus are independent of each other. For details about signals on the external buses, refer to ch apter “12. CONNECTING EXTERNAL DEVICES.” Internal bus A to A Externaldevices Internal control signals CPU bus Internal bus Internal bus D 7 to D Internal memory Internal peripheraldevices(SFR) External busA 7 to A A to A 8/D A 7 to A Control signals Bus interface unit(BIU) Bus conversion circuit

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2.2.2 Functions of bus interface unit (BIU)

function. Table 2.2.1 Each register’s function Fig. 2.2.2 Registers’ structure of which bus interface unit (BIU) consists Name Program address register Instruction queue buffer Data address register Data buffer Functions Indicates a store address for an instruction which is next fetched into an instruction queue buffer. Temporarily stores an instruction which was fetched. Indicates an address for data which is next read or written. Temporarily stores data which was read from the memory • I/O unit by the BIU or which is to be written to the memory • I/O unit by the CPU. PA b23 b0 Q 0 b7 b0 Q 1 Q 2 DA b23 b0 DB L DB H b15 Program address register Instruction queue buffer Data address register Data buffer

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The CPU and buses operate on the basis of different signals (Note ). Between the CPU and buses, therefore, data is passed or received via the BIU. Owing to the BIU’s operation, the CPU can operate at high speed without waiting for the access by the low-speed memory • I/O unit. When an external device is connected, it is necessary to secure an access time according to the external device’s timing specifications. In this case, in order to secure an access time, the BIU extends the duration of signals required for the access. Note: The CPU operates on the basis of φCPU . The period of φCPU is normally the same as that of φ.__ The internal buses operate on the basis of E. The period of E is at least twice that of φ. The BIU’s functions are described below. (1) Reading out instruction (Instruction prefetch) When the CPU does not request to read or write data, that is, when buses are not in use, the BIU reads instructions from the memory and stores them in an instruction queue buffer. This is called “instruction prefetch.” The CPU reads instructions from the instruction queue buffer and executes them. Therefore, the CPU can operate at high speed without waiting for the access by the low-speed memory. When the instruction queue buffer becomes empty or stores only 1 byte of an instruction, the BIU prefetches a new instruction code. The instruction queue buffer can store instructions up to 3 bytes. The contents of the instruction queue buffer is initialized when a branch or jump instruction is executed and the BIU reads a new instruction code from the destination address. If instructions in the instruction queue buffer are insufficient for the CPU’s request, the BIU extends the “L”-level duration of clock φCPU in order to keep the CPU waiting until the BIU fetches the requested number of instructions or more. (2) Writing data to memory • I/O The CPU informs the BIU’s data address register of an address to which data is written and writes the data to the data buffer. The BIU outputs the address received from the CPU to the address bus and writes the data in the data buffer to the specified address. While the BIU is writing data to the specified address, the CPU advances to the next process without waiting for completion of BIU’s write operation. Note that while the BIU uses buses for instruction prefetch, the BIU keeps the CPU waiting even when the CPU requests to write data. (3) Signal input/output for access to external device When accessing external devices, the BIU inputs and outputs signals required for the access. (For details, refer to chapter “12. CONNECTING EXTERNAL DEVICES.” )

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2.2.3 Operation of bus interface unit (BIU)

Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU). When accessing external devices, some signals which are input or output to or from the external are required. For details about these signals, refer to chapter “12. CONNECTING EXTERNAL DEVICES.” (1) When fetching an instruction into an instruction queue buffer À When an instruction which is next fetched resides at an even address The BIU fetches two bytes of the instruction with waveform (a). Note that when an external device which is connected by an 8-bit external data bus (BYTE = “H”) is accessed, only one byte of the instruction is fetched. \ When an instruction which is next fetched resides at an odd address The BIU fetches only one byte of the instruction with waveform (a). The contents at an even address is not fetched into an instruction queue buffer. (2) When reading or writing data from or to memory • I/O À When accessing 16-bit data which starts from an even address, waveform (a) is applied. The 16- bit data is accessed at a time. \ When accessing 16-bit data which starts from an odd address, waveform (b) is applied. The 16-bit data is accessed by the 8 bits. Invalid data is not fetched into a data buffer. ´ When accessing 8-bit data at an even address, waveform (a) is applied. Data at an odd address is not fetched into a data buffer. ˆ When accessing 8-bit data at an odd address, waveform (a) is applied. Data at an even address is not fetched into a data buffer. For instructions which are affected by the data length flag (m) or index register length flag (x), an operation is applied as follows:

• When “m” or “x” = “0,” operation À or \` is applied.
• When “m” or “x” = “1,” operation ´ or ˆ is applied.

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E (a) (b) AddressInternal address bus (A0 to A23) Data (Even address)Internal data bus (D0 to D 7) Data (Odd address)Internal data bus (D8 to D 15) E Address (Odd address) Address (Even address) Data (Even address) Data (Odd address) Invalid data Invalid data Internal address bus (A0 to A23) Internal data bus (D0 to D 7) Internal data bus (D8 to D 15) Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU)

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Figure 2.3.1 shows the M37733MHBXXXFP’s accessible area. Although the program counter (PC) consists of 16 bits, it can access the 16-Mbyte area at addresses 016 to FFFFFF16, combined with the program bank register (PG). For details about access to the external, refer to chapter “12. CONNECTING EXTERNAL DEVICES.” The memories and I/O units are allocated in the same accessible area. Therefore, operations such as data transfer, arithmetic, and others can be performed with the same instructions. (It is not necessary to distinguish the memories and I/O units.) Fig. 2.3.1 M37733MHBXXXFP’s accessible area 00000016 00008016 00FFFF 16 01000016 FE0000 16 FF000016 FFFFFF 16 00100016 02000016 000FFF 16 00007F16

• SFR : Special Function Register represents the memory allocation of internal areas. indicates that nothing is allocated. Note: Memory allocation of the internal area in bank 016 depends on the microcomputer’s type and settings of the memory allocation selection bits. The above diagram shows the M37733MHBXXXFP’s accessible area immediately after reset. For the other microcomputers of the 7733 Group, refer to section “Appendix 1. Memory allocation of 7733 Group.” For settings of the memory allocation selection bits, refer to section “2.4 Memory allocation .” SFR area Internal RAM area Bank 016 Internal ROM area Bank 116 Bank FF16 Bank FE16 01FFFF 16

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2.3.1 Banks

The accessible area is divided by the 64 Kbytes. This 64-Kbyte area is called “bank.” The high-order 8 bits of an address, which consists of 24 bits, indicate the bank. A bank is specified by the program bank register (PG) or data bank register (DT). Each bank can be accessed efficiently by using an addressing mode where the data bank register (DT) is used. At each bank’s boundary, when an overflow occurs in the program counter (PC), the contents of the program bank register (PG) is incremented by 1; when a borrow occurs in the program counter (PC), the contents of the program bank register (PG) is decremented by 1. Accordingly, when normally programming, it is not necessary to give consideration to bank boundaries.

2.3.2 Direct page

A 256-byte area specified by the direct page register (DPR) is called “direct page.” When setting a direct page, set the base address (the lowest address) of an area which is to be specified as a direct page to the direct page register (DPR). (Refer to section “2.1.8 Direct page register (DPR).”) By using a direct page addressing mode, a direct page can be accessed with less instruction cycles.

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The internal area’s memory allocation is described below. For the external area, refer to section “2.5 Processor modes.”

2.4.1 Memory allocation in internal area

SFR (Special Function Register), internal RAM, and internal ROM are allocated in the internal area. (1) SFR (Special Function Register) area Registers required for setting internal peripheral devices are allocated to addresses 016 to 7F16. This area is called “SFR (Special Function Register) area.” Figure 2.4.4 shows the SFR area’s memory map. For each register in the SFR area, refer to the corresponding functional description. For the state of the SFR area immediately after reset, refer to section “13.1.2 State of CPU, SFR area and internal RAM area.” (2) Internal RAM area In the M37733MHBXXXFP, a 3968-byte static RAM is allocated to addresses 80 16 to FFF16 (Note). The internal RAM area is used as a data store area and as a stack area. Therefore, it is necessary to give careful consideration to nesting levels in subroutines and multiple interrupts’ levels not to destroy necessary data. (3) Internal ROM area In the M37733MHBXXXFP, a 124-Kbyte mask ROM is allocated to addresses 1000 16 to 1FFFF16 immediately after reset (Note ). The internal ROM’s size and area can be changed by the memory allocation selection bits (bits 0 to 2 at address 6316). Figure 2.4.1 shows the structure of the memory memory map. (Refer to section “Appendix 9. Q & A. ”) Vector addresses for reset and interrupts (interrupt vector table) are allocated to addresses FFD6 16 to FFFF16 in the internal ROM. In the microprocessor mode, where the internal ROM area is inhibited from use, the ROM must be allocated to addresses FFD6 16 to FFFF16. Note: For the other microcomputers of the 7733 Group, refer to section “Appendix 1. Memory allocation of 7733 Group.”

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Fig. 2.4.1 Structure of memory allocation control register and its setting method ROM size ROM size 7 to 5 Not implemented. Notes 1: The case where value “5516” is written in À of the procedure listed below is not included. 2: When changing these bits, this change must be performed in an area which is internal ROM area before and after this change, for example addresses 00C00016 to 00FFFF16. Also, when changing these bits, be sure to follow the procedure listed below. 3: This figure is applied only to the M37733MHBXXXFP. For the other microcoputers, please refer to the latest datasheets on the English document CD-ROM or our Web site. Bit Bit name Functions At reset RW Memory allocation selection bits (Notes 1 and 2) 0 0 0: 124 Kbytes, 3968 bytes 0 0 1: 120 Kbytes, 3968 bytes 0 1 0: 60 Kbytes, 2048 bytes 0 1 1: Do not select. 1 0 0: 32 Kbytes, 2048 bytes 1 0 1: 16 Kbytes, 2048 bytes 1 1 0: 96 Kbytes, 3968 bytes 1 1 1: Do not select. b2b1b0 Memory allocation control register (address 6316) (Note 3) b1 b0b2b3b4b5b6b7 RW RW RW RW RW Un- defined | Note: When changing bits 2 to 0, be sure to follow this procedure. Procedure À By using the LDM instruction, write value “5516” to address 6316. (By this, writing to the memory allocation selection bits is enabled.) \` By using the LDM instruction, write value “00000XXX2” to address 6316. (Values of b2, b1, and b0 shown in the above Figure) Writing is performed by the next instruction. Must be fixed to “0.” (Note 1)

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Fig. 2.4.2 M37733MHBXXXFP’s memory map (1) 01FFFF 16 FF000016 SFR area Internal RAM area 3968 bytes 00000016 00007F16 00008016 000FFF 16 FFFFFF 16 Bank 016 Bank 116 Bank FF16 Internal ROM area

60 Kbytes

64 Kbytes

(4 Kbytes) 00FFFF 16 01000016 01FFFF 16 FFFFFF 16 00000016 00007F16 A-D/UART2 trans./rece. UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide RESET 00FFD6 16 00FFFE 16 Interrupt vector table SFR area Internal RAM area 3968 bytes Internal ROM area

56 Kbytes

(SFR)

• Memory allocation selection bits (b2, b1, b0)=(0, 0, 0)
• ROM size: 124 Kbytes
• RAM size: 3.9 Kbytes
• Memory allocation selection bits (b2, b1, b0)=(0, 0, 1)
• ROM size: 120 Kbytes
• RAM size: 3.9 Kbytes UART1 transmission UART0 transmission : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section “2.5 Processor modes.”) 2: Banks 10 16 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. (Refer to section “Appendix 1 in part 2.”) Refer to Appendix 2. 02FFFF 16 02000016

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Fig. 2.4.3 M37733MHBXXXFP’s memory map (2) 00FFFF 16 01000016 UART1 transmission 01FFFF 16 FF000016 00000016 00007F16 00008016 00087F16 FFFFFF 16 00100016 00000016 00007F16 00008016 00087F16 00FFFF 16 01000016 FFFFFF 16 00000016 RESET 00007F16 00FFD6 16 00FFFE 16 A-D/UART2 trans./rece. 02000016 00800016 SFR area Internal RAM area 2048 bytes Bank 016 Bank 116 Bank FF16 Internal ROM area (29.9 Kbytes) UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT 2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide Interrupt vector table SFR area Internal RAM area 2048 bytes Peripheral device control registers (SFR) : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode

• Memory allocation selection bits (b2, b1, b0)=(0, 1, 0)
• ROM size: 60 Kbytes
• RAM size: 2048 bytes
• Memory allocation selection bits (b2, b1, b0)=(1, 0, 0)
• ROM size: 32 Kbytes
• RAM size: 2048 bytes (1.9 Kbytes) UART0 transmission Refer to Appendix 2. 02FFFF 16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section “2.5 Processor modes.”) 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Internal ROM area

32 Kbytes

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Fig. 2.4.4 M37733MHBXXXFP’s memory map (3) A-D/UART2 trans./rece. 00800016 SFR area Internal RAM area 2048 bytes Bank 016 Bank 116 Bank FF16 Internal ROM area

16 Kbytes

(28 Kbytes) UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT 2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide Interrupt vector table SFR area Internal RAM area 3968 bytes Peripheral device control registers (SFR) : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode

• Memory allocation selection bits (b2, b1, b0)=(1, 0, 1)
• ROM size: 16 Kbytes
• RAM size: 2048 bytes
• Memory allocation selection bits (b2, b1, b0)=(1, 1, 0)
• ROM size: 96 Kbytes
• RAM size: 3968 bytes (45.9 Kbytes) UART0 transmission Refer to Appendix 2. 02FFFF 16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section “2.5 Processor modes.”) 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Internal ROM area

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Fig. 2.4.5 SFR area’s memory map UART 0 transmission interrupt control register UART 1 transmission interrupt control register INT2/Key input interrupt control register Port P1 direction register UART 0 transmit/receive mode register UART 0 baud rate register (BRG0) UART 0 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 0 transmission buffer register UART 1 transmit/receive control register 0 UART 1 transmit/receive mode register UART 1 baud rate register (BRG1) UART 1 transmit/receive control register 1 UART 0 receive buffer register UART 1 transmission buffer register UART 1 receive buffer register Port P0 register A-D register 0 A-D register 2 Port P1 register Port P0 direction register Port P2 register Port P3 register Port P4 register Port P5 register Port P6 register Port P7 register Port P8 register A-D control register 0 A-D control register 1 A-D register 1 A-D register 3 A-D register 4 A-D register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001A 00001B 00001C 00001D 00001E 00001F 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002A 00002B 00002C 00002D 00002E 00002F 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003A 00003B 00003C 00003D 00003E 00003F 00000B 00000C 00000D 00000E 00000F 00000A 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F 00004B 00004C 00004D 00004E 00004F 00004A 000044 Address (Hexadecimal notation) Address (Hexadecimal notation) Timer A1 register Timer A4 register Timer A2 register Timer A3 register Timer B0 register Timer B1 register Timer B2 register Count start flag One-shot start flag Up-down flag Timer A0 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Watchdog timer register Watchdog timer frequency selection flag A-D/UART2 trans./rece. interrupt control register UART 0 receive interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register Processor mode register 1 Oscillation circuit control register 1 Serial transmit control register Port function control register Oscillation circuit control register 0 Timer A3 mode register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Reserved area (Note) A-D register 6 A-D register 7 UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Reserved area (Note) Note: Writing to reserved area is disabled. Reserved area (Note) Memory allocation control register A-D control register 1

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The M37733MHBXXXFP can operate in the following three processor modes: single-chip mode, memory expansion mode, and microprocessor mode. In the M37733MHBXXX FP, some pins’ functions, memory allocation, and accessible area differ according to processor modes. These differences according to processor modes are described below. Figure 2.5.1 shows the memory map in each processor mode. Notes 1: represents external memory area. By accessing this area, an external device connected to the M37733MHBXXXFP can be accessed. This is applied when the contents of memory allocation selection bits (bits 2 to 0 at address 6316) = “0002.” For the 7733 Group’s microcomputers other than the M37733MHBXXXFP, refer to section “Appendix 1. Memory allocation of 7733 Group.” SFR area Internal ROM area (Note 2) Single-chip mode Internal RAM area SFR area Memory expansion mode SFR area Microprocessor mode Internal RAM area Internal RAM area Internal ROM area (Note 2) Fig. 2.5.1 Memory map in each processor mode (M37733MHBXXXFP )

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2.5.1 Single-chip mode

When not using an external device, this mode is used. In this mode, ports P0 to P8 function as programmable I/O ports. (When using internal peripheral devices, they function as I/O pins.) Only the internal area (SFR, internal RAM, and internal ROM) can be accessed. Output of E can be stopped by software. (Refer to section “12.1 Signals required for accessing external devices.”)

2.5.2 Memory expansion and Microprocessor modes

When connecting an external device, these modes are used. In these modes, an external device can be connected to an arbitrary area in the 16-Mbyte accessible area. For access to an external device, refer to chapter “12. CONNECTING EXTERNAL DEVICES. ” The memory expansion and microprocessor modes have the same functions except for the followings: À In the microprocessor mode, access to the internal ROM area is forcibly disabled. This area is handled as the external area. \` In the microprocessor mode, port P42 functions as a clock φ1 output pin. (Note) In the memory expansion and microprocessor modes, pins P0 to P3, P40, and P41 function as I/O pins for signals required for access to an external device. Therefore, these pins cannot be used as programmable I/O ports. If an external device is connected to a certain area which is allocated to the internal area, when this area is read, data in the internal area is fetched into the central processing unit (BIU) but data in the external area is not fetched; when data is written to this area, the data is written to the internal area and signals are output to the external at the same timing as writing to the internal area. Note: Output of clock φ1 can be stopped by software. (For details, refer to section “12.1 Signals required for accessing external devices.”) processor modes and functions of P0 to P4. For each pin’s function, refer to section “1.3 Pin description,” chapters “3. PROGRAMMABLE I/O PORTS ” to “9. A-D CONVERTER ” and “12. CONNECTING EXTERNAL DEVICES. ”

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Fig. 2.5.2 Pin configuration in each processor mode (Top view) A20/D4 A21/D5 A22/D6 A23/D7 R/W BHE ALE HLDA VSS E XOUT XIN RESET CNV SS BYT E HOLD P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 A8/D8 A9/D9 A10/D10 P70/AN0 P67/TB2IN/f SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 14 325 P24 P25 P26 P27 P30 P31 P32 P33 VSS E XOUT XIN RESET CNV SS ]1 BYT E ]1 P40 P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TXD 2 P74/AN4/RXD 2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 P13 P14 P15 P16 P17 P20 P21 P22 P23 43 42 41 M37733MHBXXXFP 22 23 24 P41 P47 P46 P45 P44 P43 P42/f 1 P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P70/AN0 P67/TB2IN/f SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 1 432 5 P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TXD 2 P74/AN4/RXD 2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 A16/D0 A17/D1 A18/D2 A19/D3 43 42 41 M37733MHBXXXFP 22 23 24 RDY P47 P46 P45 P44 P43 ]2 P42/f 1 : These pins’ functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. ]1 Connect this pin to Vss in the single-chip mode. <Single-chip mode> <Memory expansion and Microprocessor modes> ]2 f 1 in the microprocessor mode : These pins’ functions in the single-chip mode differ from those in the memory expansion or microprocessor mode.

In the memory expansion mode, this pin functions as a programmable I/O port. Furthermore, it can be switched to be a clock The above table indicates the change of pin functions owing to the switching of the processor mode. For each signal’s I/O timing in the memory expantion or microprocessor mode, refer to chapters “12. CONNECTING EXTERNAL DEVICES. ” CENTRAL PROCESSING UNIT (CPU)

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Table 2.5.1 Relationship between processor modes and functions of P0 to P4 P31 P32 P30 P33 P47 to P43 P41 P42 P40 HLDA A15 to A8 D(odd) A7 to A0 A15 to A8 D(odd): Data at odd address A23 to A16 D(even) D(even): Data at even address A23 to A16 D D: Data ALE P RDY HOLD f 1 (Note 2) BHE R/W P P P P P Notes 1: Pin P42 can also function as a clock f 1 output pin. (Refer to chapter “12. CONNECTING EXTERNAL DEVICES. ”) f 1 output pin when selected by software. In the microprocessor mode, this pin is affected by the signal output disable selection bit (bit 6 at address 6C16 ). (Refer to chapter ) “12. CONNECTING EXTERNAL DEVICES ” and “15. ELECTRICAL CHARACTERISTICS. ” Pin name Single-chip mode Memory expansion and Microprocessor modes Processor mode n When external data bus is 16 bits wide (BYTE = “L”) n When external data bus is 8 bits wide (BYTE = “H ”) n When external data bus is 16 bits wide (BYTE = “L”) n When external data bus is 8 bits wide (BYTE = “H ”) P: Functions as a programmable I/O port. P: Functions as a programmable I/O port. P: Functions as a programmable I/O port. P: Functions as a programmable I/O port. P: Functions as a programmable I/O port. P: Functions as a programmable I/O port. (Note 1)

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2.5.3 Selection of processor mode

A processor mode can be selected by setting a voltage applied to pin CNVSS and the processor mode bits (bits 1 and 0 at address 5E16). l When V SS level is applied to pin CNVSS After reset, the microcomputer starts operating in the single-chip mode. After the microcomputer starts operating, the processor mode can be switched by the processor mode bits. When the contents of the processor mode bits = “012,” the memory expansion mode is selected; when the contents of these bits = “102,” the microprocessor mode is selected. After the processor mode bits are set, the processor mode is actually switched at the rising edge of signal E. Figure 2.5.3 shows the pin function switch timing when the processor mode is switched from the single-chip mode to the memory expansion or microprocessor mode by setting the processor mode bits. Note that, when the processor mode is switched during the program execution, the contents of the instruction queue buffer is not initialized. (Refer to section “Appendix 9. Q & A.”) l When V CC level is applied to pin CNVSS After reset, the microcomputer starts operating in the microprocessor mode. In this case, the microcomputer cannot operate in the other modes. (Fix the processor mode bits to “102.”) processor mode register 0. P07 E External address bus A7 Writing to the processor mode bits Programmable I/O port P07 Note: Functions of pins P00 to P06, P1 to P3, P40 to P42 are switched at the timing shown above. Function of pin P42 is, however, switched only when the processor mode is switched to microprocessor mode. Fig. 2.5.3 Pin function switch timing

represents that bits 2 to 7 are not used for selecting a processor mode. CENTRAL PROCESSING UNIT (CPU)

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Table 2.5.2 Method of selecting processor mode Pin CNV SS ’s level V SS (0 V) (Note 1) V SS (0 V) (Note 1) V SS (0 V) (Note 1) V CC (5 V) (Note 2) Processor mode bits Notes 1: The microcomputer starts operating in the single-chip mode after reset. By setting the processor mode bits, the processor mode of the microcomputer can be switched from the single-chip mode to the other modes. 2: The microcomputer starts operating in the microprocessor mode after reset. The microcomputer cannot operate in the other modes. Accordingly, so fix the processor mode bits (bits 1 and 0 at address 5E16) to “102.” Fig. 2.5.4 Structure of processor mode register 0 Bit Bit name Functions At reset RW Processor mode bits Wait bit Software reset bit Must be fixed to “0.” Clock f 1 output selection bit (Note 2) 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Microprocessor mode 1 1: Do not select. 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. Microcomputer is reset by setting this bit to “1.” This bit is “0” at reading. 0 0: 7 cycles of f 0 1: 4 cycles of f 1 0: 2 cycles of f 1 1: Do not select. 0: Clock f 1 output is disabled. (P4 2 functions as a 1: Clock f1 output is enabled. 2 functions as a clock f1 output pin.) b1 b0 b5 b4 Processor mode register 0 (address 5E16) (Note 1) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to “1” after reset. (When read, this bit is always “0.”) 2: This bit is ignored in the microprocessor mode. (It may be “0” or “1.”) b1 b0b2b3b4b5b6b7 RW RW RW WO RW RW RW RW Interrupt priority detection time selection bits (Port P42 programmable I/O port.)

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[Precautions on selecting processor mode] 1. The external ROM version can operate only in the microprocessor mode. Therefore, be sure to set as follows:

• Connect pin CNVss to Vcc.
• Fix the processor mode bits (b1, b0) to “102.”

3.1 Programmable I/O ports

3.2 Port peripheral circuits

3.3 Pullup function

3.4 Internal peripheral devices’ I/O functions (Ports P42 and P5 to P8)

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Functions of all ports in the single-chip mode and that of ports P43 to P47 and P5 to P8 in the memory expansion and the microprocessor modes are described below. For more information about ports P0 to P4, whose functions depend on the processor mode, refer to section “2.5 Processor modes” and chapter “12. CONNECTING EXTERNAL DEVICES.” The 7733 Group has 68 programmable I/O ports (P0 to P8). Each of ports P0 to P8 has a port direction register and a port register in the SFR area. Each input-only port has a port register in the SFR area. Figure 3.1.1 shows the memory map of port direction registers and port registers. Note that ports P4 2 and P5 to P8 also function as I/O pins for internal peripheral devices. For details, refer to section “3.4 Internal peripheral devices’ I/O functions” and the corresponding functional description. Fig. 3.1.1 Memory map of port direction registers and port registers Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register 816 916 A16 B16 C 16 D 16 E16 F16 1016 1116 1216 1316 1416 addresses Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register 316 416 516 616 716

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3.1.1 Port Pi direction register

This register determines the direction of programmable I/O ports. Each bit of this register corresponds to one specified pin. Figure 3.1.2 shows the structure of the port Pi (i = 0 to 8) direction register. Fig. 3.1.2 Structure of port Pi (i = 0 to 8) direction register Bit Bit name Functions 0: Input mode (The port functions as an input port.) 1: Output mode (The port functions as an output port.) Port Pi direction register (i = 0 to 8) (addresses 416,516,816,916,C16,D16,1016,1116,1416) b1 b0b2b3b4b5b6b7 At reset RW Note: Writing to bits 4 to 7 of the port P3 direction register is invalid and these bits are fixed to “0” when they are read.

0 Port Pi 0 direction selection bit 0 RW

1 Port Pi 1 direction selection bit 0 RW

2 Port Pi 2 direction selection bit 0 RW

3 Port Pi 3 direction selection bit 0 RW

4 Port Pi 4 direction selection bit 0 RW

5 Port Pi 5 direction selection bit 0 RW

6 Port Pi 6 direction selection bit 0 RW

7 Port Pi 7 direction selection bit 0 RW

pin Pi6 Pi5 Pi4 Pi3 Pi2 Pi1 Pi0

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3.1.2 Port Pi register

Data is input from or output to an external device by writing/reading data to/from a port register. A port register consists of a port latch, which holds the output data, and a circuit, which reads the pin state. Each bit of the port register corresponds to one specified pin. Figure 3.1.3 shows the structure of the port Pi (i = 0 to 8) register. (1) How to output data from programmable I/O port À Set the corresponding bit of the port direction register to the output mode. \ Write data to the corresponding bit of the port register, and then the data is written into the port latch. ´ Data set in the port latch is output. When a bit of a port register which corresponds to a port set for the output mode is read out, the contents of the port latch, instead of pin state, is read out. Accordingly, output data can correctly be (2) How to input data from programmable I/O port À Set the corresponding bit of the port direction register to the input mode. \ The pin enters a floating state. ´ When reading the corresponding bit of the port register in state \` , data input from the pin can be read in. When data is written to a port register which corresponds to a port set for the input mode, the data is written only into the port latch and not output to the external devices. Pins retain a floating state.

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Fig. 3.1.3 Structure of port Pi (i = 0 to 8) register Data is input from or output to a pin by reading from or writing to the corresponding bit. Port Pi register (i = 0 to 8) (addresses 216,316,616,716,A16,B16,E16,F16,1216) b1 b0b2b3b4b5b6b7 Note: Writing to bits 4 to 7 of the port P3 register is invalid and these bits are fixed to “0” when they are read. 0: “L” level 1: “H” level

7 Port Pi 7’s pin Undefined RW

Bit Bit name Functions At reset RW

0 Port Pi 0’s pin RWUndefined

1 Port Pi 1’s pin RWUndefined

2 Port Pi 2’s pin RWUndefined

3 Port Pi 3’s pin RWUndefined

4 Port Pi 4’s pin RWUndefined

5 Port Pi 5’s pin RWUndefined

6 Port Pi 6’s pin RWUndefined

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Fig. 3.2.1 Port peripheral circuits (1)

• Ports P55/TA2IN/KI1, P57/TA3IN/KI3 , P62/INT0 to P64/INT2 Data bus Pull-up selection Pull-up transistor
• Ports P54/TA2OUT /KI0, P56/TA3OUT /KI2 “1” Output Ports P50/TA0OUT , P52/TA1OUT , P60/TA4OUT , P75/AN5/ADTRG /TxD2, P82/RxD0/CLKS0 (Inside dotted-line included, and shaded area not included)
• Ports P83/TxD0, P87/TxD1 (Inside dotted-line not included, and shaded area included) Notes 1: Valid only when used as pin TxDj for Serial I/O. 2: Analog input is present only in port P75. N-channel open-drain selection (Note 1) Analog input (Note 2) Port P42/ 1 (Inside dotted-line not included, and shaded area not included)
• Ports P00 to P07, P10 to P17, P20 to P27, P30 to P33, P43 to P46 (Inside dotted-line not included) Ports P40/HOLD, P41/RDY, P47, P51/TA0IN, P53/TA1IN, P61/TA4IN, P65/TB0IN to P67/TB2IN/ f SUB , P86/RxD1 (Inside dotted-line included) Data bus Data bus Data bus Port latch Pull-up selection Output Pull-up transistor “1” Port direction register Port latch Port direction register Port latch Port direction register Port latch Port direction register

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Fig. 3.2.2 Port peripheral circuits (2)

• E
• Ports P73/AN3/CLK2, P80/CTS0/RTS0/CLKS1, P81/CLK0, P84/CTS1/RTS1, P85/CLK1 Data bus /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesOutput “1” (Note 2)Analog input
• Ports P70/AN0, P71/AN1, P76/AN6/XCOUT , P77/AN7/XCIN (Inside dotted-line not included) Ports P72/AN2/CTS2, P74/AN4/RxD2 (Inside dotted-line included) Analog input (Note 1) Sub-clock oscillation circuit Note 1: The sub-clock oscillation circuit is present only in ports P76 and P77 Note 2: Analog input is present only in port P73 “0” Data bus Port latch Port direction register Port latch Port direction register

7733 Group User’s Manual3–8

3.3 Pull-up function

3.3.1 Pull-up function for ports P54 to P57 (KI0 to KI3)

Ports P54 to P57 (KI0 to KI3) can be pulled high by setting the port P5 pull-up selection bit (bit 6 at address 6D 16). Figure 3.3.1 shows the structure of the port function control register. When pulling ports P54 to P57 high, clear bits 4 to 7 at address D16 (Port P5 direction register) to “0.”

3.3.2 Pull-up function for ports P62 to P64 (INT0 to INT2)

Ports P62 and P63 (INT0 and INT1) can be pulled high by setting the port P6 pull-up selection bit 0 (bit 3 ____ at address 6D16). Port P64 (INT2) can be pulled high by setting the port P6 pull-up selection bit 1 (bit 5 at address 6D16). Figure 3.3.1 shows the structure of the port function control register. When pulling ports P62 to P64 high, clear bits 2 to 4 at address 1016 (port P6 direction register) to “0.”

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Fig. 3.3.1 Structure of port function control register Bit Functions b7 b6 b5 b4 b3 b2 b1 b0 Port function control register (address 6D16) Bit name 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output.

0 Standby state selection bit

1 Sub-clock output selection bit/

Timer B2 clock source selection bit 0: No internal connection 1: Internal connection with timer B2

2 Timer B1 internal connect

3 Port P6 pull-up selection bit 0

0: No pull-up for pins P54/TA2OUT /KI0 to P57/TA3IN/KI3 1: With pull-up for pins P54/TA2OUT /KI0 to P57/TA3IN/KI3

6 Port P5 pull-up selection bit

7 Key input interrupt selection bit0: INT2 interrupt

1: Key input interrupt

5 Port P6 pull-up selection bit 1

4 Must be fixed to “0.” At reset RW RW RW RW0 RW0 RW0 RW0 RW0 RW0 0•Port-XC selection bit] = “0” (when the sub clock is not used) Timer B2 (event counter mode) clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer)

• Port-XC selection bit = “1” (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/f SUB functions as a programmable I/O port. 1: Sub clock f SUB is output from pin P67/TB2IN/f SUB . (Note 2) Notes 1: When the port-Xc selection bit = “0” and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is in v 2: When timer B1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 2, 4, and 7 are not used for the pull-up function.
• Key input interrupt selection bit = “0” 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2
• Key input interrupt selection bit = “1” 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 Port-Xc selection bit] : Bit 4 of the oscillation circuit control register 0 (address 6C16) and is used for the key input interrupt. valid.

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3.4 Internal peripheral devices’ I/O functions (Ports P42 and P5 to P8)

Ports P42 and P5 to P8 also function as I/O pins for the internal peripheral devices. Table 3.4.1 lists correspondence between each port and internal peripheral devices’ I/O pin. For internal peripheral devices’ I/O functions, refer to the corresponding functional description. For the clock φ 1 output pin, refer to chapter “12. CONNECTING EXTERNAL DEVICES.” For the sub-clock oscillation circuit’s I/O pins, refer to chapter “14. CLOCK GENERATING CIRCUIT.” Table 3.4.1 Correspondence between each port and internal peripheral devices’ I/O pin Port P4 2 P5 0 to P53 P5 4 to P57 P6 0, P61 P6 2 to P64 P6 5, P66 P6 7 P7 0, P71 P7 2 to P75 P7 6, P77 Internal peripheral devices’ I/O pin Clock φ 1 output pin Timer A’s I/O pins Timer A’s I/O pins/Key input interrupt function’s input pins Timer A’s I/O pins Input pins for external interrupts Timer B’s input pins Timer B’s input pin/Clock φ SUB output pin A-D converter’s input pins A-D converter’s input pins/I/O pins for serial I/O Sub-clock oscillation circuit’s I/O pins/A-D converter’s input pins I/O pins for serial I/O

4.1 Overview

4.2 Interrupt sources

4.3 Interrupt control

4.4 Interrupt priority level

4.5 Interrupt priority level

4.6 Interrupt priority level

4.7 How interrupts are processed (from acceptance of interrupt request till execution of interrupt routine)

4.8 Return from interrupt routine

4.9 Multiple interrupts

____

4.10 External interrupts (INTi

interrupt)

4.11 Precautions for interrupts

7733 Group User's Manual

4–2 Interrupt routineInterrupt request is accepted. Processing is resumed. Processing is suspended. Returns to original routine. RTI instruction Interrupt processing Routine in progress Branches to start address of interrupt routine. The 7733 Group provides 19 interrupt sources to generate interrupt requests. Figure 4.1.1 shows how interrupts are processed. When an interrupt request is accepted, a program branches to the start address of an interrupt routine which is set in the interrupt vector table (addresses FFD616 to FFFF16). Set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table. Fig. 4.1.1 How interrupts are processed

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h [S] is the initial address that the stack pointer (S) indicates when an interrupt request is accepted. S’s contents is “[S] – 5” after all of the above registers are pushed. Address [S] – 4 [S] – 3 [S] – 2 [S] – 1 [S] Processor status register’s low-order byte (PSL) Stack area [S] – 5 Processor status register’s high-order byte (PSH ) Program counter’s low-order byte (PCL) Program counter’s high-order byte (PCH ) Program bank register (PG) When an interrupt request is accepted, the following registers’ contents immediately before acceptance of an interrupt request are automatically pushed onto the stack area À , \ , and ´ in that order: À Program bank register (PG) \ Program counter (PCL, PCH ) ´ Processor status register (PSL, PSH ) Figure 4.1.2 shows the state of the stack area immediately before the program branches to an interrupt routine. At the end of the interrupt routine, execute the RTI instruction, which is an instruction for returning to the routine that was executed before acceptance of an interrupt request. By executing the RTI instruction, the above registers’ contents, which were pushed onto the stack area, are popped ´ , \` , and À in that order. Then, execution of the suspended routine is resumed from where it left off. When an interrupt request is accepted and the RTI instruction is executed, above registers (À to ´ ) are automatically pushed and popped. For other registers whose contents are necessary, be sure to push and pop them by software. Fig. 4.1.2 State of stack area immediately before program branches to interrupt routine

4–4 Low-order address 00FFFE 16 00FFFC 16 00FFFA 16 00FFF8 16 00FFF6 16 00FFF4 16 00FFF2 16 00FFF0 16 00FFEE 16 00FFEC 16 00FFEA 16 00FFE8 16 00FFE6 16 00FFE4 16 00FFE2 16 00FFE0 16 00FFDE 16 00FFDC 16 00FFDA 16 00FFD8 16 00FFD6 16 Remarks Non-maskable Non-maskable software interrupt Non-maskable software interrupt Not used usually Non-maskable interrupt External interrupt by signal input from pin INT0 External interrupt by signal input from pin INT1 External interrupt by signal input from pin INT2 or by key input Internal interrupt from Timer A0 Internal interrupt from Timer A1 Internal interrupt from Timer A2 Internal interrupt from Timer A3 Internal interrupt from Timer A4 Internal interrupt from Timer B0 Internal interrupt from Timer B1 Internal interrupt from Timer B2 Internal interrupt from UART0 Internal interrupt from UART1 Internal interrupt from A-D converter or UART2 Interrupt source Reset Zero division BRK instruction ____ DBC (Note 1) Watchdog timer INT0 INT1 INT2/Key input (Note 2) Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 reception UART0 transmission UART1 reception UART1 transmission A-D/UART2 trans./ /rece. (Note 3) High-order address 00FFFF 00FFFD 16 00FFFB 16 00FFF9 16 00FFF7 16 00FFF5 16 00FFF3 16 00FFF1 16 00FFEF 16 00FFED 16 00FFEB 16 00FFE9 16 00FFE7 16 00FFE5 16 00FFE3 16 00FFE1 16 00FFDF 16 00FFDD 16 00FFDB 16 00FFD9 16 00FFD7 16 Table 4.2.1 lists interrupt sources and their vector addresses. When programming, set the start address of each interrupt routine to the vector addresses listed below. Interrupt vector addresses Table 4.2.1 Interrupt sources and Interrupt vector addresses Notes 1: This is only for debugger control and is not used usually. 2: When the key input interrupt selection bit (bit 7 at address 6D16) = “1,” the key input interrupt function is selected. For details, refer to chapter “5 KEY INPUT INTERRUPT FUNCTION.” 3: The A-D conversion interrupt and the UART2 transmission/reception interrupt share the same interrupt vector addresses and interrupt control register. By setting the serial I/O mode selection bits (bits 0 to 2 at address 6416), the A-D conversion interrupt or UART2 transmission/reception interrupt is selected.

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Table 4.2.2 lists occurrence conditions of internal interrupt requests, which occur because of internal operations. Table 4.2.2 Occurrence conditions of internal interrupt requests Interrupt Zero division interrupt BRK instruction interrupt Watchdog timer interrupt Timer Ai interrupt (i = 0 to 4) Timer Bi interrupt (i = 0 to 2) UARTi reception interrupt (i = 0,1) UARTi transmission interrupt (i = 0,1) UART2 transmission /reception interrupt A-D conversion interrupt Occurrence conditions of interrupt requests Occurs when divider is “0” in execution of DIV instruction (Division instruction). (Refer to “7700 Family Software Manual.”) Occurs when the BRK instruction is executed. (Refer to “7700 Family Software Manual.”) Occurs when the most significant bit of the watchdog timer becomes “0.” (Refer to chapter “10 WATCHDOG TIMER.” ) Occurrence condition depends on Timer Ai’s operating modes. (Refer to chapter “6 TIMER A.” ) Occurrence condition depends on Timer Bi’s operating modes. (Refer to chapter “7 TIMER B.” ) Occurs at serial data reception. (Refer to chapter “8 SERIAL I/O.”) Occurs at serial data transmission. (Refer to chapter “8 SERIAL I/O.”) Occurs at serial data transmission/reception. (Refer to chapter “8 SERIAL I/O.”) Occurs when A-D conversion is completed. (Refer to chapter “9 A-D CONVERTER.” ) For external interrupts, refer to section “4.10 External interrupts.” For the key input interrupt, refer to chapter “5 KEY INPUT INTERRUPT FUNCTION.”

4–6 A-D/UART2 trans./rece. interrupt control register UART0 transmission interrupt control register UART0 receive interrupt control register UART1 transmission interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2/Key input interrupt control register Address 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 Maskable interrupts are enabled or disabled by setting the following: l Interrupt request bit l Interrupt priority level selection bits l Processor interrupt priority level (IPL) l Interrupt disable flag (I) The interrupt disable flag (I) and processor interrupt priority level (IPL) are allocated to the processor status register (PS). An interrupt request bit and the interrupt priority level selection bits are allocated to the interrupt control register for the corresponding interrupt. lMaskable interrupts : By software, acceptance of these interrupts’ requests can be disabled. l Non-maskable interrupts (Zero division, BRK instruction, and watchdog timer interrupts) : When an interrupt request occurs, it is certain to be accepted. They do not have interrupt control registers and are not affected by the interrupt disable flag (I). Fig. 4.3.1 Interrupt control registers’ memory map

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Fig. 4.3.2 Interrupt control registers’ structures INT0, INT1, and INT2/Key input interrupt control registers (addresses 7D16 to 7F16) b2b1b0 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 RW0 A-D/UART2 trans./rece., UART0 and 1 transmission, UART0 and 1 receive, Timers A0 to A4, Timers B0 to B2 interrupt control registers (addresses 7016 to 7C16) b7 b6 b5 b4 b3 b2 b1 b0 Bit Bit name Functions At reset RW b2b1b0 0 0 0 : Level 0 (Interrupt is disabled.) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 Not implemented. Interrupt priority level selection bits Interrupt request bit Un- defined 0: No interrupt request has occurred. 1: Interrupt request has occurred. 0: Interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1: Interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when level sense is selected. b7 b6 b5 b4 b3 b2 b1 b0 Bit Bit name Functions RW RW0 RW0 Interrupt priority level selection bits Interrupt request bit (Note) 0: No interrupt request has occurred. 1: Interrupt request has occurred. 0 RW Polarity selection bit Level sense/Edge sense selection bit 0: Edge sense 1: Level sense RW0 At reset Un- defined Not implemented. Note: The interrupt request bits of INT0 to INT2/Key input interrupts are ignored when the level sense is selected. RW RW RW RW RW RW

4–8

4.3.1 Interrupt disable flag (I)

This flag can disable all maskable interrupts. When this flag is set to “1,” all maskable interrupts are disabled; when this flag is cleared to “0,” all maskable interrupts are enabled. Because this flag is set to “1” at reset, clear this flag to “0” when enabling interrupts. This flag is allocated to the processor status register (PS).

4.3.2 Interrupt request bit

When an interrupt request occurs, this bit is set to “1.” And then, this bit remains set to “1” until the interrupt request is accepted; this bit is cleared to “0” when the interrupt request is accepted. This bit can be set to “1” or cleared to “0” by software, also. Note that when an INTi interrupt is used with the level sense selected, the INTi interrupt request bit (i = 0 to 2) is ignored.

4.3.3 Interrupt priority level selection bits and Processor interrupt priority level (IPL)

The interrupt priority level selection bits are used to set the priority level of an interrupt. When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (IPL). Only when the comparison result satisfies the following relationship, the interrupt request is enabled. Therefore, by setting the interrupt priority level to 0, the interrupt can be disabled. The processor interrupt priority level (IPL) is allocated to the processor status register (PS). Interrupt priority level > Processor interrupt priority level (IPL) contents and enabled interrupt priority levels. The interrupt disable flag (I), interrupt request bit, interrupt priority level selection bits, and processor interrupt priority level (IPL) are independent of each other; they do not affect each other. Interrupt requests are accepted only when the following conditions are satisfied. l Interrupt disable flag (I) = “0” l Interrupt request bit = “1” l Interrupt priority level > Processor interrupt priority level (IPL)

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Table 4.3.1 Settings of interrupt priority levels Interrupt priority level selection bits Interrupt priority level Low High IPL2 Enabled interrupt priority levels Level 1 and above levels Level 2 and above levels Level 3 and above levels Level 4 and above levels Level 5 and above levels Levels 6 and 7 Level 7 only All maskable interrupts are disabled. IPL1 IPL Table 4.3.2 Relationship between IPL’s contents and enabled interrupt priority levels IPL0: Bit 8 in the processor status register (PS) IPL1: Bit 9 in the processor status register (PS) IPL2: Bit 10 in the processor status register (PS) Level 0 (Interrupt is disabled.) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7

4–10 When the interrupt disable flag (I) = “0” (in other words, when interrupts are enabled), if multiple interrupt requests reside at the same sampling timing, where the presence of an interrupt request is checked, these requests are accepted in order of priority levels. In this case, an interrupt request which has the highest priority is accepted first. For 16 interrupt sources other than software interrupts (the zero division and BRK instruction) and a watchdog timer interrupt, an arbitrary priority level can be set by specifying the interrupt priority level selection bits. Note that the priority level for reset (handled as an interrupt which has the highest priority) or a watchdog timer interrupt is set by hardware. Figure 4.4.1 shows the interrupt priority level set by hardware. Note that software interrupts are not affected by the interrupt priority level. When the zero division or BRK instruction is executed, a program branches to an interrupt routine. Fig. 4.4.1 Interrupt priority level set by hardware Watchdog timer interrupt Reset Inside of dotted-line, an arbitrary priority level can be set. High LowInterrupt priority level 16 interrupt sources other than software interrupts and watchdog timer interrupt

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trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 IPL Processor interrupt priority level Interrupt with the highest priority Interrupt disable flag (I) Watchdog timer interrupt Reset Interrupt request is accepted. Interrupt priority level of each interrupt Level 0 (Initial value) Interrupt priority level of each interrupt

4.5 Interrupt priority level detection circuit

The interrupt priority level detection circuit is used to select an interrupt with the highest priority from multiple interrupts which reside at the same sampling timing. Figure 4.5.1 shows the interrupt priority level detection circuit. Fig. 4.5.1 Interrupt priority level detection circuit

4–12 Figure 4.5.2 shows the operation of the interrupt priority detection circuit. The interrupt priority level of a requested interrupt (“Y” in Figure 4.5.2) is compared with the priority level which is sent from the preceding comparator (“X” in Figure 4.5.2), and then the interrupt with the higher priority level is sent to the next comparator (“Z” in Figure 4.5.2). (Initial value of “X” is “0.”) For an interrupt which is not requested, the comparison is not performed and the priority level which is sent from the preceding comparator is forwarded to the next comparator as it is. After comparison, if the two priority levels are the same, the priority level which is sent from the preceding comparator is forwarded to the next comparator. Therefore, if the same priority is set by software, the interrupt priority levels are handled as follows: A-D conversion > UART2 transmission/reception > UART1 transmission > UART1 reception > UART0 transmission > UART0 reception > Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 > INT2/Key input > INT1 > INT0 By the above comparison, among the multiple interrupt requests which reside at the same sampling timing, one request with the highest priority level is detected. And then, the highest priority level detected by the above comparison is compared with the processor interrupt priority level (IPL). When this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable flag (I) = “0,” the corresponding interrupt request is accepted. An interrupt request which is not accepted at this time is held until it is accepted or the corresponding interrupt request bit is cleared to “0” by software (CLB instruction). The interrupt priority level is detected synchronously with the CPU’s op-code fetch cycle. However, when an op-code fetch cycle starts during the interrupt priority detection, a new interrupt priority detection does not start. (Refer to “Figure 4.6.1”) Because the interrupt request bit’s state and interrupt priority level are latched during interrupt priority detection, if they change, the interrupt priority detection is performed for the previous state before the change occurred. Fig. 4.5.2 Interrupt priority level detection model Y X Z Comparison of priority level l When X ‡ Y, Z = X l When X < Y, Z = Y Interrupt source Y X : Priority level which is sent from the preceding comparator (Highest priority at this time) Y : Priority level of interrupt source Y Z : Highest priority at this time Time Comparator

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(2) Interrupt priority level detection time Op-code fetch cycle Sampling pulse (a) 7 cycles (b) 4 cycles (c) 2 cycles Interrupt priority level detection time (Note) Note: This pulse resides when “2 cycles of ƒÓ ” is selected. b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 1 1 0 1 1 Processor mode register 0 (address 5E16) Processor mode bits Wait bit Software reset bit Must be fixed to “0.” Clock ƒÓ1 output selection bit 7 cycles of clock ƒÓ [(a) shown below] 4 cycles of clock ƒÓ [(b) shown below] 2 cycles of clock ƒÓ [(c) shown below] Interrupt priority detection time selection bits Do not select. (1) Interrupt priority detection time selection bits b5, b4

4.6 Interrupt priority level detection time

When the interrupt priority level detection time has passed after sampling starts, an interrupt request is accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the interrupt priority level detection time. Usually, select “2 cycles of φ” as the interrupt priority level detection time. Fig. 4.6.1 Interrupt priority level detection time

4–14 @ : Interrupt priority level detection time Interrupt request is generated. Interrupt request is accepted. Instruction Instruction INTACK sequence Instructions in interrupt routine Interrupt response time Time@ À Time from when an interrupt request occurs until the instruction execution which is in progress at that time is completed. \ Time from when execution of an instruction next to À begins (Note) until the instruction execution which is in progress at completion of interrupt priority level detection. Note : At this time, detection of interrupt priority level begins. ´ Time required to execute the INTACK sequence (13 cycles of ƒÓ at the shortest) À \ ´ until execution of interrupt routine) How interrupts are processed from accepting of an interrupt request until execution of the interrupt routine is described below. When an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt is cleared to “0.” And then, execution of an interrupt routine begins at the cycle immediately after the instruction execution which was in progress at acceptance of the interrupt request is completed. Figure 4.7.1 shows how interrupts are processed from acceptance of an interrupt request until execution of the interrupt routine. When the instruction execution which was in progress at acceptance of the interrupt request is completed, the INTACK (Interrupt acknowledge) sequence is executed and the program branches to the start address of the interrupt routine allocated in addresses 0 16 to FFFF16. In the INTACK sequence, the following procedure is automatically performed in this order. À The contents of the program bank register (PG) immediately before the INTACK sequence is pushed onto the stack. \` The contents of the program counter (PC) immediately before the INTACK sequence is pushed onto the stack. ´ The contents of the processor status register (PS) immediately before the INTACK sequence is pushed onto the stack. ˆ The interrupt disable flag (I) is set to “1.” ˜ The interrupt priority level of the accepted interrupt is set to IPL. ¯ The contents of the program bank register (PG) is cleared to “0016” and the contents of the interrupt vector address is set into the program counter (PC). The INTACK sequence requires at least 13 cycles of φ. Figure 4.7.2 shows the INTACK sequence’s timing. After the INTACK sequence is completed, the instruction execution begins at the start address of an interrupt routine.

4.7 How interrupts are processed

Fig. 4.7.1 How interrupts are processed from acceptance of interrupt request until execution of interrupt routine

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: CPU’s standard clock : High-order 8 bits of CPU address bus : Middle-order 8 bits of CPU address bus : Low-order 8 bits of CPU address bus : Data bus for CPU’s odd address : Data bus for CPU’s even address l When stack pointer (S)’s contens is even ƒÓCPU AP AH AL D H D L PG PC H 00 00 00 00 00 00 00 00 FF16 AD HPC H PS H PCLPG PS L AD H AD L PC L 00 55 16 D H AP AH Interrupt disable flag (I) ƒÓCPU D L AL AD L Op-code Op-code FF16 55 16 [S] 55 16 AD H AD L : Contents of stack pointer (S) : Low-order 8 bits of vector address : Contents of vector address (High-order address) : Contents of vector address (Low-order address) : Not used Fig. 4.7.2 INTACK sequence’s timing Table 4.7.1 Change in IPL at acceptance of interrupt request Change in IPL Level 0 (0002) is set. Level 7 (1112) is set. Not changed Not changed Accepted interrupt’s priority level is set. Interrupt source Reset Watchdog timer interrupt Zero division interrupt BRK instruction interrupt Other interrupts

4.7.1 Change in IPL at acceptance of interrupt request

When an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set to the processor interrupt priority level (IPL). This operation makes the processing for multiple interrupts easy. (Refer to section “4.9 Multiple interrupts.” At reset or when a watchdog timer interrupt or software interrupt is accepted, a value listed in Table 4.7.1 is set into IPL.

4–16 Pushed in 3 times ´ Pushes 16 bits at a time. À \` Pushes 16 bits at a time. (1) When stack pointer (S)’s contents is even Processor status register’s low-order byte (PS L ) Processor status register’s high-order byte (PS H ) Program counter’s low-order byte (PCL ) Program counter’s high-order byte (PCH ) Program bank register (PG) Address S–4 (even) S–3 (odd) S–2 (even) S–1 (odd) S (even) Order for pushS–5 (odd) Processor status register’s low-order byte (PS L ) Processor status register’s high-order byte (PS H ) Program counter’s low-order byte (PCL) Program counter’s high-order byte (PCH ) Program bank register (PG) Address S–4 (odd) S–3 (even) S–2 (odd) S–1 (even) S (odd) À ˆ (2) Stack Pointer (S)’s contents is odd Pushes by the 8 bits. Order for push Pushed in 5 times S–5 (even) h “S” is the initial address that the stack pointer (S) indicates when an interrupt request is accepted. S’s contents is “S–5” after the above registers are pushed.

4.7.2 How to push registers

The way to push registers depends on whether the stack pointer (S)’s contents at interrupt request acceptance is even or odd. When the stack pointer (S)’s contents is even, each of the program counter (PC)’s contents and processor status register (PS)’s contents is simultaneously pushed by the 16 bits. When the stack pointer (S)’s contents is odd, each of these registers is pushed by the 8 bits. Figure 4.7.3 shows how the registers are pushed. In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and processor status register (PS) are pushed onto the stack area. Make sure to push other necessary registers by software at the beginning of an interrupt routine. By executing the PSH instruction, all CPU registers other than the stack pointer can be pushed. Fig. 4.7.3. How registers are pushed

7733 Group User's Manual 4–17

When the RTI instruction is executed at the end of an interrupt routine, the contents of the program bank register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack area immediately before the INTACK sequence are automatically pulled. And then, a program returns to the original routine and the suspended process is resumed. Before the RTI instruction is executed, by executing the PUL instruction or others, make sure to pull registers which were pushed by software in an interrupt routine. Make sure that the data length and register length for the pull operation are equal to those for the push operation. When a program branches to an interrupt routine, the following occurs: l Interrupt disable flag (I) = “1” (Interrupts are disabled.) l Interrupt request bit of accepted interrupt = “0” l Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt Therefore, as long as the IPL remains unchanged, by clearing the interrupt disable flag (I) to “0” in an interrupt routine, an interrupt request whose priority level is higher than the priority level of the interrupt which is in progress can be accepted. In this way, multiple interrupts are processed. Figure 4.9.1 shows how multiple interrupts are processed. An interrupt request which is not accepted because its priority level is lower is held. When the RTI instruction is executed, the interrupt priority level of the routine which was in progress at acceptance of an interrupt request is pulled to the IPL. Therefore, if the following relationship is satisfied when interrupt priority level detection is performed next, the held interrupt request is accepted. Held interrupt request’s priority level > Processor interrupt priority level (IPL) which is pulled 4.8 Return from interrupt routine, 4.9 Multiple interrupts

4–18 Main routineReset I = 1 IPL = 0 I = 0 Interrupt 1 I = 1 IPL = 3 I = 0 I = 1 IPL = 5 RTI I = 0 IPL = 3 RTI I = 0 IPL = 0 I = 1 IPL = 2 RTI I = 0 IPL = 0 Interrupt 1 Interrupt priority level = 3 Cannot be accepted because its priority level is low. Interrupt request generated Nesting Time : Automatically be set. : Must be set by software. I : Interrupt disable flag IPL : Processor interrupt priority level Multiple interruptsInterrupt 2 Interrupt priority level = 5 Interrupt 3 Interrupt priority level = 2 Interrupt 2 Interrupt 3 Interrupt 3 Instruction in main routine is not executed. Fig. 4.9.1 How multiple interrupts are processed

7733 Group User's Manual 4–19

____

4.10 External interrupts (INTi interrupt)

____ An external interrupt request occurs by input signal from pin INTi (i = 0 to 2). The occurrence condition of an external interrupt request can be selected by the level sense/edge sense selection bit and the polarity ____ occurrence condition of INTi interrupt request. When using pins P62/INT0 to P64/INT2 as external interrupt input pins, set their corresponding bits at address 1016 (Port P6 direction register) to “0.” (Refer to “Figure 4.10.1.”) These pins can be pulled high by software. (Refer to section “3.3 Pull-up function of P62 to P64 pins (INT0 to INT2).” ____ The INT2 interrupt is invalid when the key input interrupt selection bit (bit 7 at address 6D16) = “1.” (Refer ____ to chapter “5 KEY INPUT INTERRUPT FUNCTION.” ) When using the INT2 interrupt function, clear the key input interrupt selection bit to “0.” ____ A signal which is input to pin INTi requires a “H”/“L”-level duration of 250 ns or more independent of the system clock frequency (Note 1). Note that even when pins P62/INT0 to P64/INT2 are used as external interrupt input pins, these pins’ state can be read in by reading bits 2 to 4 at address E16 (Port P6 register). Note 1: When the falling edge or “L” level is selected as the interrupt occurrence condition, make sure that “L”-level duration must be at least 250 ns: when the rising edge or “H” level is selected as the interrupt occurrence condition, make sure that “H”-level duration must be at least 250 ns. ____ ____ Table 4.10.1 Occurrence condition of INTi interrupt request b5 (Note 2) b4 (Note 2) Note 2: “b5” and “b4” represent bits 5 and 4 of the INT0 to INT2/key input interrupt control register. (Refer to “Figure 4.10.2.”) In an INTi interrupt, pin INTi’s state is always checked, and then an interrupt request is generated according to the state. Therefore, when an INTi interrupt is not used, clear the INTi interrupt’s priority level to “0.” ____ INTi interrupt request occurrence condition ____ Occurs at the falling edge of an input signal to pin INTi (Edge sense). ____ Occurs at the rising edge of an input signal to pin INTi (Edge sense). ____ Occurs when pin INTi is at “H” level (Level sense). ____ Occurs when pin INTi is at “L” level (Level sense).

4–20 ____ Fig. 4.10.1 Correspondence between port P6 direction register and input pins for external interrupts Fig. 4.10.2 INT0 to INT2 interrupt control register’s structure Bit

7 Pin TB2IN

6 Pin TB1IN

5 Pin TB0IN

4 Pin INT2/Key input

3 Pin INT1

2 Pin INT0

1 Pin TA4IN

0 Pin TA4OUT

Port P6 direction register (address 1016) 0 : Input mode 1 : Output mode When using a pin as an input pin for an external interrupt, clear the corresponding bit to “0.” represents that bits 0, 1 and bits 5 to 7 are not used for external interrupts. RW RW RW RW RW RW RW Corresponding pin’s name INT0, INT1, and INT2/Key input interrupt control registers (addresses 7D16 to 7F16) b2b1b0 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 RW0 0: Interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1: Interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when level sense is selected. b7 b6 b5 b4 b3 b2 b1 b0 Bit Bit name Functions RW RW0 RW0 Interrupt priority level selection bits Interrupt request bit (Note) 0: No interrupt request has occurred. 1: Interrupt request has occurred. 0 RW polarity selection bit Level sense/Edge sense selection bit 0: Edge sense 1: Level sense RW0 At reset Un- defined Not implemented. Note: The interrupt request bits of INT0 to INT2/Key input interrupts are ignored when the level sense is selected. RW RW

7733 Group User's Manual 4–21

____

4.10.1 INTi interrupt request bit’s function

(1) Functions when edge sense is selected By clearing the level sense/edge sense selection bit to “0,” the edge sense is selected. (Refer to Figure 4.10.3.) The interrupt request bit has the same functions as those for the interrupt request bit of internal interrupts. When an interrupt occurs, the interrupt request bit is set to “1” and retains this state until the interrupt request is accepted. When the interrupt request bit is cleared to “0” by software, an interrupt request is cancelled; when the interrupt request bit is set to “1” by software, an interrupt request can be generated. (2) Functions when level sense is selected By setting the level sense/edge sense selection bit to “1,” the level sense is selected. (Refer to Figure 4.10.3.) ____ The interrupt request bit is ignored. In this case, interrupt requests occur sequentially while pin INTi ____ is at the valid level] 1; when pin INTi’s level changes to the invalid level] 2 with the interrupt request not accepted, the interrupt request is not held. (Refer to Figure 4.10.4.) Valid level] 1: The level selected by the polarity selection bit (bit 4 at addresses 7D16 to 7F16) Invalid level] 2: The reverse level to “valid level” ____ ____ Fig. 4.10.3 INTi Interrupt request ____ Fig. 4.10.4 Re-occurrence of INTi interrupt request when level sense is selected Pin INTi Edge detection circuit Interrupt request Level sense/Edge sense selection bit“0” “1” Data bus Interrupt request bit Level sense Edge sense 1st interrupt routine Pin INTi’s level Valid Invalid Main routine Interrupt request is accepted. Return to main routine 2nd interrupt routine 3rd interrupt routine Main routine

4–22 ____

4.10.2 How to switch INTi interrupt request occurrence condition

____ The way to switch the INTi interrupt request occurrence condition from the level sense to the edge sense is shown in Figure 4.10.5 (1). The way to switch the polarity is shown in Figure 4.10.5 (2). ____ ____ Fig. 4.10.5 How to switch INTi interrupt request occurrence condition Set interrupt priority level to 0. ( INTi interrupt is disabled. ) Clear the level sense/edge sense selection bit to “0.” ( Edge sense selected ) Clear the interrupt request bit to “0.” Set the interrupt priority level to one of levels 1 to 7. ( INTi interrupt request is acceptable. ) Clear the interrupt request bit to “0.” Set interrupt priority level to 0. ( INTi interrupt is disabled. ) Set the polarity selection bit. Set the interrupt priority level to one of levels 1 to 7. ( INTi interrupt request is acceptable. ) (2) How to switch the polarity(1) How to switch the INTi interrupt request occurrence condition from level sense to edge sense

7733 Group User's Manual 4–23

; The write instruction for the interrupt priority level selection bits ; The NOP instruction is inserted (Note) ; The write instruction for the interrupt priority level selection bits Note: Other instructions whose cycle number corresponds to that of the NOP instruction (other than the write instructions for address 7X 16) can be inserted. For number of the NOP instructions which are to be inserted, refer to Table 4.11.1. LDM .B #0XH, 007XH NOP NOP NOP LDM .B #0XH, 007XH When the contents of the interrupt priority level selection bits (bits 0 to 2 at addresses 7016 to 7F16) is changed, 2 to 7 cycles of φ are required. Therefore, when the interrupt priority level of the same interrupt source is changed twice or more in a very short time, which consists of a few instructions, it is necessary to secure the required time by software. Figure 4.11.1 shows an program example to secure the time required for the change of an interrupt priority level. Note that the time required for the change depends on the contents of the interrupt priority level selection bits (bits 4 and 5 at address 5E16). Table 4.11.1 lists the correspondence between the number of instructions inserted in a program example and the interrupt priority level selection bits. (Refer to Figure 4.11.1, also.) Table 4.11.1 Correspondence between number of instructions to be inserted in Figure 4.11.1 and interrupt priority detection time selection bits Interrupt priority detection time selection bits (Note) Time required for change of interrupt priority level Number of inserted NOP instruction 7 cycles of φ 4 cycles of φ 2 cycles of φ 4 or more 2 or more 1 or more Set as follows, if possible: Fig. 4.11.1 Program example to secure time required for change of interrupt priority level Do not select.

4–24

5.1 Overview

5.2 Block description

5.3 Initial setting example for

KEY INPUT INTERRUPT FUNCTION

7733 Group User’s Manual5–2

The key input interrupt function is used to generate an interrupt request when one of the input levels of four or five pins falls. By using this function when terminating the stop or wait mode, the key-on wakeup can be realized. For the way to terminate the stop or wait mode, refer to section “17.4 Power saving.” For the stop and wait modes, refer to chapter “11. STOP AND WAIT MODES.” A key input interrupt request occurs when one of the input levels of pins KI0 to KI3 falls. Therefore, by configuring an external key matrix shown in Figure 5.1.1, an interrupt request can be generated only by pushing a key. Pins KI0 to KI3 can be pulled high by software and the same function can also be selected for port P64. Therefore, when using the key input interrupt function, whether to use four pins (pins KI0 to KI3) or five pins (pins KI0 to KI3 and P64) can be selected. ____ The key input interrupt and the INT2 interrupt share the same interrupt vector addresses and interrupt control register. Fig. 5.1.1 Key matrix example when key input interrupt function is used

KEY INPUT INTERRUPT FUNCTION

7733 Group User’s Manual 5–3

Port P5 direction register (address D16)000 0 b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (address 1016)0 0: Must be set to “0.” 0: Must be set to “0.” INT2/Key input interrupt control register Interrupt control register P64/INT2 P57/KI3 P55/KI1 P56/KI2 P54/KI0 INT2/Key input interrupt request Key input interrupt selection bit (address 7F16) When key input interrupt is selected, it is necessary to select edge sense which uses falling edge. Pull–up transistor Port P5 pull-up selection bit Port P57 direction register Pull–up transistor Pull–up transistor Pull–up transistor Port P6 pull-up selection bit 1 Port P64 direction register Port P6 pull-up selection bit 1 Figure 5.2.1 shows the block diagram for the key input interrupt function. Fig. 5.2.1 Block diagram for key input interrupt function

5.2.1 Pins KI0 to KI3 and P64/INT2

When the key input interrupt function is selected, pins P54 to P57 become input pins for the key input interrupt (KI0 to KI3). When selecting the key input interrupt function, clear all of bits 4 to 7 at address D16 (Port P5 direction register) to “0.” When bits 4 to 7 at address B16 (Port P5 register) are read out, the status of pins KI0 to KI3 can be read ____ in. When using pin P64/INT2 as an input pin for the key input interrupt, set both of bits 5 and 7 at address 6D 16 to “1” and bit 4 at address 1016 (Port P6 direction register) to “0.” When bit 4 at address E616 (Port ____ P6 register) is read out, the status of pin P64/INT2 can be read in. Fig. 5.2.2 Port P5 and P6 direction registers when key input interrupt function is selected

KEY INPUT INTERRUPT FUNCTION

7733 Group User’s Manual5–4

Port function control register (address 6D16) Bit name 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. Timer B2 clock source selection bit 0: No internal connection 1: Internal connection with timer B2 0: No pull-up for pins P54/TA2OUT /KI0 to P57/TA3IN/KI3 1: With pull-up for pins P54/TA2OUT /KI0 to P57/TA3IN/KI3 1: Key input interrupt 4 Must be fixed to “0.” At reset RW RW RW RW0 RW0 RW0 RW0 RW0 RW0 0•Port-XC selection bit] = “0” (when the sub clock is not used) Timer B2 (event counter mode) clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer)

• Port-XC selection bit = “1” (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/ f SUB functions as a programmable I/O port. 1: Sub clock f SUB is output from pin P67/TB2IN/f SUB . (Note 2) Notes 1: When the port-Xc selection bit = “0” and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 4 are not used for the key input interrupt function.
• Key input interrupt selection bit = “0” 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2
• Key input interrupt selection bit = “1” 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up and is used for the key input interrupt. 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 Port-Xc selection bit] : Bit 4 of the oscillation circuit control register 0 (address 6C16)

5.2.2 Port function control register

Figure 5.2.3 shows the structure of the port function control register. Fig. 5.2.3 Structure of port function control register

KEY INPUT INTERRUPT FUNCTION

7733 Group User’s Manual 5–5

(1) Port P6 pull-up selection bit (bit 5) ____ When using pin P64/INT2 as an input pin for the key input interrupt, set this bit to “1.” When this bit ____ is set to “1,” pin P64/INT2 is pulled high. (2) Port P5 pull-up selection bit (bit 6) This is a bit to pull pins KI0 to KI3 high. When configuring a key matrix, there is no need to connect pull-up transistors externally if this bit is set to “1,” in other words, if pins KI0 to KI3 are set to be pulled high. (3) Key input interrupt selection bit (bit 7) This is a bit to select the key input interrupt function. ____ The key input interrupt and the INT2 interrupt share the same interrupt vector addresses and interrupt control register. When this bit is set to “1,” the key input interrupt function is selected. When this bit ____ = “1” and bit 5 (Port P6 pull-up selection bit) = “0,” pin P64/INT2 is a programmable I/O port. (At this ____ time, the INT2 interrupt cannot be used.) When both of this bit and bit 5 (Port P6 pull-up selection bit ____ 1) are “1,” pin P64/INT2 can be used for the key input interrupt.

KEY INPUT INTERRUPT FUNCTION

7733 Group User’s Manual5–6

INT2/key input interrupt control register (address 7F16) Bit 4 Must be fixed to “0.”

3 Interrupt request bit

0 Interrupt priority level selection

0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 b2 b1 b0 0: No interrupt request has occurred. 1: Interrupt request has occurred. 6 Not implemented. Undefined RW RW RW RW RW RW

5.2.3 Interrupt function

____ The key input interrupt and the INT2 interrupt share the same interrupt vector addresses and interrupt ____ control register. Specify addresses FFF016 and FFF116 (in other words, the vector addresses for the INT2/ ____ key input interrupt) as the interrupt vector addresses; specify the INT2/key input interrupt control register ____ (address 7F16) as the interrupt control register. Figure 5.2.4 shows the structure of the INT2/key input interrupt control register when the key input interrupt function is selected. ____ The operation at accepting a key input interrupt request is the same as that at accepting an INT2 interrupt request. ____ Fig. 5.2.4 Structure of INT2/key input interrupt control register when key input interrupt function is selected

KEY INPUT INTERRUPT FUNCTION

7733 Group User’s Manual 5–7

Setting of interrupt priority level INT2/Key input interrupt control register (address 7F16) 000 Interrupt priority level selection bits One of levels 1 to 7 must be set. Interrupt request bit h In order to enable the key input interrupt, the interrupt disable flag (I) must be set to “0” and the processor interrupt priority level (IPL) must be a value smaller than the INT2/key input interrupt’s priority level. (Refer to chapter “4. INTERRUPTS.”) Selection of the key input interrupt function Selection of the key input interrupt function Pull-up selection for pins KI0 to KI3 Port function control register (address 6D16) 0: No pull-up 1: Pull-up Port P5 pull-up selection bit 0: Port P64 is a programmable I/O port with no pull-up. 1: Port P64 is an input pin with pull-up and is used for the key input interrupt. Port P6 pull-up selection bit 1 Setting of port P5 and P6 direction registers b7 b0 Port P5 direction register (address D16) P54 to P57 are set to the input mode. (Must be set to “0000.”) 0000 b7 b0 Port P6 direction register (address 1016) When setting P64 as an input pin for the key input interrupt, set this bit to “0.”

5.3 Initial setting example for related registers

Figure 5.3.1 shows an initial setting example for registers related to the key input interrupt function. Fig. 5.3.1 Initial setting example for registers related to key input interrupt function

KEY INPUT INTERRUPT FUNCTION

7733 Group User’s Manual5–8

6.1 Overview

6.2 Block description

6.3 Timer mode

6.4 Event counter mode

6.5 One-shot pulse mode

6.6 Pulse width modulation

(PWM) mode

7733 Group User’s Manual6–2

Timer A is used mainly for output to the external. It consists of five counters (Timers A0 to A4), and each has a 16-bit reload function. Timers A0 to A4 operate independently of each other. Timer Ai (i = 0 to 4) has four operating modes listed below. Except for the event counter mode, timers A0 to A4 all have the same functions. n Timer mode Timer A counts a count source internally generated, and the following functions can be used: l Gate function l Pulse output function n Event counter mode Timer A counts an external signal, and the following functions can be used: l Free-run count function (Timers A2, A3, and A4) l Pulse output function l Two-phase pulse signal processing function (Timers A2, A3, and A4) n One-shot pulse mode Timer A outputs a pulse which has an arbitrary width once. n Pulse width modulation (PWM) mode Timer A outputs pulses which have an arbitrary width in succession and functions as one of the following pulse width modulators: l 16-bit pulse width modulator l 8-bit pulse width modulator

7733 Group User’s Manual 6–3

Figure 6.2.1 shows the timer A block diagram. Registers related to timer A are described below. Fig. 6.2.1 Timer A block diagram Data bus (Odd) Data bus (Even) f 2 f 16 f 64 f 512 Clock source selection

• Timer mode
• One-shot pulse mode
• PWM mode Polarity switching Timer mode (Gate function) Event counter mode External trigger Count start flag Countdown Up-down flag (Low-order 8 bits) (High-order 8 bits) Timer Ai reload register (16) Timer Ai counter (16) Timer Ai interrupt request bit Countup/Countdown switching “Countdown” is selected when not in the event counter mode. Toggle F.F. Pulse output function selection bit TAiIN (i = 0 to 4) TAiOUT (i = 0 to 4) Clocks f2,f16,f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” (address 4016 ) (address 4416 ) TimerA0 4716 4616 4916 4816 TimerA2 4B16 4A16 TimerA3 4D16 4C16 TimerA4 4F16 4E16 addresses

7733 Group User’s Manual6–4

Timer Ai register High-order byte Low-order byte Timer A0 register Address 4716 Address 4616 Timer A1 register Address 4916 Address 4816 Timer A2 register Address 4B16 Address 4A16 Timer A3 register Address 4D16 Address 4C16 Timer A4 register Address 4F16 Address 4E16

6.2.1 Counter and reload register (Timer Ai register)

Each of timer Ai counter and its reload register consists of 16 bits. The counter performs countdown each time a count source is input. In the event counter mode, it can also function as an up-counter. The reload register is used to memorize the initial value of a counter. When an underflow/overflow occurs in the counter, the reload register’s contents is reloaded into the counter. However, when the free-run count function is used, the reload register’s contents is not reloaded into the counter. Values are set to the counter and reload register by writing the values to the timer Ai register. Table 6.2.1 lists the memory allocation of the timer Ai register. A value written into the timer Ai register while counting is stopped is set to the counter and reload register. A value written into the timer Ai register while counting is in progress is set only to the reload register. In this case, the reload register’s updated contents is transferred to the counter at the next reload time. A value obtained by reading out the timer Ai register depends on the operating mode. Table 6.2.2 lists reading and writing from and to the timer Ai register. Table 6.2.1 Memory allocation of timer Ai register Table 6.2.2 Reading and writing from and to timer Ai register Write <While counting is in progress> Written only to the reload register. <While counting is stopped> Written to both of the counter and reload register. Note: At reset, the contents of the timer Ai register is undefined. Operating mode Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode Read Counter value is read out. (Note 1) Undefined value is read out. Notes 1: Also refer to “Precautions in timer mode” and “Precautions in event counter mode.” 2: Perform reading or writing by the 16 bits.

7733 Group User’s Manual 6–5

6.2.2 Count start flag

This register is used to start or stop counting. Each bit of this register corresponds to each timer, respectively. Figure 6.2.2 shows the structure of the count start flag. Fig. 6.2.2 Structure of count start flag Bit

7 Timer B2 count start flag

6 Timer B1 count start flag

5 Timer B0 count start flag

4 Timer A4 count start flag

3 Timer A3 count start flag

2 Timer A2 count start flag

1 Timer A1 count start flag

0 Timer A0 count start flag

Count start flag (address 4016) 0: Counting is stopped. 1: Counting is started. represents that bits 7 to 5 are not used for timer A. RW RW RW RW RW RW RW RW

7733 Group User’s Manual6–6

6.2.3 Timer Ai mode register

Figure 6.2.3 shows the structure of the timer Ai mode register. The operating mode selection bits are used to select an operating mode of timer Ai. Bits 7 to 2 have different functions according to the operating mode. These bits are described in a section of each operating mode. Fig. 6.2.3 Structure of timer Ai mode register Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) 0 0: Timer mode 0 1: Event counter mode 1 0: One-shot pulse mode 1 1: Pulse width modulation (PWM) mode b1 b0 2 These bits have different functions according to the operating mode.

0 Operating mode selection bits

7733 Group User’s Manual 6–7

6.2.4 Timer Ai interrupt control register

Figure 6.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to chapter “4. INTERRUPTS.” Fig. 6.2.4 Structure of timer Ai interrupt control register (1) Interrupt priority level selection bits (bits 2 to 0) These bits select a timer Ai interrupt’s priority level. When using timer Ai interrupts, select one priority level from levels 1 to 7. If a timer Ai interrupt request is generated, its priority level is compared with the processor interrupt priority level (IPL), and then the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this is applied when the interrupt disable flag (I) = “0.”) When disabling timer Ai interrupts, set these bits to “0002” (Level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when a timer Ai interrupt request is generated. This bit is automatically cleared to “0” when the timer Ai interrupt request is accepted. This bit can be set to “1” or cleared to “0” by software. Bit Not implemented.

0 Interrupt priority level

0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 Priority is low. 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Priority is high. b2 b1 b0 0: No interrupt request has occurred. 1: Interrupt request has occurred. 7 to 4 b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai interrupt control register (i = 0 to 4) (addresses 7516 to 7916) RW RW RW RW

7733 Group User’s Manual6–8

6.2.5 Port P5 and port P6 direction registers

I/O pins of timers A0 to A3 are multiplexed with port P5, and I/O pins of timer A4 are multiplexed with port P6. When using these pins as timer Ai’s input pins, set the corresponding bits of the port P5 and port P6 direction registers to “0” in order to set these ports for the input mode. When using these pins as timer Ai’s output pins, these pins are forcibly set to output pins of timer Ai independent of the direction registers’ contents. Figure 6.2.5 shows the relationship between the port P5 and port P6 direction registers and the timer Ai’s I/O pins. Fig. 6.2.5 Relationship between port P5 and port P6 direction registers and timer Ai’s I/O pins Bit Corresponding pin name Functions Pin P50/TA0OUT Pin P52/TA1OUT Pin P53/TA1IN Pin P54/TA2OUT Pin P56/TA3OUT 0: Input mode 1: Output mode When using these pins as timer Ai’s input pins, set the corresponding bits to “0.” Pin P55/TA2IN Port P5 direction register (address D16) b1 b0b2b3b4b5b6b7 Pin P51/TA0IN Pin P57/TA3IN At resetRW Pin P60/TA4OUT Pin P62/INT0 Pin P63/INT1 Pin P64/INT2 Pin P66/TB1IN Pin P65/TB0IN Port P6 direction register (address 1016) b1 b0b2b3b4b5b6b7 Pin P61/TA4IN Pin P67/TB2IN/f SUB RW represents that bits 2 to 7 are not used for timer A. Corresponding pin name FunctionsBit At reset 0: Input mode 1: Output mode When using these pins as timer Ai’s input pins, set the corresponding bits to “0.” RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

7733 Group User’s Manual 6–9

6.3 Timer mode (Bits 1 and 0 of timer Ai mode register = “002”)

structures of the timer Ai mode register and timer Ai register in the timer mode. Table 6.3.1 Specifications of timer mode Interrupt request occurrence timing Pin TAi IN’s function Pin TAiOUT ’s function Read from timer Write to timer Specifications Clock f2, f16, f64, or f512 l Countdown l At an underflow, the reload register’s contents is reloaded, and counting is continued. When the count start flag is set to “1.” When the count start flag is cleared to “0.” At an underflow Programmable I/O port or gate input Programmable I/O port or pulse output A counter value can be read out by reading the timer Ai register. n While counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. n While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload time.) (n + 1) n: Set value in the timer Ai register Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

7733 Group User’s Manual6–10

Fig. 6.3.1 Structures of timer Ai mode register and timer Ai register in timer mode Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

3 Gate function selection bits

2 Pulse output function

0 Operating mode selection

Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) 0 0: Timer mode 0: No pulse is output. (Pin TAiOUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TAiOUT functions as a pulse output pin.) 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b66 Count source selection bits b1 b0 b4 b3 5 Must be fixed to “0” in the timer mode. 00 0

0 X: No gate function

(Pin TAiIN functions as a programmable I/O port.) 1 0: Counter counts only while pin TAiIN’s input signal level is “L.” 1 1: Counter counts only while pin TAiIN’s input signal level is “H.” Bit At reset RW b7 b0 b7 b0 (b15) (b8) Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Undefined RW RW RW RW RW RW RW RW RW

7733 Group User’s Manual 6–11

6.3.1 Setting for timer mode

Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter “4. INTERRUPTS.” Fig. 6.3.2 Initial setting example for registers related to timer mode (1) h Counter divides the count source frequency by (n + 1). b7 b0 Pulse output function selection bit 0: No pulse is output. 1: Pulse is output. 000 Selection of the timer mode and each function Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) X: It may be either “0” or “1.” Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” b7 b6 b4 b3 Gate function selection bits 1 0: Counter counts only while pin TAiIN’s input signal level is “L.” 1 1: Counter counts only while pin TAiIN’s input signal level is “H.” Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Timer mode is selected. Setting of the division ratio b7 b0 Values 000016 to FFFF16 (n) can be set. (b15) (b8) b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Continued to “Initial setting example for registers related to timer mode (2)” on the next page

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Fig. 6.3.3 Initial setting example for registers related to timer mode (2) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Counting is started. Setting of the count start flag to “1.” b7 b0 Count start flag (address 4016) Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Setting of the interrupt priority level b7 b0 Timer Ai interrupt control register (addresses 7516 to 7916) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Continued from “Initial setting example for registers related to timer mode (1)” on the preceding page Setting of the port P5 and port P6 direction registers b7 b0 Port P5 direction register (address D16) Pin TA0IN Pin TA1IN Pin TA2IN b7 b0 Port P6 direction register (address 1016) When the gate function is selected, set the bit corresponding to pin TAiIN to “0.” Pin TA4IN Pin TA3IN

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6.3.2 Count source

In the timer mode, by the count source selection bits (bits 6 and 7 at addresses 5616 to 5A16), a count source can be selected. Table 6.3.2 lists the relationship between the count source selection bits and count source. Table 6.3.2 Relationship between count source selection bits and count source When system clock = 25 MHz When system clock = 16 MHz When system clock = 8 MHz Clocks f2, f16, f64, f512, and system clock: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = “0” and the main clock division selection bit (bit 0 at address 6F16) = “0.” (For details, refer to chapter “14. CLOCK GENERATING CIRCUIT.”)

12.5 MHz

1.5625 MHz

390.625 kHz 48.8281 kHz

8 MHz

1 MHz

31.25 kHz

4 MHz

15.625 kHz

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6.3.3 Operation in timer mode

À When the count start flag is set to “1,” the counter starts counting of the count source. \ When an underflow occurs, the reload register’s contents is reloaded, and then counting is continued. ´ The timer Ai interrupt request bit is set to “1” when the underflow occurs in \ . After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 6.3.4 shows an operation example in the timer mode. Fig. 6.3.4 Operation example in timer mode (without pulse output and gate functions) Counting is stopped. Counting is restarted. FFFF 16 n 000016 Time Count start flag Timer Ai interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software Counting is started. Set to “1” by software “0” “0” 1 / fi 5 (n + 1) fi = Frequency of count source (f2, f16, f64, f512) Cleared to “0” by software

7733 Group User’s Manual 6–15

6.3.4 Selectable functions

The gate and pulse output functions are described below. (1) Gate function The gate function is selected by setting the gate function selection bits (bits 4 and 3 at addresses 5616 to 5A16) to “102” or “112.” When the gate function is selected, counting can be started or stopped by example when the gate function is selected. When selecting the gate function, set the port P5 and port P6 direction registers’ bits which correspond to pin TAi IN for the input mode. Also make sure that pin TAiIN’s input signal has a pulse width equal to or greater than two cycles of the count source. Table 6.3.3 Count valid levels Count valid level (Duration of counting) While pin TAiIN’s input signal level is “L” While pin TAiIN’s input signal level is “H” Note: The counter does not count while pin TAiIN’s input signal is not at the count valid level. Gate function selection bits

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Fig. 6.3.5 Operation example when gate function is selected FFFF 16 n 000016 Time Count start flag Timer Ai interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Pin TAiIN’s input signal Count valid level \ Counting is stopped. À Counting is started. “0” “0” À Counting is performed while the count start flag = “1” and pin TAiIN’s input signal is at the count valid level. \ Counter stops counting while pin TAiIN’s input signal is not at the count valid level, and counter value is retained. Set to “1” by software

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(2) Pulse output function The pulse output function is selected by setting the pulse output function selection bit (bit 2 at addresses 5616 to 5A16) to “1.” When this function is selected, pin TAiOUT is forcibly set as the pulse output pin independent of the corresponding bits of the port P5 and port P6 direction registers. And then, pin TAiOUT outputs the signal of which polarity is inverted each time an underflow occurs. When the count start flag (address 4016) = “0,” in other words, when counting is stopped, pin TAiOUT outputs “L” level. Figure 6.3.6 shows an operation example when the pulse output function is selected. Fig. 6.3.6 Operation example when pulse output function is selected Counting is stopped. Counting is restarted. FFFF 16 n 000016 Time Count start flag Pulse output from pin TAiOUT “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software Counting is started. “0” Timer Ai interrupt request bit “1” “0” Set to “1” by software “1” “0” Cleared to “0” by software

7733 Group User’s Manual6–18

[Precautions in timer mode] While counting is in progress, by reading out the timer Ai register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 6.3.7, value “FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. Fig. 6.3.7 Timer Ai register read out 210 n n – 1Counter value (Hex.)

210 FFFF n – 1Read value

(Hex.) Reload Timen = Reload register’s contents

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6.4 Event counter mode (Bits 1 and 0 of timer Ai mode register = “012”)

the structures of the timer Ai mode register and timer Ai register in the event counter mode. Table 6.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing function) l External signal input to pin TAiIN l “Falling edge” or “Rising edge” can be selected as the valid edge of the count source by software. l “Countup” or “countdown” can be selected by the external signal or software l At an overflow or underflow, the reload register’s contents is reloaded, and counting is continued (Note). Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing Pin TAi IN’s function Pin TAiOUT ’s function Read from timer Write to timer When the count start flag is set to “1.” When the count start flag is cleared to “0.” At an overflow or underflow Count source input Programmable I/O port, pulse output, or countup/countdown switch signal input A counter value can be read out by reading the timer Ai register. n While counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. n While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload time.) < While counting up> < While counting down> (n + 1) (FFFF 16 – n + 1) n: Set value in the timer Ai register Note:This is applied when not using the free-run count function.

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Interrupt request occurrence timing Pin TAjIN, TAjOUT ’s (j = 2 to 4) function Read from timer Write to timer Table 6.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function in timers A2, A3, and A4) Specifications External signal (two-phase pulse) input to pin TAjIN or TAjOUT (j = 2 to 4) l “Countup” or “countdown” can be selected by the external signal (two-phase pulse). l At an overflow or underflow, the reload register’s contents is reloaded, and counting is continued. (Note) When the count start flag is set to “1.” When the count start flag is cleared to “0.” At an overflow or underflow Two-phase pulse input A counter value can be read out by reading the timer A2, A3, or A4 register. n While counting is stopped When a value is written to the timer A2, A3, or A4 register, it is written to both of the reload register and counter. n While counting is in progress When a value is written to the timer A2, A3, or A4 register, it is written only to the reload register. (Transferred to the counter at the next reload time.) < While counting up> < While counting down> (n + 1) (FFFF 16 – n + 1) n: Set value in the timer Aj register Note:This is applied when not using the free-run count function.

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Fig. 6.4.1 Structures of timer A0 and A1 mode registers and timer A0 and A1 registers in event counter mode Timer A0 mode register (address 5616) Timer A1 mode register (address 5716) b7 b6 b5 b4 b3 b2 b1 b0 5 00 1 Bit

4 Up-down switching factor

3 Count polarity selection bit

6 These bits are ignored in the event counter mode. 5 Must be fixed to “0” in the event counter mode. Functions 0: Counts at falling edge of external signal 1: Counts at rising edge of external signal 0: Contents of the up-down flag 1: A signal which is input to pin TA0OUT or TA1OUT At reset RW 0: No pulse is output. (Pin TA0OUT or TA1OUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TA0OUT or TA1OUT functions as a pulse output pin.) 0 1: Event counter mode b1 b0 b7 b0 b7 b0 (b15) (b8) Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) RW 15 to 0Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (FFFF16 – n + 1) in up- counting. At reading this register, the counter value is read out. Undefined Bit Functions At reset RW RW RW RW RW RW RW RW RW

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Fig. 6.4.2 Structures of timer A2, A3, and A4 mode registers and timer A2, A3, and A4 registers in event counter mode b7 b6 b5 b4 b3 b2 b1 b0 Timer A2 mode register (address 5816) Timer A3 mode register (address 5916) Timer A4 mode register (address 5A16) 00 1 Bit

6 Count type selection bit

5 Must be fixed to “0” in the event counter mode. Note: This bit is valid only for the timer A3 mode register. For the timer A2 and A4 mode registers, this bit is ignored. (It may be “0” or “1.”)

7 Two-phase pulse signal

bit (Note) Functions 0 1: Event counter mode b1 b0 0: Contents of the up-down flag 1: A signal which is input to pin TA2OUT , TA3OUT , or TA4OUT At reset RW 0: No pulse is output. (Pin TA2OUT , TA3OUT , or TA4OUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TA2OUT , TA3OUT , or TA4OUT functions as a pulse output pin.)

3 Count polarity selection bit0: Counting is performed at the falling edge of

the external signal. 1: Counting is performed at the rising edge of the external signal. 0: Reload count type 1: Free-run count type 0: Normal processing 1: Quadruple processing b7 b0 b7 b0 (b15) (b8) FunctionsBit At reset RW 15 to 0Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (FFFF16 – n + 1) in up-counting. At reading this register, the counter value is read out. Undefined Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) RW RW RW RW RW RW RW RW RW

7733 Group User’s Manual 6–23

6.4.1 Setting for event counter mode

Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter “4. INTERRUPTS.” Fig. 6.4.3 Initial setting example for registers related to event counter mode (1) h Counter divides the count source frequency by (n + 1) while counting down or by (FFFF16 – n + 1) while counting up. Setting of the up-down flag b7 b0 Timer A0 up-down flag Continued to “Initial setting example for registers related to event counter mode (2)” on the next page b7 b0 Two-phase pulse signal processing type selection bit (Valid only for i = 3) 0: Normal processing 1: Quadruple processing 010 Selection of the event counter mode and each function Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Pulse output function selection bit 0: No pulse is output. 1: Pulse is output. Count polarity selection bit 0: Counts at falling edge of external signal. 1: Counts at rising edge of external signal. Up-down switching factor selection bit 0: Contents of the up-down flag 1: Input signal to pin TAiOUT Count type selection bit (Valid only for i = 2 to 4) 0: Reload count type 1: Free-run count type Event counter mode is selected. Setting of the division ratio b7 b0 Values 000016 to FFFF16 (n) can be set. (b15) (b8) b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Up-down flag (address 4416)

• When up-down flag is selected as up-down switching factor, set corresponding up-down flag. 0: Countdown 1: Countup
• Selection of the two-phase pulse signal processing function Set the corresponding bit to “1.” 0: Two-phase pulse signal processing function is disabled. 1: Two-phase pulse signal processing function is enabled. Timer A1 up-down flag Timer A2 up-down flag Timer A3 up-down flag Timer A4 up-down flag Timer A2 two-phase pulse signal processing selection bit Timer A3 two-phase pulse signal processing selection bit Timer A4 two-phase pulse signal processing selection bit

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Fig. 6.4.4 Initial setting example for registers related to event counter mode (2) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Counting is started. Setting of the count start flag to “1” b7 b0 Count start flag (address 4016) Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Continued from “Initial setting example for registers related to event counter mode (1)” on the preceding page Timer A3 count start flag Timer A4 count start flag Setting of the port P5 and port P6 direction registers b7 b0 Port P5 direction register (address D16) Pin TA0OUT Pin TA0IN Pin TA1OUT Pin TA1IN b7 b0 Port P6 direction register (address 1016) Pin TA4OUT Set a bit corresponding to pin TAiIN to “0.” When the two-phase pulse signal processing function is selected, or when pin TAiOUT ’s input signal is selected as the up-down switching factor, set a bit corresponding to pin TAiOUT to “0.” Pin TA2OUT Pin TA2IN Pin TA3OUT Pin TA3IN Pin TA4IN Setting of the interrupt priority level b7 b0 Timer Ai interrupt control register (addresses 75 16 to 7916) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set.

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6.4.2 Operation in event counter mode

À When the count start flag is set to “1,” the counter starts counting of the count source. \` The counter counts the count source’s valid edges. ´ When an underflow or overflow occurs, the reload register’s contents is reloaded, and then counting is continued. ˆ The timer Ai interrupt request bit is set to “1” when the underflow or overflow occurs in ´ . After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 6.4.5 shows an operation example in the event counter mode. Fig. 6.4.5 Operation example in event counter mode (without free-run count function, pulse output function, and two-phase pulse signal processing function) Timer Ai interrupt request bit FFFF 16 n 000016 Time Count start flag “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software Counting is started. Up-down flag“1” h The above is applied when the up-down flag’s content is selected as the up-down switching factor (i.e., up-down switching factor selection bit = “0”). “0” “0” “0” Set to “1” by software

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(1) Switching between countup and countdown A register named “up-down flag” (address 4416) or pin TAiOUT ’s input signal switches countup from and to countdown. This switching is performed by an up-down flag when the up-down switching factor selection bit (bit 4 at addresses 5616 to 5A16) = “0” and by pin TAiOUT ’s input signal when the up-down switching factor selection bit = “1.” When the switching between countup and countdown is set while counting is in progress, this switching is realized at the next valid edge of the count source. n When switching by up-down flag Countdown is performed when the up-down flag = “0,” and countup is performed when the up-down flag = “1.” Figure 6.4.6 shows the structure of the up-down flag. n When switching by pin TAiOUT ’s input signal Countdown is performed when pin TAiOUT ’s input signal level is “L” and countup is performed when it is “H.” When switching countup from and to countdown by pin TAiOUT ’s input signal, set a port P5 or P6 direction register’s bit which corresponds to pin TAiOUT for the input mode. Fig. 6.4.6 Structure of up-down flag Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Up-down flag (address 4416)

4 Timer A4 up-down flag

3 Timer A3 up-down flag

2 Timer A2 up-down flag

1 Timer A1 up-down flag

0 Timer A0 up-down flag

5 Timer A2 two-phase pulse signal

6 Timer A3 two-phase pulse signal

7 Timer A4 two-phase pulse signal

0: Countdown 1: Countup This bits is valid when the contents of the up-down flag is selected as the up-down switching factor. 0: Two-phase pulse signal processing function is disabled. 1: Two-phase pulse signal processing function is enabled. When not using the two-phase pulse signal processing function, be sure to set this bit to “0.” This bit is “0” at reading. RW RW RW RW RW WO WO WO Note: When writing to bits 5 to 7, use the LDM or STA instruction.

7733 Group User’s Manual 6–27

6.4.3 Selectable functions

The free-run count, pulse output, and two-phase pulse signal processing functions are described below. (1) Free-run count function (Timers A2 to A4) For timers A2 to A4, when the count type selection bit (bit 6 at addresses 5816 to 5A16) is set to “1,” the free-run count function is selected. When the free-run count function is selected, although a timer A2/A3/A4 interrupt request is generated at an overflow or underflow, the reload register’s contents is not reloaded into the counter. Figure 6.4.7 shows an operation example when the free-run count function is selected. Fig. 6.4.7 Operation example when free-run count function is selected (without pulse output function and two-phase pulse signal processing function) FFFF 16 n 000016 Time Count start flag Timer A2/A3/A4 interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software Counting is started. Up-down flag“1” “0” “0” “0” h The above is applied when the up-down flag’s contents is selected as the up-down switching factor (i.e., up-down switching factor selection bit = “0”). Set to “1” by software À After an underflow, counter starts counting from FFFF16. \` After an overflow, counter starts counting from 000016. À

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(2) Pulse output function The pulse output function is selected by setting the pulse output function selection bit (bit 2 at addresses 5616 to 5A16) to “1.” When this function is selected, pin TAiOUT is forcibly set as the pulse output pin independent of the corresponding bit of the port P5 or port P6 direction register. And then, pin TAiOUT outputs a signal of which polarity is inverted each time an underflow or overflow occurs (Refer to Figure 6.3.6). When the count start flag (address 4016) = “0,” in other words, when counting is stopped, pin TAiOUT outputs “L” level. (3) Two-phase pulse signal processing function (Timers A2 to A4) For timers A2 to A4, the two-phase pulse signal processing function is selected by setting the two- phase pulse signal processing selection bits (bits 5 to 7 at address 4416) to “1.” (Refer to Figure processing function is selected. In a timer with the two-phase pulse signal processing function selected, two kinds of pulses of which phases differ by 90 degrees are counted. There are two types of the two-phase pulse signal processing: normal processing and quadruple processing. In timer A2, normal processing is performed; in timer A4, quadruple processing is performed. In timer A3, either normal processing or quadruple processing can be selected by the two-phase pulse signal processing type selection bit (bit 7 at address 59 16). Some bits of the port P5 and P6 direction registers correspond to pins used for the two-phase pulse input. Set these bits for the input mode. 100 0 0 1 Timer A2 mode register (address 5816) Timer A3 mode register (address 5916) Timer A4 mode register (address 5A16) 0: Reload count type 1: Free-run count type b7 b6 b5 b4 b3 b2 b1 b0 h h : Bit 7 of the timer A3 mode register is used to select the two-phase pulse signal processing type of timer A3. Normal processing is selected when this bit = “0,” and quadruple processing is selected when this bit = “1.” Bit 7 of the timer A2/A4 mode register is ignored. (It may be “0” or “1.”) Fig. 6.4.8 Timer A2, A3, and A4 mode registers when two-phase pulse signal processing function is selected

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Countup is performed at the rising edges of pin TAkIN (k = 2 and 3) if the phase relationship is such that pin TAkIN’s input signal level changes from “L” to “H” while pin TAkOUT ’s input signal level is “H.” Countdown is performed at the falling edges of pin TAkIN if the phase relationship is such that pin TAk IN’s input signal level changes from “H” to “L” while pin TAkOUT ’s input signal level is “H.” (Refer to Figure 6.4.9.) Fig. 6.4.9 Normal processing n Quadruple processing Countup is performed at the rising and falling edges of pins TAIOUT (l = 3 and 4) and TAIIN if the phase relationship is such that pin TAIIN’s input signal level changes from “L” to “H” while pin TAIOUT ’s input signal level is “H.” Countdown is performed at the rising and falling edges of pins TAIOUT and TAIIN if the phase relationship is such that pin TAIIN’s input signal level changes from “H” to “L” while pin TAIOUT ’s input signal level is “H.” (Refer to Figure 6.4.10.) Table 6.4.3 lists input signals of pins TAIOUT and TAIIN when the quadruple processing is selected. Fig. 6.4.10 Quadruple processing TAlOUT TAlIN (l = 3, 4) “H” “H” “L” “L” Counted up at all edges Counted down at all edges Counted up at all edges Counted down at all edges TAkOUT TAkIN (k = 2, 3) “H” “H” “L” +1 +1 +1 –1 –1 –1 Counted down “L” Counted up Counted up Counted up Counted down Counted down

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Table 6.4.3 Pin TAIOUT and TAIIN’s input signals when quadruple processing is selected “L” level “H” level Falling edge Rising edge “H” level “L” level Input signal of pin TAIOUT “H” level “L” level Rising edge Falling edge “H” level “L” level Rising edge Falling edge

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[Precautions in event counter mode] 1. While counting is in progress, by reading out the timer Ai register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 6.4.11, value “FFFF16” is read out at an underflow and value “000016” is read out at an overflow. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. Fig. 6.4.11 Timer Ai register read out 2. Pin TAiOUT is used for all functions listed below. Therefore, only one of the following functions can be used for one timer. l Switching between countup and countdown by pin TAiOUT ’s input signal l Pulse output function l Two-phase pulse signal processing function (Timers A2 to A4) 210 n n – 1 Counter value (Hex.)

210 FFFF n – 1

(Hex.) Reload Time n = Reload register’s contents (1) While counting down FFFD FFFE FFFF n n + 1 FFFD FFFE FFFF 0000 n + 1 (2) While counting up Counter value (Hex.) Read value (Hex.) Reload Time n = Reload register’s contents

7733 Group User’s Manual6–32

6.5 One-shot pulse mode (Bits 1 and 0 of timer Ai mode register = “102”)

In this mode, a pulse which has an arbitrary width is output once. (Refer to Table 6.5.1.) After a trigger occurs, “H” level is output from pin TAiOUT for an arbitrary time. Figure 6.5.1 shows the structures of the timer Ai mode register and timer Ai register in the one-shot pulse mode. Table 6.5.1 Specifications of one-shot pulse mode Output pulse width (“H”) Count start condition Count stop condition Interrupt request occurrence timing Pin TAi IN’s function Pin TAiOUT ’s function Read from timer Write to timer Specifications Clock f2, f16, f64, or f512 l Countdown l When the counter value reaches “000016,” the reload register’s contents is reloaded, and counting stops. l When a trigger occurs while counting is in progress, the reload register’s contents is reloaded, and counting is continued. n fi n: Set value in the timer Ai register l When a trigger occurs. (Note ) l Internal or external trigger can be selected by software. l When the counter value reaches “0000 16.” l When the count start flag is cleared to “0.” When counting stops. Programmable I/O port or trigger input One-shot pulse output An undefined value is read out by reading the timer Ai register. n While counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. n While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload time.) [s] Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: A trigger occurs when the count start flag = “1.”

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Fig. 6.5.1 Structures of timer Ai mode register and timer Ai register in one-shot pulse mode b7 b0 b7 b0 (b15) (b8) Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, “H” level width of the one-shot pulse output from pin TAiOUT is n/fi. Undefined fi: Frequency of the count source (f2, f16, f64, or f512)

3 Trigger selection bits

2 Must be fixed to “1” in the one-shot pulse mode. Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) 1 0: One-shot pulse mode 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b6

6 Count source selection bits

5 Must be fixed to “0” in the one-shot pulse mode. 10 1 Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

0 X: Writing “1” to the one-shot start flag (Pin

TAiIN functions as a programmable I/O @ @@ port.) 1 0: Falling edge of the pin TAiIN’s input signal 1 1: Rising edge of the pin TAiIN’s input signal Bit At reset RW RW RW RW RW RW RW RW RW WO

7733 Group User’s Manual6–34

6.5.1 Setting for one-shot pulse mode

Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter “4. INTERRUPTS.” Fig. 6.5.2 Initial setting example for registers related to one-shot pulse mode (1) Continued to “Initial setting example for registers related to one-shot pulse mode (2)” on the next page Setting of the interrupt priority level b7 b0 Timer Ai interrupt control register (addresses 7516 to 7916) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. b7 b0 100 Selection of the one-shot pulse mode and each function Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16)1 b4 b3 Trigger selection bits

0 X: Writing “1” to the one-shot start flag: Internal trigger

1 0: Falling edge of pin TAiIN’s input signal: External trigger 1 1: Rising edge of pin TAiIN’s input signal: External trigger b7 b6 Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 X: It may be “0” or “1.” Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” One-shot pulse mode is selected. Setting of the one-shot pulse’s “H” level width b7 b0 Values 000016 to FFFF16 (n) can be set. (b15) (b8) b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) h “H” level width = n/fi fi = Frequency of the count source (f2, f16, f64, or f512) However, if n = 000016, the counter does not operate and pin TAiOUT outputs “L” level. At this time, no timer Ai interrupt request is generated.

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Fig. 6.5.3 Initial setting example for registers related to one-shot pulse mode (2) Counting is started. Trigger is generated. Trigger input to pin TAiIN When the internal trigger is selected When the external trigger is selected Continued from “Initial setting example for registers related to one-shot pulse mode (1)” on the preceding page b7 b0 One-shot start flag (address 4216) Setting of one-shot start flag to “1” Timer A0 one-shot start flag Setting of count start flag to “1” b7 b0 Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Count start flag (address 4016) b7 b0 Port P5 direction register (address D16) Setting of port P5 and port P6 direction registers Pin TA0IN Pin TA1IN Pin TA2IN Pin TA3IN Port P6 direction register (address 1016) Pin TA4IN b7 b0 Clear the corresponding bit to “0.” Setting of count start flag to “1” b7 b0 Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Count start flag (address 4016 ) Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag

7733 Group User’s Manual6–36

6.5.2 Count source

In the one-shot pulse mode, by the count source selection bits (bits 7 and 6 at addresses 5616 to 5A16), a count source can be selected. Table 6.5.2 lists the relationship between the count source selection bits and count source. Table 6.5.2 Relationship between count source selection bits and count source When system clock = 25 MHz When system clock = 16 MHz When system clock = 8 MHz Clocks f2, f16, f64, f512, and system clock: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = “0” and the main clock division selection bit (bit 0 at address 6F16) = “0.” (For details, refer to chapter “14. CLOCK GENERATING CIRCUIT.” ) 390.625 kHz 48.8281 kHz 31.25 kHz 15.625 kHz

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6.5.3 Trigger

The counter enters the count enable state when the count start flag (address 4016) is set to “1.” And then, the counter starts counting when a trigger occurs. An internal or external trigger can be selected as this trigger. An internal trigger is selected when the trigger selection bits (bits 4 and 3 at addresses 5616 to 5A16) are “002” or “012”; an external trigger is selected when the trigger selection bits are “102” or “112.” When a trigger occurs during counting, the reload register’s contents is reloaded and the counter continues counting. When generating a trigger during counting, make sure that a certain time which is equivalent to two cycles of the timer’s count source or more has passed between the trigger previously generated and a new trigger. (1) When internal trigger is selected A trigger is generated when the one-shot start flag (address 4216) is set to “1.” Figure 6.5.4 shows the structure of the one-shot start flag. (2) When external trigger is selected A trigger is generated at the falling edge of pin TAiIN’s input signal when bit 3 at addresses 5616 to 5A 16 = “0” or at the rising edge of pin TAiIN’s input signal when bit 3 = “1.” When using an external trigger, set the port P5 or P6 direction register’s bit which corresponds to pin TAiIN’s for the input mode. Fig. 6.5.4 Structure of one-shot start flag Bit 7 to 5 Not implemented.

4 Timer A4 one-shot start flag

3 Timer A3 one-shot start flag

2 Timer A2 one-shot start flag

1 Timer A1 one-shot start flag

0 Timer A0 one-shot start flag

One-shot start flag (address 4216) 1: One-shot pulse output is started. (Valid when the internal trigger is selected). “0” at reading. WO WO WO WO WO

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6.5.4 Operation in one-shot pulse mode

À When the one-shot pulse mode is selected by the operating mode selection bits, pin TAiOUT outputs “L” level. \ When the count start flag is set to “1,” the counter enters the count enable state, and then it starts counting if a trigger occurs. ´ When the counter starts counting, pin TAiOUT ’s output level becomes “H.” (However, if value “000016” is set in the timer Ai register, the counter does not operate and the output level of pin TAiOUT remains “L.” Nor is a timer Ai interrupt request generated.) ˆ When the counter value reaches “000016,” the output level of pin TAiOUT becomes “L.” And then, the reload register’s contents is reloaded, and the counter stops counting. ˜ Simultaneously with ˆ , a timer Ai interrupt request bit is set to “1.” After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 6.5.5 shows an operation example in the one-shot pulse mode. When a trigger occurs after ˆ above, the counter and pin TAi OUT perform the same operations beginning from \ again. When a trigger occurs during counting, the counter down-counts once after this new trigger occurs. And then, the reload register’s contents is reloaded and counting is continued. When generating a trigger during counting, make sure that a certain time which is equivalent to two cycles of the timer’s count source or more has passed between the trigger previously generated and a new trigger. The one-shot pulse output from pin TAiOUT can be disabled by clearing the timer Ai mode register’s bit 2 to “0.” Therefore, timer Ai can be used as an internal one-shot timer that does not output the pulse. (In this case, pin TAiOUT functions as a programmable I/O port.)

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Fig. 6.5.5 Operation example in one-shot pulse mode (when external trigger selected) Counting is stopped. Counting is started. FFFF 16 n 000116 Time À Count start flag Timer Ai interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software Counting is started. Pin TAiIN’s input signal “H” One-shot pulse output from pin TAiOUT “H” \ Trigger during counting 1 / fi 5 (n) h The above is applied when an external trigger (Rising edge of pin TAiIN’s input signal) is selected. “0” “L” “L” “0” 1 / fi 5 (n + 1) À When the count start flag = “0,” in other words, when counting is stopped, pin TAiOUT outputs “L” level. \ When a trigger occurs during counting, the counter counts the count source (n + 1) times after a new trigger occurs. fi = Frequency of count source (f2,f16,f64,f512) Counting is stopped. Reloaded Reloaded

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[Precautions in one-shot pulse mode] 1. When the count start flag is cleared to “0” during counting, the followings are performed.

• The counter stops counting, and the reload register’s contents is reloaded.
• Pin TAiOUT ’s output level becomes “L.”
• An interrupt request is generated, and a timer Ai interrupt request bit is set to “1.” 2. A one-shot pulse is output synchronously with an internally generated count source. Therefore, when an external trigger is selected, in the period from when a trigger is input to pin TAiIN until a one-shot pulse is output, there will be a delay equivalent to one cycle of the count source at maximum.

Fig. 6.5.6 Delay in one-shot pulse output 3. When a timer’s operating mode is set by the procedure listed below, a timer Ai interrupt request bit is set to “1.” l When the one-shot pulse mode is selected after reset l When the operating mode is switched from the timer mode to the one-shot pulse mode l When the operating mode is switched from the event counter mode to the one-shot pulse mode Therefore, when using a timer Ai interrupt (Interrupt request bit), be sure to clear the timer Ai interrupt request bit to “0” after setting the above. h The above is applied when an external trigger (Falling edge of pin TAiIN’s input signal) is selected. Pin TAiIN’s input signal “H” “L” Count source Trigger input One-shot pulse output is started. One-shot pulse output from pin TAiOUT

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6.6 Pulse width modulation (PWM) mode (Bits 1 and 0 of timer Ai mode register = “112”)

In this mode, a pulse which has an arbitrary width is output in succession. (Refer to Table 6.6.1.) Figure 6.6.1 shows the structures of the timer Ai mode register and timer Ai register in the PWM mode. Table 6.6.1 Specifications of PWM mode

6.6 Pulse width modulation (PWM) mode

Clock f2, f16, f64, or f512 l Countdown (Operates as an 8-bit or 16-bit pulse width modulator) l Reload register’s contents is reloaded at the rising edge of PWM pulse, and counting is continued. l A trigger generated during counting does not affect the counting. PWM period and “H” level width 216 – 1 fi Period = [s] “H” level width =K fi [s] <8-bit pulse width modulator> <16-bit pulse width modulator> (m + 1)(28 – 1) fi Period = “H” level width =n(m + 1) fi [s] [s] K: Set value in the timer Ai register m: Set value in the low-order 8 bits of the timer Ai register n: Set value in the high-order 8 bits of the timer Ai register Count start condition Count stop condition Interrupt request occurrence timing Pin TAiIN’s function Pin TAiOUT ’s function Read from timer Write to timer l When a trigger occurs. l Internal or external trigger can be selected by software. When the count start flag is cleared to “0.” At the falling edge of PWM pulse Programmable I/O port or trigger input PWM pulse output An undefined value is read out by reading the timer Ai register. n While counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. n While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

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Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b6 Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” At reset RW 2 Must be fixed to “1” in the PWM mode. 1 1: PWM mode b1 b0 b4 b3 5 16/8-bit PWM mode selection bit

0 X: Writing “1” to the count start flag (Pin TAiIN

functions as a programmable I/O port.) 1 0: Falling edge of the pin TAiIN’s input signal 1 1: Rising edge of the pin TAiIN’s input signal Bit 0: The counter operates as a 16-bit pulse width modulator. 1: The counter operates as an 8-bit pulse width modulator. n When operating as an 8-bit pulse width modulator (b15) b7 b0 b7 b0 (b8) Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) FunctionsBit At reset RW 7 to 0 Values 0016 to FF16 can be set. Assuming that the set value = m, period of the PWM pulse which is output from pin TAiOUT is (m + 1)(28 – 1)/fi. fi: Frequency of the count source (f2, f16, f64, or f512) 15 to 8Values 0016 to FE16 can be set. Assuming that the set value = n, “H” level width of the PWM pulse which is output from pin TAiOUT is n(m +1)/fi. Un- defined Un- defined b7 b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0Values 000016 to FFFE16 can be set. Assuming that the set value = n, “H” level width of the PWM pulse which is output from pin TAiOUT is n/fi. Un- defined fi: Frequency of the count source (f2, f16, f64, or f512) n When operating as a 16-bit pulse width modulator (b15) (b8) RW RW RW RW RW RW RW RW WO WO WO Fig. 6.6.1 Structures of timer Ai mode register and timer Ai register in PWM mode

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6.6.1 Setting for PWM mode

Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter “4. INTERRUPTS.” Fig. 6.6.2 Initial setting example for registers related to PWM mode (1) b7 b0 Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Selection of PWM mode and each function Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) b7 b6 16/8-bit PWM mode selection bit 0: The counter operates as 16-bit pulse width modulator. 1: The counter operates as 8-bit pulse width modulator. Continued to “Initial setting example for registers related to PWM mode (2)” on the next page Trigger selection bits

0 X: Writing “1” to the count start flag: Internal trigger

1 0: Falling edge of pin TAiIN’s input signal: External trigger 1 1: Rising edge of pin TAiIN’s input signal: External trigger b4 b3 X: It may be “0” or “1.” Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” PWM mode selected Setting of PWM pulse’s period and “H” level width b7 b0 Values 000016 to FFFE16 (n) can be set. (b15) (b8) b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) h When operating as a 16-bit pulse width modulator Period = (216 – 1)/fi fi: Frequency of the count source (f2, f16, f64, or f512) However, if n = 000016, the pulse width modulator does not operate and pin TAiOUT outputs “L” level. At this time, no timer Ai interrupt request is generated. n When operating as a 16-bit pulse width modulator b7 b0 Values 0016 to FF16 (m) can be set. (b15) (b8) b7 b0 n When operating as an 8-bit pulse width modulator Values 0016 to FE16 (n) can be set. h When operating as an 8-bit pulse width modulator Period = (m+1) (28 – 1)/fi “H” level width = n(m + 1)/fi fi: Frequency of the count source (f2, f16, f64, or f512) However, if n = 0016, the pulse width modulator does not operate and pin TAiOUT outputs “L” level. At this time, no timer Ai interrupt request is generated. Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16)

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Fig. 6.6.3 Initial setting example for registers related to PWM mode (2) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Counting is started. Trigger input to pin TAiIN When the external trigger is selected When the internal trigger is selected Continued from “Initial setting example for registers related to PWM mode (1)” on the preceding page Trigger is generated. b7 b0 Port P5 direction register (address D 16) Setting of the port P5 and port P6 direction registers Pin TA0IN Pin TA1IN Pin TA2IN Pin TA3IN Pin TA4IN b7 b0 Clear the corresponding bit to “0.” Port P6 direction register (address 10 16) Setting of the interrupt priority level b7 b0 Timer Ai interrupt control register (addresses 75 16 to 7916) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the count start flag to “1” b7 b0 Count start flag (address 4016) Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer A0 count start flag Setting of the count start flag to “1” b7 b0 Count start flag (address 4016) Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer A0 count start flag

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6.6.2 Count source

In the PWM mode, by the count source selection bits (bits 7 and 6 at addresses 5616 to 5A16), a count source can be selected. Table 6.6.2 lists the relationship between the count source selection bits and count source. Table 6.6.2 Relationship between count source selection bits and count source When system clock = 25 MHz When system clock = 16 MHz When system clock = 8 MHz Count source f16 f64 f512 Clocks f2, f16, f64, f512, and system clock: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = “0” and the main clock division selection bit (bit 0 at address 6F16) = “0.” (For details, refer to chapter “14. CLOCK GENERATING CIRCUIT.” ) 390.625 kHz 48.8281 kHz 31.25 kHz 15.625 kHz

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6.6.3 Trigger

When a trigger occurs, pin TAiOUT starts the PWM pulse output. An internal or external trigger can be selected as this trigger. An internal trigger is selected when the trigger selection bits (bits 4 and 3 at addresses 5616 to 5A16) are “002” or “012”; an external trigger is selected when the trigger selection bits are “102” or “112.” A trigger generated during PWM pulse output is invalid and does not affect the pulse output operation. (1) When internal trigger is selected A trigger is generated when the count start flag (address 4016) is set to “1.” (2) When external trigger is selected A trigger is generated at the falling edge of the pin TAiIN’s input signal when bit 3 at addresses 5616 to 5A16 = “0” or at the rising edge of the pin TAiIN’s input signal when bit 3 = “1.” However, a trigger input is accepted only when the count start flag = “1.” When using an external trigger, set the port P5 or P6 direction register’s bit which corresponds to pin TAiIN for the input mode.

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6.6.4 Operation in PWM mode

À When the PWM mode is selected by the operating mode selection bits, pin TAiOUT outputs “L” level. \` When a trigger occurs, the counter (Pulse width modulator) starts counting and pin TAiOUT outputs a PWM pulse ( Notes 1 and 2). ´ A timer Ai interrupt request bit is set to “1” each time the PWM pulse level changes from “H” to “L.” After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. ˆ Each time a PWM pulse is output for one period, the reload register’s contents is reloaded and counting is continued. Operation of the pulse width modulator is described below. [16-bit pulse width modulator] When the 16/8-bit PWM mode selection bit is set to “0,” the counter operates as a 16-bit pulse width [8-bit pulse width modulator] When the 16/8-bit PWM mode selection bit is set to “1,” the counter is divided into 8-bit halves. Then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit Notes 1: If a value of “0000 16” is set in the timer Ai register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output level of pin TAiOUT remains “L.” Nor is a timer Ai interrupt request generated. These operations are also applied to the case where a value of “0016” is set in high-order 8 bits of the timer Ai register when the counter operates as an 8-bit pulse width modulator. 2: When the counter operates as an 8-bit pulse width modulator, after a trigger occurs, pin TAiOUT outputs “L” level of which width is the same as the PWM pulse’s “H” level width which was set. And then, pin TAi OUT starts the PWM pulse output.

7733 Group User’s Manual6–48

Fig. 6.6.4 Operation example of 16-bit pulse width modulator Fig. 6.6.5 Operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 1 / fi 5 (216 – 1) 1 / fi 5 (n) Count source Pin TAiIN’s input signal PWM pulse output from pin TAiOUT h The above is applied when the reload register = 000316 and an external trigger (Rising edge of pin TAiIN’s input signal) is selected. Trigger is not generated by this signal. “H” “H” “L” “L” Timer Ai interrupt request bit “1” “0” Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software fi: Frequency of the count source (f2, f16, f64, or f512) PWM pulse output from pin TAiOUT À When an arbitrary value is reset to the timer Ai register after value “000016” is set to it, the rising timing of PWM pulse depends on this reset timing. h The above is applied when an external trigger (Rising edge of pin TAiIN’s input signal) is selected. FFFE 16 n 000116 Pin TAiIN’s input signal “H” Counter contents (Hex.) “L” “H” “L” (216 – 1) – n À Value “000016” is set to the timer Ai register. Value “200016” is set to the timer Ai register. 200016 Value “FFFE16” is set to the timer Ai register. n = Reload register’s contents fi: Frequency of the count source (f2, f16, f64, or f512) Counting is restarted. Counting is stopped. Time

7733 Group User’s Manual 6–49

Fig. 6.6.6 Operation example of 8-bit pulse width modulator À Count source Pin TAiIN’s input signal PWM pulse output from pin TAiOUT h The above is applied when the following conditions are satisfied:

• Reload register’s high-order 8 bits = “0216”
• Reload register’s low-order 8 bits = “0216”
• When an external trigger (Falling edge of pin TAiIN’s input signal) is selected. “H” “H” “H” “L” “L” “L” “1” “0” Timer Ai interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software fi: Frequency of the count source (f2, f16, f64, or f512) À 8-bit prescaler counts the count source. \ 8-bit pulse width modulator counts the 8-bit prescaler’s underflow signal. \ 8-bit prescaler’s underflow signal 1 / fi 5 (m + 1)

7733 Group User’s Manual6–50

Fig. 6.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) “H” “L” “H” “L” PWM pulse output from pin TAiOUT À Count source Pin TAiIN’s input signal 0016 Prescaler contents (Hex.) 0216 Time Counting is stopped. 0116 Counter contents (Hex.) 0416 0A16 Time À When an arbitrary value is reset to the timer Ai register after value “0016” is set to the timer Ai register’s high-order 8 bits, the rising timing of the PWM pulse depends on this reset timing. Value “000216” is set to the timer Ai register. Value “0A0216” is set to the timer Ai register. Value “040216” is set to the timer Ai register. Counting is restarted. h The above is applied when an external trigger (Falling edge of pin TAiIN’s input signal) is selected. fi: Frequency of the count source (f2, f16, f64, or f512) m: Contents of the reload register’s low-order 8 bits

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[Precautions in PWM mode] 1. When the count start flag is cleared to “0” while a PWM pulse is output, the counter stops counting. At this time, if pin TAiOUT outputs “H” level, the output level becomes “L” and a timer Ai interrupt request bit is set to “1.” If pin TAiOUT outputs “L” level, the output level does not change and a timer Ai interrupt request is not generated. 2. When a timer’s operating mode is set by the procedure listed below, a timer Ai interrupt request bit is set to “1.” l When the PWM mode is selected after reset l When the operating mode is switched from the timer mode to the PWM mode l When the operating mode is switched from the event counter mode to the PWM mode Therefore, when using a timer Ai interrupt (Interrupt request bit), be sure to clear the timer Ai interrupt request bit to “0” after setting the above.

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7.1 Overview

7.2 Block description

7.3 Timer mode

7.4 Event counter mode

7.5 Pulse period/Pulse width

7.6 Clock timer

7733 Group User’s Manual7–2

Timer B consists of three counters (Timers B0 to B2), and each has a 16-bit reload function. Timers B0 to B2 operate independently of each other. Timer Bi (i = 0 to 2) has three operating modes listed below. Furthermore, timer B2 can function as a clock timer. Except that timer B2 functions as a clock timer and timer B1 has an internal connect function, timers B0 to B2 have the same functions. n Timer mode Timer B counts a count source internally generated. n Event counter mode Timer B counts an external signal, and the following functions can be used: l Internal connect function (Timer B1 only) n Pulse period/Pulse width measurement mode Timer B measures an external signal’s pulse period/pulse width. n Clock timer (Timer B2)

7733 Group User’s Manual 7–3

Figure 7.2.1 shows the timer B block diagram. Registers related to timer B are described below. Fig. 7.2.1 Timer B block diagram f16 f64 f512 Clock source selection

• Timer mode
• Pulse period/Pulse width measurement mode Polarity switching and Edge pulse generating circuit Event counter mode Count start flag Counter reset circuit Data bus (Odd) Data bus (Even) (Low-order 8 bits) (High-order 8 bits) Timer Bi reload register (16) Timer Bi counter (16) Timer Bi interrupt request bit TBiIN (i = 0 to 2) Timer Bi overflow flag fc32 (Note 1) TB2 overflow signal (Note 2) (address 4016) addresses Timer B0 51 16 5016 Timer B1 5316 5216 Timer B2 5516 5416 Notes 1: Clock source for clock timer Can be selected only for TB2 (Refer to Figure 14.3.1.) 2: Can be selected only for TB1 (Internal connect mode) Clocks f2, f16, f64, and f512 : Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

7733 Group User’s Manual7–4

7.2.1 Counter and Reload register (Timer Bi register)

Each of timer Bi counter and its reload register consists of 16 bits and has the following functions. (1) Functions in timer mode, event counter mode, and clock timer The counter performs countdown each time a count source is input. The reload register is used to memorize the initial value of a counter. When an underflow occurs in the counter, the reload register’s contents is reloaded into the counter. Values are set to the counter and reload register by writing the values to the timer Bi register. Table 7.2.1 lists the memory allocation of the timer Bi register. A value written into the timer Bi register while counting is stopped is set to the counter and reload register. A value written into the timer Bi register while counting is in progress is set only to the reload register. In this case, the reload register’s updated contents is transferred to the counter when the next underflow occurs. A value obtained by reading out the timer Bi register is the counter value. Note: Perform reading or writing from/to the timer Bi register by the 16 bits. For a value read from the timer Bi register, refer to “Precautions in timer mode” and “Precautions in event counter mode.” (2) Functions in pulse period/pulse width measurement mode The counter performs countup each time a count source is input. The reload register is used to hold the pulse period or pulse width measurement result. When a valid edge is input to pin TBi IN, the counter value is transferred to the reload register. In this mode, a value obtained by reading out the timer Bi register is the reload register’s contents, and the measurement result can be obtained. Note: Perform reading from the timer Bi register by the 16 bits. Low-order byte Address 50 Address 5216 Address 5416 High-order byte Address 5116 Address 5316 Address 5516 Timer Bi register Timer B0 register Timer B1 register Timer B2 register Note: At reset, the contents of the timer Bi register is undefined. Table 7.2.1 Memory allocation of timer Bi register

7733 Group User’s Manual 7–5

7.2.2 Count start flag

This register is used to start or stop counting. Each bit of this register corresponds to each timer, respectively. Figure 7.2.2 shows the structure of the count start flag. Fig. 7.2.2 Structure of count start flag Bit Count start flag (address 4016) 0: Counting is stopped. 1: Counting is started. represents that bits 0 to 4 are not used for timer B. RW RW RW RW RW RW RW RW

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7.2.3 Timer Bi mode register

Figure 7.2.3 shows the structure of the timer Bi mode register. The operating mode selection bits are used to select an operating mode of timer Bi. Bits 7 to 5 and bits 3 and 2 have different functions according to the operating mode. These bits are described in a section of each operating mode. Fig. 7.2.3 Structure of timer Bi mode register RW RW RW RW RW RW RW Bit 7 @ 4 Must be fixed to “0” (i = 0). 3 @ Bit name At reset Un- defined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) 0 0: Timer mode 0 1: Event counter mode 1 0: Pulse period/Pulse width measurement mode 1 1: Do not select. b1 b0 2 These bits have different functions according to the operating mode. Note: In the timer and event counter modes, bit 5 is ignored and undefined at reading. 5 These bits have different functions according to the operating mode. Not implemented (i = 1, 2). Un- defined RO (Note)

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7.2.4 Timer Bi interrupt control register

Figure 7.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer to chapter “4. INTERRUPTS” Fig. 7.2.4 Structure of timer Bi interrupt control register (1) Interrupt priority level selection bits (bits 2 to 0) These bits select a timer Bi interrupt’s priority level. When using timer Bi interrupts, select one priority level from levels 1 to 7. If a timer Bi interrupt request is generated, its priority level is compared with the processor interrupt priority level (IPL), and then the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this is applied when the interrupt disable flag (I) = “0.”) When disabling timer Bi interrupts, set these bits to “000 2” (Level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when a timer Bi interrupt request is generated. This bit is automatically cleared to “0” when the timer Bi interrupt request is accepted. This bit can be set to “1” or cleared to “0” by software. At resetBit 7 to 4 Not implemented. 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 Priority is low. 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Priority is high. b2 b1 b0 0: No interrupt request has occurred. 1: Interrupt request has occurred. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi interrupt control register (i = 0 to 2) (addresses 7A16 to 7C16) RW RW RW RW

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7.2.5 Port P6 direction register

I/O pins of timer Bi are multiplexed with port P6. When using these pins as timer Bi’s input pins, set the corresponding bits of the port P6 direction register to “0” in order to set these ports for the input mode. Figure 7.2.5 shows the relationship between the port P6 direction register and the timer Bi’s input pins. Fig. 7.2.5 Relationship between port P6 direction register and timer Bi’s input pins At resetBit Corresponding pin name Functions Pin P60/TA4OUT Pin P62/INT0 Pin P63/INT1 Pin P64/INT2 Pin P66/TB1IN Pin P65/TB0IN Port P6 direction register (address 1016) b1 b0b2b3b4b5b6b7 Pin P61/TA4IN Pin P67/TB2IN/ SUB 0: Input mode 1: Output mode When using these pins as timer Bi’s input pins, set the corresponding bits to “0.” represents that bits 0 to 4 are not used for timer B. RW RW RW RW RW RW RW RW RW

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7.2.6 Port function control register

Figure 7.2.6 shows the structure of the port function control register. Notes 1: When the port-Xc selection bit = “0” and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 and 3 to 7 are not used for timer B. Port-Xc selection bit] : Bit 4 of the oscillation circuit control register 0 (address 6C16) Bit Functions b7 b6 b5 b4 b3 b2 b1 b0 Port function control register (address 6D16) Bit name 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. Timer B2 clock source selection bit 0: No internal connection 1: Internal connection with timer B2 0: No pull-up for pins P54/TA2OUT /KI0 to P57/TA3IN/KI3 1: With pull-up for pins P54/TA2OUT /KI0 to P57/TA3IN/KI3 (TA2IN and TA3IN inputs are assigned to pins P55 and P57.) 1: Key input interrupt (TA2IN and TA3IN inputs are assigned to pins P72 and P73.) 4 Must be fixed to “0.” At reset RW RW RW RW0 RW0 RW0 RW0 RW0 RW0 0•Port-XC selection bit] = “0” (when the sub clock is not used) Timer B2 (event counter mode) clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer)

• Port-XC selection bit = “1” (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/ SUB functions as a programmable I/O port. 1: Sub clock SUB is output from pin P67/TB2IN/ SUB . (Note 2)
• Key input interrupt selection bit = “0” 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2
• Key input interrupt selection bit = “1” 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up and is used for the key input interrupt. 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 Fig. 7.2.6 Structure of port function control register

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7.3 Timer mode (Bits 1 and 0 of timer Bi mode register = “002”)

structures of the timer Bi mode register and timer Bi register in the timer mode. Table 7.3.1 Specifications of timer mode Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing Pin TBiIN’s function Read from timer Write to timer Specifications Clock f2, f16, f64, or f512 l Countdown l At an underflow, the reload register’s contents is reloaded, and counting is continued. n: Set value in the timer Bi register When the count start flag is set to “1.” When the count start flag is cleared to “0.” At an underflow Programmable I/O port (Pin TB2IN is a programmable I/O port or φSUB output pin.) A counter value can be read out by reading the timer Bi register. n While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. n While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload time.) (n + 1) Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

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Fig. 7.3.1 Structures of timer Bi mode register and timer Bi register in timer mode At reset Un- defined Un- defined RWBit Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) b1 b0 b4 b3 00XXX 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b66 Count source selection bits 5 This bit is ignored in the timer mode and is undefined at reading. Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” b7 b0 b7 b0 (b15) (b8) Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) FunctionsBit At reset RW 15 to 0Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Un- defined 2 These bits are ignored in the timer mode. 0 0: Timer mode 4 •Timer B0 mode register Must be fixed to “0.”

• Timer B1 and B2 mode registers Not implemented. RW RW RW RW RW RO RW RW RW

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7.3.1 Setting for timer mode

Figure 7.3.2 shows an initial setting example for registers related to the timer mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter “4. INTERRUPTS.”

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Fig. 7.3.2 Initial setting example for registers related to timer mode /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Counting is started. b7 b0 Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Selection of the timer mode and the count source Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Setting of the count start flag to “1” b7 b0 Count start flag (address 4016) Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag b7 b6 Setting of the interrupt priority level b7 b0 Timer Bi interrupt control register (addresses 7A16 to 7C16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. X Must be fixed to “0” (for i = 0). X: It may be “0” or “1.” Clocks f2, f16, f64, and f512 : Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Timer mode is selected. h Counter divides count source frequency by (n + 1). Setting of the division ratio b7 b0 Values 000016 to FFFF16 (n) can be set. (b15) (b8) b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) XX0

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7.3.2 Count source

In the timer mode, by the count source selection bits (bits 7 and 6 at addresses 5B16 to 5D16), a count source can be selected. Table 7.3.2 lists the relationship between the count source selection bits and count source. Table 7.3.2 Relationship between count source selection bits and count source When system clock = 25 MHz When system clock = 16 MHz When system clock = 8 MHz Clocks f2, f16, f64, f512, and system clock: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = “0” and the main clock division selection bit (bit 0 at address 6F16) = “0.” (For details, refer to chapter “14. CLOCK GENERATING CIRCUIT.”) 390.625 kHz 48.8281 kHz 31.25 kHz 15.625 kHz

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7.3.3 Operation in timer mode

À When the count start flag is set to “1,” the counter starts counting of the count source. \ When an underflow occurs, the reload register’s contents is reloaded, and then counting is continued. ´ The timer Bi interrupt request bit is set to “1” when the underflow occurs in \ . After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 7.3.3 shows an operation example in the timer mode. Fig. 7.3.3 Operation example in timer mode Counting is stopped. Counting is restarted. FFFF 16 n 000016 Time Count start flag Timer Bi interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software Counting is started. Set to “1” by software “0” “0” 1 / fi 5 (n + 1) fi = Frequency of count source ( 2, f16, f64, f512 ) Cleared to “0” by software f

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[Precautions in timer mode] While counting is in progress, by reading out the timer Bi register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 7.3.4, value “FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting, the set value is correctly read out. Fig. 7.3.4 Timer Bi register read out 210 n n – 1Counter value (Hex.) (Hex.) Reload Time n = Reload register’s contents

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7.4 Event counter mode (Bits 1 and 0 of timer Bi mode register = “012”)

timer Bi mode register and timer Bi register in the event counter mode. Table 7.4.1 Specifications of event counter mode Specifications l External signal input to pin TBiIN (Notes 1 and 2). l “Falling edge,” “Rising edge,” or “Falling and Rising edges” can be selected as the valid edge of the count source by software. l Countdown l At an underflow, the reload register’s contents is reloaded, and counting is continued. n: Set value in the timer Bi register When the count start flag is set to “1.” When the count start flag is cleared to “0.” At an underflow Count source input A counter value can be read out by reading the timer Bi register. n While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. n While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing Pin TBi IN’s function Read from timer Write to timer (n + 1) Notes 1: When the timer B1 internal connect selection bit (bit 2 at address 6D16) = “1,” timer B1 counts the timer B2’s underflow signal. (Refer to section “7.4.3 Selectable functions.”) 2: When using timer B2 in the event counter mode, set both of the port-Xc selection bit (bit 4 at address 6C16) and the sub-clock output selection bit/Timer B2 clock source selection bit (bit 1 at address 6D16) to “0.” When one of or both of these bits = “1,” timer B2 functions as a clock timer. (Refer to section “7.6 Clock timer.”)

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Fig. 7.4.1 Structures of timer Bi mode register and timer Bi register in event counter mode 0 0: Counting is performed at the falling edge of the external signal. 0 1: Counting is performed at the rising edge of the external signal. 1 0: Counting is performed at both falling and rising edges of the external signal. 1 1: Do not select. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit 5 This bit is ignored in the event counter mode and is undefined at reading. 4 •Timer B0 mode register Must be fixed to “0.”

2 Count polarity selection bits

0 1: Event counter mode b1 b0 b3 b2 X 01 6 These bits are ignored in the event counter mode. At reset Un- defined Un- defined RW

• Timer B1 and B2 mode registers Not implemented. b7 b0 b7 b0 (b15) (b8) Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) FunctionsBit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Un- defined XX RW RW RW RW RW RO RW RW RW

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7.4.1 Setting for event counter mode

Figure 7.4.2 shows an initial setting example for registers related to the event counter mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter “4. INTERRUPTS.”

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Fig. 7.4.2 Initial setting example for registers related to event counter mode h Counter divides count source frequency by (n + 1). Setting of the division ratio b7 b0 Values 000016 to FFFF16 (n) can be set. (b15) (b8) b7 b0 Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Counting is started. b7 b0 0 0: Counts at falling edge of external signal. 0 1: Counts at rising edge of external signal. 1 0: Counts at both of falling and rising edges of external signal. 1 1: Do not select. Selection of the event counter mode and the count polarity Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Setting of the count start flag to “1” b7 b0 Count start flag (address 4016) Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag X: It may be “0” or “1.” b3b2 Setting of the interrupt priority level b7 b0 Timer Bi interrupt control register (addresses 7A16 to 7C16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the port P6 direction register b7 b0 Port P6 direction register (address 1016) Clear the corresponding bit to “0.” X Must be fixed to “0” (for i = 0). Pin TB0IN Pin TB1IN Pin TB2IN Event counter mode is selected. Count polarity selection bits XX0 Selection of the timer B1 internal connection b7 b0 Port function control register (address 6D16) Timer B1 internal connect selection bit 0: No internal connection 1: Internal connection with timer B2

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7.4.2 Operation in event counter mode

À When the count start flag is set to “1,” the counter starts counting of the count source. \` The counter counts the count source’s valid edges. ´ When an underflow occurs, the reload register’s contents is reloaded, and then counting is continued. ˆ The timer Bi interrupt request bit is set to “1” when the underflow occurs in ´ . After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 7.4.3 shows an operation example in the event counter mode. Fig. 7.4.3 Operation example in event counter mode Counting is stopped. Counting is restarted. FFFF 16 n 000016 Time Count start flag Timer Bi interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software Counting is started. “0” “0” Set to “1” by softwareCleared to “0” by software

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7.4.3 Selectable functions

Timer B1 internal connection is described below. (1) Timer B1 internal connection When the timer B1 internal connect selection bit (bit 2 at address 6D16) is set to “1,” timer B1 is internally connected to timer B2 and counts the timer B2’s underflow signal. Accordingly, timers B2 and B1 function as a 32-bit (16 bits + 16 bits) timer and counts the timer B2’s count source. This function can be used when timer B2 operates in the timer or event counter mode, or as a clock timer. Figure 7.4.4 shows connection between timers B2 and B1 when timer B1 internal connection is selected. Figure 7.4.5 shows structures of the timer B1 mode register and port function control register when timer B1 internal connection is selected. Figure 7.4.6 shows an operation example when timer B1 internal connection is selected. Fig. 7.4.4 Connection between timers B2 and B1 when timer B1 internal connection is selected b7 b0 Timer B1 mode register (address 5C16)1 b7 b0 Port function control register (address 6D16) /LiteDiagLines /LiteDiagLines 10 0 X: It may be “0” or “1.” XXXX Fig. 7.4.5 Structures of timer B1 mode register and port function control register when timer B1 internal connection is selected Timer B1 (Event counter mode) Timer B1 interrupt request bitCounter (16)Timer B2 count source TB 1IN Timer B2 interrupt request bit Reload register (16) Timer B2 Timer mode Event counter mode Clock timer Timer B1 internal connect selection bit Counter (16) Reload register (16)

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Fig. 7.4.6 Operation example when timer B1 internal connection is selected Timer B1/B2 count start flag Timer B2 interrupt request bit Timer B2 counter’s content (Hex.) h : Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software “0” “1” Timer B1 counter’s contents (Hex.) “0” “1”Timer B1 interrupt request bit h The above is applied in the following case. Set value of timer B2 register = “000316” Set value of timer B1 register = “000216” h h h h h Time

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[Precautions in event counter mode] 1. While counting is in progress, by reading out the timer Bi register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 7.4.7, value “FFFF 16” is read out. If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting, the set value is correctly read out. Fig. 7.4.7 Timer Bi register read out 2. The internal connect function between timer B2 and timer B1 can be used when timer B2 operates in the timer or event counter mode, or as a clock timer. Do not use this function in the pulse period/pulse width measurement mode. 210 n n – 1Counter value (Hex.) (Hex.) Reload Time n = Reload register’s contents

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7.5 Pulse period/Pulse width measurement mode

(Bits 1 and 0 of timer Bi mode register = “102”) In this mode, an external signal’s pulse period or pulse width is measured. (Refer to Table 7.5.1.) Figure 7.5.1 shows the structures of the timer Bi mode register and timer Bi register in the pulse period/pulse width measurement mode. n Pulse period measurement The pulse period of an external signal which is input to pin TBiIN is measured. n Pulse width measurement The pulse width (“L” level width and “H” level width) of an external signal which is input to pin TBiIN is measured. Note: When the port-Xc selection bit (bit 4 at address 6C16) = “1,” timer B2 functions as a clock timer. Accordingly, pulse period/pulse width measurement cannot be performed. Table 7.5.1 Specifications of pulse period/pulse width measurement mode Item Count source Count operation Count start condition Count stop condition Interrupt request occurrence timing Pin TBi IN’s function Read from timer Write to timer Specifications Clock f2, f16, f64, or f512 l Countup l When valid edge of the measurement pulse is input, the counter value is transferred to the reload register. And then, the counter value is cleared to “0000 16,” and counting is continued. When the count start flag is set to “1.” When the count start flag is cleared to “0.” l When the valid edge of the measurement pulse is input (Note 1). l At an overflow (Simultaneously, the overflow flag is set to “1.”) Measurement pulse input By reading the timer Bi register, the reload register’s contents (Measurement result) is read out (Note 2). Ignored Clocks f 2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Overflow flag: A flag used to identify the source of an interrupt request occurrence. Notes 1: An interrupt request is not generated when the first valid edge is input after counting starts. 2: From when counting starts until the second valid edge is input, a value obtained by reading the timer Bi register is undefined.

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Fig. 7.5.1 Structures of timer Bi mode register and timer Bi register in pulse period/pulse width measurement mode b7 b0 b7 b0 (b15) (b8) Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) FunctionsBit At reset RW 15 to 0The result of the pulse period or pulse width measurement is read out. Un- defined 0 0: Pulse period measurement (interval between falling edges of the measurement pulse) 0 1: Pulse period measurement Interval between rising edges of the measurement pulse) 1 0: Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of the measurement pulse) 1 1: Do not select. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit Count source selection bits Timer Bi overflow flag (Note)

• Timer B0 mode register Must be fixed to “0.” Measurement mode selection bits Operating mode selection bits Bit name Functions 1 0: Pulse period/pulse width measurement b1 b0 0: No overflow 1: Overflow b3 b2 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b6 At reset Un- defined RW
• Timer B1 and B2 mode registers Not implemented. Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: Timer Bi overflow flag is cleared to “0” when writing to the timer Bi mode register is performed with the count start flag = “1.” This flag cannot be set to “1” by software. RW RW RW RW RW RO RW RW RO mode

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7.5.1 Setting for pulse period/pulse width measurement mode

Figure 7.5.2 shows an initial setting example for registers related to the pulse period/pulse width measurement mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter “4. INTERRUPTS.”

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Fig. 7.5.2 Initial setting example for registers related to pulse period/pulse width measurement mode /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Counting is started. b7 b0 Measurement mode selection bits Selection of the pulse period/pulse width measurement mode and each function Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Setting of the count start flag to “1” b7 b0 Count start flag (address 4016) Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Must be fixed to “0” (for i = 0). b3 b2 Setting of the interrupt priority level b7 b0 Timer Bi interrupt control register (addresses 7A16 to 7C16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Count source selection bits b7 b6 Timer Bi overflow flag (Note) 0: No overflow 1: Overflow Setting of the port P6 direction register b7 b0 Port P6 direction register (address 1016) Clear the corresponding bit to “0.” Pin TB0IN Pin TB1IN Pin TB2IN 0 0: Pulse period measurement (Interval between falling edges) 0 1: Pulse period measurement (Interval between rising edges) 1 0: Pulse width measurement 1 1: Do not select. 0 0: Clock f 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Note: The timer Bi overflow flag is a read-only flag. This flag is cleared to “0” when writing to timer Bi mode register is performed with the count start flag = “1.” Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Pulse period/Pulse width measurement mode is selected.

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7.5.2 Count source

In the pulse period/pulse width measurement mode, by the count source selection bits (bits 7 and 6 at addresses 5B16 to 5D16), a count source can be selected. Table 7.5.2 lists the relationship between the count source selection bits and count source. Table 7.5.2 Relationship between count source selection bits and count source Count source f16 f64 f512 Frequency of count source When system clock = 25 MHz When system clock = 16 MHz When system clock = 8 MHz 390.625 kHz 48.8281 kHz 15.625 kHz 31.25 kHz Clocks f 2, f16, f64, f512, and system clock: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = “0” and the main clock division selection bit (bit 0 at address 6F16) = “0.” (For details, refer to chapter “14. CLOCK GENERATING CIRCUIT.”)

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7.5.3 Operation in pulse period/pulse width measurement mode

À When the count start flag is set to “1,” the counter starts counting of the count source. \ When a valid edge of the measurement pulse is input, the counter value is transferred to the reload register. (Refer to “(1) Pulse period/Pulse width measurement.”) ´ After a transfer in \ , the counter value becomes “000016,” and the counter continues counting. ˆ The timer Bi interrupt request bit is set to “1” when the counter value becomes “000016” in ´ ,(Note ). After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. ˜ Operations \` to ˆ are repeated. Note: Timer Bi interrupt request is not generated when the first valid edge is input after counting starts. (1) Pulse period/Pulse width measurement Whether to measure the pulse period or the pulse width of an external signal can be selected by the measurement mode selection bits (bits 3 and 2 at addresses 5B 16 to 5D16). Table 7.5.3 lists the relationship between the measurement mode selection bits and the pulse period/pulse width measurement. Make sure that the measurement interval from the falling edge to the rising edge and that of from the rising edge to the falling edge are two cycles of the count source or more. When measuring pulse width of a signal whose duty ratio is not 50%, identify whether the measurement result is the “H” level width or the “L” level width by software. Table 7.5.3 Relationship between measurement mode selection bits and pulse period/pulse width measurement Pulse period/Pulse width measurement Pulse period measurement Pulse width measurement Measurement interval (Valid edge) From falling edge to falling edge (Falling edge) From rising edge to rising edge (Rising edge) From falling edge to rising edge, and from rising edge to falling edge (Falling and Rising edges)

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(2) Timer Bi overflow flag When a measurement pulse’s valid edge is input or an overflow occurs, a timer Bi interrupt request is generated. The timer Bi overflow flag is used to identify the cause of an interrupt request occurrence, in other words, determine whether it is an overflow or a valid edge input. When an overflow occurs, the timer Bi overflow flag is set to “1.” Therefore, the source of the interrupt request occurrence can be identified by checking the timer Bi overflow flag’s state in the interrupt routine. The timer Bi overflow flag is cleared to “0” at the next count timing of the count source when a value is written to the timer Bi mode register with the count start flag = “1.” The timer Bi overflow flag is a read-only flag. Do not use this flag for detection of overflow timing. during pulse width measurement. Fig. 7.5.3 Operation during pulse period measurement Count source Measurement pulse Timing when counter is cleared to “000016” “1” “H” “1” h The above is applied when measurement is performed from one falling edge of the measurement pulse until the next falling edge of that. Reload register@@ Counter Transfer timing “L” “0” “0” Count start flag “1” “0” À Initialization of the counter because of measurement completion \ Overflow À \À Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Timer Bi interrupt request bit Timer Bi overflow flag Transferred (Undefined value) Transferred (Measured value)

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Fig. 7.5.4 Operation during pulse width measurement Measurement pulse“H” Count source Reload register Counter Transfer timing Timing when counter is cleared to “000016” “1” “1” Transferred (Measured value) “L” “0” “0” “1” “0” Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software À Initialization of the counter because of measurement completion \ Overflow À \ÀÀÀ Count start flag Timer Bi interrupt request bit Timer Bi overflow flag Transferred (Measured value) Transferred (Measured value) Transferred (Undefined value)

7733 Group User’s Manual 7–33

[Precautions in pulse period/pulse width measurement mode] 1. A timer Bi interrupt request is generated by the following sources: l The measurement pulse’s valid edge which is input l An overflow The interrupt request source shown above can be determined by the timer Bi overflow flag. 2. At reset, the timer Bi overflow flag is set to “1.” This flag can be cleared to “0” by performing writing to the timer Bi mode register with the count start flag = “1.” 3. When the first valid edge is input after counting starts, an undefined value is transferred to the reload register. At this time, a timer Bi interrupt request is not generated. 4. At start of counting, the counter value is undefined. Therefore, there is a possibility that a timer Bi interrupt request is generated by an overflow which occurs immediately after counting starts. 5. When the measurement mode selection bits are changed after counting starts, the timer Bi interrupt request bit is set to “1.” Note that the timer Bi interrupt request bit does not change if the same value as before is written to the measurement mode selection bits. 6. When an input signal to pin TBiIN is affected by noise or others, there is a possibility that the counter cannot perform the exact measurement. We recommend to verify, by software, that the measurement values are within a constant range.

7733 Group User’s Manual7–34

Timer B2 functions as a clock timer on the following condition (Refer to Table 7.6.1.): l When the port-Xc selection bit (bit 4 at address 6C16) = “1” l When the port-Xc selection bit = “0” and the timer B2 clock source selection bit (bit 1 at address 6D16) = “1” Figure 7.6.1 shows the structures of the timer B2 mode register and timer B2 register when a clock timer is used. Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing Pin TB2 IN’s function Read from timer Write to timer Table 7.6.1 Specifications of clock timer Specifications fc32 (Sub clock divided by 32: f(XCIN )/32), or Main clock divided by 32: f(XIN)/32) l Countdown l At an underflow, the reload register’s contents is reloaded, and counting is continued. (n + 1) When the count start flag is set to “1.” When the count start flag is cleared to “0.” At an underflow Programmable I/O port or φSUB output pin A counter value can be read out by reading the timer B2 register. n While counting is stopped When a value is written to the timer B2 register, it is written to both of the reload register and counter. n While counting is in progress When a value is written to the timer B2 register, it is written only to the reload register. (Transferred to the counter at the next reload time.) n: Set value in the timer B2 register Clocks fc32 and f(XCIN ): Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Either of f(XCIN )/32 or f(XIN)/32 can be selected as the clock timer’s count source, fc32. The way to generate f(XCIN )/32 is different from that for clocks whose source is the system clock (e.g., internal clock φ, clocks f2 to f512, and so on). (Refer to chapter “14. CLOCK GENERATING CIRCUIT.” ) f(XCIN )/32 is not affected by the system clock selection bit and system clock stop bit at wait state (bits 3 and 5 at address 6C16). Therefore, in the wait mode, (Refer to chapter “11. STOP AND WAIT MODES.” ) only the clock timer can operate by itself. In other words, it is possible to supply fc32 only. Oppositely, the way to generate f(XIN)/32 is the same as that for the system clock. Therefore, when the system clock stop bit at wait state = “1,” fc32 is not supplied in the wait mode. Figure 7.6.2 shows the structure of the clock timer.

7733 Group User’s Manual 7–35

Fig. 7.6.1 Structures of timer B2 mode register and timer B2 register when clock timer is used At resetFunctions Un- defined Un- defined RWBit 3 Must be fixed to “0” for the clock timer. b7 b6 b5 b4 b3 b2 b1 b0 Timer B2 mode register (address 5D16) 1010 06 These bits are ignored for the clock timer. 5 This bit is ignored for the clock timer. b7 b0 b7 b0 (b15) (b8) Timer B2 register (addresses 5516 and 5416) FunctionsBit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Un- defined 2 Must be fixed to “1” for the clock timer. 1 Must be fixed to “0” for the clock timer. 0 Must be fixed to “1” for the clock timer. 4 Not implemented. X XX RW RW RW RW RO RW RW RW

7733 Group User’s Manual7–36

: f(XCIN) Main clock : f(XIN) Clock timer (Timer B2 counter) System clock (Clock source for f2 to f512, and internal clock ) Timer B2 interrupt request bit1/32 fc32 Clock prescaler Timer B2 reload register Fig. 7.6.2 Structure of clock timer

7733 Group User’s Manual 7–37

7.6.1 Setting for clock timer

Figure 7.6.3 shows an initial setting example for registers related to the clock timer. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter “4. INTERRUPTS.” Fig. 7.6.3 Initial setting example for registers related to clock timer /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Counting is started. b7 b0 Selection of the clock timer Oscillation circuit control register 0 (address 6C16) Setting of the count start flag to “1” b7 b0 Count start flag (address 4016) Timer B2 count start flag Setting of the interrupt priority level b7 b0 Timer B2 interrupt control register (address 7C16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Initialization of the clock prescaler By using LDM instruction, write value “8016” to address 6F16. 1: XCIN–XCOUT selected (Sub clock used) Note: After oscillation of an oscillator connected to the sub-clock oscillation circuit is stabilized, set the count start flag to “1.” Port-Xc selection bit 1010 b7 b0 Timer B2 mode register (address 5D16) h Counter divides the count source frequency by (n + 1). b7 b0 b7 b0 Setting of the division ratio Values 000016 to FFFF16 (n) can be set. (b15) (b8) Timer B2 register (addresses 5516 and 5416) X X: It may be “0” or “1.” XX b7 b0 Selection of the clock timer Oscillation circuit control register 0 (address 6C 16) Port-Xc selection bit 0: Ports P77 and P76 selected (Sub clock not used) 1010 b7 b0 Timer B2 mode register (address 5D16)X X: It may be “0” or “1.” XX When using sub clock (Xc) b7 b0 Port function control register (address 6D16) Sub-clock output selection bit/Timer B2 clock source selection bit Timer B2 (Event counter mode) clock source selection 1: Main clock divided by 32 When not using sub clock (Xc)

7733 Group User’s Manual7–38

7.6.2 Operation of clock timer

À When the count start flag is set to “1,” the counter starts counting of the count source. \ When an underflow occurs, the reload register’s contents is reloaded, and then counting is continued. ´ The timer B2 interrupt request bit is set to “1” when the underflow occurs in \ . After this, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. For example, if f(XCIN) = 32.768 kHz, a timer B2 interrupt request can be issued every second when value “3FF16” is set into the timer B2 register (addresses 5416 and 5516) and every minute when value “EFFF16” is set into the register. Figure 7.6.4 shows an operation example of clock timer. Fig. 7.6.4 Operation example of clock timer FFFF 16 n 000016 Count start flag Timer B1 interrupt request bit “1” “1” Timer B2 counter’s contents (Hex.) Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software Set to “1” by software “0” “0” 000016 FFFF 16 n Timer B2 counter’s contents (Hex.) Cleared to “0” by software

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[Precautions for clock timer] 1. While counting is in progress, by reading out the timer B2 register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 7.6.5, value “FFFF 16” is read out. If reading is performed in the period from when a value is set into the timer B2 register with the counter stopped until the counter starts counting, the set value is correctly read out. Fig. 7.6.5 Timer B2 register read out 210 n n – 1Counter value (Hex.) (Hex.) Reload Time n = Reload register’s contents 2. For the clock prescaler reset, refer to section “14.3.4 Clock prescaler reset.”

7733 Group User’s Manual7–40

8.1 Overview

8.2 Block description

8.3 Clock synchronous serial

8.4 Clock asynchronous serial

I/O (UART) mode

7733 Group User’s Manual8–2

The serial I/O consists of 3 channels: UART0, UART1 and UART2. They each have a dedicated timer for generating a transfer clock and can operate independently. UARTi (i = 0 to 2) has the following two operating modes: clock synchronous serial I/O and clock asynchronous serial I/O (UART) modes. Except for a few functions in the clock synchronous serial I/O mode, UART0, UART1 and UART2 have the same functions. l Clock synchronous serial I/O mode Transmitter and receiver use the same clock as a transfer clock. Transfer data has a length of 8 bits. l Clock asynchronous serial I/O (UART) mode Transfer rate and transfer data format can arbitrarily be set. The transfer data length can be selected from the following three types: 7 bits, 8 bits, and 9 bits. between UART0, UART1 and UART2. Fig. 8.1.1 Transfer data formats in each operating mode n Clock synchronous serial I/O mode n UART mode Transfer data length : 7 bits Transfer data length : 8 bits Transfer data length : 9 bits

7733 Group User’s Manual 8–3

Table 8.1.1 Differences between UART0, UART1 and UART2 Communication Clock synchronous or asynchronous (UART) mode is selectable. Clock synchronous or asynchronous (UART) mode is selectable. Clock synchronous or asynchronous (UART) mode is selectable. UART0 UART1 UART2 Notes 1: The A-D conversion interrupt and UART2 transmission/reception interrupt share the interrupt vector addresses and the interrupt control register. When the UART2 mode is selected by specifying bits 2 to 0 of the UART2 transmit/receive mode register (address 64 16), the A-D conversion interrupt function cannot be used. 2: UART2 is fixed as follows.

• Data output (TxD2 pin): CMOS output
• Polarity of CLK2: Transmit data is output at the falling edge of the transfer clock. Receive data is input at the rising edge of the transfer clock. When not transferring, CLK 2 pin’s level is “H.” (Used in the clock synchronous serial I/O mode)
• Transfer format: LSB (the least significant bit) first

available. Both functions are available. Only CTS input function is available. Interrupt function

• UART0 transmission
• UART0 reception (2 systems)
• UART1 transmission
• UART1 reception (2 systems)
• UART2 transmission /reception (Note 1) (1 system) Data output/CLK polarity/transfer format select function Available Available Not available (Note 2)

7733 Group User’s Manual8–4

Note: The bit converter, the polarity reversing circuit and RTSi output function are not assigned for UART2. n: Value set to the UARTi baud rate register Divider [1/(n+1)] UART2 (Address 6516) Divider(1/16 ) CLKi CTSi / RTSi

0000000 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

Data bus (odd) Transfer clockReceive control circuit Transmission control circuit Transmission register D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 UART0 (Addresses 3716, 3616) Receive buffer register UART1 (Addresses 3F16, 3E16) Transmission buffer register Divider(1/16 ) UART transmission Divider (1/2 ) f16 f64 f512 Clock synchronous (When internal clock is selected) UART receive Clock synchronous Clock synchronous Clock synchronous (Internal clock) Clock synchronous (External clock) Internal External Baud rate register UART0 (Address 3116) Clock source selection RxD i TxD i Bit converter Receive register Data bus (odd) Bit converter Polarity reversing circuit Data bus (even) UART2 (Addresses 6B16, 6A16) (Note) (Note) (Note) (Note) Data bus (even) Transfer clock UART0 (Addresses 3316, 3216) UART1 (Addresses 3B16, 3A16) UART2 (Addresses 6716, 6616) UART1 (Address 3916) Figure 8.2.1 shows the block diagram for serial I/O. Registers related to serial I/O are described below. Fig. 8.2.1 Block diagram for serial I/O

7733 Group User’s Manual 8–5

7 Sleep selection bit

(Valid in the UART mode.) (Note)

6 Parity enable bit

(Valid in the UART mode.) (Note)

5 Odd/Even parity selection bit

(Valid in the UART mode when the parity enable bit = “1.”) (Note)

4 Stop bit length selection bit

(Valid in the UART mode.) (Note)

3 Internal/External clock selection

0 Serial I/O mode selection bits

0 0 0: Serial I/O is disabled. (P8 functions as a programmable I/O port.) 0 0 1: Clock synchronous serial I/O mode 0 1 0: Do not select. 0 1 1: Do not select. 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Do not select. UART0 transmit/receive mode register (address 3016) UART1 transmit/receive mode register (address 3816) Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be “0” or “1.”) Fix bit 7 to “0.” b2 b1 b0 0: Odd parity 1: Even parity 0: Parity is disabled. 1: Parity is enabled. The sleep mode is terminated. (Ignored.) 1: The sleep mode is selected. 0: Internal clock 1: External clock 0: One stop bit 1: Two stop bits RW RW RW RW RW RW RW RW

8.2.1 UARTi transmit/receive mode register

selection bits are used to select a UARTi’s operating mode. For bits 4 to 6, refer to section “8.4.2 Transfer data format.” For bit 7, refer to section “8.4.8 Sleep mode.” Fig. 8.2.2 Structure of UARTi transmit/receive mode register (1)

In the clock synchronous serial I/O mode, bits 4 to 6 are ignored. (They may be “0” or “1.”) SERIAL I/O

7733 Group User’s Manual8–6

Not implemented. Parity enable bit (Valid in the UART mode.) (Note 2) Odd/Even Parity selection bit (Valid in the UART mode when the parity enable bit = “1”.) (Note 2) (Valid in the UART mode.) (Note 2) Internal/External clock selection bit Serial I/O mode selection bits (Note 1) Bit name At reset Un- defined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0 0: Serial I/O is ignored. (P7 functions as a programmable I/O port) 0 0 1: Clock synchronous serial I/O mode 0 1 0: 0 1 1: 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Do not select. UART2 transmit/receive mode register (address 6416) Notes 1: By specifying these bits, an A-D conversion interrupt or a UART2 transmit/receive interrupt is selected. When bits 2 to 0 = “0002,” an A-D conversion interrupt is selected. When bits 2 to 0 = “0012” or “1002 to 1112,” a UART2 transmit/receive interrupt is selected. b2 b1 b0 0: Odd parity 1: Even parity 0: Parity is disabled. 1: Parity is enabled. 0: Internal clock 1: External clock 0: One stop bit 1: Two stop bits RW RW RW RW RW RW RW Do not select. Fig. 8.2.3 Structure of UARTi transmit/receive mode register (2) Stop bit length selection bit

7733 Group User’s Manual 8–7

(1) Internal/External clock selection bit (bit 3) l Clock synchronous serial I/O mode When an internal clock is selected by clearing this bit to “0,” a clock which is specified with the BRG count source selection bits (bits 1 and 0 at addresses 3416, 3C16 and 6816) becomes the count source of BRGi (described later). At this time, the BRGi’s output divided by 2 is the transfer clock. The transfer clock is output from the CLKi pin (Note ). When an external clock is selected by setting this bit to “1,” a clock input to the CLKi pin becomes the transfer clock. Note : When selecting an internal clock and performing only transmission in UART0, the number of the transfer clock output pins varies according to the contents of the transmit clock output pin selection bits (bits 5 and 4 at address 6E16). (Refer to section “8.3.1 Transfer clock.”) l UART mode When an internal clock is selected by clearing this bit to “0,” a clock which is specified with the BRG count source selection bits (bits 1 and 0 at addresses 3416, 3C16 and 6816) becomes the count source of the BRGi (described later). At this time, the CLKi pin functions as a programmable I/O port. When an external clock is selected by setting this bit to “1,” a clock input to the CLKi pin becomes the count source of BRGi . Note that, in the UART mode, the BRGi’s output divided by 16 is always the transfer clock. BRGi: UARTi baud rate register (Refer to section “8.2.7 UARTi baud rate register (BRGi).”)

0: The SERIAL I/O

7733 Group User’s Manual8–8

0: At the falling edge of the transfer clock, transmit data is output; at the rising edge of the transfer clock, receive data is input. When not in transferring, pin CLK i’s level is “H.” 1: At the rising edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. When not in transferring, pin CLK i’s level is “L.” 0: The CTS /RTS function is enabled. 1: The CTS /RTS function is disabled. (P80 and P84 function as  programmable I/O ports.) (Valid when the CTS /RTS enable bit is “0.”)

2 CTS /RTS function selection bit

0 BRG count source selection bits

0: Data is present in the transmission register. (Transmission is in progress.) 1: No data is present in the transmission register. (Transmission is completed.) RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) b1 b0 CTS function is selected. 1: The RTS function is selected.

4 CTS /RTS enable bit

3 Transmission register empty flag

Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: Fix bits 6 and 7 to “0” in the UART mode. 5 Data output selection bit 0: Pin TxDi is set for CMOS output. 1: Pin TxDi is set for N-channel open- drain output. 6 0 7 0: LSB (Least Significant Bit) first 1: MSB (Most Significant Bit) first CLK polarity selection bit (This bit is used in the clock synchronous serial I/O mode.) (Note) Transfer format selection bit (This bit is used in the clock synchronous serial I/O mode.) (Note) RW RW RW RO RW RW RW RW Fig. 8.2.4 Structure of UARTi transmit/receive control register 0 (1)

8.2.2 UARTi transmit/receive control register 0

refer to section “(1) Internal/External clock selection bit” in page 8-7. For bits 7 to 4, refer to the description of each operating mode.

7733 Group User’s Manual 8–9

2 CTS enable bit

0 BRG count source selection

Bit name At resetFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 UART2 transmit/receive control register 0 (address 6816) b1 b0 0: The CTS function is enabled. 1: The CTS function is disabled. (P80 and P84 function as programmable I/O ports.)

3 Transmission register empty

Not implemented. 7 to 4 RW RW RW RW RO0: Data is present in the transmission register. (Transmission is in progress.) 1: No data is present in the transmission register. (Transmission is completed.) Un- defined Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Fig. 8.2.5 Structure of UARTi transmit/receive control register 0 (2) (1) CTS /RTS function selection bit (bit 2) (UART0, UART1) This bit becomes valid when the CTS /RTS enable bit (bit 6) is cleared to “0.” ____ When this bit is cleared to “0” in order to select the CTS function, the P80 and P84 pins function as CTS input pins. At this time, a “L”-level signal input to the CTS pin is one of the transmit conditions. When this bit is set to “1” in order to select the RTS function, the P80 and P84 pins function as RTS output pins. When the receive enable bit (bit 2 at addresses 3516, 3D16) is “0” (in other words, ____ reception is disabled.), the RTS pin outputs “H” level. ____ In the clock synchronous serial I/O mode, the output level of RTS pin becomes “L” when receive conditions are satisfied; it becomes “H” when reception is started. Note that, when an internal clock ____ is selected (bit 3 at addresses 3016, 3816 = “0”), the RTS function is ignored. ____ In the clock asynchronous serial I/O mode, the output level of the RTS pin becomes “L” when receive enable bit is set to “1”; it becomes “H” when reception is started; it becomes “L” when the reception is completed. ____ (2) CTS enable bit (bit 2) (UART2) ____ CTS input pin is valid when this bit is set to “0.” ____ A “L”-level signal input to the CTS pin is one of the transmit conditions. (3) Transmission register empty flag (bit 3) This flag is cleared to “0” when the contents of the UARTi transmission buffer register is transferred to the UARTi transmission register. When transmission is completed and the UARTi transmission register becomes empty, this flag is set to “1.”

7733 Group User’s Manual8–10

5 Framing error flag (Notes 1 and 2)

(Valid in the UART mode.) 00: No framing error is detected. 1: Framing error is detected. RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) Notes 1: Bits 4 to 7 are cleared to “0” when the serial I/O mode selection bits (bits 2 to 0 at addresses 3016, 3816) are cleared to “0002” or when the receive enable bit is cleared to “0.” (Bit 7 is cleared to “0” when all of bits 4 to 6 are “0.”) Note also that bits 5 and 6 are cleared to “0” when the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16, 6A16) is read out. 2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode. 0 Transmit enable bit 00: Transmission is disabled. 1: Transmission is enabled.

1 Transmission buffer empty flag 10: Data is present in the transmission

buffer register. 1: No data is present in the transmission buffer register. 2 Receive enable bit 00: Reception is disabled. 1: Reception is enabled.

3 Receive completion flag 00: No data is present in the receive

buffer register. 1: Data is present in the receive buffer register. 4 Overrun error flag (Note 1) 00: No overrun error is detected. 1: Overrun error is detected.

6 Parity error flag (Notes 1 and 2)

(Valid in the UART mode.) 00: No parity error is detected. 1: Parity error is detected.

7 Error sum flag (Notes 1 and 2)

(Valid in the UART mode.) 00: No error is detected. 1: Error is detected. RW RO RW RO RO RO RO RO

8.2.3 UARTi transmit/receive control register 1

Figure 8.2.6 shows the structure of UARTi transmit/receive control register 1. For bits 7 to 4, refer to the description of each operating mode. Fig. 8.2.6 Structure of UARTi transmit/receive control register 1

7733 Group User’s Manual 8–11

(1) Transmit enable bit (bit 0) When this bit is set to “1,” UARTi enters the transmit enable state. When this bit is cleared to “0” during transmission, UARTi enters the transmit disable state after the transmission which is in progress at this clearing is completed. (2) Transmission buffer empty flag (bit 1) This flag is set to “1” when data is transferred from the UARTi transmission buffer register to the UARTi transmission register. This flag is cleared to “0” when data is set to the UARTi transmission buffer register. (3) Receive enable bit (bit 2) When this bit is set to “1,” UARTi enters the receive enable state. When this bit is cleared to “0” during reception, UARTi quits the reception immediately and enters the receive disable state. (4) Receive completion flag (bit 3) This flag is set to “1” in the following case;

• when data is ready in the UARTi receive register and is transferred to the UARTi receive buffer register (in other words, when reception is completed). This flag is cleared to “0” in one of the following cases;
• when the low-order byte of the UARTi receive buffer register is read out,
• when the receive enable bit (bit 2) is cleared to “0,”
• when port P8 is used as a programmable I/O port by clearing the serial I/O mode selection bits (bits 2 to 0 at addresses 30 16, 3816 and 6416) to “0002”

7733 Group User’s Manual8–12

Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Serial transmit control register (address 6E16) h When using multiple transfer clock output pins, satisfy the following conditions: l Serial I/O mode selection bits (bits 2 to 0 at address 3016) = “0012” l Internal/external clock selection bit (bit 3 at address 3016) = “0” l CTS /RTS enable bit (bit 4 at address 3416) = “1” l Receive enable bit (bit 2 at address 3516) = “0” (for cases À and \` in Table 8.3.4) l Transmission clock output pin selection bits = “012”, “102”, or “112” (Refer to Table 8.3.3.) Note: Bits 4 and 5 are ignored in the UART mode. (They may be “0” or “1.”) Not implemented. Un- defined

4 Transmission clock output pin

(Valid only in the clock synchronous serial I/O mode.) (Note) 00 0: One transfer clock output pin (CLK0) 0 1: 1 0: 1 1: 5 0 3 to 0 7, 6 Not implemented. Value “0” is read out from here. b5 b4 Multiple transfer clock output pins RW RW

8.2.4 Serial transmit control register

Figure 8.2.7 shows the structure of the serial transmit control register. The transmission clock output pin selection bits are valid only for UART0. For these bits, refer to section “8.3.1 Transfer clock.” Fig. 8.2.7 Structure of serial transmit control register

7733 Group User’s Manual 8–13

8.2.5 UARTi transmission register and UARTi transmission buffer register

transmission buffer register. Fig. 8.2.8 Block diagram for transmitter Fig. 8.2.9 Structure of UARTi transmission buffer register SP SP PAR “0” 2SP 1SP UART 7-bit UART 8-bit UART 7-bit UART 9-bit UART Clock sync. Clock sync. Clock sync. Data bus (even) Data bus (odd) TxD i UARTi transmission register Parity enabled Parity disabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP : Stop bit PAR : Parity bit UARTi transmission buffer register Bit converter 8-bit UART 9-bit UART (Note) Note: The bit converter is not assigned for UART2. b7 b0 (b15) (b8) b7 b0 UART0 transmission buffer register (addresses 3316, 3216) UART1 transmission buffer register (addresses 3B16, 3A16) UART2 transmission buffer register (addresses 6716, 6616) Bit Not implemented. The transmit data is set. At reset Un- defined RWFunctions 8 to 0 15 to 9 Un- defined WO

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Transmit data is set into the UARTi transmission buffer register. When the microcomputer operates in the clock synchronous serial I/O mode or when 7-bit or 8-bit length is selected as the transfer data’s length in the UART mode, the transmit data is set into the low-order byte of this register. When 9-bit length is selected as the transfer data’s length in the UART mode, the transmit data is set into the UARTi transmission buffer register as follows. l Bit 8 of the transmit data is set into bit 0 of the high-order byte of the UARTi transmission buffer register. l Bits 7 to 0 of the transmit data are set into the low-order byte of the UARTi transmission buffer register. When transmit conditions are satisfied, the transmit data which is set in the UARTi transmission buffer register is transferred to the UARTi transmission register, and then it is output from the TxDi pin synchronously with the transfer clock. The UARTi transmission buffer register becomes empty when data which is set in this register is transferred to the UARTi transmission register, so the next transmit data can be set. When the “MSB first” is selected in the clock synchronous serial I/O mode, bit position of set data is reversed, and then this data is written into the UARTi transmission buffer register as the transmit data. (Refer to section “8.3.2 Transfer data format.”) Transmit operation itself is the same whichever format is selected, “LSB first” or “MSB first.” When quitting the transmission which is in progress and setting the UARTi transmission buffer register again, follow the procedure described below. À Clear the serial I/O mode selection bits (bits 2 to 0 at addresses 30 16, 3816 and 6416) to “0002.” (Serial I/O is ignored.) \` Set the serial I/O mode selection bits again. ´ Set the transmit enable bit (bit 0 at addresses 3516, 3D16 and 6916) to “1” (in other words, transmission is enabled.) and set the transmit data into the UARTi transmission buffer register.

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8.2.6 UARTi receive register and UARTi receive buffer register

receive buffer register. Fig. 8.2.10 Block diagram for receiver Fig. 8.2.11 Structure of UARTi receive buffer register b7 b0 (b15) (b8) b7 b0 UART0 receive buffer register (addresses 3716, 3616) UART1 receive buffer register (addresses 3F16, 3E16) UART2 receive buffer register (addresses 6B16, 6A16) Bit Not implemented. A value of “0” is read out from here. The receive data is read out from here. At reset Un- defined RWFunctions 8 to 0 15 to 9 RO Clock sync. SPSP PAR 2SP 1SP UART 0000000 RxD i D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP : Stop bit PAR : Parity bit 8-bit UART 9-bit UART 7-bit UART 9-bit UART Clock sync. Clock sync. 7-bit UART 8-bit UART Data bus (even) Data bus (odd) Bit converter UARTi receive register Parity enabled Parity disabled UARTi receive buffer register (Note) Note: The bit converter is not assigned for UART2.

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Receive data (9 bits) Receive data (8 bits) Receive data (7 bits) <UART mode> (Transfer data length : 9 bits) <Clock synchronous serial I/O mode> During UART mode (Transfer data length : 8 bits) During UART mode (Transfer data length : 7 bits) Same value as bit 7 in low-order byte Same value as bit 6 in low-order byte High-order byte (addresses 3716, 3F16, 6B16) Low-order byte (addresses 3616, 3E16, 6A16) The UARTi receive register is used to convert serial data, which is input from the RxDi pin, into parallel data. This register takes a signal which is input from the RxDi pin by the 1 bit synchronously with the transfer clock. The UARTi receive buffer register is used to read receive data. When reception is completed, the receive data which is taken into the UARTi receive register is automatically transferred to the UARTi receive buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data is ready in the UARTi receive register before data which has been transferred to the UARTi receive buffer register is read out (in other words, when an overrun error occurs). When “MSB first” is selected in the clock synchronous serial I/O mode, bit position of data in the UARTi receive buffer register is reversed, and then this data is read out as the receive data. (Refer to section “8.3.2 Transfer data format.”) Receive operation itself is the same whichever format is selected, “LSB first” or “MSB first.” The UARTi receive buffer register is initialized when the receive enable bit (bit 2 at addresses 35 16, 3D16 and 6916) is set to “1” after clearing it to “0.” Figure 8.2.12 shows the contents of the UARTi receive buffer register when reception is completed. Fig. 8.2.12 Contents of UARTi receive buffer register when reception is completed

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8.2.7 UARTi baud rate register (BRGi)

The UARTi baud rate register (BRGi) is an 8-bit timer used only for UARTi. It generates a transfer clock and has a reload register. Assuming that a value set in BRGi is “n” (n = 0016 to FF16), the BRGi divides the count source frequency by (n + 1). In the clock synchronous serial I/O mode, BRGi is valid when an internal clock is selected. At this time, the BRGi’s output divided by 2 is the transfer clock. In the UART mode, the BRGi is always valid. At this time, the BRGi’s output divided by 16 is the transfer clock. When a value is written to addresses 3116, 3916, and 6516, the value is also written to the timer and the reload register whether transmission/reception is in progress or stopped. Therefore, when writing a value to these addresses, be sure to perform it while transmission/reception is stopped. Figure 8.2.13 shows the structure of BRGi and Figure 8.2.14 shows the block diagram of transfer clock generating section. Fig. 8.2.13 Structure of UARTi baud rate register (BRGi) Fig. 8.2.14 Block diagram of transfer clock generating section b7 b0 UART0 baud rate register (address 3116) UART1 baud rate register (address 3916) UART2 baud rate register (address 6516) FunctionsBit At reset RW 7 to 0Values 0016 to FF16 can be set. Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Un- defined WO BRG i 1/2 Transmit control circuit Receive control circuit Transfer clock for transmit operation Transfer clock for receive operation Transmit control circuit Receive control circuit Transfer clock for transmit operation Transfer clock for receive operation BRG i <Clock synchronous serial I/O mode> <UART mode> fi : Clock selected with the BRG count source selection bits (f2, f16, f64, or f512) fEXT : Clock input to the CLKi pin (external clock) fi fEXT fi fEXT

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7 to 4 Not implemented. (Note) RWFunctions 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 Priority is low. 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Priority is high. b2 b1 b0 0: No interrupt has occurred. 1: Interrupt has occurred. b7 b6 b5 b4 b3 b2 b1 b0 A-D/UART2 trans./rece. interrupt control register (address 70 16) UART0 transmission interrupt control register (address 7116) UART0 receive interrupt control register (address 7216) UART1 transmission interrupt control register (address 7316) UART1 receive interrupt control register (addresses 7416) RW RW RW RW Note: When the UART2 function is selected, bit 3 of the A-D conversion/UART2 trans./rece. interrupt control register is set to “1.” Accordingly, before enabling interrupts, write value “0” to this bit.

8.2.8 Interrupt control register related to UARTi

When UARTi is used, the following interrupts can be used: UARTi transmission interrupt and UARTi reception interrupt. Each interrupt has its corresponding interrupt control register. However, in UART2, an interrupt for transmission and an interrupt for reception are controlled with the same register. Figure 8.2.15 shows the structure of interrupt control registers related to UARTi. For details about interrupts, refer to chapter “4 Interrupts.” The UART2 transmission/reception interrupt and the A-D conversion interrupt share the same interrupt vector addresses and interrupt control register. Switching between the A-D conversion interrupt and the UART2 transmission/reception interrupt is performed with bits 2 to 0 of the UART2 transmission/reception mode register. (Refer to Figure 8.2.3.) Fig. 8.2.15Structure of interrupt control registers related to UARTi

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(1) Interrupt priority level selection bits (bits 2 to 0) These bits are used to select the priority level of the UARTi transmission interrupt or UARTi reception interrupt. When using the UARTi transmission/reception interrupt, select one of priority levels 1 to 7. When a UARTi transmission/reception interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL) and the requested interrupt is enabled only when its priority level is higher than the IPL. (Note that this is applied when the interrupt disable flag (I) = “0.”) When these bits are set to “000 2” (level 0), the UARTi transmission/reception interrupt is disabled. (2) Interrupt request bit (bit 3) The UARTi transmission interrupt request bit is set to “1” when data is transferred from the UARTi transmission buffer register to the UARTi transmission register. The UARTi reception interrupt request bit is set to “1” when data is transferred from the UARTi receive register to the UARTi receive buffer register. Note that these bits do not change when an overrun error occurs. When each interrupt request is accepted, the corresponding interrupt request bit is automatically cleared to “0.” Note that each bit can be set to “1” or cleared to “0” by software.

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8.2.9 Ports P7 and P8 direction registers

I/O pins of UARTi are multiplexed with ports P7 and P8. When using the P74, P82 and P86 pins as serial data input pins (RxDi), set the corresponding bits of the ports P7 and P8 direction registers to “0” to set these ports for the input mode. When using the P72 pin as the CTS 2 input pin, set bit 2 of the port P7 direction register to “0” to set this port for the input mode. When using the P73, P75, P80, P81, P83–P8 5, and P87 pins as UARTi’s I/O pins (CTSi/RTSi, CLKi, TxDi), these pins are forcibly set as the UARTi’s I/O pins, regardless of the ports P7 and P8 direction register’s contents. Also, as for CLKS0 and CLKS 1, refer between the ports P7, P8 direction registers and UARTi’s I/O pins. Note that the functions of the UARTi’s I/O pins can be switched by software. For details, refer to the description of each operating mode. Bit Corresponding pin name Functions Pin P74/AN4/RxD2 Pin P76/AN6/XCOUT 0: Input mode 1: Output mode When using pin P72 as the CTS 2 input pin and using pin P74 as serial data’s input pin (RxD2), set the corresponding bit to “0.”Pin P75/AN5/AD TRG /TxD2 Port P7 direction register (address 1116) b1 b0b2b3b4b5b6b7 Pin P70/AN0 Pin P72/AN2/CTS 2 Pin P73/AN3/CLK2 Pin P71/AN1 Pin P77/AN7/XCIN At reset RW Pin P80/CTS 0/RTS 0/CLKS1 Pin P82/RxD0/CLKS0 Pin P83/TxD0 Pin P84/CTS 1/RTS 1 Pin P86/RxD1 Pin P85/CLK1 Port P8 direction register (address 1416) b1 b0b2b3b4b5b6b7 Pin P81/CLK0 Pin P87/TxD1 RW Not used for serial I/O Corresponding pin name FunctionsBit At reset 0: Input mode 1: Output mode When using pins P82 and P86 as serial data’s input pins (RxD0, RxD1), set the corresponding bits to “0.” RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Note: For pins CLKS0 and CLKS1, refer to section “8.3.1 (4) Number of transfer clock output pins (UART0).” Fig. 8.2.16 Relationship between ports P7, P8 direction register and UARTi’s I/O pins

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____ Note: The RTS function is not assigned for UART2. Table 8.3.2 Functions of I/O pins in clock synchronous serial I/O mode

8.3 Clock synchronous serial I/O mode

Table 8.3.1 lists the performance overview in the clock synchronous serial I/O mode and Table 8.3.2 lists the functions of I/O pins in this mode. Table 8.3.1 Performance overview in clock synchronous serial I/O mode Item Transfer data format Transfer rate Transmit/Receive control Functions Transfer data has a length of 8 bits. LSB first or MSB first is selected by software. BRGi’s output divided by 2 Maximum of 5 Mbps CTS function or RTS function is selected by software (Note). When internal clock is selected When external clock is selected Pin name TxDi (P8 3, P87, P75) RxDi (P8 2, P86, P74) CLKi (P8 1, P85, P73) CTS 0/RTS 0 (P80), CTS 1/RTS 1 (P84) (Note 1) CTS 2 (P72) Functions Serial data output Serial data input Transfer clock output Transfer clock input ____ CTS input ____ RTS output Programmable I/O port ____ CTS input Programmable I/O port Method of selection (They output dummy data when only reception is performed.) Ports P7 and P8 direction registers’ corresponding bits =“0” (They can be used as input ports when only transmission is performed.) Internal/External clock selection bit = “0” Internal/External clock selection bit = “1” CTS /RTS enable bit = “0” CTS /RTS function selection bit = “0” CTS /RTS enable bit = “0” CTS /RTS function selection bit = “1” CTS /RTS enable bit = “1” ____ CTS enable bit = “0” ____ CTS enable bit = “1” Port P7 direction register: Address 1116 Port P8 direction register: Address 1416 Internal/External clock selection bit: Bit 3 at addresses 3016, 3816, and 6416 CTS /RTS enable bit: Bit 4 at addresses 3416 and 3C16 CTS /RTS function selection bit: Bit 2 at addresses 3416 and 3C16 ____ CTS enable bit: Bit 2 at address 6816 h The TxDi pin outputs “H” level from when a UARTi’s operating mode is selected until transfer starts. (The TxDi pin is in a floating state when N-channel open-drain output is selected.) h In UART0, multiple transfer clock output pins can be used. (Refer to Table 8.3.3.) ____ Notes 1: The RTS function is not assigned for UART2. 2: As for CLKS0 and CLKS 1, refer to section “8.3.1 (4) Number of transfer clock output pins (UART0).”

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8.3.1 Transfer clock (sync clock)

Data is transferred synchronously with the transfer clock. For the transfer clock, the following items can be specified: l Whether to generate the transfer clock internally or to input it from the external. l Polarity of a clock which is output from the CLKi pin (UART0, UART1) l Number of transfer clock output pins (UART0). Note that the transfer clock is generated while the transmit control circuit is operating. Therefore, even when performing only reception, set the transmit enable bit to “1” and make the transmit control circuit operate by setting dummy data into the UARTi transmission buffer register. (1) How to generate transfer clock internally A count source is selected with the BRG count source selection bits. The count source is divided in the BRGi, and then the BRGi’s output is further divided by 2. (In this way, the transfer clock is generated.) This transfer clock is output from the CLKi pin. [Setting for related registers] l An internal clock is selected (bit 3 at addresses 3016, 3816, and 6416 = “0”). l The BRGi’s count source is selected (bits 1 and 0 at addresses 3416, 3C16, and 6816). l A value of “divide value – 1” (= n: 0016 to FF16) is set into the BRGi (addresses 3116, 3916, and 6516). Transfer clock’s frequency = fi: BRGi’s count source frequency (f2, f16, f64, and f512) l Transmission is enabled (bit 0 at addresses 3516, 3D16, and 6916 = “1”). l Data is set into the UARTi transmission buffer register (addresses 3216, 3A16, and 6616) [Pin status] l Transfer clock is output from the CLKi pin. l Serial data is output from the TxDi pin. (Dummy data is output when only reception is performed.) (2) How to input transfer clock from the external A clock which is input from the CLKi pin is the transfer clock. [Setting related registers] l An external clock is selected (bit 3 at addresses 30 l Transmission is enabled (bit 0 at addresses 3516, 3D16, and 6916 = “1”). l Data is set into the UARTi transmission buffer register (addresses 3216, 3A16, 6616). [Pin status] l Transfer clock is input from the CLKi pin. l Serial data is output from the TxDi pin. (Dummy data is output when only reception is performed.) fi 2 (n+1)

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D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1 D 2 D 3 D 4 D 5 D 6 D 7 TXD i R XD i CLK i D 0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1 D 2 D 3 D 4 D 5 D 6 D 7 TXD i R XD i CLK i D 0 D 0 When CLK polarity selection bit = “1.” h The transmit data is output to the TxDi pin at the rising edge of the transfer clock; the receive data is input from the RxDi pin at the falling edge of the transfer clock. When not transferring, the CLKi pin’s level is “L.” When CLK polarity selection bit = “0.” h The transmit data is output to the TxDi pin at the falling edge of the transfer clock; the receive data is input from the RxDi pin at the rising edge of the transfer clock. When not transferring, the CLKi pin’s level is “H.” (3) How to select polarity of transfer clock The polarity of a clock which is output from the CLKi pin can be selected with the CLK polarity selection bit (UART0, UART1) as shown in Figure 8.3.1. The CLK polarity select bit is not implemented for UART2. The CLK 2 pin outputs the transmit data at the fall of the transfer clock; this pin inputs the receive data at the rise of the transfer clock. [Setting for related registers] l The CLK polarity is selected (bit 6 at addresses 3416, 3C16). Fig. 8.3.1 Polarity of transfer clock

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Note: This is applied when the following conditions are satisfied:

• Only transmission is performed.
• Clock synchronous serial I/O mode is selected.
• An internal clock is selected. (4) Number of transfer clock output pins (UART0) Only in UART0, when an internal clock is selected, one pin can be selected as the transfer clock output pin from the following pins: CLK0, CLKS0 (in common with RxD0), and CLKS1 (in common with CTS 0/RTS 0). By this selection, data can be transmitted to the maximum of three external receiving devices. (Refer to À in Table 8.3.4). In this case, since the RxD0 and CTS 0/RTS 0 pins function as the transfer clock output pins (CLK0, CLKS1), the CTS /RTS function and reception are disabled. When only the CLK0 and CLKS 0 pins are used as the transfer clock output pins, the P80 (CTS 0/RTS 0/ CLKS 1) pin can be used as a programmable I/O port. (Refer to \ in Table 8.3.4.) Also, when the CLK0 and CLKS 1 pins are used as the transfer clock output pins and bit 2 of the port P8 direction register is set to “0,” data can be received from the RxD0 pin. (Refer to ´ in Table 8.3.4.) [Setting for related registers] l An internal clock is selected (bit 3 at address 3016 = “0”). l The CTS /RTS function is disabled (bit 4 at address 3416 = “1”). l Reception is disabled (bit 2 at address 3516 = “0”). (Refer to À and \ in Table 8.3.4.) l Number of transfer clock output pins is selected. (bits 5 and 4 at address 6E16; Refer to Table 8.3.3.) l Conditions for “output when not transferring” (described later) are set. (CLKS 0: bit 2 at address 1416 = “1”: CLKS 1: bit 0 at address 1416 = “1,” bit 0 at address 1216 = level at “output when not transferring”) [Pin status] Refer to Table 8.3.3. Table 8.3.3 Pin functions when one transfer clock output pin is selected Transfer clock output pin selection bits Number of pins from which one transfer clock output pin is selected Selectable TxD 0 (P83) Outputs serial data. CLK 0 (P81) Outputs transfer clock. Outputs transfer clock. Output when not transferring* Output when not transferring* RxD 0/CLKS 0 (P82) Programmable I/O port h Outputs transfer clock. h Output when not transferring*: When the CLK polarity selection bit (bit 6 at address 3416) = “0,” the CLK0 pin outputs “H” level; when this bit = “1,” the CLK0 pin outputs “L” level. h When bit 2 at address 1416 (port P8 direction register) = “0,” the RxD0/CLKS 0 pin is in a floating state; when this bit = “1,” the RxD0/CLKS 0 pin do the processing of “output when not transferring.” Functions Fig. 8.3.2 Connection example when one transfer clock output pin is selected from three pins CTS 0/RTS 0/CLKS 1 (P80) Programmable I/O port Programmable I/O port Programmable I/O port Outputs transfer clock.

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[Switching of transfer clock output pin] When the transfer clock output pin is switched while transmission is enabled, follow the procedure described below. Transmission starts when step ´ is executed: À Check whether the previous transfer is completed or not. (Refer to Figure 8.3.6.) \` If the previous transfer has been completed, change the contents of the transmit clock output pin selection bit. ´ Set the transmit data. For usage examples, refer to section “17.2.2 Examples of transmission for several peripheral ICs (Clock synchronous serial I/O mode).” Table 8.3.4 Number of channels for serial I/O transmission/reception for the case where multiple transfer clock output pins are used Pin CTS 0/RTS 0/CLKS 1 (P80) CLK 0 (P81) RxD 0/CLKS 0 (P82) TxD 0 (P83)

• Number of channels for serial I/O transmission/ reception
• Status of transmit clock output pin selection bits (b5, b4) Setting example Outputs transfer clock. Outputs transfer clock. Receives data. Transmits data. 1 channel for transmission CLKS TxD 0 1 channel for transmission/reception CLK 0 RxD 0 TxD 0 Programmable I/O port Outputs transfer clock. Outputs transfer clock. Transmits data. 2 channels for transmission CLK TxD 0 CLKS 0 TxD 0 À Outputs transfer clock. Outputs transfer clock. Outputs transfer clock. Transmits data. 3 channels for transmission CLKS TxD 0 CLK 0 TxD 0 CLKS 0 TxD 0 (1, 1) (0, 1) (1, 0) (0, 1) (1, 0) (1, 1) (0, 1) Note: Set bit 2 at address 1416 (port P8 direction register) to “0.”

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Transfer data format When data is written to UARTi transmission buffer register When data is read from UARTi receive buffer register LSB (Least Significant Bit) first Data bus UARTi transmission buffer register Data bus UARTi receive buffer register MSB (Most Significant Bit) first Data bus UARTi transmission buffer register Data bus UARTi receive buffer register

8.3.2 Transfer data format

LSB-first or MSB-first can be selected (UART0, UART1). Table 8.3.5 lists the relationship between the transfer data format and the way to write/read to and from the UARTi transmission/receive buffer register. By setting the transfer format selection bit (bit 7 at addresses 3416, 3C16), transfer data format can be selected. When this bit is cleared to “0,” the set data is written to the UARTi transmission buffer register as the transmit data. Similarly, the data in the UARTi receive buffer register is read out as the receive data. (Refer to the upper row in Table 8.3.5.) When this bit is set to “1,” each bit’s position of the set data is reversed, and then this data is written to the UARTi transmission buffer register as the transmit data. Similarly, each bit’s position of data in the UARTi receive buffer register is reversed, and then this data is read out as the receive data. (Refer to the lower row in Table 8.3.5.) Note that only the way to write/read to and from the UARTi transmission/receive buffer register is affected by the transfer data format. The transmit/receive operation is unaffected. The transfer data format for UART2 is fixed to “LSB-first.” Table 8.3.5 Relationship between transfer data format and way to write/read to and from UARTi transmission/receive buffer register

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8.3.3 Method of transmission

is started when all of the following conditions (À to ´ ) are satisfied. When an external clock is selected, satisfy conditions À to ´ with the following preconditions satisfied. [Preconditions for UART0 and UART1]

• The CLKi pin’s input is at “H” level. (When an external clock is selected and the CLK polarity selection bit = “0.”)
• The CLKi pin’s input is at “L” level. (When an external clock is selected and the CLK polarity selection bit = “1.”) Note: When an internal clock is selected, the above preconditions are ignored. [Preconditions for UART2]
• The CLKi pin’s input is at “H” level. (When an external clock is selected) Note: When an internal clock is selected, the above precondition is ignored. À Transmit enable state (transmit enable bit = “1”) \` Transmit data is present in the UARTi transmission buffer register (transmission buffer empty flag = “0”). ´ The CTSi pin’s input is at “L” level (when the CTS function is selected) ____ Note: When the CTS function is not selected or in UART2, this condition is ignored. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched (UART0, UART1). For details, refer to section “8.3.6 Receive operation.” When using interrupts, settings for enabling interrupts are required. For details, refer to chapter “4. Interrupts.” Figure 8.3.5 shows how to write data after transmission is started and Figure 8.3.6 shows how to detect the transmit completion.

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Multiple transfer clock output pins can be selected when performing only transmission with an internal clock selected in UART0. In this case, the CTS function cannot be used. 0 0: One transfer clock output pin 0 1: 1 0: Multiple transfer clock output pins 1 1: The CTS / RTS function selection bit is valid when the CTS / RTS enable bit = “0.” Note 2: 1000 UART0 transmit/receive mode register (address 3016) UART1 transmit/receive mode register (address 3816) UART2 transmit/receive mode register (address 6416) b7 b0 Internal/External clock selection bit 0: Internal clock 1: External clock : It may be “0” or “1.” 555 Clock synchronous serial I/O mode h Continued to “Initial setting example for related registers when transmitting (2)” on the next page UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) b7 b0 BRG count source selection bits CTS / RTS function selection bit (Note 2) 0: The CTS function is selected. 1: The RTS function is selected. (CTS function is disabled.) CTS / RTS enable bit 0: The CTS / RTS function is enabled. 1: The CTS / RTS function is disabled. Data output selection bit 0: TXD i pin is set for CMOS output. 1: TXD i pin is set for N-channel open-drain output. CLK polarity selection bit 0: At the falling edge of the transfer clock, transmit data is output. 1: At the rising edge of the transfer clock, transmit data is output. Transfer format selection bit 0: LSB first 1: MSB first Clocks f 2, f 16, f 64, and f 512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b1 b0 b7 b0 Transmission clock output pin selection bits Serial transmit control register (address 6E16) b5 b4 UART2 transmit/receive control register 0 (address 6816) b7 b0 BRG count source selection bits CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled (I/O port). 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b1 b0 Note 1: Nothing is implemented to bit 7 of UART2 transmit/receive mode register. Fig. 8.3.3 Initial setting example for related registers when transmitting (1)

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UART0 transmission buffer register (address 3216) UART1 transmission buffer register (address 3A16) UART2 transmission buffer register (address 6616) b7 b0 Transmit data is set here. Transmission is started. UART0 baud rate register (BRG0) (address 3116) UART1 baud rate register (BRG1) (address 3916) UART2 baud rate register (BRG2) (address 6516) b7 b0 A value from 0016 to FF16 is set. h Necessary only when internal clock is selected. Port P8 register (address 1216) b7 b0 Set the output level of CLKS1 pin when not transferring 0: “L” (when clock polarity selection bit = “1”) 1: “H” (when clock polarity selection bit = “0”) UART0 transmission interrupt control register (address 7116) UART1 transmission interrupt control register (address 7316) A-D/UART2 trans./rece. interrupt control register (address 7016) b7 b0 Interrupt priority level selection bits When using interrupts, one of level 1 to 7 must be set. When disabling interrupts, level 0 must be set. Continued from “Initial setting example for related registers when transmitting (1)” on the preceding page (If the CTS function is selected, transmission is started when the CTS i pin’s input level is “L.”) Port P8 direction register (address 1416) b7 b0 1515 CLKS1 pin CLKS0 pin h 1 h 2 h 1: Set this bit only when the number of the transfer clock output pins is 3. h 1 5 : It may be “0” or “1.” h 2: Set this bit only when the number of the transfer clock output pins is 2 or 3. UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 Transmit enable bit 1: Transmission is enabled. Fig. 8.3.4 Initial setting example for related registers when transmitting (2)

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[When not using interrupts] [When using interrupts] A UARTi transmission interrupt request occurs when the UARTi transmission buffer register becomes empty.UARTi transmission interrupt h UART0 transmission buffer register (address 3216) UART1 transmission buffer register (address 3A16) UART2 transmission buffer register (address 6616) b7 b0 Writing of next transmit data Transmit data is set here. UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) Transmission buffer empty flag 0: Data is present in the transmission buffer register. 1: No data is present in the transmission buffer register. (Next transmit data can be written.) Checking status of the UARTi transmission buffer register This diagram indicates bits and registers required for processing. Refer to Figure 8.3.8 for details about the change of flag status and the occurrence timing of an interrupt request. Fig. 8.3.5 How to write data after transmission is started

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[When not using interrupts] [When using interrupts] UARTi transmission interrupt h UART0 transmission interrupt control register (address 7116) UART1 transmission interrupt control register (address 7316) A-D/UART2 trans./rece. interrupt control register (address 7016) b7 b0 Interrupt request bit Checking the start of transmission UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) UART2 transmit/receive control register 0 (address 6816) b7 b0 Checking the completion of transmission Transmission register empty flag 0: Transmission is in progress. 1: Transmission is completed. Processing at completion of transmission No interrupt request has occurred. Interrupt request has occurred. (Transmission has been started.) A UARTi transmission interrupt request occurs when the transmission is started. This diagram indicates bits and registers required for processing. Refer to Figure 8.3.8 for details about the change of flag status and the occurrence timing of an interrupt request. Note: Nothing is allocated to bits 7 to 4 of the UART2 transmit/receive control register 0. Fig. 8.3.6 How to detect of transmit completion

7733 Group User’s Manual8–32

8.3.4 Transmit operation

When the transmit conditions described in section “8.3.3 Method of transmission” are satisfied while an internal clock is selected, the transfer clock is generated. And then, the following operations are automatically performed after one cycle of the transfer clock has passed. When the transmit conditions are satisfied and the external clock is input to the CLKi pin while the external clock is selected, the following operations are automatically performed. l The UARTi transmission buffer register’s contents is transferred to the UARTi transmission register. l The transmission buffer empty flag is set to “1.” l The transmission register empty flag is cleared to “0.” l A UARTi transmission interrupt request occurs and the interrupt request bit is set to “1.” l Eight transfer clocks are generated (when an internal clock is selected). The transmit operation is described below. À Data in the UARTi transmission register is transmitted from the TxDi pin synchronously with the valid edge h of the CLKi pin’s clock. \` This data is transmitted bit by bit sequentially beginning with the least significant bit (LSB). ´ When one byte of data has been transmitted, the transmission register empty flag is set to “1.” This indicates the completion of transmission. Valid edgeh : In UART0 and UART1, this means the falling edge when the CLK polarity selection bit = “0” and the rising edge when the CLK polarity selection bit = “1”; in UART2, this means the rising edge. Figure 8.3.7 shows the transmit operation. When an internal clock is selected, if the transmit conditions for the next data are satisfied at completion of transmission, the next transfer clock is generated immediately. Accordingly, when performing transmission in succession, set the next transmit data to the UARTi transmission buffer register during transmission (when the transmission register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the transfer clock stops at “H” level when the CLK polarity selection bit = “0,” and it stops at “L” level when the CLK polarity selection bit = “1.” ____ Figure 8.3.8 shows an example of transmit timing (when an internal clock and the CTS function are selected).

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Fig. 8.3.7 Transmit operation ____ Fig. 8.3.8 Example of transmit timing (when internal clock and CTS function are selected) CLKi pin’s clock UARTi transmission buffer register D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 7 D 6 D 5 D 4 D 3 D 2 D 7 D 6 D 5 D 4 D 3 Transmit data MSB b7 b0 D 0 D 1 D 2 D 7 LSB h UARTi transmission register This is applied when the CLK polarity selection bit = “0.” When the CLK polarity selection bit = “1,” data is shifted at the rising edge of the transfer clock of CLKi pin. D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc TCLK CTS i CLK i TEND i TxD i “H” “L” “0” “1” “0” “1” “0” “1” “0” “1” Data is set in UARTi transmission buffer register. Transmit enable bit Transmission buffer empty flag Transfer clock Stopped because CTSi pin’s level = “H” UARTi transmission register‹ UARTi transmission buffer register The above timing diagram is applied when the following conditions are satisfied:

• Internal clock is selected. CTS function is selected. CLK polarity selection bit = “0.” UARTi transmit interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Transmission register empty flag Stopped because transmit enable bit = “0” TENDi : Next transmit conditions are checked when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1)/fi fi: BRGi’s count source frequency (f2, f16, f64, or f512) n: Value set to BRGi

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____ Fig. 8.3.9 Example of transmit timing (when internal clock is selected and CTS function is not selected) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc TCLK CLK i TEND i TxD i “0” “1” “0” “1” “0” “1” “0” “1” D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 Data is set in UARTi transmission buffer register. Transmit enable bit Transmission buffer empty flag Transfer clock UARTi transmission register‹ UARTi transmission buffer register The above timing diagram is applied when the following conditions are satisfied: œ Internal clock is selected. œ CTS function is not selected. œ CLK polarity selection bit = “0.” TENDi : Next transmit conditions are checked when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1)/fi fi: BRGi’s count source frequency (f2, f16, f64, or f512) n: Value set to BRGi UARTi transmit interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Transmission register empty flag Stopped because transmit enable bit = “0”

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8.3.5 Method of reception

started when all of the following conditions (À to ´ ) are satisfied. When an external clock is selected, satisfy conditions À to ´ with the following preconditions satisfied. [Preconditions for UART0 and UART1]

• The CLKi pin’s input is at “H” level. (When an external clock is selected and the CLK polarity selection bit = “0.”)
• The CLKi pin’s input is at “L” level. (When an external clock is selected and the CLK polarity selection bit = “1.”) Note: When an internal clock is selected, the above preconditions are ignored. [Preconditions for UART2]
• The CLKi pin’s input is at “H” level. (When an external clock is selected) Note: When an internal clock is selected, the above precondition is ignored. À Receive enable state (receive enable bit = “1”) \` Transmit enable state (transmit enable bit = “1”) ´ Dummy data is present in the UARTi transmission buffer register (transmission buffer empty flag = “0”). By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched (UART0, UART1). For details, refer to section “8.3.6 Receive operation.” When using interrupts, settings for enabling interrupts are required. For details, refer to chapter “4. Interrupts.” Figure 8.3.12 shows the processing after reception is completed.

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h Necessary only when an internal clock is selected. UART0 baud rate register (BRG0) (address 3116) UART1 baud rate register (BRG1) (address 3916) UART2 baud rate register (BRG2) (address 6516) b7 b0 A value from 0016 to FF16 is set. Notes 2: The CTS / RTS function selection bit is valid when the CTS / RTS enable bit = “0.” The RTS function is ignored when an internal clock is selected. 3: The RTS output function is not assigned for UART2. 1000 UART0 transmit/receive mode register (address 3016) UART1 transmit/receive mode register (address 3816) UART2 transmit/receive mode register (address 6416) b7 b0 Internal/External clock selection bit 0: Internal clock 1: External clock : It may be “0” or “1.”5 555 Clock synchronous serial I/O mode Continued to “Initial setting example for related registers when receiving (2)” on the next page UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) b7 b0 BRG count source selection bits CTS / RTS function selection bit (Note 2) 0: The CTS function is selected. (The RTS function is disabled.) 1: The RTS function is selected. CTS / RTS enable bit 0: The CTS / RTS function is enabled. 1: The CTS / RTS function is disabled. CLK polarity selection bit 0: The receive data is input at the rising edge of the transfer clock. 1: The receive data is input at the falling edge of the transfer clock. Transfer format selection bit 0: LSB first 1: MSB first Clocks f2 , f16, f64, and f512 : Refer to chapter “14. CLOCK GENERATING CIRCUIT.” 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b1b0 Notes 1: Nothing is implemented to bit 7 of the UART2 transmit/receive mode register. UART2 transmit/receive control register 0 (address 6816) b7 b0 BRG count source selection bits CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled (I/O port). 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b1b0 Fig. 8.3.10 Initial setting example for related registers when receiving (1)

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Port P8 direction register (address 1416) b7 b0 R XD 0 pin R XD 1 pin Continued from “Initial setting example for related registers when receiving (1)” on the proceeding page UART0 receive interrupt control register (address 7216) UART1 receive interrupt control register (address 7416) A-D/UART2 trans./rece. interrupt control register (address 7016) b7 b0 Interrupt priority level selection bits When using interrupts, one of level 1 to 7 must be set. When disabling interrupts, level 0 must be set. UART0 transmission buffer register (address 3216) UART1 transmission buffer register (address 3A16) UART2 transmission buffer register (address 6616) b7 b0 Dummy data is set. UART0 transmit/receive control register 1(address 3516) UART1 transmit/receive control register 1(address 3D16) UART2 transmit/receive control register 1(address 6916) b7 b0 Transmit enable bit (Note 2) 1: Transmission is enabled. Receive enable bit (Note 2) 1: Receptipn is enabled. Reception is started. Notes 2: Set the receive enable bit and the transmit enable bit to “1” simultaneously. Port P7 direction register (address 1116) b7 b0 R XD 2 pin (Note 1) Notes 1: In the 7733 Group or the 7735 Group, set this bit. In the 7736 Group, it is not necessary to set this bit. Fig. 8.3.11 Initial setting example for related registers when receiving (2)

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[When not using interrupts] [When using interrupts] A UARTi receive interrupt request occurs when reception is completed. UARTi receive interrupt This diagram indicates bits and registers required for processing. Refer to Figure 8.3.15 for details about the change of flag status and the occurrence timing of an interrupt request. Processing after reading out receive data UART0 receive buffer register (address 3616) UART1 receive buffer register (address 3E16) UART2 receive buffer register (address 6A16) b7 b0 Reading of the receive data Receive data is read out. UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 Receive completion flag 0: Reception is not completed. 1: Reception is completed. Checking the completion of reception UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 Checking the error Overrun error flag 0: No overrun error is detected. 1: Error is detected. h Fig. 8.3.12 Processing after reception is completed

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8.3.6 Receive operation

When the receive conditions described in section “8.3.5 Method of reception” are satisfied while an internal clock is selected, the transfer clock is generated. And then, the receive is started after one cycle of the transfer clock has passed. When the receive conditions are satisfied while the external clock is selected, UARTi is in the reception enabled state. Then, the external clock is input to the CLKi pin and reception is started. In UART0 and UART1, when the RTS function is selected with an external clock selected, the RTSi pin’s output level is “L,” and the microcomputer informs the transmitter side that reception is enabled. When reception is started, the RTSi pin’s output level is “H.” Accordingly, by connecting the RTSi pin to the CTSi pin of the transmitter side, the timing of transmission and that of reception can be matched. When an internal clock is selected, do not use the RTS function because the RTSi output is undefined. Figure 8.3.13 shows a connection example. ____ The RTS output function is not assigned for UART2. The receive operation is described below. À The signal which is input from the RxDi pin is taken in the most significant bit of the UARTi receive register synchronously with the valid edgeh of the clock which is output from the CLKi pin or input to the CLKi pin. \ The contents of the UARTi receive register is shifted by 1 bit to the right. ´ Operations À and \ are repeated at each valid edge of the clock which is output from the CLKi pin or input to the CLKi pin. ˆ When one byte of data is prepared in the UARTi receive register, the contents of this register is transferred to the UARTi receive buffer register. ˜ Simultaneously with ˆ , the receive completion flag is set to “1.” At this time, a receive interrupt request occurs, and then an interrupt request bit is set to “1.” Valid edgeh : In UART0 and UART1, this means the rising edge when the CLK polarity selection bit = “0” and the falling edge when the CLK polarity selection bit = “1”; in UART2, this means the rising edge. The receive completion flag is cleared to “0” when the low-order byte of the UARTi receive buffer register ____ is read out. The RTSi pin continues to output “H” level until the receive conditions are next satisfied (when ____ example of receive timing (when an external clock is selected). When the contents of the UARTi receive buffer register is read out with the transfer format selection bit = “1” (MSB first), each bit’s position of this register’s contents is reversed and the resultant data is read out (UART0, UART1).

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RTS i (Note) Transmitter side Receiver side Note: The RTSi output function is not assigned for Clock which is output from or input to CLKi pin UARTi receive buffer register UARTi receive register c D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 0 D 1 D 0 Receive data c MSB b7 b0 LSB D 2 D 1 D 0 h This is applied when the CLK polarity selection bit = “0.” When the CLK polarity selection bit = “1,” data is shifted at the falling edge of the clock which is output from or input to the CLKi pin. Fig. 8.3.14 Receive operation Fig. 8.3.13 Connection example

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(Note) RTSi CLK i RxD i “H” “L” “0” “1” “0” “1” “0” “1” “0” “1” “0” “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 Dummy data is set in UARTi transmission buffer register. Transmit enable bit Transmission buffer empty flag Receive completion flag Receive enable bit Received data is taken in. UARTi transmission register ‹ UARTi transmission buffer register UARTi receive buffer register is read out. The above timing diagram is applied when the following conditions are satisfied: œ External clock is selected. œ RTS function is selected. œ CLK polarity selection bit = “0.” fEXT : Frequency of external clock When the CLKi pin’s input level is “H,” satisfy the following conditions: œ Transmit enable bit fi “1” œ Receive enable bit fi “1” œ Writing of dummy data to UARTi transmission buffer register UARTi receive register fi UARTi receive buffer register UARTi receive interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Note: The RTSi output function is not assigned for UART2. Fig. 8.3.15 Example of receive timing (when external clock is selected)

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8.3.7 Processing when an overrun error is detected

In the clock synchronous serial I/O mode, an overrun error can be detected. An overrun error occurs when the next data is prepared in the UARTi receive register with the receive completion flag = “1” (in other words, data is present in the UARTi receive buffer register), and then the next data is transferred to the receive buffer register. In other words, when the next data is prepared before the contents of the UARTi receive buffer register is read out, an overrun error occurs. When an overrun error occurs, the next data is written into the UARTi receive buffer register. At this time, the UARTi receive interrupt request bit does not change. An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register. At this time, the overrun error flag is set to “1.” The overrun error flag is cleared to “0” when the serial I/O mode selection bits are cleared to “000 2” or when the receive enable bit is cleared to “0.” When an overrun error occurs during reception, initialize the overrun error flag and the UARTi receive buffer register, and then perform reception again. When it is necessary to perform transmission owing to an overrun error which occurs in the receiver side, set the UARTi transmission buffer register again, and then starts transmission again. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmission buffer register again are described below. (1) Method of Initializing UARTi receive buffer register À Clear the receive enable bit to “0.” (Reception is disabled.) \ Set the receive enable bit to “1” again. (Reception is enabled.) (2) Method of setting UARTi transmission buffer register again À Clear the serial I/O mode selection bits to “000 2.” (Serial I/O is ignored.) \ Set the serial I/O mode selection bits to “0012” again. ´ Set the transmit enable bit to “1.” (Transmission is enabled.) And set the transmit data to the UARTi transmission buffer register.

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8.3.8 Precautions for clock synchronous serial I/O

1. The transfer clock is generated by the operation of the transmit control circuit. Accordingly, even when performing only reception, the transmit operation (setting for transmission) must be performed. In this case, dummy data is output from the TxDi pin to the external. 2. When an internal clock is selected during reception, the transfer clock is generated if the following conditions are satisfied:

• The transmit enable bit is set to “1.” (Transmission is enabled.)
• Dummy data is set to the UARTi transmission buffer register. When an external clock is selected during reception, the transfer clock is generated if the following conditions are satisfied:
• The transmit enable bit is set to “1.”
• A clock is input to the CLKi pin after dummy data is set to the UARTi transmission buffer register. 3. When an external clock is selected, make sure that the following conditions are satisfied with the CLKi pin’s input level = “H” if the CLK polarity selection bit = “0” or with the CLKi pin’s input level = “L” if the CLK polarity selection bit = “1”: [At transmitting] À Set the transmit enable bit to “1.” \ Write the transmit data to the UARTi transmission buffer register. ´ Input “L” level to the CTSi pin (when CTS function is selected). [At receiving] À Set the receive enable bit to “1.” \ Set the transmit enable bit to “1.” ´ Write dummy data to the UARTi transmission buffer register. 4. When receiving data in succession, set dummy data to the low-order byte of the UARTi transmission buffer register each time when 1-byte data is received. 5. For performing the transmission and the reception simultaneously, UART2 does not distinguish the transmission interrupt from the reception interrupt. The UART2 transmission/reception interrupt request occurs when either interrupt request occurs. Accordingly, in the system which performs the transmission and reception simultaneously for UART2, not use the UART2 transmission/reception interrupt but use the method of poling the transmission buffer empty flag and the receive completion flag by software.

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8.4 Clock asynchronous serial I/O (UART) mode

Table 8.4.1 lists the performance overview in the UART mode and Table 8.4.2 lists the functions of I/O pins in this mode. Table 8.4.1 Performance overview in UART mode Functions 1 bit 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (Odd or Even can be selected.) 1 bit or 2 bits BRGi’s output divided by 16 (Maximum of 781.25 kbps (Note)) Maximum of 312.5 kbps 4 types (Overrun, Framing, Parity, and Summing) Presence of error can be detected only by checking error sum flag. Item Start bit Character bit (Transfer data) Parity bit Stop bit When internal clock is selected When external clock is selected Transfer data format Transfer rate Error detection Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = “0” and the system clock frequency = 25 MHz (f(f2) = 12.5 MHz). (For details, refer to chapter “14. CLOCK GENERATING CIRCUIT.” Table 8.4.2 Functions of I/O pins in UART mode Pin name TxDi (P83, P87, P75) RxDi (P8 2, P86, P74) CLKi (P8 1, P85, P73) CTSi/RTSi (Note) (P80, P84) CTS 2 (P72) Functions Serial data output Serial data input Programmable I/O port BRGi count source input ____ CTS input ____ RTS output Programmable I/O port ____ CTS input Programmable I/O port Method of selection (They cannot be used as programmable I/O ports.) Ports P7 and P8 direction register’s corresponding bit = “0” (They can be used as input ports when only transmission is performed.) Internal/External clock selection bit = “0” Internal/External clock selection bit = “1” CTS /RTS enable bit = “0” CTS /RTS function selection bit = “0” CTS /RTS enable bit = “0” CTS /RTS function selection bit = “1” CTS /RTS enable bit = “1” ____ CTS enable bit = “0” ____ CTS enable bit = “1” Port P7 direction register: Address 1116 Port P8 direction register: Address 1416 Internal/External clock selection bit: Bit 3 at addresses 3016, 3816, and 6416 CTS /RTS enable bit: Bit 4 at addresses 3416 and 3C16 CTS /RTS function selection bit: Bit 2 at addresses 3416 and 3C16 ____ CTS enable bit: Bit 2 at addresses 6816 h The TxDi pin outputs “H” level while not transmitting after a UARTi’s operating mode is selected. (The TxDi pin is in a floating state when N-channel open-drain output is selected.) ____ Note: The RTSi output function is not assigned for UART2.

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8.4.1 Transfer rate (Baud rate: transfer clock frequency)

The transfer rate is determined by BRGi (addresses 3116, 3916, and 6516). When a value of “n” is set in BRGi (n = 0016 to FF16), the count source is divided by (n + 1) in the BRGi, and then the BRGi’s output is further divided by 16. (In this way, the transfer clock is generated.) Accordingly, assuming that the baud rate is B (bps), “n” is expressed by the following formula. n = –1 F : BRGi’s count source frequency An internal clock or an external clock can be selected as the BRGi’s count source by specifying the internal/external clock selection bit (bit 3 at addresses 30 16, 3816, and 6416). When an internal clock is selected, the clock selected by the BRG count source selection bits (bits 1 and 0 at addresses 3416, 3C16, and 6816) is the BRGi’s count source. When an external clock is selected, the clock which is input to the CLKi pin is the BRGi’s count source. transmitter and receiver sides. F 16 5 B

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Table 8.4.3 Example of baud rate setting (1) System clock: 19.6608 MHzSystem clock: 14.7456 MHzBaud rate (bps) 300 600 1200 2400 4800 9600 19200 38400 57600 115200 BRGi’s count source f f16 f16 BRGi’s set value: n 191 (BF16) 95 (5F16) 47 (2F16) 191 (BF16) 95 (5F16) 47 (2F16) 23 (1716) 11 (0B16) 7 (0716) 3 (0316) Actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 57600.00 115200.00 BRGi’s set value: n 255 (FF 16) 127 (7F16) 63 (3F16) 255 (FF16) 127 (7F16) 63 (3F16) 31 (1F16) 15 (F16) Actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 System clock, and clocks f2, f16: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = “0.” For details, refer to chapter “14. CLOCK GENERATING CIRCUIT.” Table 8.4.4 Example of baud rate setting (2) System clock: 25 MHzSystem clock: 24.576 MHzBaud rate (bps) 300 600 1200 2400 4800 9600 14400 19200 31250 BRGi’s count source f f16 f16 f16 BRGi’s set value: n 79 (4F16) 159 (9F16) 79 (4F16) 39 (2716) 159 (9F16) 79 (4F16) 52 (3416) 39 (2716) Actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14490.57 19200.00 BRGi’s set value: n 80 (50 16) 162 (A216) 80 (5016) 40 (2816) 162 (A216) 80 (5016) 53 (3516) 40 (2816) 24 (1816) Actual time (bps) 301.41 599.12 1205.63 2381.86 4792.94 9645.06 14467.59 19054.88 31250.00 System clock, and clocks f2, f16, f64: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = “0.” For details, refer to chapter “14. CLOCK GENERATING CIRCUIT.” Table 8.4.5 Example of baud rate setting (3) System clock: 12 MHzSystem clock: 11.0592 MHzBaud rate (bps) 300 600 1200 2400 4800 9600 14400 19200 28800 31250 BRGi’s count source f f16 f16 BRGi’s set value: n 143 (8F16) 71 (4716) 35 (2316) 143 (8F16) 71 (4716) 35 (2316) 24 (1816) 17 (1116) 12 (0C16) Actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14400.00 19200.00 28800.00 BRGi’s set value: n 155 (9B 16) 77 (4D16) 38 (2616) 155 (9B16) 77 (4D16) 38 (2616) 26 (1A16) 13 (0D16) 11 (0B16) Actual time (bps) 300.48 600.96 1201.92 2403.85 4807.69 9615.38 14423.08 28846.15 31250.00 System clock, and clocks f2, f16: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = “0.” For details, refer to chapter “14. CLOCK GENERATING CIRCUIT.”

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8.4.2 Transfer data format

The transfer data format can be selected from three formats shown in Figure 8.4.1. By setting bits 6 to 4 at addresses 3016, 3816 and 6416, the transfer data format can be selected. (Refer to Figures 8.2.2 and 8.2.3.) Be sure to set the same transfer data format for both transmitter and receiver sides. When transfer data has a length of 7 bits 1ST-7DATA 1SP 1ST-7DATA 2SP 1ST-7DATA-1PAR- 1SP 1ST-7DATA-1PAR- 2SP When transfer data has a length of 8 bits 1ST-8DATA 1SP 1ST-8DATA 2SP 1ST-8DATA-1PAR- 1SP 1ST-8DATA-1PAR- 2SP When transfer data has a length of 9 bits 1ST-9DATA 1SP 1ST-9DATA 2SP 1ST-9DATA-1PAR- 1SP 1ST-9DATA-1PAR- 2SP ST : Start bit DATA : Character bit (transfer data) PAR : Parity bit SP : Stop bit Fig. 8.4.1 Transfer data format

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DATA (8 bits) Time Next transmit/receive data (When transferring in succession) For the case where 1ST-8DATA-1PAR-1SP “H” ST LSB MSB PAR SP ST Transmit/Receive data Fig. 8.4.2 Example of transfer data format Table 8.4.6 Each bit in transmit data Name ST Start bit DATA Character bit PAR Parity bit SP Stop bit Functions “L” signal equivalent to 1 character bit which is added immediately before the character bits. It indicates start of data transmission. Transmit data which is set in the UARTi transmission buffer register. A signal which is added immediately after the character bits in order to improve data reliability. The level of this signal changes depending on odd/even parity selection in such a way that the sum of “1”s in bits (this bit and character bits) is always an odd or even number. “H” level signal equivalent to 1 or 2 character bits which is added immediately after the character bits (or parity bit when parity is enabled). It indicates end of data transmission.

7733 Group User’s Manual 8–49

8.4.3 Method of transmission

Figure 8.4.3 shows an initial setting example for related registers when transmitting. The difference derived by selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data is transmitted in different lengths. When a 7/8-bit data length is selected, set the transmit data in the low- order byte of the UARTi transmission buffer register; when a 9-bit data length is selected, set the transmit data in the low-order byte and bit 0 of the high-order byte. Transmission is started when the following conditions (À to ´ ) are satisfied: À Transmit enable state (transmit enable bit = “1”) \` Transmit data is present in the UARTi transmission buffer register (transmission buffer empty flag = “0”) ´ The CTSi pin’s input is at “L” level (when the CTS function is selected) ____ Note : When the CTS function is not selected or in UART2, this condition is ignored. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched (UART0, UART1). For details, refer to section “8.4.6 Receive operation.” When using interrupts, settings for enabling interrupts are required. For details, refer to chapter “4. Interrupts.” Figure 8.4.4 shows how to write data after transmission is started and Figure 8.4.5 shows how to detect the transmit completion.

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UART0 baud rate register (BRG0) (address 3116) UART1 baud rate register (BRG1) (address 3916) UART2 baud rate register (BRG2) (address 6516) b7 b0 A value from 0016 to FF16 is set. Interrupt priority level selection bits When using interrupts, one of level 1 to 7 must be set. When disabling interrupts, level 0 must be set. Note 2: The CTS/RTS function selection bit is valid when the CTS/RTS enable bit = “0.” UART0 transmission interrupt control register (address 7116) UART1 transmission interrupt control register (address 7316) A-D/UART2 transm./rece. interrupt control register (address 7016) UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 Transmit enable bit 1: Transmission is enabled. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Transmission is started. (If the CTS function is selected, transmission is started when the CTSi pin’s input level is “L.”) UART0 transmission buffer register (addresses 3316, 3216) UART1 transmission buffer register (addresses 3B16, 3A16) UART2 transmission buffer register (addresses 6716, 6616) b7 b0 Transmit data is set here. UART0 transmit/receive mode register (address 3016) UART1 transmit/receive mode register (address 3816) UART2 transmit/receive mode register (address 6416) b7 b0 Internal/External clock selection bit 0: Internal clock 1: External clock 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity selection bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity is disabled. 1: Parity is enabled. Sleep selection bit (Note 1) The sleep mode is terminated (ignored). 1: The sleep mode is selected. b2b1b0 UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) b7 b0 BRG count source selection bits CTS / RTS enable bit 0: The CTS / RTS function is enabled. 1: The CTS / RTS function is disabled. CTS / RTS function selection bit 0: The CTS function is selected. 1: The RTS function is selected. (The CTS function is disabled.) Data output selection bit 0: T xD i pin is set for CMOS output. 1: TxD i pin is set for N-channel open-drain output. Clocks f2, f16, f64, and f512 : Refer to chapter “14. CLOCK GENERATING CIRCUIT.” 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b1b0 (Note 2) Note 1: Nothing is allocated to bit 7 of the UART2 transmit/ receive mode register. b7 b0 BRG count source selection bits CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled (I/O port). 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b1b0 UART2 transmit/receive control register 0 (address 6816) Fig. 8.4.3 Initial setting example for related registers when transmitting

7733 Group User’s Manual 8–51

Fig. 8.4.4 How to write data after transmission is started [When not using interrupts] [When using interrupts] A UARTi transmission interrupt request occurs when the UARTi transmission buffer register becomes empty.UARTi transmission interrupt UART0 transmission buffer register (addresses 3316, 3216) UART1 transmission buffer register (addresses 3B16, 3A16) UART2 transmission buffer register (addresses 6716, 6616) b15 b8 Writing of the next transmit data Transmit data is set here. b7 b0 h This diagram indicates bits and registers required for processing. for details about the change of flag status and the occurrence timing of an interrupt request. UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 Transmission buffer empty flag 0: Data is present in the transmission buffer register. 1: No data is present in the transmission buffer register. (Next transmit data can be written.) Checking the status of the UARTi transmission buffer register

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Fig. 8.4.5 How to detect transmit completion [When not using interrupts] [When using interrupts] UARTi transmission interrupt request occurs when transmission is started. UARTi transmission interrupt h This diagram indicates bits and registers required for processing. details about the change of flag status and the occurrence timing of an interrupt request. UART0 transmission interrupt control register (address 7116) UART1 transmission interrupt control register (address 7316) A-D/UART2 trans./rece. interrupt control register (address 7016) b7 b0 Interrupt request bit 0: No interrupt has occurred. 1: Interrupt has occurred. (Transmission has been started.) Checking the start of transmission Processing at transmit completion UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) UART2 transmit/receive control register 0 (address 6816) b7 b0 Checking the completion of transmission Transmisson register empty flag 0: Transmission is in progress. 1: Transmission is completed. Note: Nothing is implemented to bits 7 to 4 of UART2.

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8.4.4 Transmit operation

When the transmit conditions described in section “8.4.3 Method of transmission” are satisfied, the transfer clock is generated and the following operations are automatically performed after one cycle of the transfer clock has passed. l The UARTi transmission buffer register’s contents is transferred to the UARTi transmission register. l The transmission buffer empty flag is set to “1.” l The transmission register empty flag is cleared to “0.” l A UARTi transmission interrupt request occurs and the interrupt request bit is set to “1.” The transmit operation is described below. À Data in the UARTi transmission register is transmitted from the TX Di pin. \` This data is transmitted bit by bit sequentially in order of ST→ DATA (LSB) → ••• → DATA (MSB) → PAR → SP according to the transfer data format. ´ In the middle of the stop bit (the second stop bit when two stop bits are selected), the transmission register empty flag is set to “1.” This indicates completion of transmission. Also, whether the transmit conditions for the next data are satisfied or not is checked. When the transmit conditions for the next data are satisfied at completion of transmission in operation ´ , a start bit is generated following the stop bit and the next data is transmitted. When performing transmission in succession, set the next transmit data in the UARTi transmission buffer register during transmission (when transmission register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the TXDi pin outputs “H” level and the transfer clock is stopped. shows an example of transmit timing when the transfer data length has a 9 bits.

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Fig. 8.4.7 Example of transmit timing when data is transferred in 9 bits (When parity is disabled and two stop bits) Fig. 8.4.6 Example of transmit timing when data is transferred in 8 bits (When parity is enabled, one ____ stop bit, and CTS function is not selected) ST D 0 TENDi TxD i D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SP D 1D 8 SP SP SP “0” “1” “0” “1” “0” “1” Tc “0” “1” Transmit enable bit Transmission buffer empty flag Transmission register empty flag Start bit Data is set in UARTi transmission buffer register. Transfer clock TENDi : Next transmit conditions are checked when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) The above timing diagram is applied when the following conditions are satisfied: l Parity is disabled. l 2 stop bits l CTS function is not selected. TC = 16(n + 1)/fi or 16(n + 1)/fEXT fi : BRGi’s count source frequency (f2, f16, f64, or f512) fEXT : BRGi’s count source frequency (external clock) n : Value set to BRGi Stopped because transmit enable bit = “0” UARTi transmission interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Stop bitStop bit UARTi transmission register UARTi transmission buffer register Tc D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP D 0 D 1D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP ST TENDi TxD i “0” “1” “0” “1” “0” “1” “0” “1” Transmit enable bit Transmission buffer empty flag Transmission register empty flag Start bit Stop bit Data is set in UARTi transmission buffer register. Transfer clock The above timing diagram is applied when the following conditions are satisfied: l Parity is enabled. l 1 stop bit l CTS function is not selected. TC = 16(n + 1)/fi or 16(n + 1)/fEXT fi : BRGi’s count source frequency (f2, f16, f64, or f512) fEXT : BRGi’s count source frequency (external clock) n : Value set to BRGi Stopped because transmit enable bit = “0” UARTi transmission interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Parity bit TENDi : Next transmit conditions are checked when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) UARTi transmission register UARTi transmission buffer register SEIRAL I/O

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Fig. 8.4.8 Example of transmit timing when data is transferred in 8 bits (When parity is enabled, one ____ stop bit, and CTS function is selected) Tc D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PS P D 0 D 1D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP ST TENDi TxD i “0” “1” “0” “1” “0” “1” “0” “1” “L” “H” CTS i Stopped because CTS pin’s level is “H.” Transmit enable bit Transmission buffer empty flag Transmission register empty flag Start bit Stop bit Data is set in UARTi transmission buffer register. Transfer clock The above timing diagram is applied when the following conditions are satisfied: l Parity is enabled. l 1 stop bit l CTS function is selected. TC = 16(n + 1)/fi or 16(n + 1)/fEXT fi : BRGi’s count source frequency (f2, f16, f64, or f512) fEXT : BRGi’s count source frequency (external clock) n : Value set to BRGi ‹ UARTi transmission buffer register Stopped because transmit enable bit = “0” UARTi transmission interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Parity bit TENDi : Next transmit conditions are checked when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) UARTi transmission register

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8.4.5 Method of reception

Figure 8.4.9 shows an initial setting example for related registers when receiving. Reception is started when the following conditions (À and \ ) are satisfied. À Receive enable state (receive enable bit = “1”). \ The start bit is detected. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched (UART0, UART1). For details, refer to section “8.4.6 Receive operation.” When using interrupts, settings for enabling interrupts are required. For details, refer to chapter “4. Interrupts.” Figure 8.4.10 shows the processing after reception is completed.

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Then, reception starts when the start bit is detected. Port P8 direction register (address 1416) b7 b0 R xD 0 pin R xD 1 pin UART0 baud rate register (BRG0) (address 3116) UART1 baud rate register (BRG1) (address 3916) UART2 baud rate register (BRG2) (address 6516) b7 b0 A value from 0016 to FF16 is set. UART0 receive interrupt control register (address 7216) UART1 receive interrupt control register (address 7416) A-D/UART2 trans./rece. interrupt control register (address 7016) b7 b0 Interrupt priority level selection bits When using interrupts, one of level 1 to 7 must be set. When disabling interrupts, level 0 must be set. Note 2: The CTS/RTS function selection bit is valid when CTS/RTS enable bit = “0.” h Set the transfer data format in the same way as set on the transmitter side. Note 1: Nothing is allocated to bit 7 of UART2 transmit/receive mode register. UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 Receive enable bit 1: Reception is enabled. UART0 transmit/receive mode register (address 3016) UART1 transmit/receive mode register (address 3816) UART2 transmit/receive mode register (address 6416) b7 b0 Internal/External clock selection bit 0: Internal clock 1: External clock 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity selection bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity is disabled. 1: Parity is enabled. Sleep selection bit (Note 1) The sleep mode is terminated (ignored). 1: The sleep mode is selected. b2b1b0 UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) b7 b0 BRG count source selection bits CTS / RTS enable bit 0: The CTS / RTS function is enabled. 1: The CTS / RTS function is disabled. CTS /RTS function selection bit (Note 2) 0: The CTS function is selected. (The RTS function is disabled.) 1: The RTS function is selected. Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b1b0 b7 b0 BRG count source selection bits CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled (I/O port). 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b1b0 Port P7 direction register (address 1116) b7 b0 R xD 2 pin (Note 3) Note 3: In the 7733 Group or the 7735 Group, set this bit. In the 7736 Group, it is not neccessary to set this bit. UART2 transmit/receive control register 0 (address 6816) Fig. 8.4.9 Initial setting example for related registers when receiving

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[When not using interrupts] [When using interrupts] A UARTi receive interrupt request occurs when reception is completed. UARTi receive interrupt h This diagram indicates bits and registers required for processing. Refer to Figure 8.4.12 for details about the change of flag status and the occurrence timing of an interrupt request. Processing after reading out receive data UART0 receive buffer register (addresses 3716, 3616) UART1 receive buffer register (addresses 3F16, 3E16) UART2 receive buffer register (addresses 6B16, 6A16) b15 b8 Reading out the receive data Read out the receive data b7 b0 0000000 UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 Receive completion flag 0: Reception is not completed. 1: Reception is completed. Checking the completion of reception UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 Checking the error Framing error flag Parity error flag Error sum flag 0: No error is detected. 1: Error is detected. UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 Checking the error Overrun error flag 0: No error is detected. 1: Error is detected. Fig. 8.4.10 Processing after reception is completed

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RTS i (Note) Transmitter side Receiver side Note: The RTSi output function is not assigned for

8.4.6 Receive operation

When the receive enable bit is set to “1,” the UARTi enters the receive enable state. And then, the transfer clock is generated when ST is detected, and reception is started. When the RTS function is selected (UART0, UART1), the RTSi pin’s output level becomes “L” if the UARTi enters the receive enable state and the microcomputer informs the transmitter side that reception is ____ enabled. When reception is started, the RTSi pin’s output level becomes “H.” Accordingly, by connecting the RTSi pin (receiver side) and the CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. Figure 8.4.11 shows an connection example. The receive operation is described below. À The signal which is input from the RxDi pin is taken in the most significant bit of the UARTi receive register synchronously with the transfer clock’s rising edge. \ The contents of UARTi receive register is shifted by 1 bit to the right. ´ Operations À and \ are repeated at each transfer clock’s rising edge. ˆ When a set of data is prepared, in other words, when shifted several times depending on the specified data format, the UARTi receive register’s contents is transferred to the UARTi receive buffer register. ˜ Simultaneously with ˆ , the receive completion flag is set to “1.” Furthermore, a UARTi receive interrupt request occurs and the interrupt request bit is set to “1.” The receive completion flag is cleared to “0” when the low-order of the UARTi receive buffer register is read out. The RTSi pin’s output level becomes “L” simultaneously with ˜ (when RTS function is selected). Figure 8.4.12 shows an example of receive timing when transfer data has a length of 8 bits. Fig. 8.4.11 Connection example

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Fig. 8.4.12 Example of receive timing when data is transferred in 8 bits (When parity is disabled and one stop bit) D0 D1 D7RxD i (Note) RTSi “1” “0” “0” “1” “H” “L” “0” “1” Receive enable bit Start bit Stop bit The above timing diagram is applied when the following conditions are satisfied: l Parity is disabled. l 1 stop bit l RTS function is selected. → UARTi receive buffer register UARTi receive interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Receive completion flag Check whether the level is “L.” Received data is taken in. The transfer clock is generated at the falling edge of start bit, and reception is started. BRG i count source Note: The RTSi output function is not assigned for Transfer clock UARTi receive register

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8.4.7 Processing when error is detected

Errors listed below can be detected in the UART mode: l Overrun error An overrun error occurs when the next data is prepared in the UARTi receive register with the receive completion flag = “1” (in other words, data is present in the UARTi receive buffer register), and then the next data is transferred to the UARTi receive buffer register. In other words, when the next data is prepared before the contents of the UARTi receive buffer register is read out. When an overrun error occurs, the next receive data is written into the UARTi receive buffer register. At this time, the UARTi receive interrupt request bit is not set to “1.” l Framing error A framing error occurs when the number of detected stop bits does not match the number which is set. (The UARTi interrupt request bit is set to “1.”) l Parity error A parity error occurs when the sum of “1”s in the parity bit and character bits does not match the number which is set. (The UARTi interrupt request bit is set to “1.”) Each error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register, and the corresponding error flag is set to “1.” Furthermore, when any of the above errors occurs, the error sum flag is set to “1.” Accordingly, the error sum flag informs whether any error has occurred or not. Error flags are cleared to “0” when the serial I/O mode selection bits are cleared to “000 2” or when the receive enable bit is cleared to “0.” (When all of the overrun, framing, and parity error flags are cleared to “0,” the error sum flag is cleared to “0.”) Note also that the framing and parity error flags are cleared to “0” when the low-order byte of the UARTi receive buffer register is read out. When an error occurs during reception, initialize the error flags and the UARTi receive buffer register, and then perform reception again. When it is necessary to perform transmission again owing to an error which occurs in the receiver side, set the UARTi transmission buffer register again, and then starts transmission again. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmission buffer register again are described below. (1) Method of initializing UARTi receive buffer register À Clear the receive enable bit to “0.” (Reception is disabled.) \ Set the receive enable bit to “1” again. (Reception is enabled.) (2) Method of setting UARTi transmission buffer register again À Clear the serial I/O mode selection bits to “000 2.” (Serial I/O is ignored.) \ Set the serial I/O mode selection bits again. ´ Set the transmit enable bit to “1.” (Transmission is enabled.) And set the transmit data to the UARTi transmission buffer register.

8.4.8 Precautions for UART

For performing the transmission and the reception simultaneously, UART2 does not distinguish the transmission interrupt from the reception interrupt. The UART2 transmission/reception interrupt request occurs when either interrupt request occurs. Accordingly, in the system which performs the transmission and reception simultaneously for UART2, not use the UART2 transmission/reception interrupt but use the method of poling the transmission buffer empty flag and the receive completion flag by software.

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Slave BSlave A Slave DSlave C Data is transferred between the master microcomputer and one specific slave microcomputer, which is selected from multiple slave microcomputers.

8.4.9 Sleep mode (UART0 and UART1)

This mode is used when data is transferred between the master microcomputer and one slave microcomputer, which is selected from multiple slave microcomputers connected to the master microcomputer using UARTi. The sleep mode is selected when the sleep selection bit (bit 7 at addresses 30 16 and 3816) is set to “1” at receiving. In the sleep mode, the receive operation is performed when the MSB (D 8 when the transfer data has a length of 9 bits; D7 when the transfer data has a length of 8 bits; D6 when the transfer data has a length of 7 bits) of the receive data = “1.” The receive operation is not performed when the MSB = “0.” (The UARTi receive register’s contents is not transferred to the UARTi receive buffer register. The receive completion flag and error flags do not change and a UARTi receive interrupt request does not occur, also.) A usage example of the sleep mode when the transfer data has a length of 8 bits is described below. À Set the same transfer data format for the master and slave microcomputers. Select the sleep mode for the slave microcomputer. \ Transmit the data, which has “1” in bit 7 and the address of the slave microcomputer to be communicated in bits 6 to 0, from the master microcomputer to all slave microcomputers. ´ All slave microcomputers receive data in operation \ . (At this time, a UARTi receive interrupt request occurs.) ˆ For all slave microcomputers, check in the interrupt routine whether bits 6 to 0 in the receive data match their own addresses. ˜ For the slave microcomputer whose address matches bits 6 to 0 in the receive data, terminate the sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.) By performing operations \ to ˜ , “the slave microcomputer which performs transmission” can be specified. ¯ Transmit the data, which has “0” in bit 7, from the master microcomputer. (Only the microcomputer selected by operations \ to ˜ receives this data. The other microcomputers do not receive this data.) ˘ By repeating operation ¯ , data is transferred between two specific microcomputers in succession. Also, by performing operations \` to ˜ , another slave microcomputer can be specified. Fig. 8.4.13 Sleep mode

9.1 Overview

9.2 Block description

9.3 A-D conversion method

9.4 Absolute accuracy and

Differential non-linearity error

9.5 One-shot mode

9.6 Repeat mode

9.7 Single sweep mode

9.8 Repeat sweep mode

9.9 Precautions for A-D converter

7733 Group User’s Manual9–2

The A-D converter is described below. For this A-D converter, 8-bit resolution or 10-bit resolution can be selected. It’s conversion method is the successive approximation method and has 8 analog input pins. The performance overview is listed in Table 9.1.1. Table 9.1.1 Performance overview Conversion rate per analog input pin Performance Successive approximation method 8/10 bits can be selected by software 8-bit resolution: ±2 LSB 10-bit resolution: ±3 LSB 8 pins (AN 0 to AN7) 8-bit resolution: 49 φAD ] cycles 10-bit resolution: 59 φAD ] cycles φAD ] : A-D converter’s operating clock The A-D convertor has the following four operation modes. n One-shot mode A-D conversion is once performed for the input voltage of one analog input pin. n Repeat mode A-D conversion is repeatedly performed for the input voltage of one analog input pin. n Single sweep mode A-D conversion is performed for the input voltage of multiple analog input pins, one at a time. n Repeat sweep mode A-D conversion is repeatedly performed for the input voltage of multiple analog input pins.

7733 Group User’s Manual 9–3

Resistor ladder network Vref Selector AN 0 AN 1 AN 2 AN 3 AN 4 AN 5/ADTRG AN 6 AN 7 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 A-D control register 1 Decoder VIN 1/2f 2 1/2 ƒÓAD Data bus (Even) A-D control register 0 Data bus (Odd) A-D conversion frequency selection VREF connection selection Figure 9.2.1 shows the block diagram of the A-D converter. Registers related to the A-D converter are described below. Fig. 9.2.1 Block diagram of A-D converter

7733 Group User’s Manual9–4

@A-D control register 0 (address 1E16) Bit A-D conversion frequency ( AD ) selection flag A-D conversion start flag Trigger selection bit 4 @ A-D operation mode selection bits 2 @ 1 @ Bit name At reset Undefined Undefined Undefined RWFunctions 0 0 0: AN0 is stopped. 0 0 1: AN1 is stopped. 0 1 0: AN2 is stopped. 0 1 1: AN3 is stopped. 1 0 0: AN4 is stopped. 1 0 1: AN5 is stopped. (Note 2) 1 1 0: AN6 is stopped. 1 1 1: AN7 is stopped. f2]: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” b2 b1 b0 0: Internal trigger 1: External trigger 0: f2/4] 1: f2/2 00: One-shot mode 01: Repeat mode 10: Single sweep mode 11: Repeat sweep mode 0: A-D conversion is stopped. 1: A-D conversion is started. b4b3 These bits are ignored in the single sweep and repeat sweep modes. (They may be “0” or “1.”) When an external trigger is selected, pin AN 5 cannot be used as an analog input pin. Writing to each bit (except bit 6) of the A-D control register 0 must be performed while the A-D converter stops operating. Analog input selection bits (Valid in the one-shot and repeat modes) (Note 1) Notes 1: RW RW RW RW RW RW RW RW

9.2.1 A-D control register 0

Figure 9.2.2 shows the structure of A-D control register 0. A-D operation mode selection bits select an operation mode of A-D converter. The other bits are described below. Fig. 9.2.2 Structure of A-D control register 0 (1) Analog input selection bits (bits 2 to 0) These bits are used to select an analog input pin in the one-shot and repeat modes. (Refer to section “9.2.5 Port P7 direction register.”) When switching the operating mode to the one-shot or repeat mode after A-D conversion is once performed in the single sweep or repeat sweep mode, set these bits again.

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15.68 18.88 A-D conversion frequency (φAD ) selection flag φAD Conversion time Resolution : 8 bits

• System clock = 25 MHz (Note) Resolution : 10 bits f2 divided by 2 7.84 9.44 (2) Trigger selection bit (bit 5) This bit selects a trigger occurrence source. (Refer to “(3) A-D conversion start flag.”) (3) A-D conversion start flag (bit 6) œWhen internal trigger is selected When this bit is set to “1,” a trigger occurs, and then the A-D converter starts operating. When this bit is cleared to “0,” the A-D converter stops operating. In the one-shot or single sweep mode, this bit is cleared to “0” after A-D conversion is completed. In the repeat or repeat sweep mode, the A-D converter continues operating until this bit is cleared to “0” by software. œWhen external trigger is selected If the AD TRG pin level goes from “H” to “L” when this bit = “1,” a trigger occurs, and then the A-D converter starts operating. The A-D converter stops operating when this bit is cleared to “0.” In the one-shot or single sweep mode, this bit remains set to “1” even after A-D conversion is completed. In the repeat or repeat sweep mode, the A-D converter continues operating until this bit is cleared to “0” by software. (4) A-D conversion frequency ( φAD ) selection flag (bit 7) Conversion time varies according to the A-D converter’s operating clock (φAD ) selected by this bit as listed in Table 9.2.1. Since the A-D converter’s comparator consists of capacity coupling amplifiers, keep that φAD ≥ 250 kHz during A-D conversion. Note: This is applied when the following conditions are satisfied;
• f(XIN) = 25 MHz
• The main clock is selected as the system clock.
• Main clock divided by 2 is available. Table 9.2.1 Conversion time per one analog input pin (Unit: µs)

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A-D control register 1 (address 1F16) Bit Bit name At reset RWFunctions 0 0: Pins AN0 and AN1 (2 pins) 0 1: Pins AN0 to AN3 (4 pins) 1 0: Pins AN0 to AN5 (6 pins) (Note 2) 1 1: Pins AN0 to AN7 (8 pins) b1 b0 Not implemented. Undefined These bits are ignored in the one-shot and repeat modes. (They may be “0” or “1.”) When an external trigger is selected, pin AN5 cannot be used as an analog input pin. Writing to each bit of the A-D control register 1 must be performed while the A-D converter stops operating. When the VREF connection selection bit is cleared from “1” to “0,” wait for an interval of 1 µs or more passed, and then start A-D conversion. 3 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution A-D sweep pin selection bits (Valid in the single sweep and repeat sweep modes.) (Note 1) 4 Must be fixed to “0.”

5 VREF connection selection

bit (Note 4) 0: Pin VREF is connected. 1: Pin VREF is disconnected. (High impedance) 6 Not implemented. Undefined RW RW RW RW RW Notes 1:

9.2.2 A-D control register 1

Figure 9.2.3 shows the structure of A-D control register 1. Fig. 9.2.3 Structure of A-D control register 1 (1) A-D sweep pin selection bits (bits 1 and 0) These bits are used to select analog input pins in the single sweep and repeat sweep modes. Refer to section “9.2.5 Port P7 direction register.” (2) VREF connection selection bit (bit 5) This bit is used to disconnect the A-D converter’s resistor ladder network from the reference voltage input pin (VREF ) when not using the A-D converter. When pin V REF is disconnected from the resistor ladder network, no current flows from pin VREF to the resistor ladder network.

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A-D register 0 (addresses 2116 and 2016) A-D register 1 (addresses 2316 and 2216) A-D register 2 (addresses 2516 and 2416) A-D register 3 (addresses 2716 and 2616) A-D register 4 (addresses 2916 and 2816) A-D register 5 (addresses 2B16 and 2A16) A-D register 6 (addresses 2D16 and 2C16) A-D register 7 (addresses 2F16 and 2E16) Bit “0” at reading. The A-D conversion result is read out. Functions At reset Undefined RO RO RW b7 b0 (b15) (b8) l When resolution = 10 bits 15 to 10 9 to 0 b7 b0 A-D register 0 (addresses 2116 and 2016) A-D register 1 (addresses 2316 and 2216) A-D register 2 (addresses 2516 and 2416) A-D register 3 (addresses 2716 and 2616) A-D register 4 (addresses 2916 and 2816) A-D register 5 (addresses 2B16 and 2A16) A-D register 6 (addresses 2D16 and 2C16) A-D register 7 (addresses 2F16 and 2E16) Bit “0” at reading. The A-D conversion result is read out. Functions At reset Undefined RO RW b7 b0 (b15) (b8) l When resolution = 8 bits 7 to 0 15 to 8 RO

9.2.3 A-D register i (i = 0 to 7)

Figure 9.2.4 shows the structure of A-D register i. When A-D conversion is completed, the conversion result (in other words, the contents of the successive approximation register) is stored into this register. Each A- D register i corresponds to an analog input pin (ANi), one for one. Table 9.2.2 lists the correspondence of an analog input pin to A-D register i. Fig. 9.2.4 Structure of A-D register i Table 9.2.2 Correspondence of analog input pin and A-D register i Analog input pin Pin AN0 Pin AN1 Pin AN2 Pin AN3 Pin AN4 Pin AN5 Pin AN6 Pin AN7 A-D register i where conversion result is stored A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7

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7 to 4 Not implemented.

3 Interrupt request bit (Note)

0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 Priority is low. 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Priority is high. b2 b1 b0 0: No interrupt request has occurred. 1: Interrupt request has occurred. b7 b6 b5 b4 b3 b2 b1 b0 A-D/UART2 trans./rece. interrupt control register (address 70 16) Note: When UART2 is selected, in other words, when a serial I/O mode is selected by specifying the serial I/O mode selection bits (bits 0 to 2 at address 6416), this bit is set to “1.” RW RW RW RW 9.2.4 A-D/UART2 trans./rece. interrupt control register The A-D conversion interrupt and UART2 transmission/reception interrupt share the same interrupt control register and interrupt vector addresses. When UART2 is selected, the A-D/UART2 trans./rece. interrupt control register functions as an register which control the UART2 transmission/reception interrupt. At this time, the A-D conversion interrupt cannot be used. For details on interrupts, refer to chapter “4. INTERRUPTS.” For details on UART2, refer to chapter “8. SERIAL I/O.” The case where this register is used as the A-D conversion interrupt control register is described below.

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(1) Interrupt priority level selection bits (bits 2 to 0) These bits select an A-D conversion interrupt’s priority level. When using A-D conversion interrupts, select one priority level from levels 1 to 7. If an A-D conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), and the requested interrupt is enabled only when its priority level is higher than the IPL. (Note that this is applied to the case where the interrupt disable flag (I) = “0.”) When disabling A-D conversion interrupts, set these bits to “000 (Level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when an A-D conversion interrupt request occurs. This bit is automatically cleared to “0” when the A-D conversion interrupt request is accepted. Note that this bit can be set to “1” or cleared to “0” by software.

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Bit Corresponding bit’s name Functions Pin AN0 Pin AN2/CTS2 Pin AN3/CLK2 Pin AN4/RxD2 Pin AN6/XCOUT 0: Input mode 1: Output mode Pin AN5/ADTRG /TxD2 Port P7 direction register (address 1116) b1 b0b2b3b4b5b6b7 Pin AN1 At reset RW When using these pins as A-D converter’s input pins, set the corresponding bits to “0.”

7 Pin AN7/XCIN

9.2.5 Port P7 direction register

Input pins of the A-D converter are multiplexed with port P7. When using these pins as A-D converter’s input pins, set the corresponding bits of the port P7 direction register to “0” to set these ports for the input mode. Figure 9.2.6 shows the relationship between the port P7 direction register and I/O pins of the sub- clock oscillation circuit and peripheral functions. Fig. 9.2.6 Relationship between port P7 direction register and I/O pins of sub-clock oscillation circuit and peripheral functions Analog input pins function as the port P7’s I/O pins and also function as I/O pins of the sub-clock oscillation circuit and UART2. For pins which are forcedly set to the output mode when the function for the sub-clock oscillation circuit or UART2 is selected, analog input is disabled. (Refer to “Table 9.2.3.”) Table 9.2.3 Port P7’s pin which is forcedly set to output mode Clock synchronous serial I/O mode is selected and an internal clock is used. (bits 3 to 0 at address 6416 = “00012”) Serial I/O mode is selected. (bits 2 to 0 at address 6416 = “0012,” “1002,” “1012,” or “1102”) Sub-clock oscillation circuit is operating by itself. (bit 4 at address 6C16 = “1” and bit 2 at address 6F16 = “0” ) Conditions where pin is forcedly set to output mode

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The A-D converter compares the comparison voltage (Vref), which is internally generated according to the contents of the successive approximation register, and the analog input voltage (VIN), which is input from the analog input pin. By reflecting the comparison result on the successive approximation register, VIN is converted into a digital value (successive approximation method). When a trigger occurs, the A-D converter performs the following processing: À Determination of successive approximation register’s bit 9 The A-D converter compares Vref and VIN. At this time, contents of the successive approximation register is “10000000002” (Initial value). Bit 9 of the successive approximation register changes according to the comparison result as follows: If Vref < VIN, bit 9 = “1” If Vref > VIN, bit 9 = “0” \` Determination of successive approximation register’s bit 8 After setting bit 8 of the successive approximation register to “1,” the A-D converter compares V ref and V IN. Bit 8 changes according to the comparison result as follows: If Vref < VIN, bit 8 = “1” If Vref > VIN, bit 8 = “0” ´ Determination of successive approximation register’s bits 7 to LSB When the LSB is determined, the contents of the successive approximation register, in other words, the conversion result is transferred to the A-D register i. Vref is generated according to the latest contents of the successive approximation register. Table 9.3.1 lists list changes of the successive approximation register and Vref during A-D conversion. Figure 9.3.1 shows theoretical A-D conversion characteristics when resolution = 10 bits. Table 9.3.1 Relationship between successive approximation register’s contents and Vref 1 to 1023 × (n – 0.5) V REF ] : Reference voltage V REF ] 1024 Successive approximation register’s contents: n V ref (V)

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Successive approximation register Vref A-D converter stopped 1st comparison 2nd comparison 3rd comparison 10th comparison Conversion complete VREF 2048 VREF VREF VREF 2048 VREF VREF VREF VREF 2048 VREF VREF VREF VREF VREF 1024 2048 VREF [V] [V] [V] [V] [V] VREF•When n9 = 1, VREF•When n9 = 0, VREF•When n8 = 1, VREF•When n8 = 0, VREF – –– – n1 n0 0 00000000 0 00000000 1 00000000 n9 n8 1 0000000 n9 n8 n7 n6 n5 n4 n3 1 00 n9 n8 n7 n6 n5 n4 n3 n2 00 b9 b0 1st comparison result 2nd comparison result Successive approximation register Vref A-D converter stopped 1st comparison 2nd comparison 3rd comparison 8th comparison Conversion complete VREF 2048 VREF VREF VREF 2048 VREF VREF VREF VREF 2048 VREF VREF VREF VREF VREF 256 2048 VREF [V] [V] [V] [V] [V] V REF•When n9 = 1, V REF•When n9 = 0, VREF•When n8 = 1, VREF•When n8 = 0, VREF – –– – Table 9.3.2 Change of successive approximation register and Vref during A-D conversion (when resolution = 8 bits) Table 9.3.3 Change of successive approximation register and Vref during A-D conversion (when resolution = 10 bits)

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1024 5 0.5 Theoretical A-D conversion characteristics A-D conversion result 3FD 16 Fig. 9.3.1 Theoretical A-D conversion characteristics when resolution = 10 bits

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0 5 1 01 52 02 53 03 54 04 55 05 5 00716 00816 00916 00A16 00B16 +3 LSB –3 LSB Ideal A-D conversion characteristics Analog input voltage (mV) Output code (A-D conversion result) Fig. 9.4.1 Absolute accuracy of A-D converter (when resolution = 10 bits)

9.4 Absolute accuracy and Differential non-linearity error

The A-D conversion’s accuracy is described below.

9.4.1 Absolute accuracy

The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result and the output code of an A-D converter with ideal characteristics. The analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an A-D converter with ideal characteristics. For example, in the case of the 10-bit resolution, when V REF = 5.12 V, 1-LSB width is 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ... are selected as the analog input voltages. The absolute accuracy = ±3 LSB when the analog input voltage = 25 mV indicates that the output code expected from an ideal A-D conversion characteristics is “005 16” but the actual A-D conversion result is between “00216” to “00816.” The absolute accuracy includes the zero error and the full-scale error. The absolute accuracy degrades when V REF is lowered. The output codes for analog input voltages between V REF and AV CC are “3FF16.”

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0 5 1 01 52 02 53 03 54 04 5 00716 00816 00916 Output code (A-D conversion result) Differential non-linearity error Analog input voltage (mV) 1-LSB width with A-D conversion characteristics

9.4.2 Differential non-linearity error

The differential non-linearity error indicates the difference between the 1-LSB step width (the ideal analog input voltage width while the same output code is expected to output) of an A-D converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). For example, in the case of the 10-bit mode, when V REF = 5.12 V, the 1-LSB width of an A-D converter with ideal characteristics is 5 mV, but if the differential non-linearity error is ±1 LSB, the actual measured 1-LSB width is 0 to 10 mV. (Refer to section “16.1.4 A-D converter standard characteristics.”) Fig. 9.4.2 Differential non-linearity error (when resolution = 10 bits)

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Analog input voltage (mV) 10 30 17.5 37.5 l 8-bit A-D converter (When VREF = 5.12 V) Output code (A-D conversion result) l M37733MHBXXXFP’s A-D converter with ideal characteristics (When VREF = 5.12 V) Output code (A-D conversion result) 8-bit resolution 10-bit resolution (h ) Analog input voltage (mV) 8-bit resolution 10-bit resolution h : Difference from output code change point VREF : Reference voltage (h )

9.4.3 Comparison voltage when resolution = 8 bits

When 8-bit resolution is selected in the M37733MHBXXXFP, the high-order 8 bits of the 10-bit successive approximation register is the conversion result. Accordingly, when compared with the 8-bit A-D converter, the comparison reference voltage is different by REF /2048 (refer to the underlined portions in the Table 9.4.1). The difference of the output code change point is generated as shown in Figure 9.4.3. M37733MHBXXXFP (When resolution = 8 bits) 8-bit A-D converter Comparison reference voltage Vref V REF ] 1/28 5 n] 2 – VREF /210 5 0.5 V REF /28 5 n – VREF /28 5 0.5 V REF ] 1: Reference voltage n] 2: Contents of successive approximation register Table 9.4.1 Compare reference voltage Fig. 9.4.3 Difference of output code change point

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• A-D operation mode selection bits (bits 4 and 3 at address 1E16) = “002” In this mode, A-D conversion is once performed for the input voltage of one analog input pin. An A-D conversion interrupt request occurs when the A-D conversion is completed. Note that an A-D conversion interrupt cannot be used when the UART2 transmission/reception interrupt is used.

9.5.1 Setting for one-shot mode

Figure 9.5.1 shows an initial setting example for registers related to the one-shot mode. When using interrupts, settings for enabling interrupts are required. For details, refer to chapter “4. INTERRUPTS.”

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A-D conversion is started. Trigger is generated. Falling edges input to pin AD TRG When external trigger is selected When internal trigger is selected Setting of the A-D conversion start flag to “1” b7 b0 A-D control register 0 (address 1E16) A-D conversion start flag Note: Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while A-D converter stops operating, in other words, before a trigger is generated. When the VREF connection selection bit is cleared from “1” to “0,” wait for an interval of 1 s or more passed, and then generate a trigger. Setting of the interrupt priority level b7 b0 A-D/UART2 trans./rece. interrupt control register (address 70 16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the A-D control registers 0, 1 b7 b0 A-D control register 0 (address 1E16)000 0 0 0: AN0 is selected. 0 0 1: AN1 is selected. 0 1 0: AN2 is selected. 0 1 1: AN3 is selected. 1 0 0: AN4 is selected. 1 0 1: AN5 is selected. 1 1 0: AN6 is selected. 1 1 1: AN7 is selected. Trigger selection bit 0: Internal trigger 1: External trigger A-D conversion start flag 0: A-D conversion is stopped. Analog input selection bits b7 b0 A-D control register 1 (address 1F16)0 5 5 : It may be “0” or “1.” f2: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” A-D conversion frequency (AD ) selection flag 0: f2/4 1: f2/2 VREF connection selection bit 0: Pin VREF is connected. Selection of the one-shot mode Setting of the port P7 direction register b7 b0 Port P7 direction register (address 1116) Set bits corresponding to selected analog input pins to “0.” When an external trigger is selected, set bit 7 to “0.” AN 0 AN 5 AN 1 AN 2 AN 3 AN 4 b2b1b0 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution AN 7 AN 6 Fig. 9.5.1 Initial setting example for registers related to one-shot mode

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A-D conversion interrupt request occurs. Trigger is generated. Input voltage of ANi pin is converted. A-D converter is stopped. Conversion result A-D register i

9.5.2 Operation in one-shot mode

Figure 9.5.2 shows the conversion operation in the one-shot mode. (1) When internal trigger is selected À By setting the A-D conversion start flag to “1,” the A-D converter starts operating. \` The A-D conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register i.

• 49 cycles of φAD have passed when resolution = 8 bits
• 59 cycles of φAD have passed when resolution = 10 bits ´ When a UART2 trans./rece. interrupt is not used, the A-D conversion interrupt request bit is set to “1” simultaneously with \ . ˆ The A-D conversion start flag is cleared to “0,” and then the A-D converter stops operating. (2) When external trigger is selected À If pin AD TRG ’s level goes from “H” to “L” when the A-D conversion start flag = “1,” the A-D converter starts operating. \ The A-D conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register i.
• 49 cycles of φAD have passed when resolution = 8 bits
• 59 cycles of φAD have passed when resolution = 10 bits ´ When a UART2 trans./rece. interrupt is not used, the A-D conversion interrupt request bit is set to “1” simultaneously with \` . ˆ The A-D converter stops operating. The A-D conversion start flag remains set to “1” after the A-D converter stops operating. Accordingly, when pin AD TRG ’s level goes from “H” to “L”, the A-D converter restarts conversion from À . Note that when pin AD TRG ’s level goes from “H” to “L” during A-D conversion, the converter quits the conversion which is performed at that time and restarts it from À .

Fig. 9.5.2 Conversion operation in one-shot mode

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• A-D operation mode selection bits (bits 4 and 3 at address 1E16) = “012” In this mode, A-D conversion is repeatedly performed for the input voltage of one analog input pin. No A-D conversion interrupt request occurs in this mode. The A-D conversion start flag (bit 6 at address 1E 16) remains set to “1” until it is cleared to “0” by software. While the A-D conversion start flag = “1,” the A-D converter repeats A-D conversion without a stop.

9.6.1 Setting for repeat mode

Figure 9.6.1 shows an initial setting example for registers related to the repeat mode.

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Fig. 9.6.1 Initial setting example for registers related to repeat mode A-D conversion is started. Trigger is generated. Falling edges input to Pin AD TRG When external trigger is selected When internal trigger is selected Setting of the A-D conversion start flag to “1” b7 b0 A-D control register 0 (address 1E16) A-D conversion start flag Note: Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while A-D converter stops operating, in other words, before a trigger is generated. When the VREF connection selection bit is cleared from “1” to “0,” wait for an interval of 1 µ s or more passed, and then generate a trigger. Setting of the port P7 direction register b7 b0 Port P7 direction register (address 1116) Set bits corresponding to selected analog input pins to “0.” When an external trigger is selected, set bit 7 to “0.” AN 0 Setting of the A-D control registers 0, 1 b7 b0 A-D control register 0 (address 1E16)010 0 0 0: AN0 is selected. 0 0 1: AN1 is selected. 0 1 0: AN2 is selected. 0 1 1: AN3 is selected. 1 0 0: AN4 is selected. 1 0 1: AN5 is selected. 1 1 0: AN6 is selected. 1 1 1: AN7 is selected. b2b1b0 Trigger selection bit 0: Internal trigger 1: External trigger A-D conversion start flag 0: A-D conversion is stopped. Analog input selection bits b7 b0 A-D control register 1 (address 1F16) 5 : It may be “0” or “1.” f2: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” VREF connection selection bit 0: Pin VREF is connected. A-D conversion frequency (AD ) selection flag 0: f2/4 1: f2/2 Selection of the repeat mode AN 5 AN 1 AN 2 AN 3 AN 4 0 5 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution AN 7 AN 6

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Trigger is generated. Input voltage of ANi pin is converted. Conversion result A-D register i

9.6.2 Operation in repeat mode

Figure 9.6.2 shows the conversion operation in the repeat mode. (1) When internal trigger is selected À When the A-D conversion start flag is set to “1,” the A-D converter starts operating. \` The first A-D conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register i.

• 49 cycles of φAD have passed when resolution = 8 bits
• 59 cycles of φAD have passed when resolution = 10 bits ´ The A-D converter continues operating until the A-D conversion start flag is cleared to “0” by software. Each time A-D conversion is completed, the conversion result is transferred to the A-D register i. (2) When external trigger is selected À If pin AD TRG ’s level goes from “H” to “L” when the A-D conversion start flag = “1,” the A-D converter starts operating. \` The first A-D conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register i.
• 49 cycles of φAD have passed when resolution = 8 bits
• 59 cycles of φAD have passed when resolution = 10 bits ´ The A-D converter continues operating until the A-D conversion start flag is cleared to “0” by software. Each time A-D conversion is completed, the conversion result is transferred to the A-D register i. Note that when pin AD TRG ’s level goes from “H” to “L” during A-D conversion, the A-D converter quits the conversion which is performed at that time and restarts it from À .

Fig. 9.6.2 Conversion operation in repeat mode

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• A-D operation mode selection bits (bits 4 and 3) = “102” In this mode, A-D conversion is performed for the input voltage of multiple analog input pins, one at a time. A-D conversion is performed in order of AN0, AN1, AN2, .... An A-D conversion interrupt request occurs when A-D conversions are completed for all analog input pins selected.

9.7.1 Setting for single sweep mode

Figure 9.7.1 shows an initial setting example for registers related to the single sweep mode. When using interrupts, settings for enabling interrupts are required. For details, refer to chapter “4. INTERRUPTS.”

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A-D conversion is started. Setting of the port P7 direction register b7 b0 Port P7 direction register (address 1116) Set bits corresponding to selected analog input pins to “0.” When an external trigger is selected, set bit 7 to “0.” AN 0 Trigger is generated. Falling edges input to Pin AD TRG When external trigger is selected When internal trigger is selected Setting of the A-D conversion start flag to “1” b7 b0 A-D control register 0 (address 1E16) A-D conversion start flag Setting of the A-D control registers 0, 1 b7 b0 A-D control register 0 (address 1E16)100 5 : It may be “0” or “1.” f2: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” b7 b0 A-D control register 1 (address 1F16) A-D sweep pin selection bits b1b0 0 0: AN0 and AN1 (2 pins) 0 1: AN0 to AN3 (4 pins) 1 0: AN0 to AN5 (6 pins) 1 1: AN0 to AN7 (8 pins) Trigger selection bit 0: Internal trigger 1: External trigger A-D conversion start flag 0: A-D conversion is stopped. A-D conversion frequency (AD ) selection flag 0: f2/4 1: f2/2 Selection of the single sweep mode VREF connection selection bit 0: Pin VREF is connected. Note: Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while A-D converter stops operating, in other words, before a trigger is generated. When the VREF connection selection bit is cleared from “1” to “0,” wait for an interval of 1s or more passed, and then generate a trigger. Setting of the interrupt priority level b7 b0 A-D/UART2 trans./rece. interrupt control register (address 70 16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. AN 5 AN 1 AN 2 AN 3 AN 4 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution AN 7 AN 6 Fig. 9.7.1 Initial setting example for registers related to single sweep mode

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9.7.2 Operation in single sweep mode

Figure 9.7.2 shows the conversion operation in the single sweep mode. (1) When internal trigger is selected À When the A-D conversion start flag is set to “1,” the A-D converter starts A-D conversion for an input voltage of pin AN0. \` The A-D conversion for pin AN0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register 0.

• 49 cycles of φAD have passed when resolution = 8 bits
• 59 cycles of φAD have passed when resolution = 10 bits ´ A-D conversion is performed for all analog input pins selected. Each time A-D conversion is completed for a pin, the conversion result is transferred to the A-D register i which corresponds to the pin. ˆ When a UART2 trans./rece. interrupt is not used, the A-D conversion interrupt request bit is set to “1” at completion of ´ . ˜ The A-D conversion start flag is cleared to “0,” and the A-D converter stops operating. (2) When external trigger is selected À If pin AD TRG ’s level goes from “H” to “L” when the A-D conversion start flag = “1,” the A-D converter starts A-D conversion for the input voltage of pin AN0. \` The A-D conversion for pin AN0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register 0.
• 49 cycles of φAD have passed when resolution = 8 bits
• 59 cycles of φAD have passed when resolution = 10 bits ´ A-D conversion is performed for all analog input pins selected. Each time A-D conversion is completed for a pin, the conversion result is transferred to the A-D register i which corresponds to the pin. ˆ When a UART2 trans./rece. interrupt is not used, the A-D conversion interrupt request bit is set to “1” at completion of ´ . ˜ The A-D converter stops operating. The A-D conversion start flag remains set to “1” after this. Accordingly, when pin AD TRG ’s level goes from “H” to “L,” the A-D converter restarts conversion from À . Note that if pin AD TRG ’s level goes from “H” to “L” during A-D conversion, the A-D converter quits the conversion which is performed at that time and restarts it from À .

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A-D converter is stopped. A-D conversion interrupt request occurs. A-D register i Trigger is generated. Conversion result A-D register 0 Input voltage of pin AN1 is converted. A-D register 1 Input voltage of pin AN0 is converted. Conversion result Input voltage of pin ANi is converted. Conversion result Fig. 9.7.2 Conversion operation in single sweep mode

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• A-D operation mode selection bits (bits 4 and 3 at address 1E16) = “112” In this mode, A-D conversion is repeatedly performed for the input voltage of multiple analog input pins. A-D conversion is performed in order of AN0, AN1, AN2, .... No A-D conversion interrupt request occurs in this mode. The A-D conversion start flag (bit 6 at address 1E 16) remains set to “1” until it is cleared to “0” by software. While the A-D conversion start flag is “1,” the A-D converter repeats A-D conversion without a stop.

9.8.1 Setting for repeat sweep mode

Figure 9.8.1 shows an initial setting example for registers related to the repeat sweep mode.

7733 Group User’s Manual9–28

A-D conversion is started. Trigger is generated. Falling edges input to pin AD TRG When external trigger is selected When internal trigger is selected Setting of the A-D conversion start flag to “1” b7 b0 A-D control register 0 (address 1E16) A-D conversion start flag Note: Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while A-D converter stops operating, in other words, before a trigger is generated. When the VREF connection selection bit is cleared from “1” to “0,” wait for an period of 1 s or more passed, and then generate a trigger. Setting of the A-D control registers 0, 1 b7 b0 A-D control register 0 (address 1E16)110 5 b7 b0 A-D control register 1 (address 1F16) A-D sweep pin selection bits b1b0 0 0: AN0 and AN1 (2 pins) 0 1: AN0 to AN3 (4 pins) 1 0: AN0 to AN5 (6 pins) 1 1: AN0 to AN7 (8 pins) Trigger selection bit 0: Internal trigger 1: External trigger A-D conversion start flag 0: A-D conversion is stopped. 5 : It may be “0” or “1.” f2: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” A-D conversion frequency (AD ) selection flag 0: f2/4 1: f2/2 VREF connection selection bit 0: Pin VREF is connected. Selection of the repeat sweep mode Setting of the port P7 direction register b7 b0 Port P7 direction register (address 1116) Set bits corresponding to selected analog input pins to “0.” When an external trigger is selected, set bit 7 to “0.” AN 0 AN 5 AN 1 AN 2 AN 3 AN 4 8-10 bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution AN 7 AN 6 Fig. 9.8.1 Initial setting example for registers related to repeat sweep mode

7733 Group User’s Manual 9–29

9.8.2 Operation in repeat sweep mode

Figure 9.8.2 shows the conversion operation in the repeat sweep mode. (1) When internal trigger is selected À When the A-D conversion start flag is set to “1,” the A-D converter starts A-D conversion for an input voltage of pin AN0. \` The A-D conversion for pin AN0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register 0.

• 49 cycles of φAD have passed when resolution = 8 bits
• 59 cycles of φAD have passed when resolution = 10 bits ´ A-D conversion is performed for all analog input pins selected. Each time A-D conversion is completed for a pin, the conversion result is transferred to the A-D register i which corresponds to the pin. ˆ A-D conversion is repeatedly performed for all analog input pins selected. ˜ The A-D converter continues operating until the A-D conversion start flag is cleared to “0” by software. (2) When external trigger is selected À If pin AD TRG ’s level goes from “H” to “L” when the A-D conversion start flag = “1,” the A-D converter starts A-D conversion for the input voltage of pin AN0. \` The A-D conversion for pin AN0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register 0.
• 49 cycles of φAD have passed when resolution = 8 bits
• 59 cycles of φAD have passed when resolution = 10 bits ´ A-D conversion is performed for all analog input pins selected. Each time A-D conversion is completed for a pin, the conversion result is transferred to the A-D register i which corresponds to the pin. ˆ A-D conversion is repeatedly performed for all analog input pins selected. ˜ The A-D converter continues operating until the A-D conversion start flag is cleared to “0” by software. Note that when pin AD TRG ’s level goes from “H” to “L” during A-D conversion, the A-D converter quits the conversion which is performed at that time and restarts it from À .

7733 Group User’s Manual9–30

Trigger is generated. A-D register i Input voltage of pin AN0 is converted. Conversion result A-D register 0 A-D register 1 Conversion result Conversion result Input voltage of pin AN1 is converted. Input voltage of pin ANi is converted. Fig. 9.8.2 Conversion operation in repeat sweep mode

7733 Group User’s Manual 9–31

9.9 Precautions for A-D converter

1. Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while the A-D converter stops operating, in other words, before a trigger is generated. When the V REF connection selection bit is cleared from “1” to “0,” in other words, when pin VREF is disconnected from the resistor ladder network, wait for an period of 1 µs or more, and then generate a trigger. 2. When an external trigger is selected, pin AN5 cannot be used as an analog input pin because this pin is disconnected from the comparator. If pin AN5 is selected as an analog input pin when an external trigger is selected, the A-D converter operates, but an undefined value is stored into the A-D register 5. 3. When using the A-D converter, refer to section “Appendix 8. Countermeasures against noise,” also.

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10.1 Block description

10.2 Operation description

10.3 Precautions for watchdog timer

instruction is executed, the watchdog timer is connected as follows; WATCHDOG TIMER

7733 Group User’s Manual10-2

The watchdog timer is described below and functions as follows:

• Detects a program runaway.
• Measures a certain time from when oscillation starts at termination of the stop mode. (Refer to chapter “11. STOP AND WAIT MODES.” )

Figure 10.1.1 shows the block diagram of the watchdog timer. Fig. 10.1.1 Block diagram of watchdog timer Watchdog timer 2Vcc detection circuit Watchdog timer frequency selection flag f32 f512 Value FFF 16 is set.Writing to the watchdog timer register (address 6016) STP instruction Hold request RESET S Q R Watchdog timer interrupt request (Note 1) Clocks f8, f32, f512 :Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Notes 1: Only when the system clock selection bit (bit 3 at address 6C 16) = “1” and the stop mode is terminated by an interrupt request generated, the watchdog timer is connected to clock f8. 2: Clock f16 is input when one of the following conditions is satisfied;

• The port-Xc selection bit = “0” and the main clock external input selection bit = “1”
• The system clock selection bit = “0” and the main clock external input selection bit = “1”
• The port-Xc selection bit = “1,” the system clock selection bit = “1” and the sub clock external input selection bit = “1” When the STP
• Connected to clock f32 when the system clock selection bit = “0”
• Connected to clock f8 when the system clock selection bit = “1” (Note 2) (Note 3)

7733 Group User’s Manual 10-3

10.1.1 Watchdog timer

The watchdog timer is a 12-bit counter that down-counts a count source which is selected by the watchdog timer frequency selection flag (bit 0 at address 6116). Value “FFF16” is automatically set in the watchdog timer in the following cases. Note that an arbitrary value cannot be set in the watchdog timer. l When dummy data is written to the watchdog timer register (Refer to Figure 10.1.2.) l When the most significant bit of the watchdog timer becomes “0” l When the STP instruction is executed (Refer to chapter “11. STOP AND WAIT MODES.” ) l At reset Fig. 10.1.2 Structure of watchdog timer register Watchdog timer register (address 6016) Bit 7 to 0 Watchdog timer is initialized. By writing dummy data to this register, watchdog timer’s value is initialized to “FFF 16” (Dummy data: 0016 to FF16). At reset Un- defined WO RWFunctions

7733 Group User’s Manual10-4

10.1.2 Watchdog timer frequency selection flag

This is used to select a watchdog timer’s count source. Figure 10.1.3 shows the structure of the watchdog timer frequency selection flag. Fig. 10.1.3 Structure of watchdog timer frequency selection flag 0 : Clock f512 1 : Clock f32 At reset Un- defined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency selection flag (address 6116) Bit 7 to 1 Not implemented.

0 Watchdog timer frequency

Clocks f32, f512 : Refer to chapter “14. CLOCK GENERATING CIRCUIT.” RW

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The watchdog timer’s operation is described below. For its operation in the stop and wait modes, refer to chapter “11. STOP AND WAIT MODES.”

10.2.1 Basic operation

À The watchdog timer starts counting down from “FFF 16.” \ When the watchdog timer’s most significant bit becomes “0,” in other words, when the countdown has been performed 2048 times, a watchdog timer interrupt request occurs. (Refer to Table 10.2.1.) ´ When the interrupt request occurs (\ ), value “FFF16” is set to the watchdog timer. The watchdog timer interrupt is a non-maskable interrupt. When a watchdog timer interrupt request is accepted, the processor interrupt priority level (IPL) is set to “1112.” Table 10.2.1 Occurrence interval of watchdog timer interrupt request When system clock = 32 kHz (Note 2) 32768 ms 2048 ms Occurrence interval of watchdog timer interrupt request When system clock =

12 MHz (Note 1)

87.4 ms 5.46 ms Watchdog timer’s count source f512 f32 When system clock =

25 MHz (Note 1)

41.9 ms 2.62 ms Clocks f 32, f512, and system clock: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” Notes 1:This is applied when the system clock selection bit (bit 3 at address 6C16; Refer to Figure 10.2.1.) = “0” and the main clock division selection bit (bit 0 at address 6F16; Refer to Figure 10.2.2.) = “0.” 2:This is applied when the port-Xc selection bit (bit 4 at address 6C16; Refer to Figure 10.2.1.) = “1” and the system clock selection bit = “1.” Make sure that dummy data must be written to address 6016 (Watchdog timer register) by software before the most significant bit of the watchdog timer becomes “0.” If writing to address 6016 is not performed because of a program runaway and the most significant bit of the watchdog timer becomes “0,” a watchdog timer interrupt request occurs. This means that a program runaway has occurred. When resetting the microcomputer after detecting a program runaway, write “1” to the software reset bit (bit 3 at address 5E16) in the watchdog timer interrupt routine. (Make sure that writing “1” to the software reset bit must be performed on the condition that the main clock is stably supplied.) (For details, refer to chapter “13. RESET” and section “17.3 Watchdog timer.”)

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10.2.2 Operation in stop mode

In the stop mode, the watchdog timer stops operating. Immediately after the stop mode is terminated, the watchdog timer operates as follows. (1) When stop mode is terminated by a hardware reset Supply of internal clock φ starts immediately after the stop mode is terminated, and the microcomputer performs the “operation after reset.” (Refer to chapter “13. RESET.”) The watchdog timer frequency selection flag becomes “0,” and the watchdog timer starts counting of the main clock] 1 divided by 512 from “FFF16.” Main clock] 1: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” (2) When stop mode is terminated by an interrupt request generated According to bit state listed in Table 10.2.2, the watchdog timer operates as “a” or “b” described below. a. Supply of internal clock φ starts immediately after the stop mode is terminated, and the routine of the interrupt which is used to terminate the stop mode is executed. From “FFF16,” the watchdog timer restarts counting of a count source which was counted just before the STP instruction is executed (Note 1). b. Immediately after the stop mode is terminated, the watchdog timer starts counting of a count source (Note 2) from “FFF16.” Supply of internal clock φ starts when the watchdog timer’s most significant bit becomes “0.” (At this time, a watchdog timer interrupt request is not generated.) When supply of internal clock φ starts, the microcomputer executes the routine of the interrupt which is used to terminate the stop mode. From “FFF16,” the watchdog timer restarts counting of a count source which was counted just before the STP instruction is executed (Note 1). Notes 1: Clock f32 or f512 is counted. 2: When the system clock selection bit = “0,” clock f32 is counted. When the system clock selection bit = “1” and the port-Xc selection bit = “0,” clock f8 is counted.

7733 Group User’s Manual 10-7

Table 10.2.2 Watchdog timer’s operation and bit state related to oscillation circuit control Bit state related to oscillation circuit control (Bit 4 at address 6C16) System clock selection bit (Bit 3 at address 6C16) Main clock external input selection bit (Bit 1 at address 6F 16) Sub clock external input selection bit (Bit 2 at address 6F 16) Watchdog timer’s operation b a b a b a b a b a clock external input selection bit and the sub clock external input selection bit, refer to Figure 10.2.3.

10.2.3 Operation in wait mode

When the system clock stop bit at wait state (bit 5 at address 6C16 ; Refer to Figure 10.2.1.) = “1,” the watchdog timer stops operating in the wait mode. Furthermore, after the wait mode is terminated, the watchdog timer restarts counting from the same state as that before the watchdog timer stops. When the system clock stop bit at wait state = “0,” the watchdog timer does not stop.

7733 Group User’s Manual10-8

10.2.4 Operation in hold state

The watchdog timer stops operating in the hold state. (Refer to section “12.4 Hold function.”) When the hold state is terminated, the watchdog timer restarts counting from the same state as that before the watchdog timer stops. Fig. 10.2.1 Structure of oscillation circuit control register 0 Bit Bit name Functions At reset RW XCOUT drivability selection bit Main clock stop bit System clock selection bit Port-Xc selection bit Not implemented. Un- defined 0: Drivability “LOW” 1: Drivability “HIGH” When the port-Xc selection bit = “0,” 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = “1,” 0: Main clock 1: Sub clock Un- defined Oscillation circuit control register 0 (address 6C16) b1 b0b2b3b4b5b6b7 Notes 0: Main clock oscillation or external clock input is available. 1: Main clock oscillation or external clock input is stopped. RW RW Not implemented. _ RW (Note 1) 0: Operate as I/O ports (P77, P76). 1: Operate as pins XCIN and XCOUT . RW (Notes 2 and 3) RW (Note 2) System clock stop bit at wait state 0: Output is enabled. 1: Output is disabled. (Refer to Tables 12.1.2 and 12.1.5) 0: Operates in the wait mode. 1: Stopped in the wait mode. Signal output disable selection bit RW (Note 1) 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = “1.” 2: When selecting the sub clock as the system clock, set bit 3 to “1” after setting bit 4 to “1.” If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to “1.” 3: Although this bit can be set to “1,” it cannot be cleared to “0” after this bit is once set to “1.” 4: represents that bits 0 to 2 and bit 7 are not used for the watchdog timer.

7733 Group User’s Manual 10-9

Fig. 10.2.2 Structure of oscillation circuit control register 1 Fig. 10.2.3 Procedure for writing data to oscillation circuit control register 1 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Bit Bit name Functions At reset RW Main clock division selection bit Sub clock external input selection bit Must be fixed to “1” in the one time PROM and EPROM versions (Notes 1 and 2). Must be fixed to “0” (Note 2). Clock prescaler reset bit Undefined Oscillation circuit control register 1 (address 6F16) 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT . Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. RW RW RW RW WO —Not implemented. Not implemented. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines b1 b0b2b3b4b5b6b7 Notes 1: When writing to this register, follow the procedure shown in Figure 10.2.3. By writing “1” to this bit, clock prescaler is initialized. RW (Note 3) Undefined Main clock external input selection bit 0: Main clock is divided by 2. 1: Main clock is not divided by 2. Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. Ignored in the mask ROM and external ROM versions. 2: The case where data “010101012” is written with the procedure shown in Figure 10.2.3 is not included. 3: In the 7735 Group, fix this bit to “0.” 4: represents that bits 3 to 7 are not used for the watchdog timer. (Note 1) (Note 1) (Note 1) Write data “010101012.” (LDM instruction)

• When writing to bits 0 to 3 Write data “00001XXX2.” (LDM instruction) Next instruction (b3 in Figure 10.2.2) (b2 to b0 in Figure 10.2.2)

7733 Group User’s Manual10-10

10.3 Precautions for watchdog timer

1. If dummy data is written to address 6016 when the data length flag (m) is “0,” writing to address 6116 is simultaneously performed. Accordingly, when a change of the watchdog timer frequency selection flag’s value (bit 0 at address 6116) is not required, write the same value that is set. 2. In order to stop the watchdog timer in the hold state, the count source which is actually counted by the_____ watchdog timer is the logical product of two signals. One is the inverted signal input from pin HOLD, and the other is a count source which is selected by the watchdog timer frequency selection flag (clock f or f512). (Refer to Figure 10.1.1.) Accordingly, there is a possibility that counting is performed when pin_____ HOLD’s input signal level changes during a duration which is shorter than 1 cycle of the selected count source (clock f 32 or f512). Pin HOLD ’s input signal level changes during a duration which is shorter than 1 cycle of clock f32 or f512. HOLD pin input signal Clock f32 or f512 Count source actually counted by watchdog timer Fig. 10.3.1 Watchdog timer’s count source 3. When the main clock is not stably supplied, do not use the software reset (that is, writing “1” to the software reset bit) as a means to reset the microcomputer at a program runaway. 4. When the STP instruction (Refer to chapter “11. STOP AND WAIT MODES” ) is executed, the watchdog timer stops operating. For the system where the watchdog timer is used to detect a program runaway, select “STP instruction disabled” with “STP instruction option” on “MASK ROM ORDER CONFIRMATION FORM.”

7733 Group User’s Manual11–2

The stop and wait modes are described below. When there is no need for operation of the central processing unit (CPU), the stop and wait modes are used to stop oscillation or internal clock φ. The microcomputer enters the stop mode when the STP instruction is executed; the microcomputer enters the wait mode when the WIT instruction is executed. Table 11.1.1 lists the differences between the stop and wait modes. The stop state of oscillation or internal clock φ can be terminated by an interrupt request occurrence or hardware reset. Table 11.1.1 Differences between stop and wait modes

Features

Operating (Note 1) Stopped Operating Stopped Operating Clock timer*1 : Refer to section “7.6 Clock timer.” Clocks f2 to f512, clock φ1*2 : Refer to Figure 11.2.1. Note 1: When the main clock external input selection bit = “1,” the main-clock oscillation circuit stops operating; when the sub clock external input selection bit = “1,” the sub-clock oscillation circuit stops operating. (Note that, in this case, an external clock can be input.) 2: When the main clock is the system clock, pin XIN is used; when the sub clock is the system clock, pin XCIN is used. Less than that when clocks f 2 to f512 operate Less than that when CPU operates Supply of internal clock φ starts after measuring a certain time by watchdog timer. Supply of internal clock φ starts after f2 x 7 cycles. Supply of internal clock φ starts immediately after termination of the wait mode. Less than that in the wait mode Functions using the external clock are enabled. Functions using clocks f2 to f512 are disabled. Operating enabled From the exter- nal, a clock must stably be input to a clock input pin (Note 2). Operation after hardware reset Long Short Oscillation Internal clock φ Clock timer*1 Clocks f2 to f512, clock φ1*2 When terminated by interrupt request occurrence When terminated by hardware reset Current consumption Internal peripheral devices Interval from termination of each mode until execution of instruction Condition

7733 Group User’s Manual 11–3

Figure 11.2.1 shows the block diagram of the clock generating circuit (with the STP and WIT instructions). Figures 11.2.2 and 11.2.3 show the structures of the oscillation circuit control register 0 and oscillation circuit control register 1, respectively. Figure 11.2.4 shows the procedure for writing data to the oscillation circuit control register 1. Fig. 11.2.1 Block diagram of clock generating circuit (with STP and WIT instructions) CMi: Bit i at address 6C16 (Refer to Figure 11.2.2.) CCi: Bit i at address 6F16 (Refer to Figure 11.2.3.) System clock S R Q STP instruction 1/4 1/2 1/2 1/81/2 f64 f512 f2 f8 f16 f32 Internal clock Q R S WIT instruction S R Q Reset Watchdog timer frequency selection flag WDC 12-bit watchdog timer XINXOUT P77/AN7/XCINP76/AN6/XCOUT CC 1 CM 3 CM5 CM 2 CM 3 CC 1 0CM 4 CC 2 ƒ 1 P67/TB2IN/ SUB (Port latch) Timer B2 (Event counter mode) (Clock timer) (Clock prescaler) fC32 CM 4 PC 1 Main clock Sub clock (Oscillation circuit control register 0: address 6C16) CM 2: Main clock stop bit CM 3: System clock selection bit CM 4: Port-Xc selection bit CM 5: System clock stop bit at wait state (Oscillation circuit control register 1: address 6F16) CC0: Main clock division selection bit CC1: Main clock external input selection bit CC2: Sub clock external input selection bit (Port function control register: address 6D16) PC1: Sub-clock output selection bit/Timer B2 clock source selection bit CM 4 PC 1

1 CC 0

Switch represented by is controlled by a signal represented by “ ”. CM 4 CC 2 CM 4 STP instruction

7733 Group User’s Manual11–4

Bit Bit name Functions At reset RW XCOUT drivability selection bit Main clock stop bit System clock selection bit Port-Xc selection bit Not implemented. Un- defined 0: Drivability “LOW” 1: Drivability “HIGH” When the port-Xc selection bit = “0,” 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = “1,” 0: Main clock 1: Sub clock Un- defined Oscillation circuit control register 0 (address 6C16) b1 b0b2b3b4b5b6b7 Notes 0: Main clock oscillation or external clock input is available. 1: Main clock oscillation or external clock input is stopped. RW RW Not implemented. _ RW (Note 1) 0: Operate as I/O ports (P77, P76). 1: Operate as pins XCIN and XCOUT . RW (Notes 2 and 3) RW (Note 2) System clock stop bit at wait state (Note 4) 0: Output is enabled. 1: Output is disabled. (Refer to Tables 12.1.2 and 12.1.5) 0: Operates in the wait mode. 1: Stopped in the wait mode. Signal output disable selection bit RW (Note 1) 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = “1.” 2: When selecting the sub clock as the system clock, set bit 3 to “1” after setting bit 4 to “1.” If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to “1.” 3: Although this bit can be set to “1,” it cannot be cleared to “0” after this bit is once set to “1.” 4: When setting the system clock stop bit at wait state to “1,” perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to “0” immediately after the wait mode is terminated. Fig. 11.2.2 Structure of oscillation circuit control register 0

7733 Group User’s Manual 11–5

Write data “010101012.” (LDM instruction)

• When writing to bits 0 to 3 Write data “00001XXX2.” (LDM instruction) Next instruction (b3 in Figure 11.2.3)(b2 to b0 in Figure 11.2.3) Bit Bit name Functions At reset RW Main clock division selection bit Sub clock external input selection bit Must be fixed to “1” in the one time PROM and EPROM versions (Notes 1 and 2). Must be fixed to “0” (Note 2) Clock prescaler reset bit Undefined Oscillation circuit control register 1 (address 6F16) 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT . Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. RW RW RW RW WO —Not implemented. Not implemented. b1 b0b2b3b4b5b6b7 Notes 1: When writing to this register, follow the procedure shown in Figure 11.2.4. By writing “1” to this bit, clock prescaler is initialized. RW (Note 3) Undefined Main clock external input selection bit 0: Main clock is divided by 2. 1: Main clock is not divided by 2. 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. Ignored in the mask ROM and external ROM versions. 2: The case where data “010101012” is written with the procedure shown in Figure 11.2.4 is not included. 3: In the 7735 Group, fix this bit to “0.” 4: represents that bits 3 to 7 are not used for the stop and wait modes. (Note 1) (Note 1) (Note 1) Fig. 11.2.3 Structure of oscillation circuit control register 1 Fig. 11.2.4 Procedure for writing data to oscillation circuit control register 1

7733 Group User’s Manual11–6

When the STP instruction is executed, the main-clock and sub-clock oscillation circuits stop operating. This state is called “stop mode.” In the stop mode, even when oscillation stops, the contents of the internal RAM can be retained if there is 2 V of Vcc (power source voltage) or more. Furthermore, because the CPU and all internal peripheral devices which use clocks f 2 to f512*1 stop operating, power consumption is lowered. Refer to section “17.4 Power saving” for lowering the power consumption. Table 11.3.1 lists the microcomputer’s state/operation in the stop mode and after the stop mode is terminated. Table 11.3.2 lists the pin state in the stop mode. Table 11.3.1 Microcomputer’s state/operation in stop mode and after stop mode is terminated f(XIN)/32 f(XCIN )/32 Stopped Stopped Operating enabled only in the event counter mode Operating enabled only when the external clock is selected Stopped Stopped Refer to Table 11.3.2 Internal peripheral devices Clocks f2 to f512*1, clock φ1*2 : Refer to Figure 11.2.1. Clock timer*3 : Refer to section “7.6 Clock timer.” Clock input pin*4 : When the system clock is the main clock, pin XIN is used; when the system clock is the sub clock, pin XCIN is used. h In order to select whether to use the watchdog timer or not when terminating the stop mode, specify the main clock external input selection bit (bit 1 at address 6F16; when the main clock is used) or the sub clock external input selection bit (bit 2 at address 6F16; when the sub clock is used). (Refer to Figure 11.2.3, sections “11.3.2 Stop mode terminating operation by interrupt request occur- rence (when using watchdog timer)” and “11.3.3 Stop mode terminating operation by interrupt request occurrence (when not using watchdog timer).” State/Operation Watchdog timer is used when terminating the stop mode Watchdog timer is not used when terminating the stop mode Supply of internal clock φ starts after measuring a certain time by watchdog timer. Operation after hardware reset Supply of internal clock φ starts after f2 x 7 cycles. Condition From the external, a clock must stably be input to a clock input pin *4. Oscillation Internal clock φ Clocks f2 to f512*1, clock φ1*2 Clock timer*3 Timer A, Timer B Serial I/O A-D converter Watchdog timer Pins

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Table 11.3.2 Pin state in stop mode Single-chip mode Memory expansion Microprocessor mode mode Pins When the standby state selection bit∗1 = “0” When the standby state selection bit∗1 = “1” n When the signal output disable selection bit = “0,” “H” level is output n When the signal output disable selection bit = “1,” “L” level is output. n When the signal output disable selection bit = “0,” “H” level is output. n When the signal output disable selection bit = “1,” “L” level is output. Same as in the micro- processor mode “H” level is output. E R/W, ____ BHE, HLDA ALE A 0–A 7, A8/D8–A 15/D15, A16/D0–A 23/D7 “L” level is output. Retains the same state in which the STP instruction is executed. n When the clock φ1 output selection bit*2 = “1” φ1: “L” level is output. n When the clock φ1 output selection bit = “0” P42: Retains the same state in which the STP instruction is executed. P0 to P8 (not including P42) :Retains the same state in which the STP instruction is executed. P4 3 to P47, P5 to P8 :Retains the same state in which the STP instruction is executed. Ports n When the signal output disable selection bit*3 = “0” φ1: “L” level is output. n When the signal output disable selection bit = “1” 2: Bit 2’s value of the port P4 register is output (Note). P42/φ1 Standby state selection bit*1: Bit 0 at address 6D16 (Refer to Figure 11.3.1.) Clock φ1 output selection bit*2: Bit 7 at address 5E16 (Refer to section “12.1 Signals required for accessing external devices.”) Signal output disable selection bit*3: Bit 6 at address 6C16 (Refer to section “12.1 Signals required for accessing external devices.”) Note: Make sure to set bit 2 of the port P4 direction register to “1.”

11.3.1 Output levels of external bus and bus control signals in stop mode

In the memory expansion or microprocessor mode, the output levels of the external bus and bus control signals in the stop mode can be set by software. By setting the standby state selection bit (bit 0 at address 6D 16) to “1,” these output levels become levels set by software. Figure 11.3.1 shows an output level setting example in the stop mode. In the single-chip mode, do not set the standby state selection bit to “1.” Output levels can be set. (Refer to section “11.3.1 Output levels of external bus and bus control signals in stop mode.”)

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executed. Note 2: This bit’s value also affects the pin state in the wait mode. (Refer to Figure 11.4.1.) Setting of the output levels for the external bus and bus control signals (not including E ) b7 b0 Port P0 direction register (address 416) Port P1 direction register (address 516) Port P2 direction register (address 816) Port P3 direction register (address 916) Must be fixed to “FF16.” b7 b0 Set output level by the bit which corresponds to each pin. 0: “L” level output 1: “H” level output Note 3: This bit's value also affects the following:

• Output state of bus control signals and others after the stop mode is terminated (Refer to chapter “12. CONNECTING EXTERNAL DEVICES”)
• Pin state in the wait mode. (Refer to Figure 11.4.1.) Furthermore, description of pin P42/ 1 is applied only in the microprocessor mode. Setting of E signal’s output level (Setting of pin P42/ 1’s state) b7 b0 Oscillation circuit control register 0 (address 6C16) Signal output disable selection bit (Note 3) 0: In the stop mode, pin E outputs “H” level, and pin P42/ 1 outputs “L” level. 1: In the stop mode, pin E outputs “L” level, and pin P42/ 1 outputs bit 2’s value of port P4 register. Port function control register (address 6D16) Standby state selection bit (Note 2) b7 b0 Setting of the standby state selection bit to “1” b7 b0 Port P4 direction register (address C16)1 b7 b0 Port P4 register (address A16) 0: “L” level output 1: “H” level output
• When setting the signal output disable selection bit to “1” in the microprocessor mode
• When setting the clock 1 output selection bit to “0” in the memory expansion mode
• When setting the signal output disable selection bit to “0” in the microprocessor mode
• When setting the clock 1 output selection bit to “1” in the memory expansion mode Note 1: This is applied only in the microprocessor mode. In the memory expansion mode, it may be “0” or “1” because the I/O port function is selected. (Note 1) Port P0 register (address 216) Port P1 register (address 316) Port P2 register (address 616) Port P3 register (address 716)

Fig. 11.3.1 Output level setting example in stop mode (Memory expansion or Microprocessor mode) 1 1 1 1 1 1 1

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11.3.2 Stop mode terminating operation by interrupt request occurrence (when using watchdog timer)

When there is little possibility that a clock is stably supplied from an oscillation circuit (Note 1) in returning from the stop mode, instruction execution can be started after a certain time (Note 2) measured by the watchdog timer. Notes 1: A clock is supplied in one of the following ways: l An oscillation circuit operates by itself. l An external clock is input. 2: “a certain time” means an interval from occurrence of an interrupt request until stabilization of clock supply. À When an interrupt request occurs, an oscillator starts oscillating. Simultaneously, supply of clocks f2 to f512 starts. \` By start of oscillation, the watchdog timer starts counting. The watchdog timer counts f32 when the system clock selection bit (bit 3 at address 6C16; Refer to Figure 11.2.2.) = “0” or f8 when the system clock selection bit = “1.” ´ When the watchdog timer’s MSB becomes “0,” supply of internal clock φ starts. At the same time, the watchdog timer’s count source returns to a count source (clock f32 or f512) which is selected by the watchdog timer frequency selection flag (bit 0 at address 6116). ˆ The interrupt request which occurs in À is accepted. Table 11.3.3 lists interrupts which can be used for termination of the stop mode. Table 11.3.3 Interrupts which can be used for termination of stop mode When the key input interrupt function is selected ____ INT2 interrupt: When the key input interrupt function is invalid. In the event counter mode When the external clock is selected Interrupt Conditions for each function which generates interrupt request Key input interrupt ____ INTi interrupt (i = 0 to 2) Timer Ai interrupt (i = 0 to 4) Timer Bi interrupt (i = 0 to 2) UARTi transmission interrupt (i = 0, 1) UARTi reception interrupt (i = 0, 1) UART2 transmission/reception interrupt Note 1: Because an oscillator has stopped oscillating, each function is available only in the conditions listed in Table 11.3.3. Note that the A-D converter and clock timer (Refer to section “7.6 Clock timer”) do not operate, also. 2: Because an oscillator has stopped oscillating, interrupts not listed in Table 11.3.3 cannot be used. 3: For each interrupt, refer to chapters “4. INTERRUPTS,” “5. KEY INPUT INTERRUPT FUNCTION,” “6. TIMER A,” “7. TIMER B,” and “8. SERIAL I/O.”

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When using the watchdog timer in termination of the stop mode, make sure to set as follows before executing the STP instruction. n Enable an interrupt which is used for termination. Also, make sure that the interrupt priority level of an interrupt which is used for termination is higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed. Furthermore, when multiple interrupts in Table 11.3.3 are enabled, the stop mode is terminated by the interrupt request which occurs first. After oscillation starts (À ), there is a possibility that an interrupt request occurs until the supply of internal clock φ starts (´ ). Interrupt requests which occur during this period are accepted in order of priority after the watchdog timer’s MSB becomes “0.” For interrupts which have no need to be accepted, set their interrupt priority levels to “0” (Interrupt disabled) before executing the STP instruction. n When the system clock is the main clock or the main clock divided by 8, set the main clock external input selection bit (bit 1 at address 6F16; Refer to Figure 11.2.3.) to “0.” When the system clock is the sub clock, set the sub clock external input selection bit (bit 2 at address 6F16) to “0.”

11.3.3 Stop mode terminating operation by interrupt request occurrence (when not using watchdog timer)

instruction execution can be started immediately after the termination of the stop mode. À When an interrupt request occurs, clock input from pin XIN starts. Simultaneously, supply of clocks f2 to f512 starts. \` Supply of internal clock φ starts after 7 cycles of f2. ´ The interrupt request which occurs in À is accepted. Table 11.3.3 lists interrupts which can be used for termination. When not using the watchdog timer in termination of the stop mode, make sure to set as follows before executing the STP instruction. n Enable an interrupt which is used for termination. Also, make sure that the interrupt priority level of an interrupt which is used for termination is higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed. Furthermore, when multiple interrupts in Table 11.3.3 are enabled, the stop mode is terminated by the interrupt request which occurs first. n When the system clock is the main clock or the main clock divided by 8, set the main clock external input selection bit (bit 1 at address 6F16; Refer to Figure 11.2.3.) to “1.” When the system clock is the sub clock, set the sub clock external input selection bit (bit 2 at address 6F16) to “1.”

Interrupt request which was used for STOP AND W AIT MODES

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When not using watchdog timer l Watchdog timer starts counting. l Supply of CPU (internal clock ) starts. l Interrupt request which was used for termination is accepted. Internal clock CPU Internal peripheral devices l STP instruction is executed l Interrupt request which is used for termination occurs. l Clock input from pin XIN or XCIN starts. Value of watchdog timer “FFF16” “7FF16” Interrupt request which is used for termination (Interrupt request bit) System clock : f(XIN) or f(XCIN) l Interrupt request which is used for termination occurs. l Oscillation starts. (When an external clock is input from pin XIN, clock input starts.) Watchdog timer starts counting. Internal clock CPU Internal peripheral devices l STP instruction is executed l Watchdog timer’s MSB = “0” (However, watchdog timer interrupt request does not occur.) Supply of CPU (internal clock ) starts. l termination is accepted. Value of watchdog timer “FFF16” “7FF16” Interrupt request which is used for termination (Interrupt request bit) When using watchdog timer System clock : f(XIN) or f(XCIN) Note 1: Sub clock (f(XCIN)) is stopped at “L” level in the stop mode. Stopped 32/f(XIN) 5 2048 counts or 8/f(XCIN) 5 2048 counts Stop mode (Note 1) Operating Operating Operating Operating Operating 2/f(XIN) 5 7 counts Stop mode (Note 2) StoppedOperating Operating Operating Operating OperatingStopped Stopped Note 2: In the stop mode, clock input can be stopped. In order to stop clock input, be sure to generate an interrupt request after a clock is stably supplied when returning from the stop mode. “0” “1” “0” “1” Fig. 11.3.2 Stop mode terminating sequence by interrupt request occurrence l l

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11.3.4 Stop mode terminating operation by hardware reset

When terminating the stop mode by hardware reset, input “L” level to pin RESET from the external circuit until oscillation of an oscillator which is connected to the main-clock oscillation circuit is stabilized. The CPU and SFR area are initialized in the same way as at system reset. However, the internal RAM area retains the same contents as that before the STP instruction was executed. The terminating sequence is the same as the internal processing sequence after reset. When determining whether hardware reset was applied for termination of the stop mode or system reset was applied, use software after reset. For reset, refer to chapter “13. RESET.”

11.3.5 Precautions for stop mode

1. In the mask ROM version, select “STP instruction enabled” with “STP instruction option” on “MASK ROM ORDER CONFIRMATION FORM.” (In the built-in PROM and external ROM versions, STP instruction is always enabled.) 2. “Stop mode terminating operation by an interrupt request occurrence (when not using watchdog timer)” can be selected only when an external clock is stably input to a clock input pin for a clock which is selected as the system clock. In one of the following cases, select “Stop mode terminating operation by an interrupt request occur- rence (when using watchdog timer)”: l When an oscillator is connected between input and output pins for a clock which is selected as the system clock l When there is a possibility that the above external clock is temporarily unstable in termination of the stop mode

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When the WIT instruction is executed, internal clock φ stops. (The oscillator does not stop oscillating.) This state is called “wait mode.” In the wait mode, power consumption can be lowered with Vcc (power source voltage) retained. Refer to section “17.4 Power saving” for lowering the power consumption. Table 11.4.1 lists the microcomputer’s state/operation in the wait mode and after the wait mode is terminated. Table 11.4.2 lists the pin state in the wait mode. Table 11.4.1 Microcomputer’s state/operation in wait mode and after wait mode is terminated Supply of internal clock φ starts immediately after termination. Operation after hardware reset State in wait mode Operation after wait mode is terminated Stopped Operating Stopped Operating Refer to Table 11.4.2. Oscillation Internal clock φ Clocks f2 to f512*1, clock φ1*2 Clock timer Timer A, Timer B Serial I/O A-D converter Watchdog timer Pins Internal peripheral devices f(XIN)/32 f(XCIN )/32 Stopped Operating Item Clocks f2 to f512∗1, clock φ1∗2 : Refer to Figure 11.2.1. Clock timer∗3 : Refer to section “7.6 Clock timer.” h In order to select the state of clocks f2 to f512 in the wait mode, specify the system clock stop bit at wait state (bit 5 State/Operation When clocks f2 to f512 are stopped When clocks f2 to f512 are not stopped Operating enabled only in the event counter mode. Operating enabled only when the external clock is selected.

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Table 11.4.2 Pin state in wait mode State Single-chip mode Memory expansion Microprocessor mode mode Pins When the standby state selection bit∗1 = “0” When the standby state selection bit ∗1 = “1” n When the signal output disable selection bit = “0,” “H” level is output. n When the signal output disable selection bit = “1,” “L” level is output. n When the signal output disable selection bit = “0,” “H” level is output. n When the signal output disable selection bit = “1,” “L” level is output. Same as in the micro- processor mode “H” level is output. E R/W, ____ BHE, HLDA ALE A 0–A 7, A 8/D8–A 15/D15, A 16/D0–A 23/D7 Output levels can be set. (Refer to section “11.4.2 Output levels of external bus and bus control signals in wait mode”) “L” level is output. n When the signal output disable selection bit*3 = “0” φ1: Operating when the system clock stop bit at wait state = “0.” “L” level is output when the system clock stop bit at wait state = “1.” n When the signal output disable selection bit = “1” P4 2: Bit 2’s value of port P4 register is output (Note). n When the clock φ1 output selection bit*2 = “1” φ1: Operating when the system clock stop bit at wait state*4 = “0.” “L” level is output when the system clock stop bit at wait state = “1.” n When the clock φ1 output selection bit = “0” P4 2: Retains the same state in which the WIT instruction is executed. P42/φ1 Retains the same state in which the WIT instruction is ex- ecuted. P4 3 to P47, P5 to P8 : Retains the same state in which the WIT instruction is executed. Ports P0 to P8 (not including P42) : Retains the same state in which the WIT instruction is executed. Standby state selection bit*1: Bit 0 at address 6D16 (Refer to Figure 11.4.1.) Clock φ1 output selection bit*2: Bit 7 at address 5E16 (Refer to section “12.1 Signals required for accessing external devices.”) Signal output disable selection bit*3: Bit 6 at address 6C16 (Refer to section “12.1 Signals required for accessing external devices.”) System clock stop bit at wait state*4: Bit 5 at address 6C16 (Refer to section “11.4.1 State of clocks f2 to f512 in wait mode.”) Note: Make sure to set bit 2 of the port P4 direction register to “1.”

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11.4.1 State of clocks f2 to f512 in wait mode

The state of clocks f2 to f512 in the wait mode can be selected by the system clock stop bit at wait state (bit 5 at address 6C16: Refer to Figure 11.2.2.). When supply of clocks f2 to f512 is stopped in the wait mode, power consumption can further be lowered. When supply of clocks f2 to f512 is stopped, internal peripheral devices which use clocks f2 to f512 stop operating as in the stop mode. Furthermore, when pin P42/φ1 functions as a clock φ1 output pin, this pin outputs “L” level. (Refer to Table 11.4.2.) When supply of clocks f2 to f512 is not stopped, both of the internal peripheral devices’ operation and clock φ1 output do not stop. Note that, in the microprocessor mode, clock φ1 output stops when the signal output disable selection bit = “1.” In both cases, internal clock φ stops, so that the CPU does not operate. Furthermore, because clock fc32 does not stop operating, the clock timer continues operating. (Refer to Table 11.4.3.)

11.4.2 Output levels of external bus and bus control signals in wait mode

In the memory expansion or microprocessor mode, the output levels of the external bus and bus control signals in the wait mode can be set by software. By setting the standby state selection bit (bit 0 at address 16) to “1,” these output levels become levels set by software. Figure 11.4.1 shows an output level setting example in the wait mode. In the single-chip mode, do not set the standby state selection bit to “1.” (Fix this bit to “0.”)

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• When setting the signal output disable selection bit to “1” in the microprocessor mode
• When setting the clock 1 output selection bit to “0” in the memory expansion mode Note 2: This bit’s value also affects the pin state in the stop mode. (Refer to Figure 11.3.1.) Setting of the output levels for the external bus and bus control signals (not including E) b7 b0 Port P0 direction register (address 416) Must be fixed to “FF16.” Port P1 direction register (address 516) Port P2 direction register (address 816) Port P3 direction register (address 916) b7 b0 Port P0 register (address 216) Set output level by the bit which corresponds to each pin. 0: “L” level output 1: “H” level output Port P1 register (address 316) Port P2 register (address 616) Port P3 register (address 716) Setting of E signal’s output level (Setting of pin P42/ 1’s state) b7 b0 Oscillation circuit control register 0 (address 6C16) Signal output disable selection bit (Note 3) 0: In the wait mode, pin E outputs “H” level. Pin P42/ 1 operates when system clock stop bit at wait state = “0” and outputs “L” level when this bit = “1.” 1: In the wait mode, pin E outputs “L” level. Pin P42/ 1 outputs bit 2’s value of port P4 register. Port function control register (address 6D16) Standby state selection bit (Note 2) b7 b0 Setting of the standby state selection bit to “1” b7 b0 Port P4 direction register (address C16)1 b7 b0 Port P4 register (address A16) 0: “L” level output 1: “H” level output WIT instruction is executed. Note 3: This bit’s value also affects the following:
• Output state of bus control signals and others after the wait mode is terminated (Refer to chapter “12. CONNECTING EXTERNAL DEVICES.” )
• Pin state in the stop mode. (Refer to Figure 11.3.1.) Furthermore, description of pin P42/ 1 is applied only in the microprocessor mode.
• When setting the signal output disable selection bit to “0” in the microprocessor mode
• When setting the clock 1 output selection bit to “1” in the memory expansion mode Note 1: This is applied only in the microprocessor mode. In the memory expansion mode, it may be “0” or “1” because the I/O port function is selected. (Note 1)

Fig. 11.4.1 Output level setting example in wait mode (Memory expansion or Microprocessor mode) 1 1 1 1 1 1 1

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11.4.3 Wait mode terminating operation by interrupt request occurrence

À When an interrupt request occurs with supply of clocks f2 to f512 stopped, the clock supply restarts. \` Supply of internal clock φ starts. ´ The interrupt request which occurs in À is accepted. An interrupt which can be used for termination depends on the state of clocks f2 to f512 in the wait mode. (Refer to Table 11.4.3.) Table 11.4.3 Interrupts which can be used for termination of wait mode Conditions for each function which generates interrupt requestInterrupt When the key input interrupt function is selected ____ INT2 interrupt: When the key input interrupt function is invalid. Enabled only when the external clock is selected Disabled When timer B2 functions as the clock timer Disabled Key input interrupt ____ INTi interrupt (i = 0 to 2) Timer Ai interrupt (i = 0 to 4) Timer Bi interrupt (i = 0 to 2) UARTi transmission interrupt (i = 0 to 2) UARTi reception interrupt (i = 0 to 2) Clock timer (timer B2) interrupt A-D conversion interrupt When clocks f2 to f512 are not stopped In the event counter mode Enabled in all modes Always enabled f(XIN)/32 f(XCIN )/32 Enabled in one-shot mode and single sweep mode Clock timer∗: Refer to section “7.6 Clock timer.” h For each interrupt, refer to chapters “4. INTERRUPTS,” “5. KEY INPUT INTERRUPT FUNCTION,” Before executing the WIT instruction, be sure to enable an interrupt which is used for termination. Also make sure that the interrupt priority level of an interrupt which is used for termination is higher than the processor interrupt priority level (IPL) of a routine where the WIT instruction is executed. Furthermore, when multiple interrupts in Table 11.4.3 are enabled, the wait mode is terminated by the interrupt request which occurs first.

11.4.4 Wait mode terminating operation by hardware reset

The CPU and SFR area are initialized in the same way as at system reset. However, the internal RAM area retains the same contents as that before the WIT instruction was executed. The terminating sequence is the same as the internal processing sequence after reset. When determining whether hardware reset was applied for termination of the wait mode or system reset was applied, use software after reset. For reset, refer to chapter “13. RESET.” When clocks f2 to f512 are stopped

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12.1 Signals required for accessing

CONNECTING EXTERNAL DEVICES

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Functions and operations of signals required for accessing external devices are described below. When connecting external devices which require a long access time, refer to sections “12.2 Software wait,” “12.3 Ready function,” and “12.4 Hold function,” also. When connecting external devices, make sure that the microcomputer operates in the memory expansion or microprocessor mode. (Refer to section “2.5 Processor modes.”) When the microcomputer operates in these modes, ports P0 to P4 and pin E function as I/O pins of signals required for accessing external devices. lists the functions of ports P0 to P4 and pin E in the memory expansion or microprocessor mode.

CONNECTING EXTERNAL DEVICES

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h 1 in the microprocessor mode By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin’s level can be fixed in the stop or wait mode. When external data bus is 8 bits wide (BYTE = “H”) : External address bus, external data bus, and bus control signals When external data bus is 16 bits wide (BYTE = “L”) : External address bus, external data bus, and bus control signals A20/D4(P24) A21/D5(P25) A22/D6(P26) A23/D7(P27) R/W(P3 0) BHE(P3 1) ALE(P32) HLDA(P3 3) Vss E XOUT XIN RESET CNV SS BYTE HOLD A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A16/D0(P20) A17/D1(P21) A18/D2(P22) A19/D3(P23)RDY P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 A0(P00) A1(P01) A2(P02) A3(P03) A4(P04) A5(P05) A6(P06) A7(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 14 325 P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 6 7 8 9 101 1 121 31 41 51 61 7 181 9 202 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 M37733MHBXXXFP 22 23 24 P47 P46 P45 P44 P43 h P42/ 1 A20/D4(P24) A21/D5(P25) A22/D6(P26) A23/D7(P27) R/W(P3 0) BHE(P3 1) ALE(P32) HLDA(P3 3) Vss E XOUT XIN RESET CNVss BYTE HOLD RDY A11(P13) A12(P14) A13(P15) A14(P16) A15(P17) A16/D0(P20) A17/D1(P21) A18/D2(P22) A19/D3(P23) P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 A0(P00) A1(P01) A2(P02) A3(P03) A4(P04) A5(P05) A6(P06) A7(P07) A8(P10) A9(P11) A10(P12) 14 32 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 40P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 M37733MHBXXXFP P47 P46 P45 P44 P43 h P42/ 1 h 1 in the microprocessor mode By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin’s level can be fixed in the stop or wait mode. Fig. 12.1.1 Pin configuration in memory expansion or microprocessor mode (Top view)

This signal is affected by the signal output disable selection bit (bit 6 at address 6C CONNECTING EXTERNAL DEVICES

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Notes 1: In the memory expansion mode, this pin functions as a programmable I/O port. Furthermore, it can be switched to be a clock 1 output pin when selected by software. In the microprocessor mode, this pin is affected by the signal output disable selection bit (bit 6 at address 6C16). (Refer to Table 12.1.5.) 2: 16). (Refer to Table 12.1.2.) Pin name HLDA ALE 16 bits (BYTE = “L”) 8 bits (BYTE = “H”) External data bus width ALE P RDY HOLD RDY HOLD E (Note 2) P : Functions as programmable I/O port P47 to P43 (Note 1) HLDA R/W BHE P47 to P43 HOLD RDY BHE ALE R/W HLDA A7 to A0 A7 to A0A7 to A0 A15/D15 to A8/D8 A15 to A8 D(odd) D(odd) : Data at odd address A15/D15 to A8/D8 A 15 to A8A15 to A8 A23/D7 to A16/D0 A23 to A16 D(even) D(even) : Data at even address A23/D7 to A16/D0 A23 to A16 A23/D7 to A16/D0 D D : Data BHE R/W E Table 12.1.1 Functions of ports P0 to P4 and pin E in memory expansion or microprocessor mode

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: External area 00000016 Internal RAM area SFR area Memory expansion mode 02000016 FFFFFF 16 Internal RAM area SFR area Microprocessor mode 00100016 00000016 FFFFFF 16 00100016 00008016 Internal ROM area (Note) 00008016 Note: This is applied when the memory allocation selection bits (bits 2 to 0 at address 6316) = “0002.” For details, refer to section “2.4 Memory allocation.”

12.1.1 External bus (A0 to A7, A8/D8 to A15/D15, and A16/D0 to A23/D7)

The address is output from pins A0 to A23 and specify the external area. Figure 12.1.2 shows the external area. Pins A8 to A23 of the external address bus and pins D0 to D15 of the external data bus share the same pins. When pin BYTE’s level, which is described later, is “L,” in other words, when the external data bus is 16 bits wide, pins A8/D8 to A15/D15 and A16/D0 to A23/D7 perform address output and data input/ output with the time-sharing method. When pin BYTE’s level is “H,” in other words, when the external data bus is 8 bits wide, pins A16/D0 to A23/D7 perform address output and data input/output with the time-sharing method and pins A8 to A15 output the address. Fig. 12.1.2 External area

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12.1.2 External data bus width selection signal (Pin BYTE’s level)

This signal is used to select the external data bus width from 8 bits and 16 bits. When this signal level is “L,” the external data bus is 16 bits wide; when this signal level is “H,” the external data bus is 8 bits This signal is valid only for the external areas. (When the internal area is accessed, the data bus is always 16 bits wide.)

12.1.3 Enable signal (E)

When data is read or written, this signal level is “L.” This signal is affected by the signal output disable selection bit (bit 6 at address 6C16). (Refer to Table 12.1.2.) Table 12.1.2 E state When the external area is accessed When the internal area is accessed When the standby state selection bit = “1” in the stop or wait mode When the standby state selection bit = “0” in the stop or wait mode When not in the stop or wait mode When in the stop or wait mode Signal output disable selection bit Memory expansion or Microprocessor mode Single-chip mode Processor mode Conditions Table 12.1.3 Data bus state E R/W Data bus state H H Not used L L H Read L Write h For the stop and wait modes and the standby state selection bit, refer to chapter “11. STOP AND WAIT MODES.” : Not affected by the signal output disable selection bit.

12.1.4 Read/Write signal (R/W )

This signal indicates data bus state. When data is written, this signal level is “L.” Table 12.1.3 lists the data __ __ bus state indicated by signals E and R/W . Operating Operating Stopped at “H” level Stopped at “H” level Stopped at “L” level Stopped at “H” level Operating Stopped at “L” level Stopped at “H” level Stopped at “L” level

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____

12.1.5 Byte high enable signal (BHE )

This signal indicates access to an odd address. This signal level is “L” when accessing only an odd address or when simultaneously accessing both an odd address and an even address. This signal is used when connecting memory or I/O of which data bus is 8 bits wide with the 16-bit external data bus used. Table 12.1.4 lists the relationship between signal A0 of the external address bus, signal ____ BHE , and access address. ____ Table 12.1.4 Relationship between signals A0, BHE and access address A 0 ____ BHE Access address Odd address (1-byte access) H L Even and Odd addresses (Simultaneous 2-byte access) L L L H Even address (1-byte access)

12.1.6 Address latch enable signal (ALE)

This signal is used to latch an address from a multiplexed signal. This multiplexed signal consists of the address and data and is input or output to or from pins A 8/D8 to A15/D15, A16/D0 to A23/D7. When this signal level is “H,” take the address into a latch and output it simultaneously. When this signal level is “L,” retain the latched address. ____

12.1.7 Signal related to ready function (RDY )

This signal is required to use the ready function. (Refer to section “12.3 Ready function.”)

12.1.8 Signals related to hold function (HOLD , HLDA )

These signals are required to use the hold function. (Refer to section “12.4 Hold function.”)

12.1.9 Clock φ1

This signal has the same period as internal clock φ. Whether to output or stop clock φ1 can be selected by software. However, the method of this selection depends on the processor mode. Table 12.1.5 lists the method to select whether to output or stop clock φ1. Figure 12.1.3 shows the clock φ1 output start timing. Table 12.1.5 Method to select whether to output or stop clock φ1 Clock φ1 output Clock φ1 stopped Remark Processor mode Single-chip or Memory expansion mode Microprocessor mode Clear the signal output disable selection bit*2 to “0.” Set the signal output disable selection bit to “1.” (Note) Clock φ1 is output after reset. The clock φ1 output selection bit is ignored. Set the clock φ1 output selection bit*1 to “1.” Clear the clock φ1 output selection bit to “0.” (Pin P42 functions as a programmable I/O port.) Clock φ1 is stopped after reset. The signal output disable selection bit is ignored. Clock φ1 output selection bit*1: Bit 7 at address 5E16 Signal output disable selection bit*2: Bit 6 at address 6C16 (Refer to Table 12.1.2.) Note: In this case, make sure that bit 2 at address C16 (Port P4 direction register) is set to “1.” When bit 2 at address A16 (Port P4 register) = “0,” “L” level is output: when this bit = “1,” “H” level is output.

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1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = “1.” 2: When selecting the sub clock as the system clock, set bit 3 to “1” after setting bit 4 to “1.” If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to “1.” 3: Although this bit can be set to “1,” it cannot be cleared to “0” after this bit is once set to “1.” 4: When setting the system clock stop bit at wait state to “1,” perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to “0” immediately after the wait mode is terminated. 5: represents that bits 0 to 5 and 7 are not used for access control of external area. (Functions of these bits are valid.) Bit Bit name Functions At reset RW XCOUT drivability selection bit Main clock stop bit System clock selection bit Port-Xc selection bit. Not implemented. Un- defined 0: Drivability “LOW” 1: Drivability “HIGH” When the port-Xc selection bit = “0,” 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = “1,” 0: Main clock 1: Sub clock Un- defined Oscillation circuit control register 0 (address 6C16) b1 b0b2b3b4b5b6b7 Notes 0: Main clock oscillation or external clock input is available. 1: Main clock oscillation or external clock input is stopped. RW RW Not implemented. RW (Note 1) 0: Operate as I/O ports (P77, P76). 1: Operate as pins XCIN and XCOUT . RW (Notes 2 and 3) RW (Note 2) System clock stop bit at wait state (Note 4) 0: Output is enabled. 1: Output is disabled. (Refer to Tables 12.1.2 and 12.1.5) 0: Operates in the wait mode. 1: Stopped in the wait mode. Signal output disable selection bit RW (Note 1) Fig. 12.1.3 Clock φ1 output start timing (when clock φ1 output selection bit is set from “0” to “1”) Fig. 12.1.4 Structure of oscillation circuit control register 0 Clock 1 E Notes 1: There is a possibility that the first cycle of clock1 output is not an exact square; the shaded section may be lost. 2: This is applied when “1” is written to the clock1 output selection bit while pin P42 outputs “L” level. The clock 1 output selection bit is set to “1.”

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Signal is stopped. Clock 1 (in the microprocessor mode) Value “1” is written to the signal output disable selection bit. E (Note) Fig. 12.1.5 Relationship between setting of signal output disable selection bit and stop timing of clock φ1 and E

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12.1.10 Operation of bus interface unit (BIU)

Figures 12.1.6 and 12.1.7 show operating waveform examples of signals which are input to or output from the external when accessing external devices. These waveforms are described in relation to the basic operating waveforms. (Refer to section “2.2.3 Operation of bus interface unit (BIU).”) (1) When fetching an instruction into an instruction queue buffer À When an instruction which is next fetched resides at an even address When the external data bus is 16 bits wide, the BIU fetches two bytes of the instruction at a time with waveform (a). When the external data bus is 8 bits wide, the BIU fetches only one byte of the instruction with the first half of waveform (e). \ When an instruction which is next fetched resides at an odd address When the external data bus is 16 bits wide, the BIU fetches only one byte of the instruction with waveform (d). When the external data bus is 8 bits wide, the BIU fetches only one byte of the instruction with the first half of waveform (f). When branched to an odd address by executing a branch instruction or others with the 16-bit external data bus, at first, the BIU fetches one byte of an instruction with waveform (d) and then fetches instructions by the two bytes with waveform (a). (2) When reading or writing data from or to memory • I/O À When accessing 16-bit data which starts from an even address, waveform (a) or (e) is applied. \ When accessing 16-bit data which starts from an odd address, waveform (b) or (f) is applied. ´ When accessing 8-bit data which resides at an even address, waveform (c) or the first half of waveform (e) is applied. ˆ When accessing 8-bit data which resides at an odd address, waveform (d) or the first half of waveform (f) is applied. For instructions which are affected by data length flag (m) and index register length flag (x), an operation is applied as follows:

• When “m” or “x” = “0,” operation À or \` is applied.
• When “m” or “x” = “1,” operation ´ or ˆ is applied. Settings of flags “m” and “x” and selection of the external data bus width do not affect each other.

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Fig. 12.1.6Operating waveform examples of signals which are input to or output from the external (1) l When external data bus is 16 bits wide (BYTE = “L” ) <16-bit data access> A0 to A7 Address A8/D8 to A15/D15 Data (odd) BHE E A 0 (a) Access starting from even address ALE A16/D0 to A23/D7 Data (even) A0 to A7 A8/D8 to A15/D15 E (b) Access starting from odd address ALE Address Address Address Address Address AddressData (odd) <8-bit data access> A0 to A7 A16/D0 to A23/D7 E (d) Access to odd address ALE BHE A8/D8 to A15/D15 A0 to A7 A16/D0 to A23/D7 E (c) Access to even address ALE BHE A8/D8 to A15/D15 BHE A 0 A16/D0 to A23/D7 Address Address Data (even) Address Address Address Address Address AddressData (even) Data (odd)

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Fig. 12.1.7 Operating waveform examples of signals which are input to or output from the external (2) l When external data bus is 8 bits wide (BYTE = “H” ) <8/16-bit data access> Note: When 16-bit data is accessed, the low-order 8 bits of data are accessed first, and then, the high-order 8 bits are accessed. E (f) Access starting from odd address ALE A 0 to A 7 BHE A8 to A15 A16/D0 to A23/D7 E (e) Access starting from even address ALE A0 to A7 Address BHE A8 to A15 A16/D0 to A23/D7 Data 8-bit data access 16-bit data access 8-bit data access 16-bit data access Address Address Address Address Address Data Address Address AddressAddress Address AddressData Data

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The software wait facilitates access to external devices which require a long access time. There are two types of software waits: wait 0 and wait 1. The software wait is set by the wait bit (bit 2 at address 5E16) and the wait selection bit (bit 0 at address 5E 16) and processor mode register 1 (address 5F16). Figure 12.2.2 shows bus timing examples when the software wait is used. The software wait is valid only for the external area. (Access to the internal areas is always performed with no wait.) Table 12.2.1 Setting method of software wait Wait bit Wait selection bit Software wait Bus cycle Invalid (No wait) Wait 0 Wait 1 Cycle of “internal clock φ divided by 2” (clock φ1’s cycle 5 2) “Cycle in the no-wait state” 5 2 (clock φ1’s cycle 5 4) “Cycle in the no-wait state” 5 1.5 (clock φ1’s cycle 5 3)

represents that bits 3 to 6 are not used for access control of the external area. CONNECTING EXTERNAL DEVICES

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Processor mode register 1 (address 5F16) Bit Bit name Function At reset 7 to1 Wait selection bit 0 : Wait 0 1 : Wait 1 0 Not implemented. Un- defined RW RW Bit Bit name Functions At reset RW Processor mode bits Wait bit Software reset bit Interrupt priority detection time selection bits Must be fixed to “0.” Clock f1 output selection bit (Note 2) 00: Single-chip mode 01: Memory expansion mode 10: Microprocessor mode 11: Do not select. 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. Microcomputer is reset by setting this bit to “1.” This bit is “0” at reading. 00: 7 cycles of f 01: 4 cycles of f 10: 2 cycles of f 11: Do not select. 0: Clock f1 output is disabled. (P42 functions as a programmable /O port.) 1: Clock f1 output is enabled. (Port P42 functions as a clock f1 output pin.) b1 b0 b5 b4 Processor mode register 0 (address 5E16) (Note 1) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to “1” after reset. (At reading, this bit is always “1.”) This bit is ignored in the microprocessor mode. (It may be “0” or “1.”) (Functions of these bits are valid.) b1 b0b2b3b4b5b6b7 RW RW RW WO RW RW RW RW Fig. 12.2.1 Structures of processor mode register 0 and processor mode register 1

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A 8/D8 to A15/D15, A16/D0 to A23/D7 ALE Address Data 1-bus cycle (Note) E l This waveform is always applied when the internal area is accessed. <<Wait 0>> A 0 to A7 A 8/D8 to A15/D15, A16/D0 to A23/D7 ALE <<Wait 1>> Clock 1 A8/D8 to A15/D15, A16/D0 to A23/D7 ALE Data 1-bus cycle Note: When the external data bus is 8 bits wide (BYTE = “H” ), operating waveform of A8/D8 to A15/D15 is the same as that of A0 to A7. E A 0 to A7 E Data Address Address AddressAddress <<No wait>> Address AddressAddress Data 1-bus cycle Clock 1 (Note) Address Address Address Address Data Data (Note) Fig. 12.2.2 Bus timing examples when software wait is used (BYTE = “L” ).

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P4 2/φ1 Timers A and B, Serial I/O, A-D converter, Watchdog timer Item State The ready function facilitates access to external devices which require a long access time. ____ By applying “L” level to pin RDY in the memory expansion or microprocessor mode, the microcomputer ____ enters the ready state. While pin RDY ’s level is “L,” this state is retained. Table 12.3.1 lists the microcomputer’s state in the ready state. In the ready state, oscillation of the oscillator does not stop. Therefore, the internal peripheral devices can operate even in the ready state. The ready function is valid for the internal and external areas. Table 12.3.1 Microcomputer’s state in ready state Clock φ1 output selection bit*1: Bit 7 at address 5E16 Signal output disable selection bit*2: Bit 6 at address 6C16 ____ Note: When “L” level which was input to pin RDY is sampled at one of the following timings, this signal is not accepted. (Note that φ CPU is stopped at “L” level.) l When the level of signal E is “H” while the bus is in use (Refer to \` in Figure 12.3.1.) l Immediately before a wait generated by the software wait (Refer to ˜ in Figure 12.3.1.) Oscillation φCPU Operating Stopped at “L” level ____ Retains the same state in which RDY was accepted. HLDA , E, R/W , BHE , ALE, A0 to A7, A8/D8 to A15/D15, A16/ D 0 to A23/D7, P4 3 to P47, P5 to P8 In the memory expansion mode n When the clock φ1 output selection bit*1 = “1” Outputs clock φ1. n When the clock φ1 output selection bit = “0” ____ Retains the same state in which RDY was accepted. In the microprocessor mode n When the signal output disable selection bit*2 = “1” ____ Retains the same state in which RDY was accepted. n When the signal output disable selection bit = “0” Outputs clock φ1. Operating

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12.3.1 Operation in ready state

____ When “L” level is input to pin RDY , this signal is accepted at the falling edge of clock φ1 and the microcomputer ____ enters the ready state. The ready state can be terminated by setting pin RDY ’s level to “H” again. When ____ “H” level is input to pin RDY , this signal is also accepted at the falling edge of clock φ1 and the ready state is terminated. Figure 12.3.1 shows timings when the ready state is accepted and terminated. Refer to section “17.1 Memory expansion” for the way to use the ready function.

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<<No wait>> Sampling timing Clock 1 CPU E RDY ALE ˆÀ\ ´ Bus is not in use. Bus is in use. ˆ Ready state is terminated. À “L” level which is input to pin RDY is accepted, so that signal E is stopped at “H” level for 1 cycle of clock1 (area ), andCPU is stopped at “L” level. \ “L” level which is input to pin RDY is not accepted, butCPU is stopped at “L” level. ´ “L” level which is input to pin RDY is accepted, so that signal E is stopped at “L” level for 1 cycle of clock1 (area ), andCPU is stopped at “L” level. ˜ “L” level which is input to pin RDY is not accepted because it is sampled immediately before a wait generated by software (area ), butCPU is stopped at “L” level. Sampling timing Clock 1 CPU RDY ALE <<Wait 0>> Bus is in use. Sampling timing Clock 1 CPU RDY ALE <<Wait 1>> Bus is in use. ˜ˆ ´ ˜ˆ ´ E E Fig. 12.3.1 Timings when ready state is accepted and terminated

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When an external circuit which accesses the bus without using the central processing unit (CPU), for example DMA, is used, it is necessary to generate a timing for transferring the right to use of the bus from the CPU to the external circuit. The hold function is used to generate this timing. By applying “L” level to pin HOLD in the memory expansion or microprocessor mode, the microcomputer enters the hold state. While pin HOLD ’s level is “L,” this state is retained. Table 12.4.1 lists the microcomputer’s state in the hold state. In the hold state, oscillation of the oscillator does not stop. Therefore, the internal peripheral devices can operate even in the hold state. (Note that the watchdog timer stops.) Table 12.4.1 Microcomputer’s state in hold state Item State Operating Stopped at “L” Floating Oscillation φCPU A 0 to A7, A8/D8 to A15/D15, A 16/D0 to A23/D7, R/W , BHE Outputs “L” level. In the memory expansion mode n When the clock φ1 output selection bit*1 = “1” Outputs clock φ1. n When the clock φ1 output selection bit = “0” Retains the same state in which HOLD was accepted. In the microprocessor mode n When the signal output disable selection bit*2= “1” Retains the same state in which HOLD was accepted. n When the signal output disable selection bit = “0” Outputs clock φ1. Retains the same state in which HOLD was accepted. Operating Stopped Clock φ1 output selection bit*1: Bit 7 at address 5E16 Signal output disable selection bit*2: Bit 6 at address 6C16 HLDA , ALE P4 2/φ1 P4 3 to P47, P5 to P8 Timers A and B, Serial I/O, A-D converter Watchdog timer

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12.4.1 Operation in Hold state

When “L” level is input to pin HOLD while the bus is not in use, this signal is accepted at the falling edge of clock φ1 in each bus cycle. When “L” level is input to pin HOLD while the bus is in use, this signal is starts from an odd address is accessed by the two bus cycles, determination is performed only in the second bus cycle. (Refer to Figure 12.4.1.) When “L” level which was input to pin HOLD is accepted, φCPU is stopped at the next rising edge of clock φ1. At this time, pin HLDA outputs “L” level, and so the external is informed that the microcomputer is in the hold state. After one cycle of clock φ1 has passed since pin HLDA ’s level becomes “L,” pins R/W , BHE and the external bus enter the floating state. The hold state can be terminated by setting pin HOLD ’s level to “H” again. When “H” level is input to pin HOLD , the signal is accepted at the falling edge of clock φ1. When “H” level which was input to pin HOLD is accepted, pin HLDA ’s level goes from “L” to “H.” And then, the hold state is terminated after one cycle of clock φ1 has passed. h In the ready state, determination of pin HOLD ’s input level is not performed. A Clock 1 ALE At reading At writing E l Determination timing of pin HOLD ’s input level A Not determined Determined Word data is accessed by the two bus cycles. (in this case, no wait) A AWW Fig.12.4.1 Determination when word data which starts from odd address is accessed by the two bus cycles

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Fig. 12.4.2 Timing when hold state is accepted and terminated (1) External data bus Data length External data bus width Software wait 8, 16 No wait, Not in use l State when “L” level is input to pin HOLD Wait 1, Wait 08, 16 ALE E External address bus/ External data bus HLDA HOLD External address bus Address B ƒÓ1 5 1 ƒÓ1 5 1 À Sampling timing Bus is in use.Bus is not in use. Note: The same operation is performed independent of the software wait (no wait, wait 0, or wait 1). This diagram shows the operation when no wait is selected. À Because the bus is not in use, the address which was output immediately before is output again, instead of a new address. R/W Clock 1 Address A Data <<When “L” level is input to pin HOLD while bus is not in use>> BHE Floating Address A Floating Floating Bus is in use. Hold state

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External data bus Data length 8,16 (When accessed starting from even address) No waitIn use œ State when “L” level is input to pin HOLD External data bus width Software wait ALE E HLDA HOLD R/W Address A 1 5 1 1 5 1 Hold state Sampling timing Bus is in use. <<When “L” level is input to pin HOLD while bus is in use (1)>> À When “L” level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. External address bus/ External data bus External address bus Clock 1 Data Floating BHE Address A Floating Address B Bus is in use. Floating À Fig. 12.4.3 Timing when hold state is accepted and terminated (2)

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À When “L” level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. Address A External address bus/ External data bus External data bus Data length External data bus width Software wait 8,16 (When accessed starting from even address) Wait 1In use l State when “L” level is input to pin HOLD ALE E HLDA HOLD R/W Address A Address B 1 5 1 1 5 1 Hold state À Sampling timing Bus is in use. <<When “L” level is input to pin HOLD while bus is in use (2)>> External address bus Clock 1 Data Floating Floating Floating Bus is in use. BHE Fig. 12.4.4 Timing when hold state is accepted and terminated (3)

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À When “L” level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. External data bus Data length External data bus width Software wait 8,16 (When accessed starting from even address) Wait 0In use l State when “L” level is input to pin HOLD ALE E HLDA HOLD R/W Address A Address B 1 5 1 1 5 1 Hold state Data Sampling timing Bus is in use. <<When “L” level is input to pin HOLD while bus is in use (3)>> External address bus/ External data bus External address bus Clock 1 Address A Floating Floating Bus is in use. Floating BHE À Fig. 12.4.5 Timing when hold state is accepted and terminated (4)

CONNECTING EXTERNAL DEVICES

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À When “L” level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. \ Sampling is not performed until 16-bit data input/output is finished. ( “L” level input to pin HOLD is not accepted.) External address bus/ External data bus ALE E HLDA HOLD R/W Address 1 5 1 1 5 1 Hold state Not sampled\ External data bus Data length External data bus width Software wait (When accessed starting from odd address) No wait In use l State when “L” level is input to pin HOLD Sampling timing Bus is in use. <<When “L” level is input to pin HOLD while bus is in use (4)>> External address bus Clock 1 Data High-order address Floating Floating Floating À Bus is in use. BHE Data Low-order address Fig. 12.4.6 Timing when hold state is accepted and terminated (5)

CONNECTING EXTERNAL DEVICES

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13.1 Hardware reset

13.2 Software reset

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“H” “L” À 4 to 5 cycles of internal clock 2 s or more Internal processing sequence after reset Program executed How to reset the microcomputer is described below. There are two methods to reset the microcomputer: hardware reset and software reset. When the power source voltage satisfies the recommended operating conditions, the microcomputer is reset by applying “L” level to pin RESET . (This is called “Hardware reset.”) Figure 13.1.1 shows an example of hardware reset timing. The microcomputer’s operation during periods À to ˆ is described below. À After “L” level is applied to pin RESET , pins are initialized within a period of several ten ns. (Refer to Table 13.1.1.) While pin RESET is at “L” level or within a period of 4 to 5 cycles of internal clock φ after pin RESET ’s level changes from “L” to “H,” the central processing unit (CPU) and SFR area are initialized. At this time, the contents of the internal RAM area is undefined (except the cases where the stop or wait mode is ´ After \` , “Internal processing sequence after reset” is performed. Refer to Figure 13.1.7. ˆ A program is executed beginning with the address set in the reset vector addresses (addresses FFFE16 and FFFF 16). Fig. 13.1.1 Example of hardware reset timing (when main clock is stably supplied.)

7733 Group User’s Manual 13–3

Pin CNV SS ’s level V SS or VCC V SS V CC V CC Pin (Port) name P0 to P8 E P0 to P8 E P0, P1, P3 to P8 E A 0 to A7, ____ A 8/D8 to A23/D7, BHE R/W , HLDA , E , ALE P4 to P8 Pin state Floating “H” level is output. Floating “H” level is output. Floating

• Floating when “H” level is applied to both or one of pins P5 1 and P52
• “H” or “L” level is output when “L” level is applied to both of pins 1 and P52. “H” level is output. Undefined value is output. “H” level is output. “L” level is output. Floating Table 13.1.1 lists the pin state while pin RESET is at “L” level. Table 13.1.1 Pin state while pin RESET is at “L” level

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13.1.2 State of CPU, SFR area, and internal RAM area

the state of the SFR area and internal RAM area immediately after reset. Fig. 13.1.2 State of CPU registers immediately after reset Processor status register (PS)0 00 0 00 0 0 00 0 1 b7 b0b15 b8 NV mx D IZ CIPL ??? ? : “0” immediately after reset. : “1” immediately after reset. : Undefined immediately after reset. : Nothing is allocated. Always “0” at reading Contents of address FFFE16Contents of address FFFF16 00160016Direct page register (DPR) b7 b0b15 b8 Program counter (PC) b7 b0b15 b8 Program bank register (PG) b7 b0 Data bank register (DT) b7 b0 Register name State immediately after reset 0016 0016

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Fig. 13.1.3 State of SFR area and internal RAM area immediately after reset (1) : “0” immediately after reset. : “1” immediately after reset. : Undefined immediately after reset. : Always “0” at reading 0 : Always undefined at reading : “0” immediately after reset. Must be fixed to “0.” 1016 1116 1216 1316 Port P8 direction register1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 016 116 216 316 416 516 616 716 816 916 B16 C 16 D 16 E16 F16 A16 Address Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register 0 A-D control register 1 Port P0 register Port P1 register Port P2 register Port P3 register Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Register name Access characteristics State immediately after reset RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0016 0016 0016 0016 0016 0000 00000000 0016 0 0 000 ? 00 11 b7 b0 b7 b0 : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Not implemented. It is impossible to read the bit state. The written value becomes invalid. RW RO WO n SFR area (addresses 016 to 7F16) RW 0016 ] Do not write data to addresses 1C16 and 1D16. Abbreviations and symbols which represent access characteristics RW RW ?? 0 ? ??? 0016 (Reserved area)] (Reserved area)]

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Fig. 13.1.4 State of SFR area and internal RAM area immediately after reset (2) UART0 transmit/receive control register 0 UART0 transmit/receive mode register UART0 baud rate register UART0 transmission buffer register UART1 receive buffer register Register name UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register UART1 transmission buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 2816 2916 2B16 2C 16 2D 16 2E16 2F16 2A16 2016 2116 2216 2316 2416 2516 2616 2716 3F16 Address Access characteristics RW WO WO RO RO b7 b0 WO RWRO RO RORW RW RO RO RW WO WO WO RWRO RO RO RW RW State immediately after reset 0 01000 0016 0 000 00 0 ? b7 b0 0016 0000 0 0 1 0 0000000 0 01000 00000010 A-D register 5 A-D register 1 A-D register 3 A-D register 2 A-D register 4 A-D register 0 A-D register 6 A-D register 7 RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW ? ?

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State immediately after reset 0016 0016 0016 0016 0016 b7 b0 0016 00 0 000 00 0 0 0 0 WO RW RW RW Timer A0 mode register Timer A4 mode register RW RW RW 0000 0 0 0 0 0000 0 0 00 0 0 0 00 0 0 0 0 0RWRW Processor mode register 10 ]3 ]3 ]1 Access characteristics at addresses 4616 to 5516 vary according to the timer’s operating mode. (Refer to chapters “6. TIMER A” and “7. TIMER B.”) ]2 Access characteristics for bit 5 at addresses 5B16 to 5D16 vary according to the timer B’s operating mode. (Refer to chapter “7. TIMER B.”) ]3 Access characteristics for bit 1 at address 5E16 and its state immediately after reset vary according to the voltage level applied to pin CNVSS . (Refer to section “2.5 Processor modes.”) Fig. 13.1.5 State of SFR area and internal RAM area immediately after reset (3)

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UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address Oscillation circuit control register 0 Serial transmit control register A-D / UART2 trans./rece. interrupt control register UART0 transmission interrupt control register UART1 transmission interrupt control register INT2/Key input interrupt control register Watchdog timer frequency selection flag Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW( ]2) RW RW RW RW b7 b0 WO RW RW RW RW RW RW RW RW RW RW State immediately after reset 0 00 0 ? 0 ? (]1) b7 b0 0 0 0 0 0 00 0 0 0 0 0 00 0 00 0 Port function control register UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register RW RW WO RW RW RW 00 0 0 0 1 00 00 0 00 0 0 00 0 0 00 0 0 00 0 0 0 0 0 0 00 0 0 00 0 0 00 0 0 0 0 00 0 00 0 00 0 Value “FFF16” is set to the watchdog timer. (Refer to chapter “10. WATCHDOG TIMER.” ) For access characteristics at address 6C16, also refer to Figure 14.3.2. State immediately after reset for bit 3 at address 6F16 vary according to the microcomputer. (Refer to Figure 14.3.3.) Do not write data to address 6216. n Internal RAM area (M37733MHBXXXFP: addresses 8016 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset. When the stop or wait mode is terminated (when hardware reset is applied)...Retains the state immediately before the STP or WIT instruction was executed. RW ]3 00 0 (Reserved area) ]4 Memory allocation control register UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Oscillation circuit control register 1 RW ? 0 00 0 RW ? 00 0 0000 WO WO WO RWRO 1 00 0 RW RO RWRO 00 0 0 0 1 00 RO 0 0 0 000 ? RW ?? 0 00 0 0 00 0 Fig. 13.1.6 State of SFR area and internal RAM area immediately after reset (4)

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(1) Single-chip and Memory expansion modes (2) Microprocessor mode CPU Ap AH AL DATA E 0016 FFFE 16 AD H , ADL 0016 Next op-code IPL, vector address Internal clock CPU Ap AH AL DATA E Internal clock 000016 AD H , ADLUnused

000016 FFFE 16 AD H , ADL

AD H , ADLUnused Next op-code IPL, vector address CPU : CPU’s standard clock Ap: High-order 8 bits of CPU address bus AH AL: Low-order 16 bits of CPU address bus DATA: CPU data bus AD H , ADL: Contents of reset vector addresses (addresses FFFE16 and FFFF16) Unused Unused

13.1.3 Internal processing sequence after a reset

Figure 13.1.7 shows the internal processing sequence after reset. Fig. 13.1.7 Internal processing sequence after reset

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4.5V 0.9V Note: For the low voltage version, refer to Figure 18.3.1.

13.1.4 Time required for applying “L” level to pin RESET

Time required for applying “L” level to pin RESET varies according to the main clock oscillation circuit’s state. n The case where an oscillator is stably oscillating or an external clock is stably input from pin XIN Apply “L” level for 2 µs or more. n The case where an oscillator is not stably oscillating (including the cases where power-on reset is applied and where the microcomputer operates in the stop mode) Apply “L” level until oscillation is stabilized. The time required for stabilizing oscillation varies according to the oscillator. For details, contact with the oscillator manufacturer. circuit. h For the stop mode, refer to chapter “11. STOP MODE AND WAIT MODES.” For clocks, refer to chapter “14. CLOCK GENERATING CIRCUIT.” Fig. 13.1.8 Power-on reset conditions

7733 Group User’s Manual 13–11

h Delay time td is about 11 ms when Cd = 0.033 mF. td » 0.345 C d [ ms], Cd: [ pF ] Note: For the low voltage version, refer to Figure 18.3.2. Fig. 13.1.9 Example of power-on reset circuit

represents that bits 0 to 2 and bits 4 to 7 are not used for software reset. functions as a output pin.) RESET

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Bit Bit name Functions At reset RW Processor mode bits Wait bit Software reset bit Must be fixed to “0.” Clock 1 output selection bit (Note 2) 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Microprocessor mode 1 1: Do not select. 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. Microcomputer is reset by setting this bit to “1.” This bit is “0” at reading. 0 0: 7 cycles of 0 1: 4 cycles of 1 0: 2 cycles of 1 1: Do not select. 0: Clock 1 output is disabled. (P4 programmable I/O port.) 1: Clock 1 output is enabled. (Port P42 functions as a clock b1 b0 b5 b4 Processor mode register 0 (address 5E16) (Note 1) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to “1” after reset. (At reading, this bit is always “1.”) This bit is ignored in the microprocessor mode. (It may be “0” or “1.”) b1 b0b2b3b4b5b6b7 RW RW RW WO RW RW RW RW Interrupt priority detection time selection bits When the power source voltage satisfies the recommended operating conditions and the main clock is stably supplied (Note), the microcomputer is reset by writing “1” to the software reset bit (bit 3 at address 5E16). (This is called “Software reset.”) In this case, the microcomputer initializes pins, CPU, and SFR area as in the case of a hardware reset. However, the microcomputer retains the contents of the internal RAM area. After completing initialization, the microcomputer performs “internal processing sequence after reset.” (Refer to Figure 13.1.7.) Then, a program is executed beginning with the address set in the reset vector addresses (addresses FFFE16 and FFFF 16). Note: This means “when a oscillator is stably oscillating or when an external clock is stably input from pin X IN.” For clocks, refer to chapter “14. CLOCK GENERATING CIRCUIT.” Fig. 13.2.1 Structure of processor mode register 0

14.1 Overview

14.2 Oscillation circuit example

14.3 Clock control

7733 Group User’s Manual14–2

Stopped (Note 1)

• A clock which is externally generated can be input.
• Sub clock can be input to external devices. (Refer to 14.3.1.) Usage of clock Resonator/Oscillator which can be connected Pins which are connected to resonator/oscillator Oscillation stop/restart (Note 2) Oscillator’s state just after reset Remarks
• Operating clock source of CPU
• Operating clock source of internal peripheral devices
• Operating clock source of clock timer
• Ceramic resonator
• Quartz-crystal oscillator Pins X IN and XOUT Available Operating A clock which is externally generated can be input. Main-clock oscillation circuit Sub-clock oscillation circuit Notes 1: Immediately after reset, pins X CIN and XCOUT function as ports P77 and P76, respectively. The oscillator starts operating when pins’ function is switched by the port-XC selection bit (bit 4 at address 6C16). 2: Whether oscillation is stopped or restarted is set by the main clock stop bit (bit 2 at address 6C16). In the main-clock/sub-clock oscillation circuit, oscillation can be stopped by the STP instruction; oscillation can be restarted by an interrupt request generated. (Refer to Figure 14.3.9.) The clock generating circuit is described below.

This clock generating circuit includes two oscillation circuits, which are main-clock and sub-clock oscillation circuits. Each of the main and sub clocks can be used as an operating clock for the CPU, internal peripheral devices, and clock timer. Table 14.1.1 Main-clock and sub-clock oscillation circuits

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Externally generated clock Open XIN XOUT VCC VSS M37733MHBXXXFP XIN XOUT R f C IN C OUT R d Main-clock and sub-clock oscillation circuits’ examples are described below. Fig. 14.2.1 Connection example of resonator/oscillator Fig. 14.2.2 Externally generated clock input example

14.2.1 Main-clock oscillation circuit example

To the main-clock oscillation circuit, a resonator/ oscillator can be connected, or a clock which is externally generated can be input. (1) Connection example of resonator/oscillator Figure 14.2.1 shows an example where pins X IN and X OUT connect across a ceramic resonator/quartz-crystal oscillator. Circuit constants such as Rf, Rd, CIN, and COUT (shown in Figure 14.2.1) depend on the resonator/oscillator. These values shall be set to the resonator/oscillator manufacturer’s recommended values. (2) Input example of clock which is externally generated Figure 14.2.2 shows an input example of a clock which is externally generated. When inputting a main clock from an external circuit, set “1” to bit 1 of the main-clock oscillation circuit control register 1. (Refer to Figure 14.3.3.) By this setting, the main-clock oscillation circuit stops operating and power consumption can be held down. Note that this bit has a function to select return conditions from the stop mode. (Refer to chapter “11. STOP AND WAIT MODES.” ) Furthermore, when writing to the oscillation circuit control register 1, follow the procedure shown in Figure 14.3.4. When inputting a main clock from an external circuit, that the external clock must be input from pin X IN, and pin XOUT must be left open.

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Externally generated clock XCIN P76/AN6 VCC VSS External circuit M37733MHBXXXFP XCIN XCOUT R Cf C CIN C COUT R Cd Fig. 14.2.3 Connection example of quartz-crystal oscillator Fig. 14.2.4 Externally generated clock input example

14.2.2 Sub-clock oscillation circuit example

To the Sub-clock oscillation circuit, an oscillator can be connected, or a clock which is externally generated can be input. (1) Connection example of oscillator When using an oscillator, connect a quartz- crystal oscillator between pins X CIN and XCOUT . (A ceramic resonator cannot be connected.) Figure 14.2.3 shows a quartz-crystal oscillator connection example. Circuit constants such as Rcf, Rcd, C CIN , and C COUT (shown in Figure 14.2.3) depend on the oscillator. These values shall be set to the oscillator manufacturer’s recommended values. When connecting an oscillator to the sub-clock oscillation circuit, set the port-Xc selection bit (bit 4 at address 6C 16) to “1” and the sub clock external input selection bit (bit 2 at address 6F16) to “0.” Note that the sub clock external input selection bit has a function to select return conditions from the stop mode. (Refer to chapter “11. STOP AND WAIT MODES.” ) (2) Input example of clock which is externally generated Figure 14.2.4 shows an input example of a clock which is generated in an external circuit. When inputting a sub clock from an external circuit, be sure to set the sub clock external input selection bit to “1,” and then, select pins X CIN and XCOUT by the port-Xc selection bit. In this case, an externally generated clock is input to pin XIN, and pin XOUT functions as pin P7 6/AN6. Note that the sub clock external input selection bit has a function to select return conditions from the stop mode. (Refer to chapter “11. STOP AND WAIT MODES.” ) If the sub-clock output selection bit (bit 1 at address 6D 16) is set to “1” when the port-Xc selection bit = “1” (Note), sub clock φSUB is output from port P67. Accordingly, a 32-kHz sub clock can be supplied to external gates. Note: At this time, a sub clock is used.

7733 Group User’s Manual 14–5

Figure 14.3.1 shows the clock generating circuit block diagram. Fig. 14.3.1 Clock generating circuit block diagram CM 3 CM 4 CMi: Bit i at address 6C16 (Refer to Figure 11.2.2.) CCi: Bit i at address 6F16 (Refer to Figure 11.2.3.) System clock S R Q STP instruction 1/4 1/2 1/2 1/81/2 f64 f512 f2 f8 f16 f32 Internal clock Q R S WIT instruction S R Q Reset Watchdog timer frequency selection flag WDC 12-bit watchdog timer XINXOUT P77/AN7/XCINP76/AN6/XCOUT CC 1 CM 3 CM 5 CM 2 CM 3 CC 1 0CM 4 CC 2 P67/TB2IN/ SUB (Port latch) Timer B2 (Event counter mode) (Clock timer) (Clock prescaler) fC32 CM 4 PC 1 Main clock Sub clock (Oscillation circuit control register 0: address 6C16) CM 2: Main clock stop bit CM 3: System clock selection bit CM 4: Port-Xc selection bit CM 5: System clock stop bit at wait state (Oscillation circuit control register 1: address 6F16) CC0: Main clock division selection bit CC1: Main clock external input selection bit CC2: Sub clock external input selection bit (Port function control register: address 6D16) PC1: Sub-clock output selection bit/Timer B2 clock source selection bit CM 4 PC 1 Switch represented by is controlled by a signal represented by “ ”. CM 4 CC 2 CM 4 STP instruction

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14.3.1 Clock generated in clock generating circuit

(1) System clock It is the clock source of the system clock divided by 2, internal clock φ, clock φ 1, and clocks f2 to f512. (Refer to Figure 14.3.1.) Each of the main clock, main clock divided by 8, and the sub clock can be selected as the system clock by the system clock selection bit (bit 3 at address 6C16). Table 14.3.1 lists clock combinations of the system clock, internal clock φ, φ 1, and f2. Port-Xc selection bit (bit 4 at 6C16) System clock selection bit (bit 3 at 6C 16) Main clock division selection bit (bit 0 at 6C16) System clock Table 14.3.1 Clock combinations of system clock, internal clock φ, φ1, and f2 Internal clock φ, φ1, f2 (Sub clock is not used.) Main clock Main clock Main clock divided by 8 Main clock divided by 8 Main clock Main clock Sub clock Main clock divided by 2 Main clock Main clock divided by 16 Main clock divided by 8 Main clock divided by 2 Main clock Sub clock divided by 2(Sub clock is used.) (2) Main clock It is the clock supplied by the main-clock oscillation circuit. This clock is selected as the system clock immediately after reset. After the sub clock is selected as the system clock, the main-clock supply is stopped/restarted by the main clock stop bit (bits 2 at address 6C By stopping the main-clock supply, power consumption can be held down. Figure 14.3.5 shows the clock f 2 state transition when a sub clock is not used because the port-Xc selection bit (bit 4 at address 6C16) = “0.” During reset and till after reset state is terminated, the main clock divided by 2 is selected as clock f2. If the system clock selection bit (bit 3 at address 6C16) is set to “1,” at this time, the main clock divided by 16 is selected as clock f2, and the clock frequency which is supplied to the CPU and peripheral devices becomes 1/8. Though this slow down the processing speed, current consumption is held down. Furthermore, by setting “1” to both of the main clock division selection bit (bit 0 at address 6F 16) and system clock selection bit, the main clock divided by 8 is selected as clock f2. When the port-Xc selection bit = “0,” clock fC32 , which is the main clock divided by 32, is connected as the timer B2’s count source if the timer B2 clock source selection bit (bit 1 at address 6D16) = “1” and timer B2 is used as a clock timer. By this, even when the main clock’s ratio is changed, the clock timer can use the same clock source. (Refer to Figure 14.3.1.)

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(3) Sub clock It is the clock supplied by the sub-clock oscillation circuit. The sub-clock supply is stopped immediately after reset (Note). When the port-Xc selection bit (bit 4 at address 6C16) is set to “1,” the sub-clock oscillation circuit starts operating, in other words, oscillation starts or an external clock is input. Furthermore, in this case, fC32 (sub clock divided by 32) is connected. (Refer to section “7.6 Clock timer.”) Furthermore, a sub clock can be the system clock by specifying the system clock selection bit after the oscillation is stabilized. (Refer to Figure 14.3.6.) The X COUT pin’s drivability can be lowered by the XCOUT drivability selection bit (bit 0 at address 6C16) after oscillation of the sub-clock oscillation circuit is stabilized. By lowering the X COUT pin’s drivability, power consumption is held down. When a sub clock is used, in other words, bit 4 at address 6C16 = “1,” sub clock φSUB is output from pin P67/TB2IN/φSUB if the sub-clock output selection bit (bit 1 at address 6D16) is set to “1.” Note: At this time, the oscillator which is connected to the sub-clock oscillation circuit stops operating, and pins XCIN and XCOUT function as ports P76 and P77. (4) Internal clock φ It is the CPU’s operating clock source, and its clock source is the system clock. (5) Clocks f2 to f512 Each of them is the internal peripheral devices’ operating clock, and its clock source is the system clock. (6) Clock φ 1 It is output to external circuits and has the same period as internal clock φ, and its clock source is the system clock. (7) fC32 It is the main clock/sub clock divided by 32 (Refer to Figure 14.3.1.) and the count source of the clock timer. (Refer to “7.6 Clock timer.”) (8) Sub clock φSUB Sub clock φSUB is output from port P67 if the sub clock output selection bit (bit 1 at address 6D16) is set to “1” when the port Xc selection bit = “1,” in other words, when the sub clock is used. Therefore, the 32-kHz sub clock can be supplied to the external gate.

7733 Group User’s Manual14–8

Bit Bit name Functions At reset RW XCOUT drivability selection bit Main clock stop bit System clock selection bit Port-Xc selection bit Not implemented. Un- defined 0: Drivability “LOW” 1: Drivability “HIGH” When the port-Xc selection bit = “0,” 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = “1,” 0: Main clock 1: Sub clock Un- defined Oscillation circuit control register 0 (address 6C16) b1 b0b2b3b4b5b6b7 Notes 0: Main clock oscillation or external clock input is available. 1: Main clock oscillation or external clock input is stopped. RW RW Not implemented. – RW (Note 1) 0: Operate as I/O ports (P77, P76). 1: Operate as pins XCIN and XCOUT . RW (Notes 2 and 3) RW (Note 2) System clock stop bit at wait state (Note 4) 0: Output is enabled. 1: Output is disabled. (Refer to Tables 12.1.2 and 12.1.5) 0: Operates in the wait mode. 1: Stopped in the wait mode. Signal output disable selection bit RW (Note 1) 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = “1.” 2: When selecting the sub clock as the system clock, set bit 3 to “1” after setting bit 4 to “1.” If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to “1.” 3: Although this bit can be set to “1,” it cannot be cleared to “0” after this bit is once set to “1.” 4: When setting the system clock stop bit at wait state to “1,” perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to “0” immediately after the wait mode is terminated. Fig. 14.3.2 Structure of oscillation circuit control register 0

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Write data “010101012.” (LDM instruction)

• When writing to bits 0 to 3 Write data “00001XXX2.” (LDM instruction) Next instruction (b3 in Figure 14.3.3)(b2 to b0 in Figure 14.3.3) Bit Bit name Functions At reset RW Main clock division selection bit Sub clock external input selection bit Must be fixed to “1” in the one time PROM and EPROM versions (Notes 1 and 2). Must be fixed to “0” (Note 2). Clock prescaler reset bit Undefined Oscillation circuit control register 1 (address 6F16) 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT . Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. RW RW RW RW WO —Not implemented. Not implemented. b1 b0b2b3b4b5b6b7 Notes 1: When writing to this register, follow the procedure shown in Figure 14.3.4. By writing “1” to this bit, clock prescaler is initialized. RW (Note 3) Undefined Main clock external input selection bit 0: Main clock is divided by 2. 1: Main clock is not divided by 2. 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. Ignored in the mask ROM and external ROM versions. 2: The case where data “010101012” is written with the procedure shown in Figure 14.3.4 is not included. 3: In the 7735 Group, fix this bit to “0.” 4: represents that bits 3 to 7 are not used for the clock generating circuit (Note 1) (Note 1) (Note 1)

Fig. 14.3.3 Structure of oscillation circuit control register 1 Fig. 14.3.4 Procedure for writing data to oscillation circuit control register 1

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Fig. 14.3.5 Clock f2 state transition (when sub clock is not used) f2 = f(XIN)/2 f2 = f(XIN)/16f2 = f(XIN) f2 = f(XIN)/8 CC 0 = “1” CC 0 = “0” CC 0 = “1” CC 0 = “0” CM 3 = “0” CM 3 = “1” CM 3 = “1” CM 3 = “0” (Note 1) (Note 2) Notes 1: f2 = f(XIN)/2 represents that clock f2 is the main clock divided by 2. 2: f2 = f(XIN) represents that clock f2 is the main clock not divided. Reset CC 0: Main clock division selection bit CM 3: System clock selection bit CM 4: Port-Xc selection bit

• When the sub clock is not used (CM4 = “0”)

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14.3.2 System clock switching procedure

Fig. 14.3.6 System clock switching procedure (1) State of bits 4 to 1 of the oscillation circuit control register 0 when switching the system clock Stopped OperatingOperating Port-Xc selection bit (bit 4) System clock selection bit (bit 3) Main clock stop bit (bit 2) (Sub-clock oscillation circuit: Oscillating) (Main clock) (Sub clock) (Main clock) (Stopped) (Oscillating) ab “1” “0” “1” “0” “1” “0” System clock Main clock Sub clock Main clock (Main-clock oscillation circuit: Oscillating) Oscillation of the main-clock oscillation circuit Oscillation stabilizing time Stopped OperatingOscillation of the sub-clock oscillation circuit Oscillation stabilizing time Notes 1: Before selecting the sub clock, make sure that oscillation of the sub clock is fully stabilized after oscillation starts. 2: Before selecting the main clock, make sure that oscillation of the main clock is fully stabilized after oscillation restarts. (Note 1) (Note 2)

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Fig. 14.3.7 System clock switching procedure (2) System clock switching procedure in order to stop the main clock supply when oscillator connected to the sub-clock oscillation circuit stops operating. (Refer to “a” in Figure 14.3.6.) b7 b0 Operation start of the sub-clock oscillation circuit Port-XC selection bit 1: Function as pins XCIN and XCOUT : Oscillation circuit control register 0 (address 6C16) 1010 b7 b0 System clock switching : Oscillation circuit control register 0 (address 6C 16) System clock selection bit 1: Sub clock 011 b7 b0 Stop of the the main-clock supply : Oscillation circuit control register 0 (address 6C16) Main clock stop bit 1: Stopped 111 (Waiting for oscillation stabilized in the sub-clock oscillation circuit)

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Fig. 14.3.8 System clock switching procedure (3) (Waiting for oscillation stabilized in the main-clock oscillation circuit) System clock switching System clock selection bit 0: Main clock : Oscillation circuit control register 0 (address 6C16) b7 b0 010 Operation start of the main-clock oscillation circuit b7 b0 Main clock stop bit 0: Oscillator operates (or clock which is externally generated is input). : Oscillation circuit control register 0 (address 6C16) 011 System clock switching procedure in order to select the main clock as the system clock when the main clock supply stops. (Refer to “b” in Figure 14.3.6.)

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14.3.3 Clock transition

Figure 14.3.9 shows the clock transition. Fig. 14.3.9 Clock transition Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Oscillating System clock: Sub clock Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating System clock: Sub clock Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating System clock: Main clock Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Oscillating f2 – f512 (Note 2) Internal clock φ : Stopped Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating f2 – f512 (Note 2) Internal clock φ : Stopped Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating f2 – f512 (Note 2) Internal clock φ : Stopped Wait mode Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Stopped f2 – f512 (Note 2) Internal clock φ : Stopped Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Stopped System clock: Main clock WIT instruction Interrupt request generated Port-Xc selection bit: “1” STP instruction Reset System clock selection bit: “1” (Note 1)System clock selection bit: “0” (Note 1) Main clock stop bit: “1” Stop mode Main clock stop bit: “0” WIT instruction WIT instruction WIT instruction STP instruction STP instructionMain-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Interrupt request generated Interrupt request generated Interrupt request generated Interrupt request generated Interrupt request generated Interrupt request generated h For the stop and wait modes, refer to chapter “11. STOP AND WAIT MODES.” Notes 1: Before selecting the system clock, make sure that operation of the oscillator is fully stabilized. Additionally, generate oscillation stabilizing time by software. 2: In the wait mode, whether clocks f2 to f512 are supplied or stopped can be specified by the system clock stop bit at wait state. STP instruction Interrupt request generated Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped

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14.3.4 Clock prescaler reset

The clock prescaler, which divides a sub clock by 32, is reset by writing “1” to the clock prescaler reset bit (bit 7 at address 6F16). By this function, the count source (fC32 ) error immediately after the clock timer starts counting can be held down. Figure 14.3.10 shows the operation timing of the clock prescaler and timer B2. Figure 14.3.10 Operation timing of clock prescaler and timer B2 Clock prescaler reset bit write pulse XCIN Clock timer clock source fC32 Timer B2 count value Timer B2 count start flag XCIN divided by 31(Note) n (Set value) n—1 The above is applied when the main clock is selected as the system clock, in other words, when the system clock selection bit (CM 3) = “0.” Note: Only in this period, XCIN divided by 31 is selected. After this period, XCIN divided by 32 is selected. XCIN divided by 32

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15.1 Absolute maximum ratings

15.2 Recommended

15.3 Electrical characteristics

15.4 A-D converter characteristics

15.5 Internal peripheral devices

15.7 Single-chip mode

15.8 Memory expansion mode and Microprocessor mode : with no wait

15.9 Memory expansion mode and

Microprocessor mode : with wait 1

15.10 Memory expansion mode and

Microprocessor mode : with wait 0

15.11 Measuring circuit for ports

P0 to P8 and pins φ1 and E

ELECTRICAL CHARACTERISTICS

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M37733MHBXXXFP’s electrical characteristics are described below. For low voltage version, refer to section “18.4 Electrical characteristics.” For the latest data, inquire of addresses described last (+ “CONTACT ADDRESSES FOR FURTHER INFORMATION”) . Analog power source voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ta = 25 °C Unit V V V V V mW Symbol Vcc AVcc V I VI VO Pd Topr Tstg Ratings –0.3 to 7 –0.3 to 7 –0.3 to 12 –0.3 to Vcc+0.3 –0.3 to Vcc+0.3 300 –20 to 85 –40 to 150 RESET , CNVss, BYTE P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, VREF , XIN P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XOUT , E

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15.2 Recommended operating conditions

Recommended operating conditions (Vcc = 5 V ± 10 %, Ta = –20 to 85 °C, unless otherwise noted) f(XIN) :Operating f(XIN) :Stopped, f(XCIN) = 32.768 kHz P00–P07, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) P10–P17, P20–P27 (in single-chip mode) P10–P17, P20–P27 (in memory expansion mode and microprocessor mode) 0–P07, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) P10–P17, P20–P27 (in single-chip mode) 0–P17, P20–P27 (in memory expansion mode and microprocessor mode) 0–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P43, P54–P57, P60–P67, P70–P77, P80–P87 P44–P47, P50–P53 P00–P07, P10–P17, P20–P27, P30–P33, P40–P43, P54–P57, P60–P67, P70–P77, P80–P87 P44–P47, P50–P53 ParameterSymbol Limits Min. Max. 5.5 5.5 4.5 2.7 5.0 Vcc 32.768 Typ. Unit

0.8 Vcc

0.2 Vcc

0.16 Vcc

–10

0.5 Vcc

Analog power source voltage Power source voltage Analog power source voltage High-level input voltage High-level input voltage High-level input voltage Low-level input voltage Low-level input voltage Low-level input voltage High-level peak output current High-level average output current Low-level peak output current Low-level peak output current Low-level average output current Low-level average output current Main-clock oscillation frequency (Note 4) Sub-clock oscillation frequency Vcc AVcc Vss AVss V IH VIH VIH VIL VIL VIL IOH (peak) IOH (avg) IOL (peak) IOL (peak) IOL (avg) IOL (avg) f(XIN) f(XCIN) V V V V V V V V V V mA mA mA mA mA mA MHz kHz Notes 1: Average output current is the average value of a 100 ms interval. 2: The sum of I OL (peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH (peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL (peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH (peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3: Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1.” 4: The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = “1.”

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Hysteresis X CIN (When external clock is input) High-level input current Low-level input current Low-level input current RAM hold voltage P00–P07, P10–P17, P20–P27, P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P33 P30–P32 E P00–P07, P10–P17, P20–P27, P33, P40–P43, P54–P57, P60–P67, P70–P75, P80–P87 P44–P47, P50–P53 P00–P07, P10–P17, P20–P27, P33 P30–P32 E P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVss, BYTE P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P53, P6 0, P61, P65– P67, P70–P7 7, P80–P87, XIN, RESET , CNVss, BYTE P54–P57, P62–P64 Electrical characteristics (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) VT+–VT– VT+–VT– VT+–VT– VT+–VT– IIH IIL IIL VRAM Symbol Parameter Measuring conditions Min. Max. V V V V V V V V V V V V V µA µA µA mA V Limits Unit 0.45 1.9 0.43 1.6 0.4 0.5 0.4 0.4 –1.0 –0.25 Typ. –0.5 HOLD , RDY , TA0 IN–TA4 IN, TB0 IN–TB2 IN, INT0–INT2, ADTRG , CTS 0, CTS 1, CTS 2, CLK0, CLK 1, CLK2, KI0–KI3 IOH = –10 mA IOH = –400 µA IOH = –10 mA IOH = –400 µA IOH = –10 mA IOH = –400 µA IOL = 10 mA IOL = 20 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA VI = 5 V VI = 0 V VI = 0 V, without a pull-up transistor VI = 0 V, with a pull-up transistor When clock is stopped 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 0.1

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Max. 2.6 100 Limits Vcc = 5 V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 12.5 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 5V, f(XIN) = 25 MHz (Square waveform), f(XCIN) : Stopped, in operating (Note 1) Vcc = 5V, f(XIN) = 25 MHz (Square waveform), f(XCIN) = 32.768 kHz, when the WIT instruction is executed (Note 2) Vcc = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped 15.3 Electrical characteristics 15.4 A-D converter characteristics ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted) UnitMeasuring conditionsSymbol Parameter ICC Power source current Min. Typ. 9.5 1.3 mA mA µA µA µA µA µA In single-chip mode, output pins are open, and the other pins are con- nected to Vss. Notes 1: This is applied when the main clock external input selection bit = “1,” the main clock division selection bit = “0,” and the signal output disable selection bit = “1.” 2: This is applied when the main clock external input selection bit = “1” and the system clock stop selection bit at wait state = “1.” 3: This is applied when the CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1.” A-D CONVERTER CHARACTERISTICS (Vcc = AVcc = 5 V, Vss = AVss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted) Limits Min. Typ. Max. — Resolution VREF = Vcc 10 Bits — Absolute accuracy VREF = Vcc ± 3 LSB R LADDER Ladder resistance VREF = Vcc 10 25 k tCONV Conversion time 9.44 µs VREF Reference voltage 2 Vcc V VIA Analog input voltage 0 VREF V Symbol Parameter Measuring conditions Unit Note : This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.

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Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Min. Max. ns ns ns UnitSymbol Parameter tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note 3) TAiIN input high-level pulse width (Note 3) TAiIN input low-level pulse width (Note 3) Min. Max. UnitSymbol Parameter Timer A input (Gating input in timer mode) Parameter Limits Timer A input (External trigger input in one-shot pulse mode) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Max. UnitSymbol Min. 320 tc(TA) tw(TAH) tw(TAL) Limits TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns Min. Max. tw(TAH) tw(TAL) UnitParameterSymbol tc(UP) tw(UPH) tw(UPL) tsu(UP–TIN) th(TIN–UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time ns ns ns ns ns Min. Max. UnitSymbol Parameter Timer A input (Up-down input in event counter mode) Timer A input (External trigger input in pulse width modulation mode) 2000 1000 1000 400 400 Timer A input (Count input in event counter mode) Data formula (Min.) Data formula (Min.) 8 5 109 25 f(f2) 4 5 109 25 f(f2) 4 5 109 25 f(f2) (Note 2) (Note 2) (Note 2) 8 5 109 25 f(f2) (Note 2) Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 3: The TAiIN input cycle time must be 4 cycles of a count source or more. The TAiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively.

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Max. ns ns ns ns ns ns ns ns ns UnitSymbol Parameter Timer A input (Two-phase pulse input in event counter mode) Min. 800 800 800 500 250 200 500 250 200 Measuring conditions f(XIN) = 8 MHz f(XIN) = 16 MHz f(XIN) = 25 MHz f(XIN) = 8 MHz f(XIN) = 16 MHz f(XIN) = 25 MHz f(XIN) = 8 MHz f(XIN) = 16 MHz f(XIN) = 25 MHz TAjIN input cycle time TAjIN input setup time TAjOUT input setup time tc(TA) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) Note: This is applied when the main clock division selection bit = “0.”

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Internal peripheral devices TAiIN input tc(TA) tw(TAH) tw(TAL) TAiOUT input (Up-down input) tc(UP) tw(UPH) tw(UPL) TAiIN input (When fall count is selected) TAiIN input (When rise count is selected) TAiOUT input (Up-down input) th(TIN–UP) tsu(UP–TIN) l Count input in event counter mode l Gating input in timer mode l External trigger input in one-shot pulse mode l External trigger input in pulse width modulation mode l Up-down input and count input in event counter mode Measuring conditions

• VCC = 5 V ± 10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V tsu(TAjIN–TAjOUT ) TAjIN input TAjOUT input tsu(TAjOUT –TAjIN) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) l Two-phase pulse input in event counter mode tc(TA)

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Min. 320 160 160 Max.Min. 320 160 160 Timer B input (Count input in event counter mode) tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Min. Max. ns ns ns ns ns ns Limits UnitSymbol TBiIN input cycle time (Note 1) TBiIN input high-level pulse width (Note 1) TBiIN input low-level pulse width (Note 1) tc(TB) tw(TBH) tw(TBL) ns ns ns Limits UnitSymbol Parameter Timer B input (Pulse period measurement mode) Parameter TBiIN input cycle time (One edge count) TBiIN input high-level pulse width (One edge count) TBiIN input low-level pulse width (One edge count) TBiIN input cycle time (Both edges count) TBiIN input high-level pulse width (Both edges count) TBiIN input low-level pulse width (Both edges count) 160 Timer B input (Pulse width measurement mode) tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Limits UnitSymbol Parameter Max. AD TRG input cycle time (Minimum allowable trigger) AD TRG input low-level pulse width Min. Max. ns ns Limits UnitParameterSymbol tc(AD) tw(ADL) A-D trigger input 1000 125 Serial I/O CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TxD i output delay time TxD i hold time RxD i input setup time RxD i input hold time tc(CK) tw(CKH) tw(CKL) td(C–Q) th(C–Q) tsu(D–C) th(C–D) Min. Max. Limits UnitSymbol Parameter 200 100 100 Data formula (Min.) Data formula (Min.) 8 5 109 25 f(f2) 4 5 109 25 f(f2) 4 5 109 25 f(f2) (Note 2) (Note 2) (Note 2) 8 5 109 25 f(f2) 4 5 109 25 f(f2) 4 5 109 25 f(f2) (Note 2) (Note 2) (Note 2) Notes 1: The TBiIN input cycle time must be 4 cycles of a count source or more. The TBiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1.

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Min. 250 250 250 External interrupt INTi input, Key input interrupt KIi input INTi input high-level pulse width INTi input low-level pulse width KIi input low-level pulse width tw(INH) tw(INL) tw(KIL) Max. Limits UnitSymbol Parameter Measuring conditions

• VCC = 5 V ± 10 %
• Input timing voltage
• Output timing voltage : VIL = 1.0 V, VIH = 4.0 V : VOL = 0.8 V, VOH = 2.0 V TBiIN input tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) AD TRG input tw(INL) tw(INH) INTi input tc(CK) tw(CKH) tw(CKL) th(C–Q) tsu(D–C) CLK i input TxD i output RxD i input td(C–Q) th(C–D) tw(KIL) KIi input Internal peripheral devices

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Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. HOLD input setup time RDY input hold time HOLD input hold time Limits tsu(RDY– φ1) tsu(HOLD– φ1) th(φ1–RDY) th(φ1–HOLD) RDY input setup time Max. ns ns ns ns Min. ParameterSymbol Unit Note: This is applied when the main clock division selection bit = “0” and f(f 2) = 12.5 MHz. Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) HLDA output delay timetd(φ1–HLDA) ns Min. Max. Limits UnitConditionsParameter Fig. 15.11.1 Symbol

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tsu(RDY– 1) th( 1–RDY) tsu(RDY– 1) th( 1–RDY) Measuring conditions

• VCC = 5 V ± 10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage: VOL = 0.8 V, VOH = 2.0 V HOLD input HLDA output th( 1–HOLD) td( 1–HLDA) tsu(HOLD– 1) Hold td( 1–HLDA)

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Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. tc tw(H) tw(L) tr tf tsu(P0D–E) tsu(P1D–E) tsu(P2D–E) tsu(P3D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P0D) th(E–P1D) th(E–P2D) th(E–P3D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Limits UnitParameter External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Port P0 input setup time Port P1 input setup time Port P2 input setup time Port P3 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P0 input hold time Port P1 input hold time Port P2 input hold time Port P3 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Symbol Max. Notes 1: This is applied when the main clock division selection bit = “0” and f(f 2) = 12.5 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 80 ns. 3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. td(E–P0Q) td(E–P1Q) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) Port P0 data output delay time Port P1 data output delay time Port P2 data output delay time Port P3 data output delay time Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time ns ns ns ns ns ns ns ns ns UnitSymbol Max. Min. LimitsParameter Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Conditions Fig. 15.11.1 Note: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.

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td(E–P0Q) tsu(P0D–E) th(E–P0D) td(E–P1Q) tsu(P1D–E) th(E–P1D) td(E–P2Q) tsu(P2D–E) th(E–P2D) td(E–P3Q) tsu(P3D–E) th(E–P3D) tW(H)tctrtf E Port P0 output Port P0 input Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input XIN td(E–P4Q) tsu(P4D–E) th(E–P4D) td(E–P5Q) tsu(P5D–E) th(E–P5D) td(E–P6Q) tsu(P6D–E) th(E–P6D) td(E–P7Q) tsu(P7D–E) th(E–P7D) td(E–P8Q) tsu(P8D–E) th(E–P8D) Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input tW(L) Single-chip mode Measuring conditions

• VCC = 5 V ± 10 %
• Input timing voltage
• Output timing voltage : V IL = 1.0 V, VIH = 4.0 V : VOL = 0.8 V, VOH = 2.0 V

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Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. tc tw(H) tw(L) tr tf tsu(D–E) th(E–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 80 ns. 3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Limits Max.Data formula (Min.)Min. 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) – 28 – 28 – 22 – 18 – 35 Symbol td(An–E) td(A–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ 1) Parameter Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time E pulse width Floating start delay time Floating release delay time BHE output delay time R/W output delay time BHE hold time R/W hold time φ 1 output delay time Conditions Fig. 15.11.1 Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 2 5 109 25 f(f2) – 22 – 30 – 20 – 28 – 28 – 22 – 22

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th(ALE–A) th(E–DQ) td(E–DQ) Address/Data output A16/D0–A23/D7, A8/D8–A15/D15 (BYTE = “L”) DataAddress td(A–E) tpxz(E–DZ) tpzx(E–DZ) td(E–φ1) tw(EL) th(E–An) td(E–φ1) tw(ALE) td(BHE–E) th(E–BHE) td(R/W–E) th(E–R/W) XIN E Address output A0–A7 A8–A15 (BYTE = “H”) Data input D 8–D 15 (BYTE = “L”), D 0–D 7 (BYTE = “H”) ALE output BHE output R/W output Address Measuring conditions( 1, E, Ports P0–P3)

• VCC = 5 V ± 10 %
• Output timing voltage
• Port P1, P2 input : VOL = 0.8 V, VOH = 2.0 V : VIL = 0.8 V, VIH = 2.5 V With no wait (Wait bit = “1”) td(E–φ1) td(An–E) tsu(D–E) th(E–D) td(ALE–E) td(BHE–E) td(R/W–E) Address Memory expansion mode and Microprocessor mode : tw(H)tw(L) tc tftr Port Pi output (i = 4–8) Port Pi input (i = 4–8) td(E–PiQ) tsu(PiD–E) th(E–PiD) tw(ALE) tw(EL) td(An–E) td(ALE–E) th(E–An) th(E–BHE) th(E–R/W) tftr tc tw(H)tw(L) (Write) (Read) td(E–φ1) Measuring conditions (Ports P4–P8)
• VCC = 5 V ± 10 %
• Input timing voltage
• Output timing voltage : VIL = 1.0 V, VIH = 4.0 V : VOL = 0.8 V, VOH = 2.0 V tsu(A–ALE) Address

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Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. tc tw(H) tw(L) tr tf tsu(D–E) th(E–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 80 ns. 3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Limits Max.Data formula (Min.)Min. 130 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) – 28 – 28 – 22 – 18 – 35 Symbol td(An–E) td(A–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ 1) 1 5 109 25 f(f2) 4 5 109 25 f(f2) Parameter Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time E pulse width Floating start delay time Floating release delay time BHE output delay time R/W output delay time BHE hold time R/W hold time φ 1 output delay time Conditions Fig. 15.11.1 Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) – 22 – 30 – 20 – 28 – 28 – 22 – 22

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When external memory area is accessed with wait 1 (Wait bit = “0” and Wait selection bit = “1”) tc th(E– R/W) td(R/W–E) td(BHE–E) th(E– BHE) tw(ALE) th(E–An) tw(EL) td(E–φ1) td(E–φ1) Address XIN E Address output A0–A7, A8–A15 (BYTE = “H”) Data input D 8–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H”) ALE output BHE output R/W output th(E– BHE) td(ALE–E) tsu(D–E) th(E–D) td(An–E) td(E–φ1) Address Memory expansion mode and Microprocessor mode : Port Pi output (i = 4–8) Port Pi input (i = 4–8) td(E–PiQ) tsu(PiD–E) th(E–PiD) tw(H)tw(L) td(E–DQ) th(ALE–A) th(E–DQ)Address/Data output A16/D0–A23/D7, A8/D8–A15/D15 (BYTE = “L”) Data tpxz(E–DZ) tpzx(E–DZ) (Write) (Read) td(E–φ1) tw(EL) th(E–An) td(An–E) td(ALE–E) tw(ALE) trtf tw(L) tw(H) trtf tc td(R/W–E) td(BHE–E) th(E– R/W) Measuring conditions (Ports P4–P8)

• VCC = 5 V ± 10 %
• Input timing voltage
• Output timing voltage : VIL = 1.0 V, VIH = 4.0 V : VOL = 0.8 V, VOH = 2.0 V Measuring conditions (1, E, Ports P0–P3)
• VCC = 5 V ± 10 %
• Output timing voltage
• Ports P1, P2 input : VOL = 0.8 V, VOH = 2.0 V : VIL = 0.8 V, VIH = 2.5 V tsu(A–ALE) td(A–E) Address Address

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Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. tc tw(H) tw(L) tr tf tsu(D–E) th(E–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 80 ns. 3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Limits Max.Data formula (Min.)Min. 130 3 5 109 25 f(f2) 3 5 109 25 f(f2) 1 5 109 25 f(f2) 2 5 109 25 f(f2) 2 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) – 33 – 45 – 22 – 23 – 35 – 25 – 30 Symbol td(An–E) td(A–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ 1) Parameter Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time E pulse width Floating start delay time Floating release delay time BHE output delay time R/W output delay time BHE hold time R/W hold time φ 1 output delay time Conditions Fig. 15.11.1 Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 1 5 109 25 f(f2) 4 5 109 25 f(f2) 1 5 109 25 f(f2) 3 5 109 25 f(f2) 3 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) – 22 – 30 – 20 – 33 – 33 – 22 – 22

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A0–A7, A8–A15 (BYTE = “H”) ALE output E BHE output R/W output tc Data input D 8–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H”) td(E–φ1)td(E–φ1) tw(EL) th(E–An) tw(ALE) td(BHE–E) th(E–BHE) td(R/W–E) th(E–R/W) Address Measuring conditions (1, E, Ports P0–P3)

• VCC = 5 V ± 10 %
• Output timing voltage
• Ports P1, P2 input : VOL = 0.8 V, VOH = 2.0 V : VIL = 0.8 V, VIH = 2.5 V td(E– 1) td(An–E) tsu(D –E) th(E–D) td(ALE–E) th(E–BH E) th(E–R/W) Address/Data output A16/D0–A23/D7, A8/D8–A15/D15 (BYTE = “L”) th(E–DQ)th(ALE–A) td(E–DQ) tsu(A–ALE) Data tpxz(E–DZ ) tpzx(E–DZ ) A ddress A ddress Port Pi output (i = 4–8) Port Pi input (i = 4–8) td(E–PiQ) tsu(PiD–E) th(E–PiD) tw(L) tw(H) trtf <Write> <R ead> tw(EL) tf tr tw(L) tw(H) tc td(E– 1) td(An–E) td(ALE–E) th(E–An) tw(ALE) td(BH E–E) td(R/W –E) Measuring conditions (Ports P4–P8)
• VCC = 5 V ± 10 %
• Input timing voltage
• Output timing voltage : VIL = 1.0 V, VIH = 4.0 V : VOL = 0.8 V, VOH = 2.0 V td(A–E) When external memory area is accessed with wait 0 (Wait bit = “0” and Wait selection bit = “0”) Memory expansion mode and Microprocessor mode : Address

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15.11 Measuring circuit for ports P0 to P8 and pins φ1 and E

E Fig. 15.11.1 Measuring circuit for ports P0 to P8 and pins φ1 and E

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16.1 Standard characteristics

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Standard characteristics described below are characteristic examples of the M37733MHBXXXFP and are not guaranteed. For each parameter’s limits, refer to chapter “15. ELECTRICAL CHARACTERISTICS.”

16.1.1 Programmable I/O port (CMOS output) standard characteristics:

P0 to P3, P40 to P43, P54 to P57, P6, P7, and P8 (1) P-channel IOH –V OH characteristics (2) N-channel IOL –V OL characteristics 50.0 40.0 30.0 10.0 20.0 Ta = 25°C Ta = 85°C Power source voltage VCC = 5 V VOH [ V ] IOH [ mA ] P channel 50.0 40.0 30.0 20.0 10.0 Ta = 25°C Ta = 85°C Power source voltage VCC = 5 V VOL [ V ] IOL [ mA ] N channel

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16.1.2 Programmable I/O port (CMOS output) standard characteristics:

P4 4 to P47 and P50 to P53 (1) P-channel IOH –V OH characteristics (2) N-channel IOL –V OL characteristics Power source voltage VCC = 5 V VOH [ V ] IOH [ mA ] P channel Power source voltage VCC = 5 V VOL [ V ] IOL [ mA ] N channel 50.0 40.0 30.0 10.0 20.0 Ta = 25°C Ta = 85°C 50.0 40.0 30.0 20.0 10.0 Ta = 25°C Ta = 85°C

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16.1.3 Icc–f(XIN) standard characteristics

(1) Icc–f(XIN) characteristics on operating and at reset (2) Icc–f(XIN) characteristics in wait mode Measurement condition Vcc = 5V,Ta = 25°C, f(XIN): square waveform input, single-chip mode Register setting condition Oscillation circuit control register 0 = “2016” (In the wait mode, clocks f2 to f512 are stopped.) Oscillation circuit control register 1 = “0216” (Main clock is input from the external.) or “0016” (Main-clock oscillation circuit is operating by itself) Measurement condition Vcc = 5V,Ta = 25°C, f(X IN): square waveform input, single-chip mode Register setting condition Oscillation circuit control register 1 = “02 16” (Main clock is input from the external.) 0 4 8 1 21 62 02 42 8 f(XIN) [MHz] Icc [mA] On operating (CPU) CC1 = 0 0.5 1.5 2.5 0 4 8 1 21 62 02 42 8 f(XIN) [MHz] Icc [mA] CC1 = 1 CC1: Main clock external input selection bit (b1 of the oscillation circuit control register 1) On operating (CPU + peripheral devices)

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16.1.4 A-D converter standard characteristics

The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in output code from “0E16” to “0F16” should occur at 72.5 mV, but the measured value is 0.6 mV. Accordingly, the measured point of change is 72.5 + 0.6 = 73.1 mV. The upper lines of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is “0F16” is 4.7 mV. Accordingly, the [Measurement condition]

• V CC = AVCC = 5 V, • VREF = 5.12 V, • f(XIN) = 25 MHz, • Ta = 25 °C

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APPLICATIONS

17.2 Serial I/O

17.3 Watchdog timer

17.4 Power saving

17.5 Timer B

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Some application examples are described below. Applications shown here are just examples. Modify the desired application to suit the user’s need and make sufficient evaluation before actually using it. Memory • I/O expansion examples are described below.

• For functions and operations of pins used in memory • I/O expansion, refer to chapter “12. CONNECTING EXTERNAL DEVICES.”
• For timing characteristics, refer to chapter “15. ELECTRICAL CHARACTERISTICS.”
• For timing characteristics and applications of the low voltage version, refer to chapter “18. LOW VOLTAGE VERSION.”

17.1.1 Memory expansion model

Memory expansion to the external is enabled in the memory expansion or microprocessor mode. In the 7733 Group, the desired memory expansion model can be selected from four models listed in Table 17.1.1. This selection depends on the level of the external data bus width selection signal (BYTE). (1) Minimum model The external data bus is 8 bits wide and the accessible area can be expanded up to 64 Kbytes. No external address latch is necessary, so this model gives priority to cost and is most suitable when connecting a memory of which data bus is 8 bits wide. (2) Medium model A The external data bus is 8 bits wide and the accessible area can be expanded up to 16 Mbytes. The high-order 8 bits of the external address bus (A23 to A16) are multiplexed with the external data bus. Therefore, one n-bit (n ≤ 8) address latch is necessary in order to latch n bits of address in A23 to A16. (3) Medium model B The external data bus is 16 bits wide and the accessible area can be expanded up to 64 Kbytes. This model gives priority to speed. The middle-order 8 bits of the external address bus (A15 to A8) are multiplexed with the external data bus. Therefore, one 8-bit address latch is necessary in order to latch A 15 to A8. (4) Maximum model The external data bus is 16 bits wide and the accessible area can be expanded up to 16 Mbytes. The high- and middle- order 16 bits of the external address bus (A23 to A8) are multiplexed with the external data bus. Therefore, both of the following latches are necessary:

• One 8-bit address latch used for latching A15 to A8
• One n-bit (n ≤ 8) address latch used for latching n bits of address in A23 to A16

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Table 17.1.1 Memory expansion models h For functions and operations of pins used in memory expansion, refer to chapter “12. CONNECTING EXTERNAL DEVICES.” For timing characteristics, refer to chapter “15. ELECTRICAL CHARACTERISTICS.” h In memory expansion, the address bus can be expanded up to 24 bits wide. Accordingly, be sure to strengthen the 7733 Group’s Vss line on the system. (Refer to section “Appendix 8.Countermeasure examples against noise.”) Accessible area Memory expansion model 64 Kbytes (Max.) 16 Mbytes (Max.)External data bus BYTE BYTE BYTE = “H” 16 bits wide BYTE = “L” Minimum model Medium model A Maximum model Memory expansion model Medium model BMemory expansion model Memory expansion model A0 to A15 D 0 to D7 A0 to A15 Latch E D 0 to D15 DQ A0 to A15+n D 0 to D7 16+n E n DQ Latch Latch Latch E A0 to A15+n D 0 to D15 n 16+n DQ E DQ ALE BHE

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17.1.2 Calculation ways for timing

When expanding memory, use a memory of which specifications satisfy the following timing requirements: address access time (ta(AD)) and data setup time for writing data (tsu(D)). Calculation ways for ta(AD) and tsu(D) are described below. À Address access time of external memory [ta(AD)] ta(AD) = td(An/A-E) + tw(EL) – tsu(D-E) – (address decode time] 1 + address latch delay time] 2) td(An/A-E) : td(An-E) or td(A-E) address decode time] 1: time necessary for validating a chip select signal after an address is decoded address latch delay time] 2: delay time necesarry for latching an address (This is not necessary on the minimum model.) \` Data setup time of external memory for writing data [tsu(D)] tsu(D) = tw(EL) – td(E-D) Table 17.1.2 lists the calculation formulas and constants for each parameter in the above formulas. Figure 17.1.3 shows the relationship between tsu(D) and 2•f(f2). Table 17.1.2 Calculation formulas and constants for each parameter (Unit: ns) Software wait Wait bit Wait selection bit td(A-E) td(An-E) tw(EL) tsu(D-E) td(E-DQ) Wait 1 Wait 0 No wait 0 or 1 – 302 5 109 2•f(f2) 1 5 109 2•f(f2) – 28 3 5 109 2•f(f2) – 45 4 5 109 2•f(f2) – 30 Wait bit: Bit 2 at address 5E16 Wait selection bit: Bit 0 at address 5F16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = “0.”

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Fig. 17.1.1 Bus timing diagrams tsu(D-E) When BYTE = “L” (External data bus = 16 bits wide) E ALE High-order address Low-order address td(An-E) td(A-E) tsu(D-E) tw(EL) When data is written High-order address Low-order data td(E-DQ) Low-order address When data is read Middle-order address td(A-E) Middle-order address High-order data td(E-DQ) R/W When BYTE = “H” (External data bus = 8 bits wide) Middle-order address E ALE High-order address Low-order address td(An-E) td(An-E) td(A-E) tsu(D-E) tw(EL) A0 to A7 A8 to A15 A16/D0 to A23/D7 High-order address Data td(E-DQ) Middle-order address Low-order address When data is writtenWhen data is readR/W Data Data Data ta(AD) tsu(D) tw(EL) ta(AD) tsu(D) tw(EL) A0 to A7 A8/D8 to A15/D15 A16/D0 to A23/D7 : Specifications of the 7733 Group (The others are specifications of external memory.)

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Fig. 17.1.3 Relationship between tsu(D) and 2•f(f2) Fig. 17.1.2 Relationship between ta(AD) and 2•f(f2) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 200 300 400 500 600 700 800 900 893 768 670 593 529 476 431 393 359 330 304 281 261 243 226 211 197 184 173 624 535 465 410 364 326 294 267 243 222 204 187 173 160 148 137 127 118 110 338 285 243 210 182 160 140 124 110 97 86 76 67 60 52 46 40 35 30 No wait Wait 1 is valid. Wait 0 is valid. Address access time ta(AD) [ns] External clock input frequency 2•f(f2) [MHz] h Address decode time and address latch delay time are not considered. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 200 300 400 500 496 425 369 325 288 258 232 210 191 175 160 147 135 125 115 106 98 91 85 175 147 125 106 91 78 67 58 50 42 36 30 25 20 15 11 8 5 No wait Wait 1 or Wait 0 is valid. External clock input frequency 2•f(f2) [MHz] Data setup time tsu(D) [ns] 210

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17.1.3 Points in memory expansion

(1) Timing for reading data Figure 17.1.4 shows the timing at which data is read from an external memory. When data is read, the external data bus enters a floating state and reads data from the external memory. The floating state of the external data bus is retained from when an interval of tpxz(E-DZ) has _ _ passed after signal E’s falling edge until an interval of tpzx(E-DZ) has passed after signal E’s rising edge. Table 17.1.3 lists the value of tpxz(E-DZ) and the calculation formula for tpzx(E-DZ). Note that the external data bus is multiplexed with the external address bus. Therefore, when reading data, it is necessary to consider timing to avoid collision between data being read-in and an address which is output preceding or following the data. (Refer to “(3) Precautions on memory expansion.”) h 1 This is applied when the external data bus = 16 bits wide (BYTE = “L”). h 2 When the external memory’s specifications are smaller than tpxz(E-DZ), there is a possibility that the tail of address collides with the head of data. fi Refer to “(3) Precautions on memory expansion.” h 3 When the external memory’s specifications are greater than tpzx(E-DZ), there is a possibility that the tail of data collides with the head of address. fi Refer to “(3) Precautions on memory expansion.” ten(OE) Address Address tpzx(E-DZ) tsu(D-E) ta(OE) ta(CE), ta(S) tDF , tdis(OE) h 2 h 3 tw(EL) Data tpxz(E-DZ) ten(CE), ten(S) External memory data output External memory output enable signal (Read signal) OE E External memory chip select signalsCE, S Address output and data input A8/D 8 to A15/D15 A16/D0 to A23/D7 h 1 : Specifications of the 7733 Group (The others are specifications of external memory.) Fig. 17.1.4 Timing at which data is read from external memory

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Table 17.1.3 Value of tpxz(E-DZ) and calculation formula for tpzx(E-DZ) (Unit: ns) Wait 0 Wait 1 1 5 109 2•f(f2) – 20 Software wait Wait bit Wait selection bit tpxz(E-DZ) tpzx(E-DZ) No wait 0 or 1 Wait bit: Bit 2 at address 5E16 Wait selection bit: Bit 0 at address 5F16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = “0.”

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(2) Timing for writing data Figure 17.1.5 shows the timing for writing data to an external memory. When data is written, the data is output from when an interval of td(E-DQ ) has passed after signal E’s falling edge until an interval of th(E-DQ ) has passed after signal E’s rising edge. Table 17.1.4 lists the value of td(E-DQ ) and the calculation formula for th(E-DQ ). Make sure that the data output timing for writing data satisfies the following specifications of the external memory: data setup time (tsu(D )) and data hold time (th(D )) for writing data. Fig. 17.1.5 Timing at which data is written to external memory Table 17.1.4 Value of td(E-DQ) and calculation formula for th(E-DQ) (Unit: ns) Wait 0 Wait 1 – 221 5 109 2•f(f2) No wait 0 or 1 Wait bit: Bit 2 at address 5E16 Wait selection bit: Bit 0 at address 5F16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = “0.” write signals W, WE External memory chip select signalsCE, S (The others are specifications of external memory.) : Specifications of the 7733 Grouph This is applied when the external data bus = 16 bits wide (BYTE = “L” ). E Address and data output hA8/D 8 to A15/D15 A16/D0 to A23/D7 tsu(D) th(D) AddressDataAddress tw(EL) th(E-DQ) td(E-DQ) Software wait Wait bit Wait selection bit t d(E-DQ ) th(E-DQ )

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(3) Precautions on memory expansion When specifications of the 7733 Group do not match those of an external memory as described in the following À to ´ , some considerations about the circuit are necessary: À When using an external memory which requires a long address access time (ta(AD)) \` When using an external memory which outputs data within an interval of tpxz(E-DZ) after signal E’s falling edge. ´ When using an external memory which outputs data for more than an interval of tpzx(E-DZ) after signal E’s rising edge À When using an external memory which requires a long address access time (ta(AD)) When an external memory requires a long address access time (ta(AD)) which does not satisfy the 7733 Group’s tsu(D-E), try to carry out the following: l Lower 2•f(f2) l Select “Software wait is inserted.” (Refer to section “12.2 Software wait.”) l Use the ready function. (Refer to section “12.3 Ready function.”) generating circuit example (with wait 1). ___ areas where the ready function is valid are specified by using the chip select signal (CS 2) which is externally generated.

7733 Group User’s Manual 17–11

Fig. 17.1.6 Ready generating circuit example (with no wait) 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN) or Wait generated by the ready function is inserted only to an area where accessed by signal CS 2. M37733MHBXXXFP CS 1 A8 to A23 (D0 to D15) A0 to A7 AC74 D T Q RDY E AC32 AC32 AC04 Address bus Data bus Address latch circuit Address decode circuit CS 2 Circuit conditions: f(XIN) £ 15.7 MHz, no wait E CS 2 Q RDY tctd(E- 1) tsu(RDY- 1) Propagation delay time of AC32 (Max.: 8.5 ns) h h Condition to satisfy the relationship of tsu(RDY- 1) ‡ 55 ns in the left timing chart is tc ‡ 63.5 ns. Accordingly, when f(XIN) £ 15.7 MHz, this example satisfies the relationship of tsu(RDY- 1) ‡ 55 ns. : Wait generated by the ready function

7733 Group User’s Manual17–12

Fig. 17.1.7 Ready generating circuit example (with wait 1) Wait generated by the ready function is inserted only to an area where accessed by signal CS2. M37733MHBXXXFP CS 1 A8 to A23 (D0 to D15) A0 to A7 RDY E F32 F32 Address bus Data bus Address latch circuit Address decode circuit CS 2 RD F04 F04 F74 h 1 h 2 h 3 E CS 2 RDY th( 1-RDY) : Wait generated by the ready function : Software waittsu(RDY- 1) h 1 to h 3 Make sure that the sum of propagation delay time is within (when 2 • f(f2) = 25 MHz, 25 ns). 2 510 2 • f(f2) – tsu(RDY– 1) Circuit conditions: f(XIN) £ 25 MHz, wait 1 is valid, 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN)or

7733 Group User’s Manual 17–13

\` When using an external memory which outputs data within an interval of tpxz(E-DZ) after signal E’s falling edge When there is a possibility that the tail of an address collides with the head of data because the external memory outputs data within an interval of tpxz(E-DZ) after signal E’s falling edge, delay only _ ___ the E’s front falling edge. In this case, the falling edge of the read signal (OE ) for the memory, which is generated from signal E, is delayed. (Refer to Figure 17.1.8.) Fig. 17.1.8 Timing example when data output is delayed External memory output enable signal (Read signal) Address output External memory data output tpxz(E-DZ) E OE d Address Address Data ten(OE ) ta(OE ) Satisfy the following conditions:

• tpxz(E-DZ) £ ten(OE)+d
• When ten(OE) £ tpxz(E-DZ) (= 5 ns), make sure that signal E’s falling edge precedes signal OE’s falling edge and an interval of “d” is secured. Note: (The others are specifications of external memory.) : Specifications of

7733 Group User’s Manual17–14

´ When using an external memory which outputs data for more than an interval of tpzx(E-DZ) after signal E’s rising edge When there is a possibility that the tail of data collides with the head of an address because the external memory outputs the data for more than an interval of tpzx(E-DZ) after signal E’s rising edge, try to carry out the following: l By using bus buffers and others, delete the tail of data which is output from the memory. l Use a memory which is made by MITSUBISHI ELECTRIC CORPORATION and can be connected without bus buffers. Table 17.1.5 lists memories which can be connected without bus buffers (made by MITSUBISHI ELEC- TRIC CORPORATION). The reason why these memories do not need buffers is that timing parameters tDF or tdis(OE) is guaranteed. (Make sure that the read signal rises within 10 ns after signal E’s rising edge.) Table 17.1.5 Memories which can be connected without bus buffers (made by MITSUBISHI ELECTRIC CORPORATION) M5M27C256AK-85, -10, -12, -15 M5M27C512AK-10, -12, -15 M5M27C100K-12, -15 M5M27C101K-12, -15 M5M27C102K-12, -15 M5M27C201K, JK-10, -12, -15 M5M27C202K, JK-10, -12, -15 M5M27C256AP, FP, VP, RV-12, -15 M5M27C512AP, FP-15 M5M27C100P-15 M5M27C101P, FP, J, VP, RV-15 M5M27C102P, FP, J, VP, RV-15 M5M27C201P, FP, J, VP, RV-12, -15 M5M27C202P, FP, J, VP, RV-12, -15 M5M28F101P, FP, J, VP, RV-10, -12, -15 M5M28F102FP, J, VP, RV-10, -12, -15 M5M5256CP, FP, KP, VP, RV-55LL, -55XL, -70LL, -70XL, -85LL, -85XL, -10LL, -10XL M5M5278CP, FP, J-20, -20L M5M5278CP, FP, J-25, -25L M5M5278DP, J-12 M5M5278DP, FP, J-15, -15L M5M5278DP, FP, J-20, -20L Type Usage conditiontDF /tdis(OE) (Max.) 15 ns (When guaranteed as kit) (Note) 8 ns 10 ns 6 ns 7 ns 8 ns 2 • f(f 2) ≤ 20 MHz 2 • f(f2) ≤ 25 MHz EPROM One time PROM Frash memory SRAM Note: Specifications of the above memories are available if a comment of “t DF/tdis(OE) = 15 ns, microcomputer and kit” is added.

7733 Group User’s Manual 17–15

Fig. 17.1.9 Bus buffer usage example (1) Circuit conditions: Wait 1 is valid, 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN) F245 BYTE A8/D8 to A1 5/D15

25 MHz

Data bus (even) Data bus (odd) LE DQ OE AC573 DIR AB LE DQ OE AC573 ALE A1 to A7 Address bus M37733MHBXXXFP DIR AB E R/W BHE BC32 AC04 RD WO WE AC32XIN XOUT F245 h 2 h 2 h 3 A16/D0 to A23/D7 h 1 CNV SS h 4 OC OC h1 Make sure that the propagation delay time is 12 ns or less. h 2, h 3 Make sure that the following relationships are satisfied: l The sum of output disable time of h 2 and propagation delay time of h 3 is 20 ns or less. l The sum of output enable time of h 2 and propagation delay time of h 3 is 5 ns or more. h4 Make sure that the propagation delay time is 12 ns or less. or

7733 Group User’s Manual17–16

Fig. 17.1.10 Timing diagram for bus buffer usage example (1) external memory (F245) E OC (F245), RD 5 (max.) 130 (min.) 20 (min.) BC32 (tPHL ) BC32 (t PLH ) D AA <At reading> F245 (tPHZ /tPLZ ) F245 PZH /tPZL ) A8/D8 to A15/D15 A16/D0 to A23/D7 Data output B to external memory (F245) E 130 (min.) BC32 (tPLH ) D AA <At writing> D F245 PHL /tPLH ) (Unit: ns) F245 PHZ /tPLZ ) OC (F245), WO , WE 45 (max.) BC32 (tPHL )

7733 Group User’s Manual 17–17

Fig. 17.1.11 Bus buffer usage example (2) (when a memory which requires a long data hold time for writing is connected) h 1 Make sure that the propagation delay time is 40.5 ns or less. h 2 Make sure that the output enable time is 5 ns or more and the output disable time is 42.5 ns or less. Circuit conditions: Wait 1 is valid, 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN) or ALS245A BYTE E

16 MHz

Data bus (even) Data bus (odd) LE DQ OE AC573 OCDIR AB LE DQ OE AC573 ALE A1 to A7 Address bus DIR AB R/W BHE AC32 AC04 RD WE WO 1D 1Q 2Q2T

1 AC74

These circuits make the rising edge of the write signal earlier by 1/2 1, so that the write hold time is extended.

7733 Group User’s Manual17–18

Fig. 17.1.12 Timing diagram for bus buffer usage example (2) (ALS245A) RD 5 (max.) 220 (min.) 42.5 (min.) AC32 (tPHL ) AC32 (tPLH ) D A <At reading> ALS245A (tPHZ /tPLZ ) E, OC (ALS245A) ALS245A (tPZH /tPZL ) <At writing> (Unit: ns) D A D AC32 5 2 (tPLH ) Write hold time ALS245A (tPHZ /tPLZ ) A8/D8 to A15/D15 A16/D0 to A23/D7 Data output B to external memory (ALS245A) WO , WE 2Q(AC74) 1Q (AC74) E, OC (ALS245A) AC04 (tPLH )+AC74 (tPLH ) 70 (max.) ALS245A (tPHL /tPLH ) 220 (min.) AC04 (tPLH )+AC74 (tPHL ) 5 2 (tPHL )AC32 A

7733 Group User’s Manual 17–19

17.1.4 Memory expansion example

(1) ROM expansion example on minimum model Figure 17.1.3 shows a ROM expansion example on the minimum m odel (with a 32-Kbyte ROM, memory expansion mode). Figure 17.1.4 shows the corresponding timing diagram. Fig. 17.1.13 ROM expansion example on minimum model Circuit conditions: Wait 1 is valid, A0 to A14 D 0 to D7 AC00 E BHE A0 to A14 D 0 to D7 OE CE M5M27C256AK-10 A15 h Open 1 = 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN) h Make sure that the propagation delay time is 10 ns or less. 000016 008016 088016 800016 External ROM area (M5M27C256AK) SFR area Internal RAM area Not used Memory map FFFF 16 or

7733 Group User’s Manual17–20

Fig. 17.1.14 Timing diagram for ROM expansion example on minimum model D 0 to D7 External ROM data output (A) (A) D CE <At reading> ta(AD) 130 (min.) 12 (min.) 5 (max.) 20 (min.) ta(OE) tsu(D-E) ‡ 32 15 (max.) (Guaranteed as kit.) E, OE AC00 (tPLH )AC00 (tPHL ) ta(CE) (Unit: ns) A0 to A14 A

7733 Group User’s Manual 17–21

(2) ROM expansion example on maximum model Figure 17.1.5 shows a ROM expansion example on the maximum model (with a 2-Mbit ROM, micro- processor mode). Figure 17.1.6 shows the corresponding timing diagram. Fig. 17.1.15 ROM expansion example on maximum model M5M27C202K-10 A0 to A16 OE A1 to A7 AC04 A 16/D0, A17/D1 ALE D 1 to D7 E R/W A 8/D8 to A15/D15 AC573 CE D 0 to D15 D 0 to D15 A8 to A15 000016 008016 SFR area Internal RAM area External ROM area (M5M27C202K) Memory map Q LE D CNVss h 1, h 2 Make sure that the propagation delay time is 10 ns or less. h 2 h 1 AC573 Q LE D A16, A17 3FFFF 16 088016 Circuit conditions: Wait 1 is valid, 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN) or

7733 Group User’s Manual17–22

Fig. 17.1.16 Timing diagram for ROM expansion example on maximum model <At reading> 130 (min.) 12 (min.) ta(AD)+AC573 (tPHL /tPLH ) External ROM data output CE ta(OE) R/W 12 (min.) ta(CE) AC04 (tPHL ) 20 (min.) A 5 (max.) D (Guaranteed as kit.) tsu(D-E) ‡ 32 (Unit: ns) 18 (max.) E, OE AC04 (tPLH ) 15 (max.)

7733 Group User’s Manual 17–23

(3) ROM and SRAM expansion example on maximum model Figure 17.1.17 shows an expansion example for ROM and SRAM on the maximum model (with two 32-Kbyte ROMs and two 32-Kbyte SRAMs, microprocessor mode). Figure 17.1.18 shows the corre- sponding timing diagram. Fig. 17.1.17 Expansion example for ROM and SRAM on maximum m odel 000016 008016 External ROM area (M5M27C256AK 5 2) SFR area Internal RAM area External RAM area (M5M5256CP 5 2) Memory map 1FFFF 16 1000016 088016 AC32AC04

20 MHz

Data bus (even) Data bus (odd) AC573 DQ LE AC32 AC04 RD D0 to D7D8 to D15 Address bus WO A0 to A14 D 0 to D7 M5M27C256AK-15 A1 to A15 D 0 to D7 OE A0 to A14 CE A1 to A15 S S A0 to A14 A0 to A14 DQ 1 to DQ8 DQ 1 to DQ8 OE W OE W A1 to A15 A1 to A15 D0 to D7 M5M5256CP-70LL OE D8 to D15 CE WE A1 to A7 A8/D8 to A15/D15 ALE A16/D0 D 1 to D7 R/W E BHE CNV SS h 2 h 1 h 3 AC573 DQ LE h 2 Circuit conditions: Wait 1 is valid, 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN) or h 1, h 2 Make sure that the following relationship is satisfied: l The sum of propagation delay time of h 1 and that of h 2 is 90 ns or less. h2 Make sure that the propagation delay time is 10 ns or less. h3 Make sure that the propagation delay time is 15 ns or less.

7733 Group User’s Manual17–24

Fig. 17.1.18 Timing diagram for ROM and SRAM expansion examp le on maximum model <At writing> E A8/D 8 to A15/D 15 A16/D 0, D 1 to D7 S A D 170 (min.) 45 (max.) 22 (min.) AC32 (tPHL ) tsu(D) ‡ 30 (Unit: ns) WE , WO AC573 (tPHL )+AC04 (tPHL ) AC32 (tPLH ) A8/D 8 to A15/D 15 A16/D 0 External memory data output A D <At reading> E 170 (min.) 22 (min.) 5 (max.) 30 (min.) (Guaranteed as kit.) ta(AD), ta(CE) tsu(D-E) ‡ 32 ta(S) OE AC32 (tPLH ) A1 to A7 A CE , S ta(OE) AC04 (tPHL ) AC573 (tPHL ) CE S AC32 (tPHL ) 15 (max.) 23 (min.) A A A A

7733 Group User’s Manual 17–25

17.1.5 I/O expansion example

(1) Port expansion example where the M66010FP is used Fig. 17.1.19 shows a port expansion example where the M66010FP is used. The frequency of a transmit clock for serial I/O must be 1.923 MHz or less. Serial I/O control in this expansion example is described below. In this expansion example, 8-bit data transmission/reception is performed three times by using UART0, and so ports expand by 24 bits. UART0 is set as follows: l Clock synchronous serial I/O mode is selected. Transmission/Reception is enabled. l An internal clock is selected. Transfer rate = 1.5625 MHz l LSB first is selected. The control procedure is as follows: À “L” level is output from port P4 (By this signal, the expanded I/O ports of the M66010FP enter a floating state.) \` “H” level is output from port P45. ´ “L” level is output from port P44. ˆ 24-bit data is transmitted/received using UART0. ˜ “H” level is output from port P44. Fig. 17.1.20 shows the timing of serial transfer between the M37733MHBXXXFP and M66010FP.

7733 Group User’s Manual17–26

Fig. 17.1.19 Port expansion example where M66010FP is used Circuit conditions: UART0 is used in clock synchronous serial I/O mode. Internal clock is selected. Transfer clock frequency S Vcc GND CNVss BYTE M66010FP Expanded I/O ports D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 A0 to A7 A8/D8 to A15/D15 A16/D0 to A23/D7 ALE E R/W BHE Open

7733 Group User’s Manual 17–27

Fig. 17.1.20 Timing of serial transfer between M37733MHBXXXFP and M66010FP DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO20 DO21 DO22 DO23 DO24 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI20 DI21 DI22 DI23 DI24 DI1 DI2 DI24 S CS CLK DI DO Expanded I/O port Expanded I/O port Expanded I/O port Data of expanded I/O ports are input to the shift register 1. Expanded I/O ports are released from the floating state. Data of the shift register 1 is output in serial. Serial data is input to the shift register 2. DO24 DO2 DO1 Data of the shift register 2 is output to expanded I/O ports. D24 P45 P44 CLK 0 TX D 0 R X D 0 h Output structure of expanded I/O ports is N-channel open drain output. : Pins’ names of the 7733 Group. The others are pins’ names or operations of the M66010FP. to

7733 Group User’s Manual17–28

Examples for serial I/O are described below:

• Examples where the microcomputer is connected with an external device by using serial I/O
• Examples where serial data is transmitted and received

17.2.1 Connection examples with external device (Clock synchronous serial I/O mode)

(1) Connection with peripheral ICs Fig. 17.2.2 Example where transmission/recep- tion is performed Fig. 17.2.1 Example where only transmission is performed Fig. 17.2.3 Example where transmission/reception is performed (Connection example with wired- OR) CLK i TXD i CLK IN M37733MHBXXXFP Peripheral IC (OSD controller and so on) CLK i TXD i R XD i CLK IN OUT M37733MHBXXXFP Peripheral IC (E PROM and so on)2 CLK i TXD i R XD i CLK IN OUT M37733MHBXXXFP Peripheral IC (E PROM and so on)2 h Set pin TxDi to N-channel open-drain output. UART0: Data output selection bit ( bit 5 at address 3416) “1” UART1: Data output selection bit ( bit 5 at address 3C16) “1” When receiving, be sure to set pin TxDi’s output to “H” level. (Pin RxDi is in a floating state.)

7733 Group User’s Manual 17–29

One of three transmit clock output pins, which is selected by software, outputs a transmit clock. Multiple transmit clock output pins can be used only when the following conditions are satisfied: l Clock synchronous serial I/O mode is selected. l Internal clock is selected. l Only transmission is performed with UART0 used. h CLK i CTS i R XD i CLK Port OUT M37733MHBXXXFP Microcomputer TXD i IN i = 0 to 2 i = 0 to 2, j = 0 and 1 CLK i RTS i R XD i CLK Port OUT M37733MHBXXXFP Microcomputer TXD i IN Note: The RTS output function is not assigned for UART2. Fig. 17.2.4 Case where transmission for several peripheral devices is performed with 1-channel serial I/O used (2) Connection with microcomputer

7733 Group User’s Manual17–30

17.2.2 Examples of transmission for several peripheral ICs (Clock synchronous serial I/O mode)

In this example, transmission for three peripheral ICs is performed with UART0 used. (Note that simulta- neous transmission for several peripheral ICs is disabled.) (1) Specifications À Clock synchronous serial I/O mode is selected. \` An internal clock is selected. Transfer rate = 2 MHz ´ MSB first is selected. ˆ Transmit data is output at the falling edge of the transfer clock. ˜ Pin TxD 0’s output structure: CMOS output ¯ Completion of transmission is determined by checking the transmission register empty flag. Fig. 17.2.7 Connection example

7733 Group User’s Manual 17–31

(2) Initial settings for related registers X: It may be “0” or “1.” Clock synchronous serial I/O mode b7 b0 UART0 transmit/receive mode register (address 3016)0X X Internal clock is selected. X0 0 0 1 Must be fixed to “0.” CTS /RTS function is disabled. BRG0 count source: f2 b7 b0 UART0 transmit/receive control register 0 (address 3416)10 1 0X X 0 0 Pin TXD 0’s output structure: CMOS output Transmit data is output at the falling edge of the transfer clock. MSB first When the system clock (main clock) frequency = 16 MHz, transfer rate = 2 MHz b7 b0 UART0 baud rate register (BRG0) (address 3116)0116 Transmission is enabled. b7 b0 UART0 transmit/receive control register 1 (address 3516)XX X Reception is disabled. XX 0 X 1 000X b7 b0 UART0 transmission interrupt control register (address 7116) UART0 transmission interrupt is disabled. Pin CLKS1 is in the output mode when not transferring. b7 b0 Port P8 direction register (address 1416)XX 1 Pin CLKS1 outputs “H” level when not transferring. b7 b0 Port P8 register (address 1216)X XX 1 By this setting, pin CLKS1 functions as port P80 and outputs “H” level when not transferring, in other words, when no clock is output. h Pin CLKS0 do the processing of “output when not transferring.” (“H” level is output.) h h Fig. 17.2.8 Initial settings for related registers

7733 Group User’s Manual17–32

(3) Approximate flowchart Transmission buffer empty flag = “1” ? (bit 1 at address 3516) Serial transmit control register “XX01XXXX2” (address 6E16) Main routine Transfer clock is output from pin CLK0. (Data is transmitted to peripheral IC1.) UART0 transmission buffer register [Transmit data 1] (address 3216) Transmission register empty flag = “1” ? (bit 3 at address 3416) 1: Transfer is completed. Serial transmit control register “XX10XXXX2” (address 6E16) UART0 transmission buffer register [Transmit data 2] (address 32 16) Transmission register empty flag = “1” ? (bit 3 at address 3416) 1: Transfer is completed. 1: Transmission is completed. 1: Transmission is completed. At first, transmit data 1 is transmitted to peripheral IC1, and then transmit data 2 is transmitted to peripheral IC2. Transmit data is set. Waiting for the completion of transmission Waiting for the start of transmission Transfer clock is output from pin CLKS0. (Data is transmitted to peripheral IC2.) Transmit data is set. Waiting for the completion of transmission Waiting for the start of transmission Transmission buffer empty flag = “1” ? (bit 1 at address 3516) X: It may be “0” or “1.” Fig. 17.2.9 Approximate flowchart

7733 Group User’s Manual 17–33

17.2.3 Transmission/Reception example (UART mode, transfer data length = 8 bits)

In this example, transmission/reception is performed with UART1 used (transfer data length = 8 bits). (1) Specifications À UART mode is selected (transfer data length = 8 bits) \` An internal clock is selected. Baud rate = 9,600 bps ´ Parity is disabled. ˆ 1 stop bit is selected. ˜ Pin TxD1’s output structure: CMOS output ¯ The sleep mode is invalid. ˘ Transmission start is determined by using a UART1 transmission interrupt. ˙ Receive data is read out by using a UART1 reception interrupt. Fig. 17.2.10 Connection example M37733MHBXXXFP Peripheral IC

7733 Group User’s Manual17–34

(2) Initial settings for related registers Fig. 17.2.11 Initial settings for related registers X: It may be “0” or “1.” When the system clock (main clock) frequency = 16 MHz, baud rate = 9,600 bps b7 b0 UART1 baud rate register (BRG1) (address 3916)3316 b7 b0 UART1 transmit/receive control register 1 (address 3D16) Transmission is enabled. XX X Reception is enabled. XX 1 X 1 Pin RXD 1: Input mode b7 b0 Port P8 direction register (address 1416)X0 X X UART mode (Transfer data length = 8 bits) b7 b0 UART1 transmit/receive mode register (address 3816)00 0 Internal clock is selected. X0 1 0 1 1 stop bit Parity is disabled. Sleep mode is invalid. Must be fixed to “0.” BRG1 count source: f2 b7 b0 UART1 transmit/receive control register 0 (address 3C16)00 0 RTS function is selected. 0X 1 0 0 CTS /RTS function is enabled. Pin TXD 1’s output structure: CMOS output b7 b0 UART1 transmission interrupt control register (address 7316) Interrupt priority level is set. (Note that a value other than “0002” is set.) Interrupt request bit: 0 (Initialized) b7 b0 UART1 receive interrupt control register (address 7416)0 Interrupt request bit: 0 (Initialized) Interrupt disable flag (I) “0”: Interrupt is enabled. Interrupt priority level is set. (Note that a value other than “0002” is set.)

7733 Group User’s Manual 17–35

(3) Approximate flowchart Fig. 17.2.12 Approximate flowchart (1) Whether transmission of the preceding data has started or not is determined. (Whether the next data can be set to the UART1 transmission buffer register or not is determined.) Register save processing UART1 transmission interrupt routine [F_DATAOUT] “1” Flag used to determine whether a transmission interrupt request has occurred or not: “1” Register return processing RTI [F_DATAOUT]: Flag used to determine whether a transmission interrupt request has occurred or not. [TRA_DATA]: RAM where transmit data is stored. Main routine [F_DATAOUT] = “1” ? [F_DATAOUT] “0” UART1 transmission buffer register [TRA_DATA] (address 3A16) 1: Transmission interrupt request has occurred. The flag used to determine whether a transmission interrupt request has occurred or not is initialized. Transmit data is set.

7733 Group User’s Manual17–36

Fig. 17.2.13 Approximate flowchart (2) Main routine [F_DATAIN] = “1” ? [F_DATAIN] 0” 1: Reception interrupt request has occurred.

0 Whether reception has been completed

or not is determined. The flag used to determine whether a reception interrupt request has occurred or not is initialized. [F_DATAIN]: Flag used to determine whether a reception interrupt request has occurred or not [F_ERROR]: Flag used to determine whether a data reception error has occurred or not [F_ERROR] ? 0: No error is found. 1: Error is found. Whether data has been correctly received or not is determined. Error processing(Note) Received data processing When an error occurs, reception is disabled in a reception interrupt routine. Therefore, when restarting reception after error processing is completed in the main routine, make reception enabled again. Note:

7733 Group User’s Manual 17–37

Fig. 17.2.14 Approximate flowchart (3) Flag used to determine whether a data reception error has occurred or not = “0” Confirmed receive data is stored in [REC_DATA] [F_ERROR] “0” 0: No error is found. 1: Error is found. Whether data has been correctly received or not is determined. [F_ERROR]: Flag used for determination of data reception error [WORK_RAM]: RAM where receive data is temporarily stored [REC_DATA]: RAM where confirmed receive data is stored [F_DATAIN]: Flag used to determine whether a reception interrupt request has occurred or not [REC_DATA] [WORK_RAM] 0: No error is found. (Note) [WORK_RAM] UART1 receive buffer register (address 3E16) [F_DATAIN] “1” Flag used to determine whether a reception interrupt request has occurred or not = “1” Register return processing RTI Register save processing UART1 reception interrupt routine Error sum flag? (bit 7 at address 3D 16) Overrun error flag? (bit 4 at address 3D 16) 1: Error is found. [F_ERROR] “1” Reception enable bit “0” ( bit 2 at address 3D16) All of error flags = “0” (Reception is disabled.) Receive data is temporarily stored in [WORK_RAM] Framing error flag = “0” Parity error flag = “0” If the next data is received from when the error sum flag is checked until the contents of the UART1 receive buffer register is transferred to [WORK_RAM], an overrun error occurs. Therefore, at this timing, the content of the overrun error flag is checked again. Note: Flag used to determine whether a data reception error has occurred or not = “1”

7733 Group User’s Manual17–38

17.2.4 8-bit transmission example (Clock synchronous serial I/O mode) In this example, after 8-bit data is transmitted with UART1 used, a strobe signal is output. (1) Specifications À Clock synchronous serial I/O mode is selected. \` An internal clock is selected. Transfer rate = 2 MHz ´ LSB first is selected. ˆ Transmit data is output at the falling edge of the transfer clock. ˜ Pin TxD 1’s output structure: CMOS output ¯ A strobe signal is output from port P43 each time 8-bit data is transmitted. (Refer to Figure 17.2.16.) ˘ Completion of the transmission is determined by checking the transmission register empty flag. Fig. 17.2.15 Connection example Fig. 17.2.16 Strobe signal output timing P43 (Strobe signal) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7TXD 1 CLK 1 TXD 1 P43 CLK IN STB M37733MHBXXXFP Peripheral IC

7733 Group User’s Manual 17–39

(2) Initial settings for related registers Fig. 17.2.17 Initial settings for related registers When the system clock (main clock) frequency = 16 MHz, transfer rate = 2 MHz. UART1 baud rate register (BRG1) (address 3916)0116 Transmission is enabled. b7 b0 UART1 transmit/receive control register 1 (address 3D16)XX X Reception is disabled. XX 0 X 1 b7 b0 UART1 transmission interrupt control register (address 7316)000 UART1 transmission interrupt is disabled. X Pin P43: Output mode b7 b0 Port P4 direction register (address C16)1 Must be fixed to “0.” Clock synchronous serial I/O mode b7 b0 UART1 transmit/receive mode register (address 3816)0X X Internal clock is selected. X0 0 0 1 UART1 transmit/receive control register 0 (address 3C16) CTS /RTS function is disabled. Pin TXD 1’s output structure: CMOS output Transmit data is output at the falling edge of the transfer clock. LSB first BRG1 count source: f2 b7 b0 0 01 0 55 00 X: It may be “0” or “1.” Pin P43’s output level: “L” b7 b0 Port P4 register (address A16)0

7733 Group User’s Manual17–40

(3) Approximate flowchart Port P4 register “5555 1555 2” (address A16) Waiting for the start of transmission Transmit data is set. Main routine Transmission buffer empty flag = “1” ? (bit 1 at address 3D16) Transmission register empty flag = “1” ? (bit 3 at address 3C16) 1: Transfer is completed. UART1 transmission buffer register [Transmit data 2] (address 3A16) Transmission buffer empty flag = “1” ? (bit 1 at address 3D16) 1: Transfer is completed. 1: Transmission is completed. 1: Transmission is completed. 16-bit data is transmitted by the 8 bits in two operations. Waiting for the completion of transmission Strobe signal’s level: “H” Transmit data is set. Waiting for the completion of transmission Waiting for the start of transmission UART1 transmission buffer register [Transmit data 1] (address 3A16) Waiting Port P4 register “XXXX0XXX2” (address A16) Strobe signal’s level: “L” Port P4 register “XXXX1XXX2” (address A16) Strobe signal’s level: “H” Waiting Port P4 register “XXXX0XXX2” (address A16) Strobe signal’s level: “L” NOP instruction or others are used. “H” level output time for a strobe signal is set. NOP instruction or others are used. “H” level output time for a strobe signal is set. Transmission register empty flag = “1” (bit 3 at address 3C16) X: It may be “0” or “1.” Fig. 17.2.18 Approximate flowchart

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A program runaway detection example with using the watchdog timer is described below.

17.3.1 Program runaway detection example

In this example, when the watchdog timer detect a program runaway, the microcomputer is reset. (1) Specifications À The main clock is the system clock and f(XIN) = 16 MHz. \` When an interval of 4.09 ms has passed after value “FFF16” is set, the watchdog timer issues an interrupt request. (When writing to address 6016 is not performed because of a program runa- way.) ´ When a watchdog timer interrupt request occurs, the microcomputer is reset. (“Software reset” is applied.) (2) Initial setting for related register Fig. 17.3.1 Initial setting for related register Watchdog timer count source: clock f32 (In the case where f(XIN) = 16 MHz, a watchdog timer interrupt request occurs when an interval of 4.09 ms has passed after value “FFF16” is set.) b7 b0 @Watchdog timer frequency selection flag (address 6116)1

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(3) Approximate flowchart Fig. 17.3.2 Approximate flowchart Watchdog timer register 8-bit dummy data (address 6016) Main routine Watchdog timer is initialized. Watchdog timer’s value: FFF16 (Note 1) Watchdog timer interrupt routine Software reset bit “1 ” (bit 3 at address 5E16) RTI Watchdog timer interrupt request occurs. (Detection of a program runaway) (Note 2) Microcomputer is resset. Notes 1: The watchdog timer is initialized again from when the watchdog timer is initialized until the most significant bit of the watchdog timer becomes “0,” in other words, until a watchdog timer interrupt request occurs. 2: When a program runaway occurs, there is a possibility that values of data bank register (DT), direct page register (DPR), and others are incorrect. When accessing the software reset bit by using an addressing mode which uses DT, DPR, and others, be sure to set values of DT, DPR, and others again.

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(4) Precautions 1. The watchdog timer stops counting when the STP instruction is executed. For systems which use the watchdog timer, select “STP instruction disabled” with “STP instruction option” on “MASK ROM ORDER CONFIRMATION FORM.” 2. The watchdog timer stops counting when the WIT instruction is executed after the system clock stop bit at wait state (bit 5 at address 6C16) is set to “1.” 3. The contents of the processor interrupt priority level (IPL) is not initialized in the following cases: l When a value which is the same as the reset vector address’s contents is set to the watchdog timer’s vector address l When a program branches to the destination address at reset in a watchdog timer interrupt routine. Reset of the microcomputer is realized by applying the software reset.

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Power saving examples (in other words, examples to save power consumption) with the stop or wait mode used are described below.

17.4.1 Power saving example with stop mode used

In this example, power saving is realized by using the stop mode. The stop mode is terminated by using the key input interrupt function. (1) Specifications À The microcomputer operates in the single-chip mode. \` Pins P5 0 to P53 are used as output pins for the key matrix scanning. Input pins (KI0 to KI3) for the key input interrupt function are used as key input pins. Pins KI0 to KI3 are pulled high by using the pull-up function. ´ The initial output levels of pins P50 to P53 are “L.” ˆ When a key input interrupt request occurs owing to a key push, the key data is read-in. (This reading is surely performed independent of power saving.) ˜ In the stop mode, interrupts other than a key input interrupt are disabled. ¯ An external clock is used as the main clock.

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(2) Initial settings for related registers Fig. 17.4.1 Initial settings for related registers Pins KI0 to KI3 are pulled high. Port P5 direction register (address D16) Pins P50 to P53: Output mode b7 b0 00 0 Pins P54 to P57 (KI0 to KI3): Input mode 01 1 1 1 X: It may be “0” or “1.” Pins P50 to P53’s output (scan output) level: “L” b7 b0 Port P5 register (address B16)00 0 0 Key input interrupt function is selected. Must be fixed to “0.” b7 b0 Port function control register (address 6D16)11 0 Interrupt disable flag (I) b7 b0 INT2/Key input interrupt control register (address 7F16)000 Interrupt priority level is set. (Note that a value other than “0002” is set.) Interrupt request bit: 0 (Initialized) Must be fixed to “0.” “0”: Interrupt is enabled. Must be fixed to “0.” An external clock is selected as the main clock. Watchdog timer is not used when the stop mode is terminated. Oscillation circuit control register 1 (address 6F16) (Note) In the one time PROM version or EPROM version of the 7733 Group, this bit must be fixed to “1.” (In the 7735 Group, this bit must be fixed to “0.” ) b7 b0 10 1 Pin P64/INT 2 is not used for the key input interrupt. Note: When writing a value to this register, write a value of “55 16” by executing the LDM instruction, and then write a desired value. (Refer to Figure 11.2.4.) XXXX X

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Fig. 17.4.2 Approximate flowchart (3) Approximate flowchart Interrupts other than a key input interrupt are disabled. Notes 1:When pin VREF and resistor ladder network are connected, current flows into the resistor ladder network. When using the A-D converter after the stop mode is terminated, do as follows: qReconnect pin VREF and resistor ladder network. wAnd then, start A-D conversion after a period of 1 µs or more passed. When a port is connected to an external device and so on, there is a possibility that current consumption increases according to the port’s level. In order to avoid this problem, do as follows:

• When output mode is selected: Fix the port’s level to a level where no current flows into the external.
• When input mode is selected : Pull the port high or low via a resistor. (Floating state is disabled.) Key input interrupt request occurs. (Key is pushed.) Main routine STP VREF connection selection bit “1” (bit 5 at address 1F16) Pin VREF is disconnected from resistor ladder network. (Note 1) Port level is fixed. (Note 2) Stop mode is selected. Bits 2 to 0 at addresses 7016 to 7E16 “0002” Key input (INT2) interrupt routine Key data is read-in. Register return processing RTI Port P5 register’s bits which correspond to pins P50 to P53 “0” (bits 0 to 3 at address B16) Scan output: “L” level Port P5 register’s bits which correspond to pins P50 to P53 “0” (bits 0 to 3 at address B16) Scan output: “L” level Register save processing

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(4) Settings for performing power saving in memory expansion or microprocessor mode In the memory expansion or microprocessor mode, when saving power consumption, it is necessary to fix the I/O pins’ levels of the external bus and bus control signals in the stop mode. For this purpose, set the standby state selection bit to “1.”

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Note: Regardless of this setting, in the following cases, pin 1 outputs “L” level in the stop mode: l When the signal output disable selection bit is set to “0” in the microprocessor mode l When the clock 1 output selection bit is set to “1” in the memory expansion mode STP VREF connection selection bit “1” (bit 5 at address 1F16) Pin VREF is disconnected from resistor ladder network. Stop mode is selected.Interrupt request occurs. Port P0 register “001111112” (address 216) Port P1 register “000000002” (address 316) Port P2 register “000000002” (address 616) Port P3 register “000010112” (address 716) Levels of ports other than the above are fixed. Signal output disable selection bit “1” (bit 6 at address 6C16) I/O pins’ levels of external bus and bus control signals in the stop mode are set. (These levels can be set by the corresponding port register’s bits.) In this example, I/O pins for “L”-active signals are set to “H” and the other pins are set to “L.” Ports which correspond to I/O pins of external bus and bus control signals: Output mode (This setting is done in order to output a value set to a port register in the stop mode) Pin 1’s state in the stop mode is set (Note). In this example, “L” level output is set. Pin E’s output level in the stop mode is set. In this example, it is set to “L.” Port P0 direction register “FF16” (address 416) Port P1 direction register “FF16” (address 516) Port P2 direction register “FF16” (address 816) Port P3 direction register “FF16” (address 916) Main routine Port P4 register’s bit which corresponds to P42 pin “0” (bit 2 at address A16) Port P4 direction register’s bit which corresponds to P42 pin “1” (bit 2 at address C16) Standby state selection bit “1” (bit 0 at address 6D16) Standby state selection bit: “1” (In the stop mode, a value which is set to the corresponding port register is output from an I/O pin of the external bus or bus control signals.) Fig. 17.4.3 Fixing I/O pins’ levels of external bus and bus control signals (Microprocessor mode)

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17.4.2 Power saving example with wait mode used

In this example, power saving is realized by using the wait mode. While power is saved, the clock function is realized by using the clock timer (Timer B2). (1) Specifications À The microcomputer operates in the single-chip mode. \` The frequency of the sub clock (f(XCIN)) = 32.768 kHz. An external clock is used as the sub clock. ´ Clock counting is performed by using the clock timer. (An interrupt request occurs every second.) ˆ When an INT0 interrupt request occurs (Note), the wait mode is terminated. Note: An interrupt request occurs at every falling edge of the signal input from pin INT0. ˜ In the wait mode, interrupts other than the following interrupts are disabled.

• Timer B2 interrupt
• INT0 interrupt ¯ An external input is used as the main clock.

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(2)Initial settings for related registers Fig. 17.4.4 Initial settings for related registers X: It may be “0” or “1.” b7 b0 Timer B2 interrupt control register (address 7C16) Interrupt priority level is set. (Note that a value other than “0002” is set.) Interrupt request bit: 0 (Initialized) Interrupt disable flag (I) “0”: Interrupt is enabled. b7 b0 INT0 interrupt control register (address 7D16) Interrupt priority level is set. (Note that a value other than “0002” is set.) Interrupt request bit: 0 (Initialized) An interrupt request occurs at the falling edge. Interval of the clock timer’s interrupt request occurrence: 1 second b15 b8 Timer B2 register (addresses 5516 and 5416)0316 b7 b0 FF16 Settings for the clock timer b7 b0 Timer B2 mode register (address 5D16)X 01 0 1 XCIN-XCOUT is selected. (Sub clock is used.) b7 b0 Oscillation circuit control register 0 (address 6C16)1 In the wait mode, clocks 2 to 512 are stopped. 1 X XX An external clock is selected as the main clock. Watchdog timer is not used when the stop mode is terminated. b7 b0 Oscillation circuit control register 1 (address 6F16)0X1 1 1 An external clock is selected as the sub clock and P76 functions as a port. Watchdog timer is not used when the stop mode is terminated. In the one time PROM version or EPROM version of the 7733 Group, this bit must be fixed to “1.” (In 7735 Group, this bit must be fixed to “0.” ) Must be fixed to “0.” Note: When writing a value to this register, write a value of “5516” by executing the LDM instruction, and then write a desired value. (Refer to Figure 11.2.4.)

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(3) Approximate flowchart Fig. 17.4.5 Approximate flowchart (1) [F_WIT]: Flag used to determine whether an INT0 interrupt request has occurred or not Main clock oscillation circuit: Oscillating <<C>> Main routine System clock selection bit “1” (bit 3 at address 6C16) System clock: Main clock Sub clock <<A>> VREF connection selection bit “1” (bit 5 at address 1F16) Pin VREF is disconnected from resistor ladder network. (Note 1) Port level is fixed. (Note 2) Wait mode is selected. Main clock stop bit “1” (bit 2 at address 6C16) Main clock oscillation circuit: Stopped <<B>> Main clock stop bit “0” (bit 2 at address 6C16) 0: INT0 interrupt [F_WIT] “1” Clock timer interrupt request occurs. [F_WIT] = “1” ? “1”: Clock timer interrupt WITINT0 interrupt request occurs. (By this setting, the wait mode is terminated only when an INT0 interrupt request occurs.) Bits 2 to 0 at addresses 7016 to 7B16, 7E16, and 7F16 “0002” Interrupts other than timer B2 and INT0 interrupts are disabled. Timer B2 count start flag “1” (bit 7 at address 4016) Clock timer starts counting. System clock selection bit “0” (bit 3 at address 6C 16) System clock: Sub clock Main clock (Note 3) <<D>> <<A>> <<B>> <<C>> <<D>>: Refer to Figure 17.4.8.For Notes 1 to 3, refer to the next page.

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Fig. 17.4.6 Approximate flowchart (2) Notes 1: When pin VREF and resistor ladder network are connected, current flows into the resistor ladder network. When using the A-D converter after the wait mode is terminated, do as follows: À Reconnect pin VREF and resistor ladder network. Á And then, start A-D conversion after a period of 1s or more passed. 2: When a port is connected to an external device and so on, there is a possibility that current consumption increases according to the port’s level. In order to avoid this problem, do as follows:

• When output mode is selected: Fix the port’s level to a level where no current flows into the external.
• When input mode is selected: Pull the port high or low via a resistor. (Floating state is disabled.) 3: Do not switch the system clock until oscillation of a clock which is input from the external is stabilized. Timer B2 interrupt routine Register save processing Clock count Register return processing RTI INT0 interrupt routine Register save processing [F_WIT] “0” Register return processing RTI [F_WIT]: Flag used to determine whether an INT0 interrupt request has occurred or not

Fig. 17.4.6 Approximate flowchart (2) Notes 1: When pin VREF and resistor ladder network are connected, current flows into the resistor ladder network. When using the A-D converter after the wait mode is terminated, do as follows: qReconnect pin VREF and resistor ladder network. And then, start A-D conversion after a period of 1s or more passed. 2: When a port is connected to an external device and so on, there is a possibility that current consumption increases according to the port’s level. In order to avoid this problem, do as follows:

• When output mode is selected: Fix the port’s level to a level where no current flows into the external.
• When input mode is selected: Pull the port high or low via a resistor. (Floating state is disabled.) 3: Do not switch the system clock until oscillation of a clock which is input from the external is stabilized. Timer B2 interrupt routine Register save processing Clock count Register return processing RTI INT0 interrupt routine Register save processing [F_WIT] “0” Register return processing RTI [F_WIT]: Flag used to determine whether an INT0 interrupt request has occurred or not

w

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“1” “0” “1” “0” Main clock Sub clock Main clock Fig. 17.4.7 State of main clock, sub clock, and system clock

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An application example of the clock timer (Timer B) is described below.

17.5.1 Application example of clock timer

In this example, the clock timer is controlled by a clock of 32.768 kHz. When the main power source is off, the clock timer can continue counting for the maximum of approximate 45 days by using the backup power source and the internal connect function between timers B1 and B2. (1) Specifications À Main power source = 5 V to 2.75 V. Backup power source = 2.75 V to 2.2 V \` Timer B2 uses the sub clock (32.768 kHz) divided by 32 as the count source and counts the time up to 1 minute. ´ Timer B2 counts the power-source-off time up to the maximum of approximate 45 days, checking the timer B2’s overflow signal. ˆ The clock counter is counted up each time timer B2 interrupt occurs, in other words, every 1 minute. ˜ When Vcc is less than 2.75 V, in other words, when the main power source is off, the INT0 input’s level changes from “H” to “L” and the microcomputer enters the wait mode at this falling edge. (Refer to “a” in Figure 17.5.2.) ¯ In the wait mode (Vcc = 2.2 V or more), only timers B2 and B1 do counting. (In this case, note that clock display is disabled and the timer B2 and B1 interrupts are disabled.) ˘ When Vcc = 2.75 V or more in the wait mode, in other words, when the main power source is on, the INT0 input’s level changes from “L” to “H” and the wait mode is terminated at the INT0 input’s rise. (Refer to “b” in Figure 17.5.2.) At this time, the following is done according to the timer B1’s state.

• When no overflow has occurred in timer B1 (Timer B1 interrupt request bit = “0”), timer B1’s value is added to the clock counter’s value which was obtained immediately before the wait mode.
• When an overflow has occurred in timer B1, in other words, when a period of approximate 45 days or more has passed, a message for resetting time is displayed. ˙ When Vcc = 2.2 V or less, the microcomputer enters the reset state owing to the power source microcomputer is released from reset state. (Refer to “d” in Figure 17.5.2.) Fig. 17.5.1 Connection example Detection voltage Vcc RESET INT0 Vss XCIN XCOUT 32.768 kHz M37733MHBXXXFPPower source detection circuit Reset signal Control signal Clock display Main power source (5 V)Backup power source

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Fig. 17.5.2 Timing chart (2) Structure of timer B block where timers B1 and B2 are internally connected Figure 17.5.3 shows the structure of the timer B block. Fig. 17.5.3 Structure of timer B block 5 V 2.75 V 2.2 V 0 V Vcc RESET INT0 Wait mode Approx. 45.5 days (Max.) ab c d Main power source Backup power source Main clock : f(XIN) Sub clock : f(XCIN) 1/32 Clock timer fc32 Timer B2 reload register Timer B1 reload register Timer B1 counter Timer B1 interrupt request bit Timer B2 interrupt request bit Event counter mode Timer B1 internal connect selection bitClock prescaler (Timer B2 counter) System clock (Clock source for clocks f2 to f512 and internal clock )

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(3) Initial settings for related registers Fig. 17.5.4 Initial settings for related registers b15 b0 EFFF 16 Clocks f2 to f512 are operating in the wait mode. (Note 2) b7 b0 Oscillation circuit control register 0 (address 6C16)XX Sub clock is used. (Note 1) X01 Timer B1 mode register (address 5C16) Timer B2 mode register (address 5D16) 01: Count at the rising edge 01: Event counter mode b7 b0 XX 1 X X 01 0 Timer B1 interrupt control register (address 7B16) No interrupt is requested. Interrupt is disabled. b7 b0 0 000 Timer B2 interrupt control register (address 7C16) Interrupt priority level (any value other than “0002”) is set. No interrupt is requested. b7 b0 00 01 Port function control register (address 6D16) Timers B1 and B2 are connected internally. Must be fixed to “0.” b7 b0 1XXX X 0X X INT0 interrupt control register (address 7D16) b7 b0 Interrupt priority level (any value other than “0002”) is set. 00 00 Edge sense Interrupt request bit is set at the falling edge ( “H” to “L”). No interrupt is requested. Timer B2 register (addresses 5516 and 5416) b15 b0 FFFF 16 Timer B1 register (addresses 5316 and 5216) X: It may be “0” or “1.” Notes 1: Once this bit is set to “1,” it cannot be cleared to “0.” 2: When setting this bit to “1,” set “1” to this bit immediately before the WIT instruction is executed. Furthermore, clear this bit to “0” immediately after the wait mode is terminated.

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(4) Approximate flowchart Fig. 17.5.5 Approximate flowchart Clock prescaler is initialized. A value of “8016” is written to address 6F16 by executing the LDM instruction. Main routine INT0 interrupt control register “1116” (address 7D16) Oscillation circuit control register (address 6F16) “8016” Count start flag (address 4016) “C016” Timer B2 interrupt routine Count-up processing for clock RTI Counted up every minute INT0 interrupt routine INT0 level/edge selection bit = “?” (bit 4 at address 7D16) Timer B1 count start flag “0” (bit 6 at address 40 16) By setting interrupt priority level, interrupts other than INT 0 are disabled. System clock stop bit at wait state (bit 5 at address 6C16) “1” Timer B1 count start flag “1 ” (bit 6 at address 40 16) Timer B1 register FFFF16 (addresses 5316 and 5216) Timer B1 count start flag “0” (bit 6 at address 4016) Timer B1 register FFFE16 (addresses 5316 and 5216) Timer B1 count start flag “1” (bit 6 at address 4016) Make INT0 interrupt priority level higher. WIT instruction Make INT0 interrupt priority level to the former level. RTI INT0 interrupt control register (address 7D16) “0116” Timer B1 interrupt request bit = ? (bit 3 at address 7B16) Count value of timers B1 and B2 Clock counter Display urging user to set time again INT0 interrupt polarity is selected. (Falling edge: “H” “L”) INT0 interrupt polarity is selected. (Rising edge: “L” “H”) Counting for timer B1 stops. Counting for timer B1 starts. Counting for timer B1 stops. 0: No request 0: No request1: Requested 1: Rising edge (“L” “H”) 0: Falling edge (“H” “L”) Count start flag Counting for timers B1 and B2 start 1: Requested h By software initial settings, interrupt priority level is set as follows: l Timer B2 < INT0 Counting for timer B1 starts. Timer B2 interrupt request bit = ? (bit 3 at address 7C16)

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18.1 Performance overview

18.2 Pin configuration

18.3 Functional description

18.4 Electrical characteristics

18.5 Standard characteristics

18.6 Applications

7733 Group User’s Manual18–2

The low voltage version has the following characteristics:

• Low power source voltage (2.7 to 5.5 V)
• Wide operating temperature range (–40 to 85 °C) The low voltage version is suitable to control equipment which is required to process a large amount of data with a little power dissipation, for example portable equipment which is driven by a battery and OA equip- ment. Differences between the M37733MHLXXXHP, which is the low voltage version of the 7733 Group, and the M37733MHBXXXFP are mainly described below. For the EPROM mode of the built-in PROM version, refer to chapter “19. BUILT-IN PROM VERSION.”

7733 Group User’s Manual 18–3

Number of basic instructions The minimum instruction execution time Main-clock frequency f(XIN) Sub-clock frequency f(XCIN) Memory size Programmable input/output ports Multi-function timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuits Power source voltage Power consumption (in single-chip mode) Port input/output characteristics Memory expansion Operating temperature range Device structure Package Table 18.1.1 shows the performance overview of the M37733MHLXXXHP. Table 18.1.1 M37733MHLXXXHP performance overview ROM RAM Ports P0–P2, P4–P8 Port P3 Timers A0–A4 Timers B0–B2 UART0–UART2 Main-clock oscillation circuit Sub-clock oscillation circuit Input/Output withstand voltage Output current Performance 103 333 ns (When f(XIN) = 12 MHz and main clock is system clock) 12 MHz (Max.) (Note) 32.768 kHz (Typ.) 124 kbytes 3968 bytes 8 bits 5 8 4 bits 5 1 16 bits 5 5 16 bits 5 3 (UART or clock synchronous serial I/O) 5 3 (10-bit successive approximation method) 5 1(8 channels) 12 bits 5 1 3 external, 16 internal (By software, one of interrupt priority levels 0 to 7 can be set for each interrupt.) Built-in (externally connected to a ceramic reso- nator or a quartz-crystal oscillator) Built-in (externally connected to a quartz-crystal oscillator) 2.7 V – 5.5 V 9 mW (When f(X IN) = 12 MHz, Vcc = 3 V, and the main clock is the system clock, Typ.) 22.5 mW (When f(X IN) = 12 MHz, Vcc = 5 V, the main clock is the system clock, Typ.) 90 µW (When f(XCIN ) = 32 kHz, Vcc = 3 V, the sub clock is the system clock, and the main clock is stopped, Typ.) 5 V 5 mA Possible (Maximum of 16 Mbytes) –40 °C to +85 °C High-performance CMOS silicon gate process 80-pin plastic molded fine-pitch QFP Note: When the main clock division selection bit = “1,” the maximum value of f(XIN) = 6 MHz.

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Figure 18.2.1 shows the M37733MHLXXXHP pin configuration. Fig. 18.2.1 M37733MHLXXXHP pin configuration (Top view) 2/AL E 1/BH E 3/HL DA X OU T E CNV SS R ESET 0/HO LD P86/R xD 1 P87/TxD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D 8 P11/A9/D 9 P12/A10/D 10 P13/A11/D 11 P14/A12/D 12 P15/A13/D 13 P16/A14/D 14 P17/A15/D 15 P20/A16/D 0 P21/A17/D 1 30 31 32 33 34 35 36 37 38 39 40 26 27 28 2921 2322 1/RDY BYT E X IN V SS 0/R/ W 7/A 6/A 5/A 4/A 3/A 2/A P66/TB 1IN P65/TB 0IN P64/INT 2 P63/INT 1 P62/INT 0 P61/TA 4IN P60/TA 4OU T P57/TA 3IN /KI3 P5 6/TA 3OU T/KI2 P55/TA 2IN /KI1 P54/TA 2OU T/KI0 P53/TA 1IN P52/TA 1OU T P51/TA 0IN P50/TA 0OU T P47 P8 5/CL K1 P8 4/CT S1/RT S1 P8 3/TXD 0 P8 2/R XD 0/CL K S0 1/CL K P8 0/CT S0/RT S0/CL K S1 V CC AV CC V RE F AV SS V SS 7/AN 7/X CI N 6/AN 6/X CO UT 5/AN 5/AD TR G /TxD 2 4/AN 4/RxD 2 3/AN 3/CL K2 2/AN 2/CT S2 1/AN 0/AN 7/TB 2IN/ SUB M37733MHLXXXHP P43 P44 P45 P46 Outline 80P6D-A 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 64 63 62 61 24 25

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The M37733MHLXXXHP has the same functions as the M37733MHBXXXFP except for the power-on reset conditions. Power-on reset conditions are described below. For the other functions, refer to chapters “2. CENTRAL PROCESSING UNIT” to “14. CLOCK GENERAT- ING CIRCUIT.”

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18.3.1 Power-on reset conditions

Figure 18.3.1 shows the power-on reset conditions and Figure 18.3.2 shows an example of power-on reset circuit. For details of reset, refer to chapter “13. RESET.” Fig. 18.3.1 Power-on reset conditions Fig. 18.3.2 Example of power-on reset circuit Vcc RESET Powered on here 2.7V 0.55V Vcc GND RESET Vcc C d M62003L M37733MHLXXXHP h Delay time td is about 10 ms when Cd = 0.07 µF. td ≈ 0.152 5 C d [ µs ], Cd: [ µF ] RESET INTi (i = 0 to 2)INT (Interrupt signal) (Reset signal) h C d

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The M37733MHLXXXHP’s electrical characteristics are described below. For the latest data, inquire of addresses described last (“CONTACT ADDRESSES FOR FURTHER INFORMATION”) .

18.4.1 Absolute maximum ratings

Analog power source voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ta = 25 °C Unit V V V V V mW Ratings –0.3 to 7 –0.3 to 7 –0.3 to 12 –0.3 to Vcc+0.3 –0.3 to Vcc+0.3 200 –40 to 85 –65 to 150 RESET , CNVss, BYTE P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, VREF , XIN P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XOUT , E Symbol Vcc AVcc V I VI VO Pd Topr Tstg

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18.4.2 Recommended operating conditions

Recommended operating conditions (Vcc = 2.7 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) V V V V V V V V V V mA mA mA mA mA mA MHz kHz Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage High-level input voltage High-level input voltage Low-level input voltage Low-level input voltage Low-level input voltage High-level peak output current High-level average output current Low-level peak output current Low-level peak output current Low-level average output current Low-level average output current Main-clock oscillation frequency (Note 4) Sub-clock oscillation frequency f(X IN) :Operating f(XIN) :Stopped, f(XCIN) = 32.768 kHz P00–P07, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) P10–P17, P20–P27 (in single-chip mode) 0–P17, P20–P27 (in memory expansion mode and microprocessor mode) 0–P07, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) P10–P17, P20–P27 (in single-chip mode) 0–P17, P20–P27 (in memory expansion mode and microprocessor mode) 0–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P43, P54–P57, P60–P67, P70–P77, P80–P87 P44–P47, P50–P53 P00–P07, P10–P17, P20–P27, P30–P33, P40–P43, P54–P57, P60–P67, P70–P77, P80–P87 P44–P47, P50–P53 Vcc AVcc Vss AVss V IH VIH VIH VIL VIL VIL IOH (peak) IOH (avg) IOL (peak) IOL (peak) IOL (avg) IOL (avg) f(XIN) f(XCIN) ParameterSymbol Limits Min. Max. 5.5 5.5 2.7 2.7 Vcc 32.768 Typ. Unit –10 Notes 1: Average output current is the average value of an interval of 100 ms. 2: The sum of IOL (peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH (peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL (peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH (peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3: Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1.” 4: The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = “1.”

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18.4.3 Electrical characteristics

Electrical characteristics (Vcc = 5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz, unless otherwise noted) High-level output voltage High-level output voltage High-level output voltage High-level output voltage Low-level output voltage Low-level output voltage Low-level output voltage Low-level output voltage Low-level output voltage Hysteresis Hysteresis RESET Hysteresis XIN Hysteresis XCIN (When external clock is input) High-level input current Low-level input current Low-level input current RAM hold voltage Symbol Parameter Test conditions Min. Max. V V V V V V V V V V V V V µA µA µA mA V Limits UnitTyp. Vcc = 5 V, IOH = –10 mA Vcc = 3 V, IOH = –1 mA Vcc = 5 V, IOH = –400 µA Vcc = 5 V, IOH = –10 mA Vcc = 5 V, IOH = –400 µA Vcc = 3 V, IOH = –1 mA Vcc = 5 V, IOH = –10 mA Vcc = 5 V, IOH = –400 µA Vcc = 3 V, IOH = –1 mA Vcc = 5 V, IOL = 10 mA Vcc = 3 V, IOL = 1 mA Vcc = 5 V, IOL = 16 mA Vcc = 3 V, IOL = 10 mA Vcc = 5 V, IOL = 2 mA Vcc = 5 V, IOL = 10 mA Vcc = 5 V, IOL = 2 mA Vcc = 3 V, IOL = 1 mA Vcc = 5 V, IOL = 10 mA Vcc = 5 V, IOL = 2 mA Vcc = 3 V, IOL = 1 mA Vcc = 5 V Vcc = 3 V Vcc = 5 V Vcc = 3 V Vcc = 5 V Vcc = 3 V Vcc = 5 V Vcc = 3 V Vcc = 5 V, V I = 5 V Vcc = 3 V, VI = 3 V Vcc = 5 V, VI = 0 V Vcc = 3 V, VI = 0 V VI = 0 V, without a pull-up transistor VI = 0 V, with a pull-up transistor When clock is stopped 0.5 1.8 1.5 0.45 1.9 0.43 0.4 1.6 0.4 0.4 0.7 0.5 0.4 0.4 0.26 0.4 0.26 –1.0 –0.35 P00–P07, P10–P17, P20–P27, P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P33 P30–P32 E P00–P07, P10–P17, P20–P27, P33, P40–P43, P54–P57, P60–P67, P70–P75, P80–P87 P44–P47, P50–P53 P00–P07, P10–P17, P20–P27, P33 P30–P32 E P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVss, BYTE P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P53, P6 0, P61, P65– P67, P70–P7 7, P80–P87, XIN, RESET , CNVss, BYTE 4–P57, P62–P64 HOLD , RDY , TA0 IN–TA4 IN, TB0 IN–TB2 IN, INT0–INT2, ADTRG , CTS 0, CTS 1, CTS 2, CLK0, CLK 1, CLK2, KI0–KI3 VOH VOH VOH VOH VOL VOL VOL VOL VOL VT+–VT– VT+–VT– VT+–VT– VT+–VT– IIH IIL IIL VRAM Vcc = 5 V Vcc = 3 V Vcc = 5 V Vcc = 3 V –0.5 –0.18 2.5 4.7 3.1 4.8 2.6 3.4 4.8 2.6 0.4 0.1 0.2 0.1 0.1 0.06 0.1 0.06 –0.25 –0.08

7733 Group User’s Manual18–10

Vcc = 5 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(X IN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(X IN) = 12 MHz (Square waveform), (f(f2) = 0.75 MHz), f(XCIN) : Stopped, in operating (Note 1) Vcc = 3V, f(X IN) = 12 MHz (Square waveform), f(XCIN) = 32.768 kHz, when the WIT instruction is executed (Note 2) Vcc = 3 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 3 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Unit Measuring conditionsSymbol Parameter ICC Power source current Min. Typ. 4.5 0.4 mA mA mA µA µA µA µA µA Max. 0.8 Notes 1: This is applied when the main clock external input selection bit = “1,” the main clock division selection bit = “0,” and the signal output disable selection bit = “1.” 2: This is applied when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1.” 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the X COUT drivability selection bit = “0” and the system clock stop bit at wait state = “1.”

18.4.4 A-D converter characteristics

A-D CONVERTER CHARACTERISTICS (Vcc = AVcc = 5 V, Vss = AVss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note) , unless otherwise noted) In single-chip mode, output pins are open, and the other pins are con- nected to Vss. Limits Min. Typ. Max. — Resolution V REF = Vcc 10 Bits — Absolute accuracy V REF = Vcc ± 3 LSB R LADDER Ladder resistance V REF = Vcc 10 25 k Ω tCONV Conversion time 19.6 µs VREF Reference voltage 2.7 Vcc V VIA Analog input voltage 0 V REF V Symbol Parameter Measuring conditions Unit Note: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz.

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18.4.5 Internal peripheral devices

Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Min. 250 125 125 Max. ns ns ns UnitSymbol Parameter tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note 3) TAiIN input high-level pulse width (Note 3) TAiIN input low-level pulse width (Note 3) Min. Max. UnitSymbol Parameter Timer A input (Gating input in timer mode) Parameter Limits Timer A input (External trigger input in one-shot pulse mode) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Max. UnitSymbol Min. 666 166 166 tc(TA) tw(TAH) tw(TAL) Limits TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns Min. 166 166 Max. tw(TAH) tw(TAL) UnitParameterSymbol tc(UP) tw(UPH) tw(UPL) tsu(UP–TIN) th(TIN–UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time ns ns ns ns ns Min. Max. UnitSymbol Parameter Timer A input (Up-down input in event counter mode) Timer A input (External trigger input in pulse width modulation mode) 3333 1666 1666 666 666 Timer A input (Count input in event counter mode) Data formula (Min.) Data formula (Min.) 8 5 109 25 f(f2) 4 5 109 25 f(f2) 4 5 109 25 f(f2) (Note 2) (Note 2) (Note 2) 8 5 109 25 f(f2) (Note 2) Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 3: The TAiIN input cycle time must be 4 cycles of a count source or more. The TAiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively.

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Max. µs ns ns UnitSymbol Parameter Timer A input (Two-phase pulse input in event counter mode) Min. 500 500 Measuring conditions TAjIN input cycle time TAjIN input setup time TAjOUT input setup time tc(TA) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) Note: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz.

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Internal peripheral devices TAiIN input tc(TA) tw(TAH) tw(TAL) TAiOUT input (up-down input) tc(UP) tw(UPH) tw(UPL) TAiIN input (When fall count is selected) TAiIN input (When rise count is selected) TAiOUT input (up-down input) th(TIN–UP) tsu(UP–TIN) l Count input in event counter mode l Gating input in timer mode l External trigger input in one-shot pulse mode l External trigger input in pulse width modulation mode l Up-down input and count input in event counter mode Measuring conditions

• VCC = 2.7 to 5.5 V
• Input timing voltage : VIL = 0.2 VCC , VIH = 0.8 VCC tsu(TAjIN–TAjOUT ) TAjIN input TAjOUT input tsu(TAjOUT –TAjIN) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) l Two-phase pulse input in event counter mode tc(TA)

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Min. 666 333 333 Max.Min. 666 333 333 Timer B input (Count input in event counter mode) tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Min. Max. ns ns ns ns ns ns Limits UnitSymbol TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width tc(TB) tw(TBH) tw(TBL) ns ns ns Limits UnitSymbol Parameter Timer B input (Pulse period measurement mode) Parameter TBiIN input cycle time (One edge count) TBiIN input high-level pulse width (One edge count) TBiIN input low-level pulse width (One edge count) TBiIN input cycle time (Both edges count) TBiIN input high-level pulse width (Both edges count) TBiIN input low-level pulse width (Both edges count) 250 125 125 500 250 250 Timer B input (Pulse width measurement mode) tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Limits UnitSymbol Parameter Max. AD TRG input cycle time (Minimum allowable trigger) AD TRG input low-level pulse width Min. Max. ns ns Limits UnitParameterSymbol tc(AD) tw(ADL) A-D trigger input 1333 166 Serial I/O CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TxD i output delay time TxD i hold time RxD i input setup time RxD i input hold time tc(CK) tw(CKH) tw(CKL) td(C–Q) th(C–Q) tsu(D–C) th(C–D) Min. Max. 100 Limits UnitSymbol Parameter 333 166 166 Data formula (Min.) Data formula (Min.) 8 5 109 25 f(f2) 4 5 109 25 f(f2) 4 5 109 25 f(f2) (Note 2) (Note 2) (Note 2) Notes 1: The TBiIN input cycle time must be 4 cycles of a count source or more. The TBiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 8 5 109 25 f(f2) 4 5 109 25 f(f2) 4 5 109 25 f(f2)

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Min. 250 250 250 External interrupt INTi input, Key input interrupt KIi input INTi input high-level pulse width INTi input low-level pulse width KIi input low-level pulse width tw(INH) tw(INL) tw(KIL) Max. Limits UnitSymbol Parameter Measuring conditions

• VCC = 2.7 to 5.5 V
• Input timing voltage
• Output timing voltage : V IL = 0.2 VCC , VIH = 0.8 VCC : VOL = 0.8 V, VOH = 2.0 V TBiIN input tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) AD TRG input tw(INL) tw(INH) INTi input tc(CK) tw(CKH) tw(CKL) th(C–Q) tsu(D–C) CLK i input TxD i output RxD i input td(C–Q) th(C–D) tw(KIL) KIi input Internal peripheral devices

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Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits tsu(RDY– φ1) tsu(HOLD– φ1) th(φ1–RDY) th(φ1–HOLD) Max. ns ns ns ns Min. ParameterSymbol Unit Note: This is applied to the case where the main clock division selection bit = “0” and f(f 2) = 6 MHz. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz, unless otherwise noted) ns Min. Max. 120 Limits UnitConditionsParameter Fig. 18.4.1 Symbol HLDA output delay timetd(φ1–HLDA) ____ RDY input setup time HOLD input setup time ____ RDY input hold time HOLD input hold time

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tsu(RDY– 1) th( 1–RDY) tsu(RDY– 1) th( 1–RDY) Measuring conditions

• VCC = 2.7 to 5.5 V
• Input timing voltage : VIL = 0.2 VCC , VIH = 0.8 VCC
• Output timing voltage: VOL = 0.8 V, VOH = 2.0 V HOLD input HLDA output th( 1–HOLD) td( 1–HLDA) tsu(HOLD– 1) Hold td( 1–HLDA)

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18.4.7 Single-chip mode

Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. td(E–P0Q) td(E–P1Q) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) Port P0 data output delay time Port P1 data output delay time Port P2 data output delay time Port P3 data output delay time Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time ns ns ns ns ns ns ns ns ns UnitSymbol Max. 300 300 300 300 300 300 300 300 300 Min. LimitsParameter Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 2), unless otherwise noted) Conditions Fig. 18.4.1 Note: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. tc tw(H) tw(L) tr tf tsu(P0D–E) tsu(P1D–E) tsu(P2D–E) tsu(P3D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P0D) th(E–P1D) th(E–P2D) th(E–P3D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Limits UnitParameter 200 200 200 200 200 200 200 200 200 External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Port P0 input setup time Port P1 input setup time Port P2 input setup time Port P3 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P0 input hold time Port P1 input hold time Port P2 input hold time Port P3 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Symbol Max. Notes 1: This is applied when the main clock division selection bit = “0” and f(f 2) = 6 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 166 ns. 3: When the main clock division selection bit = “1,” values of tw (H)/tc and tw (L)/tc must be set to values from 0.45 through 0.55.

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td(E–P0Q) tsu(P0D–E) th(E–P0D) td(E–P1Q) tsu(P1D–E) th(E–P1D) td(E–P2Q) tsu(P2D–E) th(E–P2D) td(E–P3Q) tsu(P3D–E) th(E–P3D) tW(H)tctrtf E Port P0 output Port P0 input Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input XIN td(E–P4Q) tsu(P4D–E) th(E–P4D) td(E–P5Q) tsu(P5D–E) th(E–P5D) td(E–P6Q) tsu(P6D–E) th(E–P6D) td(E–P7Q) tsu(P7D–E) th(E–P7D) td(E–P8Q) tsu(P8D–E) th(E–P8D) Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input tW(L) Single-chip mode Measuring conditions

• VCC = 2.7 to 5.5 V
• Input timing voltage
• Output timing voltage : VIL = 0.2 VCC , VIH = 0.8 VCC : VOL = 0.8 V, VOH = 2.0 V

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Floating release delay time BHE output delay time R/W output delay time BHE hold time R/W hold time φ 1 output delay time 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Limits Typ.Data formula (Min.) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) – 63 – 63 – 43 – 43 – 73 Symbol td(An–E) td(A–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ 1) – 43 – 35 – 30 – 63 – 63 – 50 – 50 Conditions Fig. 18.4.1 Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 1 5 109 25 f(f2) 2 5 109 25 f(f2) tc tw(H) tw(L) tr tf tsu(D–E) th(E–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 166 ns. 3: When the main clock division selection bit = “1,” values of tw (H)/tc and tw (L)/tc must be set to values from 0.45 through 0.55. Min. 131

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th(ALE–A) th(E–DQ) td(E–DQ) Address/Data output A16/D0–A23/D7, A8/D8–A15/D15 (BYTE = “L”) DataAddress td(A–E) tpxz(E–DZ) tpzx(E–DZ) td(E–φ1) tw(EL) th(E–An) td(E–φ1) tw(ALE) td(BHE–E) th(E–BHE) td(R/W–E) th(E–R/W) XIN E Address output A0–A7 A8–A15 (BYTE = “H”) Data input D 8–D 15 (BYTE = “L”), D 0–D 7 (BYTE = “H”) ALE output BHE output R/W output Address Measuring conditions

• VCC = 2.7 to 5.5 V
• Output timing voltage
• Data input : VOL = 0.8 V, VOH = 2.0 V : VIL = 0.16 VCC , VIH = 0.5 VCC With no wait (Wait bit = “1”) td(E–φ1) td(An–E) tsu(D–E) th(E–D) td(ALE–E) td(BHE–E) td(R/W–E) Address Memory expansion mode and Microprocessor mode : tw(H)tw(L) tc tftr Port Pi output (i = 4–8) Port Pi input (i = 4–8) td(E–PiQ) tsu(PiD–E) th(E–PiD) tw(ALE) tw(EL) td(An–E) td(ALE–E) th(E–An) th(E–BHE) th(E–R/W) tftr tc tw(H)tw(L) (Write) (Read) td(E–φ1) tsu(A–ALE) Address

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Floating release delay time BHE output delay time R/W output delay time BHE hold time R/W hold time φ 1 output delay time 1 5 109 25 f(f2) 1 5 109 2 5f(f2) 1 5 109 2 5f(f2) 1 5 109 2 5f(f2) 1 5 109 2 5f(f2) Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Limits Typ.Data formula (Min.)Min. 298 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) – 63 – 63 – 43 – 43 – 73 Symbol td(An–E) td(A–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ 1) 1 5 109 25 f(f2) 4 5 109 25 f(f2) – 43 – 35 – 30 – 63 – 63 – 50 – 50 Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. tc tw(H) tw(L) tr tf tsu(D–E) th(E–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 166 ns. 3: When the main clock division selection bit = “1,” values of tw (H)/tc and tw (L)/tc must be set to values from 0.45 through 0.55. Conditions Fig. 18.4.1

7733 Group User’s Manual 18–23

When external memory area is accessed with wait 1 (Wait bit = “0” and Wait selection bit = “1”) tc th(E– R/W) td(R/W–E) td(BHE–E) th(E– BHE) tw(ALE) th(E–An) tw(EL) td(E–φ1) td(E–φ1) Address XIN E Address output A0–A7, A8–A15 (BYTE = “H”) Data input D 8–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H”) ALE output BHE output R/W output th(E– BHE) td(ALE–E) tsu(D–E) th(E–D) td(An–E) td(E–φ1) Address Memory expansion mode and Microprocessor mode : Port Pi output (i = 4–8) Port Pi input (i = 4–8) td(E–PiQ) tsu(PiD–E) th(E–PiD) tw(H)tw(L) td(E–DQ) th(ALE–A) th(E–DQ)Address/Data output A16/D0–A23/D7, A8/D8–A15/D15 (BYTE = “L”) Data tpxz(E–DZ) tpzx(E–DZ) <Write> <Read> td(E–φ1) tw(EL) th(E–An) td(An–E) td(ALE–E) tw(ALE) trtf tw(L) tw(H) trtf tc td(R/W–E) td(BHE–E) th(E– R/W) Measuring conditions

• VCC = 2.7 to 5.5 V
• Output timing voltage
• Data input : VOL = 0.8 V, VOH = 2.0 V : VIL = 0.16 VCC , VIH = 0.5 VCC tsu(A–ALE) td(A–E) Address Address

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25 f(f2) 3 5 109 25 f(f2) 3 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Limits Typ.Data formula (Min.)Min. 182 162 123 298 182 182 3 5 109 25 f(f2) 3 5 109 25 f(f2) 1 5 109 25 f(f2) 2 5 109 25 f(f2) 2 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) – 68 – 88 – 43 – 43 – 73 – 43 – 43 Symbol td(An–E) td(A–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ 1) – 43 – 35 – 30 – 68 – 68 – 50 – 50 Parameter Address output delay time Address output delay time Address hold time ALE pulse width Address output set up time Address hold time ALE output delay time Data output delay time Data hold time E pulse width Floating start delay time Floating release delay time BHE output delay time R/W output delay time BHE hold time R/W hold time φ 1 output delay time Conditions Fig. 18.4.1 Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 1 5 109 25 f(f2) 4 5 109 25 f(f2) tc tw(H) tw(L) tr tf tsu(D–E) th(E–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 166 ns. 3: When the main clock division selection bit = “1,” values of tw (H)/tc and tw (L)/tc must be set to values from 0.45 through 0.55.

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A0–A7, A8–A15 (BYTE = “H”) ALE output E BHE output R/W output tc Data input D 8–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H”) td(E–φ1)td(E–φ1) tw(EL) th(E–An) tw(ALE) td(BHE–E) th(E–BHE) td(R/W–E) th(E–R/W) Address Measuring conditions

• VCC = 2.7 to 5.5 V
• Output timing voltage
• Data input : VOL = 0.8 V, VOH = 2.0 V : VIL = 0.16 VCC , VIH = 0.5 VCC td(E– 1) td(An–E) tsu(D –E) th(E–D) td(ALE–E) th(E–BH E) th(E–R/W) Address/Data output A16/D0–A23/D7, A8/D8–A15/D15 (BYTE = “L”) th(E–DQ)th(ALE–A) td(E–DQ) tsu(A–ALE) Data tpxz(E–DZ ) tpzx(E–DZ ) Address Address Port Pi output (i = 4–8) Port Pi input (i = 4–8) td(E–PiQ) tsu(PiD–E) th(E–PiD) tw(L) tw(H) trtf <Write> <R ead> tw(EL) tf tr tw(L) tw(H) tc td(E– 1) td(An–E) td(ALE–E) th(E–An) tw(ALE) td(BH E–E) td(R/W –E) td(A–E) When external memory area is accessed with wait 0 (Wait bit = “0” and Wait selection bit = “0”) Memory expansion mode and Microprocessor mode : Address

7733 Group User’s Manual18–26

18.4.11 Measuring circuit for ports P0 to P8 and pins f1 and E

Fig. 18.4.1 Measuring circuit for ports P0 to P8 and pins f1 and E 50 pF E

18–27 (2) N-channel IOL –V OL characteristics Standard characteristics described below are just examples of the M37733MHLXXXHP’s characteristics and are not guaranteed. For rated values, refer to section “18.4 Electrical characteristics.”

18.5.1 Programmable I/O port (CMOS output) standard characteristics:

Ports P0 to P3, P40–P4 3,P54–P5 7, P6, P7, and P8 (1) P-channel IOH –V OH characteristics VOH [V] P-channel Power source voltage Vcc = 3 V 20.0 16.0 12.0 4.0 8.0 IOH [mA] Ta = 25 °C Ta = 85 °C N-channel Power source voltage Vcc = 3 V 20.0 16.0 12.0 8.0 4.0 VOL [V] IOL [mA] Ta = 25 °C Ta = 85 °C

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18.5.2 Programmable I/O port (CMOS output) standard characteristics:

Ports P44 to P47 and P5 0 to P53 (1) P-channel IOH –V OH characteristics (2) N-channel IOL –V OL characteristics VOH [V] P-channel Power source voltage Vcc = 3 V 20.0 16.0 12.0 4.0 8.0 IOH [mA] Ta = 25 °C Ta = 85 °C N-channel Power source voltage Vcc = 3 V 20.0 16.0 12.0 8.0 4.0 VOL [V] IOL [mA] Ta = 25 °C Ta = 85 °C

18–29

18.5.3 Icc–f(XIN) standard characteristics

(1) Icc–f(XIN) characteristics on operating and at reset (2) Icc–f(XIN) characteristics during wait mode 0 2 4 6 8 10 12 14

• Measuring conditions (Vcc = 3 V, Ta = 25 °C, f(XIN):square waveform input, single-chip mode)
• Register setting conditions Oscillation circuit control register 1 = “0216” (Main clock is input from the external.) On operating (CPU + peripheral devices) f(XIN) [MHz] Icc [mA] On operating (CPU) 0.2 0.4 0.6 0.8 02 46 8 10 12 14
• Measuring conditions (Vcc = 3 V, Ta = 25 °C, f(XIN):square waveform input, single-chip mode)
• Register setting conditions Oscillation circuit control register 0 = “2016” (In wait mode, clocks f2 to f512 are stopped.) Oscillation circuit control register 1 = “0216” (Main clock is input from the external.) or “0016” (Main-clock oscillation circuit is operating by itself.) f(XIN) [MHz] Icc [mA] CC 1 = 0 CC 1 = 1 CC 1 : Main clock external input selection bit (bit 1 of oscillation circuit control register 1)

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18.5.4 A-D converter standard characteristics

The lower line of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in output code from “0E 16” to “0F16” should occur at 36.25 mV, but the measured value is 0.3 mV. Accordingly, the measured point of change is 36.25 + 0.3 = 36.55 mV. The upper line of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is “0F16” is 2.2 mV. Accordingly, the [Measuring conditions]

• Vcc = AVcc = 3 V, •VREF = 2.56 V, •f(XIN) = 12 MHz, •Temp. = 25 °C

18–31

7733 Group User’s Manual18–32

Some application examples of connecting external memorys for the low voltage version are described bellow. Applications shown here are just examples. Modify the desired application to suit the user’s need and make sufficient evaluation before actually using it.

18.6.1 Memory expansion

The following items of the low voltage version are the same as section “17.1 Memory expansion,” but a part of the calculation way and constants for parameters is different:

• Memory expansion model
• Calculation way for address access time of external memory
• Bus timing
• Memory expansion way À Address access time of external memory ta(AD) ta(AD) = td(A-E) + tw(EL) – tsu(D-E) – (address decode time] 1 + address latch delay time] 2) address decode time] 1 : time necessary for validating a chip select signal after an address is decoded address latch delay time] 2 : delay time necessary for latching an address (This is not necessary on the minimum model.) \` Data setup time of external memory for writing data tsu(D) tsu(D) = tw(EL) – td(E–DQ) Table 18.6.1 lists the calculation formulas and constants for each parameter of the low voltage version. between tsu(D) and 25 f(f2). Table 18.6.1 Calculation formulas and constants for each parameter (Unit : ns) Wait 1 Wait 0 – 30 – 88 – 35 – 63 – 35 No wait 0 or 1 3 5 109 25 f(f2) 4 5 109 25 f(f2) 2 5 109 25 f(f2) 1 5 109 25 f(f2) 1 5 109 25 f(f2) Wait bit : Bit 2 at address 5E16 Wait selection bit : Bit 0 at address 5F16 Note: This is applied to the case where the system clock selection bit (bit 3 at address 6C16) = “0.” Software wait Wait bit Wait selection bit td(A-E) tw(EL) tsu(D-E) tsu(E-DQ) tpxz(E-DZ) tpzx(E-DZ)

18–33 Fig. 18.6.1 Relationship between ta(AD) and 25 f(f2) Fig. 18.6.2 Relationship between tsu(D) and 25 f(f2) 2 3 4 5 6 7 8 9 10 11 12 200 400 600 800 1000 1200 1400 1600 1800 2000 1875 1208 875 675 541 446 375 319 275 238 208 875 541 375 275 208 160 125 75 56 41 No wait Wait 1 or Wait 0 is valid. External clock input frequency 25 f(f2) [MHz] Data setup time tsu(D) [ns] 2 3 4 5 6 7 8 9 10 11 12 500 1000 1500 2000 2500 3000 3500 3297 2130 1547 1197 963 797 672 574 497 433 380 2322 1488 1072 822 655 536 447 377 322 276 238 822 572 422 322 250 197 155 122 94 72 No wait Wait 1 is valid. Wait 0 is valid. 1322 Memory access time ta(AD) [ns] External clock input frequency 25 f(f2) [MHz] ] Address decode time and address latch delay time are not considered.

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Fig. 18.6.3 Memory expansion example on minimum model

18.6.2 Memory expansion example on minimum model

Figure 18.6.3 shows a memory expansion example on the minimum model (with external RAM) and Figure 18.6.4 shows the corresponding timing diagram. In example, an Atmel company’s EPROM (AT27LV256R) is used as the external ROM. In Figure 18.6.3, the circuit condition is “No wait.” 000016 008016 External ROM area (AT27LV256R) SFR area Internal RAM area External RAM area (M5M5256CFP) Memory map A15 A0 to A14 D 0 to D7 AC04 AC32 E BHE Open A0 to A14 D 0 to D7 OE M5M5256CFP-10VLL OE RD WR CE S AT27LV256R-15DIAC04 AC32 Circuit conditions : No wait, A0 to A14 Vcc = 3.3 – 0.3 V 800016 FFFF 16 088016 ]1 Make sure that the propagation delay time is 35 ns or less. ]2 Make sure that the propagation delay time is 47 ns or less. ]3 Make sure that the propagation delay time is 62 ns or less. W 1 = , , , or 2 f(XIN) f(XIN) f(XIN) f(XCIN) DQ 1 to DQ8

18–35 Fig. 18.6.4 Timing diagram on minimum model D 0 to D7 External memory data output A A D S, OE l At reading 215 (min.) 62 (min.) 10 (max.) 95 (min.) tsu(P2D-E) ‡ 80 ROM : 25 (max.) RAM : 30 (max.) E AC32 (tPLH )AC32 (tPHL ) ta(S), ta(OE) E A1 to A14 AA l At writing D 0 to D7 AA S, W D 215 (min.) tsu(D) ‡ 40 (Unit : ns) AC32 (tPHL ) AC32 (tPLH ) 90 (max.) 82 (min.) A1 to A14 A ta(AD) ta(CE)AC04 (tPHL ) CE 62 (min.) A

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18.6.3 Memory expansion example on medium model A

corresponding timing diagram. Fig. 18.6.5 Memory expansion example on medium model A Internal ROM area Circuit conditions : No wait A16/D0 to A23/D7

10 MHz

E OpenBHE A0 to A16 OE M5M51008AFP-10VLL A0 to A15 CNV SS W External ROM area (M5M51008AFP) Memory map 00000016 00008016 DQ 1 to DQ8 ] Make sure that the propagation delay time is 22 ns or less. 03FFFF 16 000FFF 16 01FFFF 16 02000016 Internal RAM area SFR area DQ LE ALE A16 A17 AC573 D 0–D 7 VCC = 3.3 – 0.3 V 1 = , , , or 2 f(XIN) f(XIN) f(XIN) f(XCIN)

18–37 Fig. 18.6.6 Timing diagram on medium model A A0 to A15 AA l At writing E, OE, S1 A16/D 0 to A23/D 7 A16, A17, S2 AA D 165 (min.) 90 (max.) 37 (min.) tsu(D) ‡ 40 (Unit : ns) R/W, WE AC573 (tPHL ) A16/D 0 to A23/D 7 External memory data output AA D l At reading E, OE, S1 165 (min.) 37 (min.) 10 (max.) 70 (min.) ta(OE), ta(S1) tsu(P1D/P2D-E) ‡ 80 ta(S2) AC573 (tPLH ) A0 to A15 AA A16, A17, S2 AC573 (tPHL ) 35 (max.) 57 (min.) ta(A) + AC573

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18.6.4 Memory expansion example on maximum model

corresponding timing diagram. In this example, Atmel company’s EPROMs (AT27LV256R) are used as the external ROMs. In Figure 18.6.7, the circuit condition is “No wait.” Fig. 18.6.7 Memory expansion example on maximum model R/W E BHE AC04 Circuit conditions : No wait 03FFFF 16 External ROM area (AT27LV256R 5 2) SFR area Internal RAM area Memory map 00000016 00008016 00088016 External RAM area (M5M51008AFP 5 2) 00FFFF 16 02000016 Not used AC04 S1 S1 A1 to A7 A8/D8 to A15/D15 ALE D 2 to D7 A16 ]1 Make sure that the propagation delay time is 47 ns or less. ]2 Make sure that the propagation delay time is 50 ns or less. ]3 Make sure that the propagation delay time is 62 ns or less. A16 A16 Vcc = 3.3 ± 0.3 V S2 S2 ] 1 ] 3 ] 2 ] 2 1 = , , , or2 f(XIN) f(XIN) f(XIN) f(XCIN)

18–39 Fig. 18.6.8 Timing diagram on maximum model A1 to A7 l At writing E A8/D 8 to A15/D 15 A16/D 0, D1 to D7 A D 215 (min.) 90 (max.) 62 (min.) AC32 (tPHL ) tsu(D) ≥ 40 (Un it : ns) W AC32 (tPLH ) A8/D 8 to A15/D 15 A16/D 0 External memory data output A D l At reading E 215 (min.) 62 (min.) 10 (max.) 95 (min.) ta(AD), ta(CE) tsu(P1D/P2D-E) ≥ 80 OE AC32 (tPLH ) A1 to A7 A CE, S1 ta(OE) AC573 (tPHL ) CE AC32 (tPHL ) ROM : 25 (max.) RAM : 35 (max.) 82 (min.) ta(S1) AC04 (tPHL ) AC573 (tPHL ) + AC04 (tPHL ) A A A A A

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18.6.5 Ready generating circuit example

When validating “wait” only for a certain area (for example, ROM area) in Figures 18.6.3 to 18.6.8, use the ready function. Figure 18.6.9 shows a ready generating circuit example. Fig. 18.6.9 Ready generating circuit example M37733MHLXXXHP CS 1 A8 to A23 (D0 to D15) A0 to A7 AC74 D T Q RDY E AC32 AC32 AC04 Address bus Data bus Address latch circuit Address decode circuit CS 2 Wait generated by the ready function is inserted only to an area where accessed by Signal CS2. Circuit conditions : f(XIN) £ 10.8 MHz, no wait, E CS 2 Q RDY tctd(E- 1) tsu(RDY- 1) Propagation delay time of AC32 (Max. : 11.9 ns) ] Condition to satisfy the relationship of tsu(RDY- 1) ‡ 80 ns in the left timing chart is t Accordingly, when f(XIN) £ 10.8 MHz, this example satisfies the relationship of tsu(RDY- 1) ‡ 80 ns. : Wait generated by the ready function 1 = , , , or 2 f(XIN) f(XIN) f(XIN) f(XCIN) VCC = 3.0 to 5.5 V c ‡ 91.9 ns.

19.1 EPROM mode

19.2 Usage precaution

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In the PROM version, programming to the built-in PROM is possible by using a general-purpose PROM programmer and a programming adapter which is suitable for the microcomputer. The built-in PROM version has the following two types : l One Time PROM version Programming to the PROM is possible once. This version is suitable for a small quantity of and various production. l EPROM version Programming to the PROM is possible repeatedly because a program can be erased by exposing the erase window on the top of the package to an ultraviolet light source. This version can be used only for program development (Evaluation only). The built-in PROM version differs from the mask ROM version in the following:

• The built-in PROM version has a built-in PROM.
• Bit 3 of the oscillation circuit control register 1 (address 6F16) of the built-in PROM version is “1” at reset.
• Bit 3 of the oscillation circuit control register 1 (address 6F16) of the built-in PROM version must be fixed to “1.”

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The built-in PROM version has the following two modes : l Normal operating mode The microcomputer has the same function as the mask ROM version. l EPROM mode Programming to the built-in PROM can be performed. The built-in PROM version enters this mode when “L” level is input to pin RESET .

19.1.1 Pin description

Table 19.1.1 lists the pin description in the EPROM mode. In the normal operating mode, each pin has the same function as the mask ROM version. Functions Apply 5 V ± 10% to pin Vcc, and 0 V to pin Vss. Apply VPP level when programming or verifying. Connect to pin Vss. Connect pins XIN and XOUT via a ceramic resonator or a quartz-crystal oscillator. When an external clock is used, the clock should be input to pin XIN, and pin XOUT should be left open. Open. Connect pin AVcc to pin Vcc and pin AVss to pin Vss. Connect to pin Vss. Input pins for low-order 8 bits (A 0–A 7) of address Input pins for middle-order 8 bits (A8–A15) of address I/O pins for 8-bit data (D0–D 7) Input pin for the most significant bit (A16) address Connect to pin Vss. Connect to pin Vss. P5 0, P51 and P52 respectively function as PGM , OE and CE input pins. Connect P53–P5 6 to pin Vcc, and P57 to pin Vss. Connect to pin Vss. Connect to pin Vss. Connect to pin Vss. Pin Vcc, Vss CNVss BYTE RESET X IN X OUT E AVcc, AVss V REF P0 0–P0 7 P1 0–P1 7 P2 0–P2 7 P3 0 P3 1–P3 3 P4 0–P4 7 P5 0–P5 7 P6 0–P6 7 P7 0–P7 7 P8 0–P8 7 Input/Output Input Input Input Output Output Input Input Input I/O Input Input Input Input Input Input Input Name Power source input V PP input Reset input Clock input Clock output Enable output Analog power source input Reference voltage input Address input (A 0–A 7) Address input (A8–A 15) Data input/output (D0–D 7) Address input (A16) Input port P3 Input port P4 Control input Input port P6 Input port P7 Input port P8 Table 19.1.1 Pin description in EPROM mode

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16–1FFFF 16 0200016–1FFFF 16 0100016–0FFFF 16 0800016–0FFFF 16 0C000 16–0FFFF 16 0800016–1FFFF 16 V PP Vss A 0–A 16 D 0–D 7 CE OE PGM Vcc V PP Vss Address input Data I/O CE OE PGM Table 19.1.2 Pin correspondence in EPROM mode Vcc CNVss, BYTE Vss P0, P1, P30 P52 P51 P50 Table 19.1.3 Programmable area Memory allocation selection bits Programmable area M37733EHBFP (M37733EHBXXXFP) M37733EHBFS M37733EHLHP (M37733EHLXXXHP)

19.1.2 Reading/Programming from and to built-in PROM

In the EPROM mode, ports P0, P1, P2, P30, P50, P51, P52 and pins CNVss and BYTE are EPROM pins (M5M27C101K equivalent), and reading/programming from and to the built-in PROM can be performed in the same manner as for M5M27C101K. However, there is no device identification code. Accordingly, programming conditions must be set carefully. Furthermore, specify addresses from 01000 16 to 1FFFF16 as the programmable area. Table 19.1.2 lists the pin correspondence in the EPROM mode and Table 19.1.3 lists the programmable Note: When changing the allocation of the internal memory by the memory allocation selection bits (Refer

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Fig. 19.1.1 Pin connections in EPROM mode (M37733EHBFP) P82/RxD0/CLKS 0 P81/CLK0 P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P41/RDY

64 P84/CTS1/RTS1

63 P85/CLK1

62 P86/RxD1

61 P87/TxD1

60 P00/A0

59 P01/A1

58 P02/A2

57 P03/A3

56 P04/A4

55 P05/A5

54 P06/A6

53 P07/A7

52 P10/A8/D8

51 P11/A9/D9

50 P12/A10/D10

49 P13/A11/D11

48 P14/A12/D12

47 P15/A13/D13

46 P16/A14/D14

45 P17/A15/D15

44 P20/A16/D0

43 P21/A17/D1

42 P22/A18/D2

41 P23/A19/D3

E VSS P33/HLDA P32/ALE P31/BHE P30/R/W P27/A23/D7 P24/A20/D4 M37733EHBFP Outline 80P6N-A * : Connect these pins to a resonator or an oscillator. A10 A11 A12 A13 A14 D 0 D 1 D 2 D 3 OE CE VPP D 4 D 5 D 6 D 7 VSS : EPROM pin. A15 PGM VCC P70/AN0 P67/TB2IN/ SUB A16

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Fig. 19.1.2 Pin connections in EPROM mode (M37733EHLHP) XOUT P32/ALE P30/R/W P31/BHE D 2 A14 Outline 80P6D-A P86/RXD 1 P87/TXD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 75 74 73 72 71 69 68 67 66 657080 79 78 77 76 64 63 62 61 3026 27 28 29 31 32 33 34 35 3621 2322 24 25 37 38 39 40 P42/ 1 P41/RDY P40/HOLD BYTE CNV SS RESET XIN E VSS P33/HLDA P27/A23/D7 P26/A22/D6 P25/A21/D5 P24/A20/D4 P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P85/CLK1 P84/CTS1/RTS1 P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 P70/AN0 P67/TB2IN/ SUB M37733EHLHP P43 P44 P45 P46 P23/A19/D3 P22/A18/D2 VCC A15 A13 A12 A10 A11 D 0 D 1 D 7 D 6 D 5 D 4 D 3 VPP VSS * : Connect these pins to a resonator or an oscillator. : EPROM pin. CE PGM OE A16

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(1) Read When pins CE and OE are set to “L” level and an address is input to address input pins, the contents___ ___ of the built-in PROM can be read from data I/O pins; When pins CE and OE are set to “H” level, data I/O pins enter the floating state. (2) Program When pin CE is set to “L” level, pin OE is set to “H” level, and VPP level is applied to pin VPP , programming to the PROM can be performed. Input an address to address input pins and supply data to be programmed to data I/O pins in 8-bit ____ parallel. On this condition, when pin PGM is set to “L” level, the data is programmed into the built-in PROM. (3) Erase (Available only in EPROM version) The contents of the built-in PROM is erased by exposing the glass window on top of the package to an ultraviolet light which has a wave length of 2537 Angstrom. The light must be 15 W•s/cm 2 or more. Table 19.1.4 I/O signals in EPROM mode Pin name Data I/O Output Floating Floating Input Output Floating VIL VIL V IH VIL VIL V IH V IL V IH X V IH V IL V IH X X X VIL V IH V IH 5 V 5 V 5 V 12.5 V 12.5 V 12.5 V VccV PPPGMCE 5 V 5 V 5 V 6 V 6 V 6 V OE X : It may be VIL or VIH. Mode Read-out Output disable Program Program verify Program disable

7733 Group User’s Manual19-8

19.1.3 Programming algorithm to built-in PROM

\` After applying a programming pulse of 0.2 ms, check whether data can be read or not. ´ If the data cannot be read, apply a programming pulse of 0.2 ms again. ˆ Repeat the procedure, which consists of applying a programming pulse of 0.2 ms and read check, until the data can be read. Additionally, record the number of pulses applied ( X ) before the data was read. ˜ Apply X pulses (0.2 5 X ms) (described in ˆ ) as additional programming pulses. ¯ When this procedure ( À to ˜ ) is complete, increment the address and repeat the above procedure until the last address is reached. ˘ After programming to the last address, read data when Vcc = VPP = 5 V (or Vcc = VPP = 5.5 V). Figure 19.1.3 shows the programming algorithm flow chart. Fig. 19.1.3 Programming algorithm flow chart VERIFY ALL BYTE START ADDR = FIRST LOCATION X = 0 VCC = VPP = *5.0 V DEVICE FAILED DEVICE PASSED VCC = 6.0 V VPP = 12.5 V X = X + 1 X = 25? VERIFY BYTE INCREMENT ADDR VERIFY BYTE DEVICE FAILED LAST ADDR? FAIL YES NO PASS PASS YES FAIL PASS NO FAIL PROGRAM ONE PULSE OF 0.2 ms PROGRAM PULSE OF 0.2 x ms DURATION * : 4.5 V ≤ VCC = VPP ≤ 5.5 V

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AC electrical characteristics (Ta = 25 ± 5 °C, Vcc = 6 V ± 0.25 V, VPP = 12.5 ± 0.3 V, unless otherwise noted)

19.1.4 Electrical characteristics of programming algorithm

Max. 130 0.21 5.25 150 Typ. 0.2 Min. Limits UnitParameter µs µs µs µs µs ns µs µs ms ms µs ns Address setup time OE setup time Data setup time Address hold time Data hold time ___ Output floating delay time after OE Vcc setup time V PP setup time ____ PGM pulse width ____ Additional PGM pulse width ___ CE setup time ___ Data delay time after OE tAS tOES tDS tAH tDH tDFP tVCS tVPS tPW tOPW tCES tOE Symbol 0.19 0.19 Switching characteristics measuring conditions l Input voltage : VIL = 0.45 V, VIH = 2.4 V l Input signal rise/fall time (10%–90%) : £ 20 ns l Reference voltage in timing measurement : Input/output “L” = 0.8 V, “H” = 2 V tVCS tVPS tDS tDH tDFP tAS tAH VerifyProgram Data set Data output valid VIH VIL VIH/VOH VIL/VOL VPP VCC VCC + 1 VCC Address Data V PP V CC tOES tOE tOPW tPW VIH VIL VIH VIL PGM OE VIH VIL tCES CE Programming timing diagram

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[Precautions on all built-in PROM versions] When programming to the built-in PROM, high voltage is required. Accordingly, be careful not to apply excessive voltage to the microcomputer. Furthermore, be especially careful during power-on. [Precautions on One Time PROM version] One Time PROM versions shipped in blank (M37733EHBFP, M37733EHLHP), of which built-in PROMs are programmed by users, are also provided. For these microcomputers, a programming test and screening are not performed in the assembly process and the following processes. To improve their reliability after programming, we recommend to program and test as the flow shown in Figure 19.2.1 before use. Fig. 19.2.1 Programming and test flow for One Time PROM version [Precautions on EPROM version] l Cover the transparent glass window with a shield or others during the read mode because exposing to sun light or fluorescent lamp can cause erasing the programmed data. A shield to cover the transparent window is available from Mitsubishi Electric Corporation. Be careful that the shield does not touch the EPROM lead pins. l Clean the transparent glass before erasing. There is a possibility that fingers’ flat and paste disturb the passage of ultraviolet rays and affect badly the erasure capability. l The EPROM version is a tool only for program development (Evaluation only), and do not use it for the mass product run. Programming with PROM programmer Screening (Note) (Leave at 150 °C for 40 hours) Verify test with PROM programmer Function check in target device Note: Never expose to 150 °C exceeding 100 hours.

20.1 Performance overview

20.2 Pin configuration

20.3 Pin description

20.4 Block description

20.5 Memory allocation

20.6 Processor modes

20.7 Timer A

20.8 Reset

20.9 Electrical characteristics

20.10 Low voltage version

7733 Group User’s Manual20–2

The external ROM version can operate only in the microprocessor mode. Functions of the external ROM version differ from those of the mask ROM version in the following. Therefore, only the differences are described in this chapter:

• Memory allocation
• Operation is available only in the microprocessor mode
• The ROM area change function is not available.
• Timer A has the pulse output port mode.
• Power source current and Current consumption For the other functions, refer to chapters “2. CENTRAL PROCESSING UNIT (CPU)” to “18. LOW VOLTAGE VERSION.” h For product expansion information of the 7733 Group, contact the appropriate office, as listed in “CONTACT ADDRESSES FOR FURTHER INFORMATION.”

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Performance overview of the external ROM version differs from that of the mask ROM version in the following: memory size and current consumption. For the other items, refer to section “1.1 Overview.” Table 20.1.1 lists the M37733S4BFP’s performance overview. Table 20.1.1 M37733S4BFP’s performance overview Performance 2048 bytes 57 mW (When f(X IN) = 25-MHz external square wave input, Vcc = 5 V, and the main clock is the system clock, Typ.) 300 µW (When f(X CIN ) = 32 kHz, Vcc = 5 V, the sub clock is the system clock, and the main clock is stopped, Typ.) Items Memory size Current consumption RAM

7733 Group User’s Manual20–4

Figure 20.2.1 shows the M37733S4BFP pin configuration. Note: For the low voltage version, refer to section “20.10 Low voltage version.” Fig. 20.2.1 M37733S4BFP pin configuration (Top view) 25 2726 28 3429 30 31 32 33 35 36 37 38 39 40 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3/RTP13 P56/TA3OUT /KI3/RTP12 P55/TA2IN/KI1/RTP11 P54/TA2OUT /KI0/RTP10 P53/TA1IN/RTP03 P52/TA1OUT /RTP02 P51/TA0IN/RTP01 P50/TA0OUT /RTP00 HOLD BYTE CNV SS RESET XIN XOUT E Vss (P33)HLDA (P32)ALE (P31)BHE (P30)R/W (P27)A23/D7 (P26)A22/D6 (P25)A21/D5 (P24)A20/D4 P74/AN4/RXD 2 P75/AN5/ADTRG /TXD 2 P76/AN6/XCOUT P77/AN7/XCIN VSS AV SS VREF AV CC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD 0/CLKS0 P83/TXD 0 P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 A0(P00) A1(P01) A2(P02) A3(P03) A4(P04) A5(P05) A6(P06) A7(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) 80 79 78 77 76 75 74 73 72 71 69 68 67 66 6570 Outline 80P6N-A A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A16/D0(P20) A17/D1(P21) A18/D2(P22) A19/D3(P23) M37733S4BFP 24RDY P47 P46 P45 P44 P43 (P42)/ 1 P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin’s level can be fixed in the stop or wait mode.

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Table 20.3.1 Pin description (1) Pin Vcc, Vss CNVss RESET X IN X OUT E BYTE AVcc AVss V REF A 0 (P00)– A 7 (P07) A 8/D8 (P10)–A15/ D 15 (P17) A 16/D0 (P2 0)–A23/ D 7 (P27) Input/Output Input Input Input Output Output Input Input Output I/O I/O Functions To pin Vcc, apply 5 V±10% (When the main clock is the system clock) or 2.7 V to 5.5 V (When the sub- clock is the system clock). To pin Vss, apply 0 V. Connect to pin Vcc. The microcomputer is reset when “L” level is input to this pin. Pins X IN and X OUT are the I/O pins of the clock generating circuit, respectively. Connect these pins via a ceramic resonator or a quartz-crystal oscillator. When an external clock is used, the clock should be input to pin X IN, and pin XOUT should be left open. This pin outputs signal E . When E ’s level is “L,” the microcomputer reads data and instruction codes or writes data. Also, output of signal E can be stopped by software. Input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. A 16-bit width is selected when the level is “L,” and an 8-bit width is selected when the level is “H.” Power source input for the A-D converter. Connect to pin Vcc. Power source input for the A-D converter. Connect to pin Vss. This is the reference voltage input pin for the A-D converter. Address’s low-order 8 bits (A 0–A 7) are output. l When the external data bus width = 8 bits (Pin BYTE is at “H” level) Address’s middle-order 8 bits (A 8–A 15) are output. l When the external bus width = 16 bits (Pin BYTE is at “L” level) Input/Output of data (D 8–D 15) and output of address’s middle-order 8 bits (A8–A 15) are performed with the time sharing method. Input/Output of data (D0–D 7) and output of address’s high-order 8 bits (A16–A 23) are performed with the time sharing method. Name Power source input CNVss Reset input Clock input Clock output Enable output External data bus width selection input Analog power source input Reference voltage input Address (low order) output Address (middle order) output/Data (high order) I/O Address (high order) output/ Data (low-order) I/O

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Table 20.3.2 Pin description (2) Input/Output Output Input Input Output I/O I/O I/O I/O I/O Functions These pins respectively output signals R/W , BHE , ALE, and HLDA . l Signal R/W This signal indicates the data bus state. When this signal level is “H,” a data bus is in the read state. When this signal level is “L,” a data bus is in the write state. ____ l Signal BHE This signal’s level is “L” when the microcomputer accesses an odd address. l Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. l Signal HLDA This signal informs the external whether the microcomputer enters the Hold state or not. In Hold state, pin HLDA outputs “L” level. The microcomputer is in Hold state while pin HOLD ’s ____ input level is “L” and is in Ready state while pin RDY ’s input level is “L.” Clock φ1 is output from pin φ1. P43–P4 7 function as I/ O ports with the same functions as port P5. P5 is a CMOS 8-bit I/O port and has an I/O direction register. Each pin can be programmed as an input port or an output port. And it can be programmed as I/O pins for timers A0–A3 and input pins ( KI0–KI3) for the key input interrupt. P6 is an 8-bit I/O port with the same function as port P5 and can be programmed as I/O pins for timer A4, external interrupt input pins, and input pins for timers B0–B2. P6 7 also functions as an output pin for the sub clock (φSUB ). P7 is an 8-bit I/O port with the same function as port P5 and can be programmed as analog input pins for the A-D converter. P7 6 and P77 can be programmed as I/O pins (XCOUT , XCIN ) for the sub-clock (32 kHz) oscillation circuit. When using P76 and P7 7 as pins X COUT and X CIN , connect a quartz-crystal oscillator between them. P72–P7 5 also function as UART2’s I/O pins. P8 is an 8-bit I/O port with the same function as port P5 and can be programmed as serial I/O’s I/O pins. Name Read write output, Byte high enable output, Address latch enable output, Hold acknowledge output Hold request, Ready, Clock output, I/O port P4 I/O port P5 I/O port P6 I/O port P7 I/O port P8 Pin R/W (P30), ____ BHE (P31), ALE (P3 2), HLDA (P33) HOLD , ____ RDY , φ1(P42), P4 3–P4 7 P5 0–P5 7 P6 0–P6 7 P7 0–P7 7 P8 0–P8 7

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Figure 20.4.1 shows the M37733S4BFP block diagram. Fig.20.4.1 M37733S4BFP block diagram Low-order address (8) XIN XOUT E RESET VREF CNVss BYTE UART1 (9) UART0 (9) AV SS (0V) AV CC (0V) VSSVCC UART2 (9) XCIN XCOUT

1 RDY HOLD HLDA ALE BHE R/W

Data Buffer DBH (8) Data Buffer DBL(8) Instruction Queue Buffer Q0(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q2(8) Data Bank Register DT(8) Program Counter PC(16) Incrementer/Decrementer(24) Program Bank Register PG(8) Input Buffer Register IB(16) Direct Page Register DPR(16) Stack Pointer S(16) Index Register Y(16) Index Register X(16) Anthmetic Logic Unit(16) Accumulator B(16) Accumulator A(16) Instruction Register(8) Data Bus(Even) Data Bus(Odd) Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Address bus Watchdog Timer External data bus width selection input Timer TB1(16) Timer TB2(16) Address bus/ Data bus Timer TB0(16) Timer TA1(16) Timer TA2(16) Timer TA3(16) Timer TA4(16) Timer TA0(16) RAM 2048 bytes Central Processing Unit (CPU) Incrementer(24) Program Address Register PA(24) Data Address Register DA(24) Address Bus Bus Interface Unit (BIU) Processor Status Register PS(11) A-D Converter(10) High-order • Middle-order address/Data (16)

7733 Group User’s Manual20–8

The internal area’s memory allocation is described below. For details, refer to section “2.4 Memory allocation.” For the external area, refer to section “20.6 Processor modes.” Figure 20.5.1 shows the M37733S4BFP’s memory map and Figure 20.5.2 shows the SFR area’s memory map.

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Fig. 20.5.1 M37733S4BFP’s memory map 01FFFF 16 FF0000 16 00000016 00007F16 00008016 00087F16 FFFFFF 16 00088016 00FFFF 16 01000016 00000016 00007F16 Timer A4 00FFD6 16 00FFFE 16 SFR area Internal RAM area 2048 bytes Bank 016 Bank 116 Bank FF16 A-D/UART2 trans./rece. UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A3 Timer A2 Timer A1 Timer A0 INT 2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide RESET Interrupt vector table Peripheral device control registers (SFR) UART1 transmission UART0 transmission Refer to Figure 20.5.2. : External memory area For the 7733 Group’s microcomputers other than the M37733S4BFP, refer to section “Appendix 1. 7733 Group memory allocation .” h

7733 Group User’s Manual20–10

Fig. 20.5.2 SFR area’s memory map UART 0 transmission interrupt control register UART 1 transmission interrupt control register INT2/Key input interrupt control register Port P1 direction register (Note 3) UART 0 transmit/receive mode register UART 0 baud rate register (BRG0) UART 0 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 0 transmission buffer register UART 1 transmit/receive control register 0 UART 1 transmit/receive mode register UART 1 baud rate register (BRG1) UART 1 transmit/receive control register 1 UART 0 receive buffer register UART 1 transmission buffer register UART 1 receive buffer register Port P0 register (Note 3) A-D register 0 A-D register 2 Port P1 register (Note 3) Port P0 direction register (Note 3) Port P2 register (Note 3) Port P3 register (Note 3) Port P4 register (Note 3) Port P5 register Port P6 register Port P7 register Port P8 register A-D control register 0 A-D control register 1 A-D register 1 A-D register 3 A-D register 4 A-D register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001A 00001B 00001C 00001D 00001E 00001F 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002A 00002B 00002C 00002D 00002E 00002F 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003A 00003B 00003C 00003D 00003E 00003F 00000B 00000C 00000D 00000E 00000F 00000A 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F 00004B 00004C 00004D 00004E 00004F 00004A 000044 Address (Hexadecimal notation) Address (Hexadecimal notation) Timer A1 register Timer A4 register Timer A2 register Timer A3 register Timer B0 register Timer B1 register Timer B2 register Count start flag One-shot start flag Up-down flag Timer A0 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Watchdog timer register Watchdog timer frequency selection flag A-D/UART2 trans./rece. interrupt control register UART 0 receive interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register Processor mode register 1 Oscillation circuit control register 1 Serial transmit control register Port function control register Oscillation circuit control register 0 Timer A3 mode register Port P2 direction register (Note 3) Port P3 direction register (Note 3) Port P4 direction register (Note 3) Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Pulse output data register 1 (Note 1) A-D register 6 A-D register 7 UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Waveform output mode register (Note 1) Notes 1: Memory map of the M37733S4BFP differs from that of the M37733MHBXXXFP in addresses 1C 16, 1D16, 6216, and 6316. 2: Writing to the reserved area is disabled. 3: These registers are used when outputting an arbitrary data in the stop or wait mode. Pulse output data register 0 (Note 1) Reserved area (Notes 1, 2) A-D control register 1

7733 Group User’s Manual 20–11

Fig. 20.6.1 Structure of processor mode register 0 Bit Bit name Functions At reset RW Processor mode bits (Note) Wait bit Software reset bit Interrupt priority detection time selection bits Must be fixed to “0.” This bit is ignored. 0 0: Do not select. 0 1: Do not select. 1 0: Microprocessor mode 1 1: Do not select. Microcomputer is reset by setting this bit to “1.” This bit is “0” at reading. 0 0: 7 cycles of 0 1: 4 cycles of 1 0: 2 cycles of 1 1: Do not select. b1 b0 b5 b4 Processor mode register 0 (address 5E16) represents that bits 2 to 7 are not used for setting the processor mode. 5 : It may be “0” or “1.” Note: Fix the processor mode bits to “102.” b1 b0b2b3b4b5b6b7 RW RW RW WO RW RW RW RW 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. The M37733S4BFP can operate only in the microprocessor mode. For the processor mode, refer to the description of the microprocessor mode in section “2.5 Processor modes.” Also, be sure to set as follows:

• Connect pin CNVss to Vcc.
• Fix the processor mode bits to “10 2.“ Figure 20.6.1 shows the structure of the processor mode register 0.

7733 Group User’s Manual20–12

Timer A is used mainly for output to the external. It consists of five counters (Timers A0 to A4) each equipped with a 16-bit reload function. Timers A0 to A4 operate independently of each other.

20.7.1 Overview

In the external ROM version, timer A has five operating modes listed below. In operating modes À to ˆ , the external ROM version operates the same as the mask ROM and PROM versions. Operating mode ˜ is described in this chapter. À Timer mode \` Event counter mode ´ One shot pulse mode ˆ Pulse width modulation (PWM) mode ˜ Pulse output mode Refer to chapter “6. TIMER A.”

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20.7.2 Pulse output port mode

(1) Overview In the pulse output mode, there are two types of pulse output port: RTP0 controlled by timer A0 and RTP1 controlled by timer A2. When an underflow occurs in timer A0 or A2, the contents of the pulse output data register 0 or 1 is output from the corresponding pulse output pins. Also, the pulse width can be modulated by timer A as follows: use timer A1 for RTP0 and use timer A3 for RTP1. In addition, RTP0 can reverse the polarity of the contents of the pulse output data register 0 by software and outputs it. Table 20.7.1 lists the specifications of the pulse output mode. Table 20.7.1 Specifications of pulse output port mode Pulse output port Control timer Pulse output pins Register where pulse data is set Pulse width modulation Output level reverse function RTP0 Timer A0 RTP0 0–RTP0 3 (Ports P50–P5 3) Pulse output data register 0 Possible (Timer A1 is used) Available RTP1 Timer A2 RTP1 0–RTP1 3 (Ports P54–P5 7) Pulse output data register 1 Possible (Timer A3 is used) Not available

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(2) Block description structures of registers related to the pulse output port mode. Also, Figure 20.7.2 shows the structure of the port P5 output control circuit. Fig. 20.7.1 Block diagram for pulse output port mode D Q D Q D Q D Q T D Q D Q D QT Timer A0 D Q 45Pulse width modulation selection bits (Bits 4, 5 at address 6216) Pulse width modulation output by timer A3 Pulse width modulation output by timer A1 Timer A2 Pulse output data register 1 (Address 1C16) RTP1 3(P57/TA3IN) Polarity selection bit (Bit 3 at address 6216) Pulse output data register 0 (Address 1D16) Data bus (even) Data bus (odd)b3 RTP1 2(P56/TA3OUT ) RTP1 1(P55/TA2IN) RTP1 0(P54/TA2OUT ) RTP0 3(P53/TA1IN) RTP0 1(P51/TA0IN) RTP0 2(P52/TA1OUT ) RTP0 0(P50/TA0OUT )

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Fig. 20.7.2 Port P5 output control circuit l P50/TA0OUT /RTP00, P52/TA1OUT /RTP02, P54/TA2OUT /RTP10, P56/TA3OUT /RTP12 Direction register Port latch Pulse output Timer A output Bit 2 of the timer Ai mode register (addresses 5616 to 5916) (Note 2) (Whether to output a pulse or not is selected.) Bits 0 and 1 of the waveform output mode register (address 62 16) (Note 1) (RTP1, RTP0 selected) Input l P51/TA0IN/RTP01, P53/TA1IN/RTP03, P55/TA2IN/RTP11, P57/TA3IN/RTP13 Bits 0 and 1 of the waveform output mode register (Note 1) (RTP1, RTP0 selected) Input Direction register Port latch Pulse output Notes 1: Ports P50 to P53 correspond to bit 1. Ports P54 to P57 correspond to bit 0. 2: Bit 2 of the timer Ai mode register which corresponds to each port “1” “1” “0” “0” “1” “1” “0” “0” “1” “0” “1” “0”

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Fig. 20.7.3 Structures of timer A0, A2 mode registers and timer A0, A2 registers in pulse output port mode X: It may be either “0” or “1.” Timer A0 mode register (address 5616) 0 0: Timer mode 1: Pulse is output. Must be fixed to “1.” 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b66 Count source selection bits b1 b0 b4 b3 5 Must be fixed to “0” in the timer mode. 00 0 0 0: 0 1: Bit At reset RW b7 b0 b7 b0 (b15) (b8) Timer A0 register (addresses 4716, 4616) Timer A2 register (addresses 4B16, 4A16) FunctionsBit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Undefined RW RW RW RW RW RW RW RW RW Timer A2 mode register (address 5816) No gate function Bit 4 must be fixed to “0.” 10 5

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Fig. 20.7.4 Structures of timer A1, A3 mode registers and timer A1, A3 registers in pulse output port mode (when pulse width modulation function is used) b7 b6 b5 b4 b3 b2 b1 b0 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Note: Fix bit 2 to “1” and bit 4 to “0” even when not using the pulse width modulation function. X: It may be “0” or “1.” At reset RW 2 Must be fixed to “1” in the PWM mode. (Note) 1 1: PWM mode b1 b0 b4 b3 5 16/8-bit PWM mode selection bit Writing “1” to the count start flag (Pin TAiIN functions as a programmable I/O port.) Bit 0: The counter operates as a 16-bit pulse width modulator. 1: The counter operates as an 8-bit pulse width modulator. n When operating as an 8-bit pulse width modulator (b15) b7 b0 b7 b0 (b8) Timer A1 register (addresses 4916, 4816) Timer A3 register (addresses 4D16, 4C16) FunctionsBit At reset RW 7 to 0 Values 0016 to FF16 can be set. Assuming that the set value = m, period of the PWM pulse which is output from pin TA1 OUT or TA3OUT is (m + 1)(28 – 1)/fi. fi: Frequency of the count source (f2, f16, f64, or f512) 15 to 8Values 0016 to FE16 can be set. Assuming that the set value = n, “H” level width of the PWM pulse which is output from pin TA1 OUT or TA3OUT is n(m +1)/fi. Undefined Undefined b7 b0 b7 b0 Timer A1 register (addresses 4916, 4816) Timer A3 register (addresses 4D16, 4C16) FunctionsBit At reset RW 15 to 0Values 000016 to FFFE16 can be set. Assuming that the set value = n, “H” level width of the PWM pulse which is output from pin TA1OUT or TA3OUT is n/fi. Undefined fi: Frequency of the count source (f2, f16, f64, or f512) n When operating as a 16-bit pulse width modulator (b15) (b8) RW RW RW RW RW RW RW RW WO WO WO Timer A1 mode register (address 5716) Timer A3 mode register (address 5916)0 5 (Note) 0 0: 0 1:

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7 Must be fixed to “0.” 6 Not implemented. This bit is “0” at reading. At reset Undefined Undefined RW

3 Polarity selection bit

2 Not implemented. This bit is “0” at reading.

0 Waveform output selection

0 0: Port P5 is a programmable I/O port. 0 1: RTP1 is selected. 1 0: RTP0 is selected. 1 1: RTP1 and RTP0 are selected. b1 b0

5 Pulse width modulation

0: Positive polarity 1: Negative polarity Bit 0: Not modulated 1: Modulated

4 Pulse width modulation

Waveform output mode register (address 6216)0 (Valid only for RTP0) 0: Not modulated 1: Modulated Fig. 20.7.5 Structures of waveform output mode register

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Fig. 20.7.6 Structures of pulse output data registers 0, 1 b7 b6 b5 b4 b3 b2 b1 b0 4 to 7 Not implemented. At reset Undefined Undefined Undefined Undefined Undefined RW

1 RTP11 output data bit

0 RTP10 output data bit

3 RTP13 output data bit

2 RTP12 output data bit

Pulse output data register 1 (address 1C16) 0: “L” level is output. 1: “H” level is output. Note: Use the LDM and STA instructions to set bits 0 to 3. b7 b6 b5 b4 b3 b2 b1 b0 4 to 7 Not implemented. At reset Undefined Undefined Undefined Undefined Undefined RW

1 RTP01 output data bit

0 RTP00 output data bit

3 RTP03 output data bit

2 RTP02 output data bit

Pulse output data register 1 (address 1D16) When the positive polarity is selected, 0: “L” level is output. 1: “H” level is output. When the negative polarity is selected, 0: “H” level is output. 1: “L” level is output. Note: Use the LDM and STA instructions to set bits 0 to 3.

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(3) Initial setting example for registers related to pulse output port mode Figures 20.7.7 to 20.7.9 show an initial setting example for registers related to the pulse output port mode. Fig. 20.7.7 Initial setting example for registers related to pulse output port mode (1) b7 b0 Setting of the pulse output data register 0 and pulse output data register 1 Pulse output data register 0 (address 1D16) Continued to “Initial setting example for registers related to pulse output port mode (2)” on the next page RTP0 0 RTP0 1 RTP0 2 RTP0 3 Setting of the division ratio for timer A0 or timer A2 b7 b0 Values 000016 to FFFF16 (n) can be set. (b15) (b8) b7 b0 Timer A0 register (addresses 4716, 4616) Timer A2 register (addresses 4B16, 4A16) h Counter divides the count source by (n + 1). b7 b0 Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Setting of the timer A0 mode register or timer A2 mode register Timer A0 mode register (address 5616) Timer A2 mode register (address 5A16) b7 b6 X: It may be “0” or “1.” Output data is set to the corresponding bit. b7 b0 Pulse output data register 1 (address 1C16) RTP1 0 RTP1 1 RTP1 2 RTP1 3 Output data is set to the corresponding bit. 0 50

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Fig. 20.7.8 Initial setting example for registers related to pulse output port mode (2) Continued from "Initial setting example for registers related to pulse output port mode (1)" on the preceding page b7 b0 Timer A1 mode register (address 5716) Timer A3 mode register (address 5916) Setting of the timer A1 mode register or timer A3 mode register Setting of the PWM pulse’s period and “H” level width b7 b0 Values 000016 to FFFE16 (n) can be set. (b15) (b8) b7 b0 Timer A1 register (addresses 4916, 4816) Timer A3 register (addresses 4D16, 4C16) n When operating as a 16-bit pulse width modulator b7 b0 Values 0016 to FF16 (m) can be set. (b15) (b8) b7 b0 When operating as an 8-bit pulse width modulator Values 0016 to FE16 (n) can be set. h When operating as an 8-bit pulse width modulator Period = (m+1) (28 – 1)/fi “H” level width = n(m + 1)/fi fi: Frequency of the count source However, if n = 0016, the counter does not operate and pin TAiOUT outputs “L” level. At this time, no timer Ai request is generated. Timer A1 register (addresses 4916, 4816) Timer A3 register (addresses 4D16, 4C16) b7 b0 110 Setting of timers A1 and A3 Timer A1 mode register (address 5716) Timer A3 mode register (address 5916)1 b4 b3 Trigger selection bits

0 X: Count start flag

Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 X: It may be “0” or “1.” 16/8-bit PWM mode selection bit 0: The counter operates as a 16-bit pulse width modulator. 1: The counter operates as an 8-bit pulse width modulator. Continued to “Initial setting example for registers related to pulse output port mode (3)” on the next page When not modulating the pulse width When modulating the pulse width h When operating as a 16-bit pulse width modulator Period = (216 – 1)/fi “H” level width = n/fi fi: Frequency of the count source However, if n = 000016, the counter does not operate and pin TAiOUT outputs “L” level. At this time, no timer Ai request is generated. n

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Fig. 20.7.9 Initial setting example for registers related to pulse output port mode (3) Counting is started. Setting of the count start flag to “1” b7 b0 Count start flag (address 4016) Timer A0 count start flag Timer A1 count start flag (Note) Timer A2 count start flag Timer A3 count start flag (Note) Setting of the waveform output mode register b7 b0 Waveform output mode register (address 6216) Continued from "Initial setting example for registers related to pulse output port mode (2)" on the preceding page Setting of the interrupt priority level b7 b0 Timer A0 interrupt control register (address 7516) Timer A1 interrupt control register (address 7616) (Note) Timer A2 interrupt control register (address 7716) Timer A3 interrupt control register (address 7816) (Note) Interrupt priority level selection bits When using interrupts, one of levels 1-7 must be set. When disabling interrupts, level 0 must be set. Note: This is used when the pulse width is modulated. Waveform output selection bits 0 0: Port P5 is a programmable I/O port. 0 1: RTP1 is selected. 1 0: RTP0 is selected. 1 1: RTP0 and RTP1 are selected. b1 b0 Polarity selection bit (Affective only for RTP0) 0: Positive polarity 1: Negative polarity Pulse width modulation selection bit by timer A1 0: Not modulated 1: Modulated Pulse width modulation selection bit by timer A3 0: Not modulated 1: Modulated Note: This is used when the pulse width is modulated.

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(4) Operation in pulse output port mode The RTP0 operation when the pulse width is not modulated and the output level reverse function is not used is described below. Note: Description in ( ) is applied to the RTP1 operation. À When the count start flag of timer A0 (A2) is set to “1,” the counter starts counting of the count source. \ When an underflow occurs, data is output from each bit of RTP0 (RTP1) according to the setting of each bit of the pulse output data register 0 (1). This data is retained until the next underflow occurs. Timer A0 (A2) reloads the contents of the reload register and continues counting. ´ When the underflow occurs in \ , the timer A0 (A2) interrupt request bit is set to “1.” Then, the interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 20.7.10 shows an operation example of the pulse output port mode. Fig. 20.7.10 Operation example of pulse output port mode n Pulse output is started. 000016 FFFF 16 Timer A0 interrupt request bit Count start flag Undefined 3 C n, m :Reloaded value Counting is started. m Contents of pulse output data register 0 3 (00112) 6 (01102) C (11002) 9 (10012) Contents of RTP0 output Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Counter contents (Hex.) Note: The output level of the pulse output port is undefined from when the pulse output port mode is set until the first timer underflow occurs. Also, this output level is at a floating state after reset because the e pulse output port becomes the input port at that time. In the above example, in order to shorten this undefined period, the following procedure is performed: p

• A small value (n) is set to the timer counter as the initial value.
• After the first underflow occurs, the normal value (m) is set to the timer counter. t RTP0 3 output RTP0 2 output RTP0 1 output RTP0 0 output

7733 Group User’s Manual20–24

(5) Selectable functions The pulse width modulation function and the RTP0 output level reverse function are described below. l Pulse width modulation function The RTP0 operation when the positive polarity is selected is described below. Note: Description in ( ) is applied to the RTP1 operation. When “the pulse width modulation selection bit by timer A1(A3)” [bit 4(5)) at address 6216] is set to “1,” “modulated” (Refer to Figure 20.7.5.) is selected. The pulse width modulation is performed while pins RTP00 to RTP03 (RTP10 to RTP13) output “H” level. (Refer to section “6.6 Pulse width “modulated” is selected. Fig. 20.7.11 Operation example when “modulated” is selected n 000016 3 (00112) 6 (01102) C (11002) 9 (10012) FFFF 16 Timer A0 interrupt request bit n, m :Reloaded value m RTP0 3 output RTP0 2 output RTP0 1 output RTP0 0 output Timer A1 interrupt request bit Count start flag Counting is started. Contents of pulse output data register 0 Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Counter contents (Hex.) Pulse output is started. Note: The output level of the pulse output port is undefined from when the pulse output port mode is set until the first timer underflow occurs. Also, this output level is at a floating state after reset because the pulse output port becomes the input port at that time. In the above example, in order to shorten this undefined period, the following procedure is performed:

• A small value (n) is set to the timer counter as the initial value.
• After the first underflow occurs, the normal value (m) is set to the timer counter.

7733 Group User’s Manual 20–25

l Output level reverse function (only for RTP0) When the polarity selection bit (bit 3 at address 6216) is set to “1,” the output level can be reversed. In this case, when the RTP00 to RTP03 output data bits (bits 0 to 3 at address 1D16) are set to “0,” pins RTP00 to RTP03 output “H” level; when these bits are set to “1,” these pins output “L” level. When the output level reverse function and “modulated” are selected, the pulse width modulation is performed while pins RTP00 to RTP0 3 output “L” level. Figure 20.7.12 shows an operation example when the output level is reversed with “modulated” selected. Fig. 20.7.12 Operation example when RTP0 output level reverse function and “modulated” are selected [Precautions for pulse output port mode (pulse output function)] 1. In order to make ports P50 (RTP00), P52 (RTP02), P54 (RTP10), and P56 (RTP12) function as the pulse output pins, fix bit 2 of the timer A0 to A3 mode registers to “1.” l When using RTP0: Fix bit 2 of the timer A0 and A1 mode registers to “1.” l When using RTP1: Fix bit 2 of the timer A2 and A3 mode registers to “1.” 2. When the pulse width modulation function is not used, timers A1 and A3 can be used as timers which do not have I/O pins. In this case, fix bit 2 of the timer A1 and A3 mode registers to “1.” In addition, fix bits 0, 1, 4, and 5 of these registers to “0.” n 000016 3 (00112) 6(01102 ) C (11002) 9 (10012) FFFF 16 n, m :Reloaded value m Pulse output is started. RTP0 3 output RTP0 2 output RTP0 1 output RTP0 0 output Timer A1 interrupt request bit Count start flag Counting is started. Contents of pulse output data register 0 Timer A0 interrupt request bit Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Cleared to “0” when an interrupt request is accepted; otherwise, cleared by software. Counter contents (Hex.) Note: The output level of the pulse output port is undefined from when the pulse output port mode is set until the first timer underflow occurs. Also, this output level is at a floating state after reset because the t pulse output port becomes the input port at that time. In the above example, in order to shorten this undefined period, the following procedure is performed: g

• A small value (n) is set to the timer counter as the initial value.
• After the first underflow occurs, the normal value (m) is set to the timer counter. n

7733 Group User’s Manual20–26

The reset description of the external ROM version differs from that of the mask ROM version in the state immediately after reset. The state immediately after reset of the external ROM version differs from that of the mask ROM version in the following addresses: addresses 1C 16, 1D16, 6216 and 6316. Only the differences are described below. Figures 20.8.1 and 20.8.2 show the state of SFR area and internal RAM area immediately after reset (1) other descriptions, refer to chapter “13. RESET.”

7733 Group User’s Manual 20–27

Fig. 20.8.1 State of SFR area and internal RAM area immediately after reset (1) : “0” immediately after reset. : “1” immediately after reset. : Undefined immediately after reset. : Always “0” at reading 0 : Always undefined at reading : “0” immediately after reset. Must be fixed to “0.” 1016 1116 1216 1316 Port P8 direction register1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 016 116 216 316 416 516 616 716 816 916 B16 C 16 D 16 E16 F16 A16 Address Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register 0 A-D control register 1 Port P0 register Port P1 register Port P2 register Port P3 register Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Register name Access characteristics State immediately after reset RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0016 0016 0016 0016 0016 0000 00000000 0016 0 0 000 ? 00 11 b7 b0 b7 b0 : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Not implemented. It is impossible to read the bit state. The written value becomes invalid. RW RO WO n SFR area (addresses 016 to 7F16) RW 0016 h The contents of addresses 1C16 and 1D16 of the M37733S4BFP differ from those of the M37733MHBXXXFP. Abbreviations which represent access characteristics RW RW ?? 0 ? ??? 0016 Pulse output data register 1 Pulse output data register 0 WO WO h h

7733 Group User’s Manual20–28

Fig. 20.8.2 State of SFR area and internal RAM area immediately after reset (4) 7A16 7B16 7C 16 7D 16 7E16 RO UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address Oscillation circuit control register 0 Serial transmit control register A-D / UART 2 trans./rece. interrupt control register UART0 transmission interrupt control register UART1 transmission interrupt control register INT2/Key input interrupt control register Watchdog timer frequency selection flag Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT 0 interrupt control register Access characteristics RW( h 2) RW RW RW RW b7 b0 WO RW RW RW RW RW RW RW RW RW RW State immediately after reset 0 000 ? 0 ? (h 1) b7 b0 0 0 0 0 0 00 0 0000 00 0 000 Port function control register UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register RW RW WO RW RW RW 000 0 0 1 0000 0 000 0 00 0 0 00 0 0 00 0 0 000 0 0 0 0 0 000 0 00 0 0 00 0 00 0 000 00 0 000 A value of “FFF16” is set to the watchdog timer. (Refer to Chapter “10. WATCHDOG TIMER.” ) For access characteristics at address 6C16, also refer to Figure 14.3.2. The contents of addresses 6216 and 6316 of the M37733S4BFP differ from those of the M37733MHBXXXFP. Do not wirte to address 6316. n Internal RAM area (M37733S4BFP: addresses 8016 to FFF16) l At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. l At software reset...Retains the state immediately before reset. l When the stop or wait mode is terminated (when hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. RW h 3 000 h 1 h 2 h 3 h 4 Waveform output mode register h 3 (Reserved area) h 4 UART 2 transmit/receive mode register UART 2 baud rate register (BRG2) UART 2 transmission buffer register UART 2 transmit/receive control register 0 UART 2 transmit/receive control register 1 UART 2 receive buffer register Oscillation circuit control register 1 RW ? 00 0 0000 WO WO WO RWRO 1 000 RW RWRORO 000 0 00 10 RO 000 000 ? RW ?? 0 000 0 000 RWRWRW 0 ? 0 00 ?

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Except for “Icc,” the electrical characteristics of the M37733S4BFP are the same as those of the M37733MHBXXXFP in the microprocessor mode. For the others, refer to chapter “15. ELECTRICAL CHARACTERISTICS.”) ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Max. 22.8 3.2 120 Limits Vcc = 5 V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 12.5 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 5V, f(X IN) = 25 MHz (Square waveform), f(XCIN) : Stopped, in operating (Note 1) Vcc = 5V, f(X IN) = 25 MHz (Square waveform), f(XCIN) = 32.768 kHz, when the WIT instruction is executed (Note 2) Vcc = 5 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 5 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped Unit Measuring conditionsSymbol Parameter ICC Power source current Min. Typ. 11.4 1.6 mA mA µA µA µA µA µA External bus is operating, output pins are open, and the other pins are connected to Vss. Notes 1: This is applied when the main clock external input selection bit = “1,” the main clock division selection bit = “0,” and the signal output disable selection bit = “1.” 2: This is applied when the main clock external input selection bit = “1” and the system clock stop selection bit at wait state = “1.” 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the X COUT drivability selection bit = “0” and the system clock stop bit at wait state = “1.”

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Differences from the M37733S4BFP are mainly described below.

20.10.1 Performance overview

The performance overview of the low voltage version differs from that of the mask ROM version in the following: memory size and current consumption. For the other items, refer to section “18.1 Performance overview.” Table 20.10.1 shows the performance overview of the M37733S4LHP. Items Memory size Current consumption Performance 2048 bytes 10.8 mW (When f(XIN) = 12-MHz external square wave input, Vcc = 3 V, and the main clock is the system clock, Typ.) 120 µW (When f(XCIN) = 32 kHz, Vcc = 3 V, the sub clock is the system clock, and the main clock is stopped, Typ.) Table 20.10.1 M37733S4LHP’s performance overview RAM

7733 Group User’s Manual 20–31

20.10.2 Pin configuration

Figure 20.10.1 shows the M37733S4LHP pin configuration. Fig. 20.10.1 M37733S4LHP pin configuration (Top view) (P32)ALE (P31)BHE (P33)HLDA XOUT E CNV SS RESET HOLD P86/RxD 1 P87/TxD 1 A0(P00) A1(P01) A2(P02) A3(P03) A4(P04) A5(P05) A6(P06) A7(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A16/D0(P20) A17/D1(P21) 75 74 73 72 71 69 68 67 66 657080 79 78 77 76 64 63 62 61 3026 27 28 29 31 32 33 34 35 3621 2322 24 25 37 38 39 40 RDY (P42)/ 1 BYTE XIN VSS (P30)R/W (P27)A23/D7 (P26)/A22/D6 (P25)A21/D5 (P24)A20/D4 (P23)A19/D3 (P22)A18/D2 P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3/RTP13 P56/TA3OUT /KI2/RTP12 P55/TA2IN/KI1/RTP11 P54/TA2OUT /KI0/RTP10 P53/TA1IN/RTP03 P52/TA1OUT /RTP02 P51/TA0IN/RTP01 P50/TA0OUT /RTP00 P47 P85/CLK1 P84/CTS1/RTS1 P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 P70/AN0 P67/TB2IN/ SUB M37733S4LHP P43 P44 P45 P46 Outline 80P6D-A By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin’s level can be fixed in the stop or wait mode.

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Vcc = 5 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(X IN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(X IN) = 12 MHz (Square waveform), (f(f2) = 0.75 MHz), f(XCIN) : Stopped, in operating (Note 1) Vcc = 3 V, f(X IN) = 12 MHz (Square waveform), f(XCIN) = 32.768 kHz, when the WIT instruction is executed (Note 2) Vcc = 3 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 3 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Unit Measuring conditionsSymbol Parameter Icc Power source current Min. Typ. 5.4 3.6 0.5 mA mA mA µA µA µA µA µA Max. 10.8 7.2 1.0 Notes 1: This is applied when the main clock external input selection bit = “1,” the main clock division selection bit = “0,” and the signal output disable selection bit = “1.” 2: This is applied when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1.” 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1.” External bus is operating, output pins are open, and the other pins are connected to Vss.

20.10.3 Functional description

Except for the power-on reset conditions, the M37733S4LHP has the same functions as the M37733S4BFP. For the other functions, refer to chapters “2. CENTRAL PROCESSING UNIT (CPU)” to “14. CLOCK GENERATING CIRCUIT.” The power-on reset conditions of the M37733S4LHP are the same as those of the M37733MHLXXXHP. For details, refer to section “18.3 Functional description”.

20.10.4 Electrical characteristics

Except for “Icc,” the electrical characteristics of the M37733S4LHP are the same as those of the M37733MHLXXXHP in the microprocessor mode. For the others, refer to section “18.4 Electrical characteristics.”

Appendix 1. Memory allocation of 7733 Group Appendix 2. Memory allocation in SFR area Appendix 3. Control registers Appendix 4. Package outlines Appendix 5. Hexadecimal instruction code table Appendix 6. Machine instructions Appendix 7. Examples of handling unused pins Appendix 8.Countermeasure examples against noise Appendix 9. Q & A

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Appendix 1. Memory allocation of 7733 Group 1. M37733MHBXXXFP, M37733EHBXXXFP, M37733EHBFS, M37733MHLXXXHP, M37733EHLXXXHP Fig. 1 Memory allocation of M37733MHBXXXFP, M37733EHBXXXFP, M37733EHBFS, M37733MHLXXXHP, M37733EHLXXXHP (1) 01FFFF 16 FF000016 SFR area Internal RAM area 3968 bytes 00000016 00007F16 00008016 000FFF 16 FFFFFF 16 Bank 016 Bank 116 Bank FF16 Internal ROM area (4 Kbytes) 00FFFF 16 01000016 01FFFF 16 FFFFFF 16 00000016 00007F16 A-D/UART2 trans./rece. UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide RESET 00FFD6 16 00FFFE 16 Interrupt vector table SFR area Internal RAM area 3968 bytes Internal ROM area (SFR)

• Memory allocation selection bits (b2, b1, b0)=(0, 0, 0)
• ROM size: 124 Kbytes
• RAM size: 3.9 Kbytes
• Memory allocation selection bits (b2, b1, b0)=(0, 0, 1)
• ROM size: 120 Kbytes
• RAM size: 3.9 Kbytes UART1 transmission UART0 transmission : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section “2.5 Processor modes.”) 2 : Memory allocation of the 7735 Group differs from that of the 7733 Group. (For the memory allocation of the 7735 Group, refer to section “Appendix 1 in part 2.”) Refer to Appendix 2. 02FFFF 16 02000016 Appendix 1. Memory allocation of 7733 Group

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Appendix 1. Memory allocation of 7733 Group Fig. 2 Memory allocation of M37733MHBXXXFP, M37733EHBXXXFP, M37733EHBFS, M37733MHLXXXHP, M37733EHLXXXHP (2) 00FFFF 16 01000016 UART1 transmission 01FFFF 16 FF000016 00000016 00007F16 00008016 00087F16 FFFFFF 16 00100016 00000016 00007F16 00008016 00087F16 00FFFF 16 01000016 FFFFFF 16 00000016 RESET 00007F16 00FFD6 16 00FFFE 16 A-D/UART2 trans./rece. 02000016 00800016 SFR area Internal RAM area 2048 bytes Bank 016 Bank 116 Bank FF16 Internal ROM area (29.9 Kbytes) UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT 2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide Interrupt vector table SFR area Internal RAM area 2048 bytes Peripheral device control registers (SFR) : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode

• Memory allocation selection bits (b2, b1, b0)=(0, 1, 0)
• ROM size: 60 Kbytes
• RAM size: 2048 bytes
• Memory allocation selection bits (b2, b1, b0)=(1, 0, 0)
• ROM size: 32 Kbytes
• RAM size: 2048 bytes (1.9 Kbytes) UART0 transmission Refer to Appendix 2. 02FFFF 16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section “2.5 Processor modes.”) 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Internal ROM area

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Appendix 1. Memory allocation of 7733 Group Fig. 3 Memory allocation of M37733MHBXXXFP, M37733EHBXXXFP, M37733EHBFS, M37733MHLXXXHP, M37733EHLXXXHP (3) 00FFFF 16 01000016 02000016 UART1 transmission 01FFFF 16 FF000016 00000016 00007F16 00008016 00087F16 FFFFFF 16 00C000 16 00000016 00007F16 00008016 000FFF 16 00FFFF 16 01000016 FFFFFF 16 00000016 RESET 00007F16 00FFD6 16 00FFFE 16 A-D/UART2 trans./rece. 00800016 SFR area Internal RAM area 2048 bytes Bank 016 Bank 116 Bank FF16 Internal ROM area (28 Kbytes) UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT 2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide Interrupt vector table SFR area Internal RAM area 3968 bytes Peripheral device control registers (SFR) : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode

• Memory allocation selection bits (b2, b1, b0)=(1, 0, 1)
• ROM size: 16 Kbytes
• RAM size: 2048 bytes
• Memory allocation selection bits (b2, b1, b0)=(1, 1, 0)
• ROM size: 96 Kbytes
• RAM size: 3968 bytes (45.9 Kbytes) UART0 transmission Refer to Appendix 2. 02FFFF 16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section “2.5 Processor modes.”) 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Internal ROM area

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1. M37733S4BFP, M37733S4LHP 01FFFF 16 FF000016 00000016 00007F16 00008016 00087F16 FFFFFF 16 00088016 00FFFF 16 01000016 00000016 00007F16 Timer A4 00FFD6 16 00FFFE 16 SFR area Internal RAM area 2048 bytes Bank 016 Bank 116 Bank FF16 A-D/UART2 trans./rece. UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide RESET Interrupt vector table Peripheral device control registers (SFR) UART1 transmission UART0 transmission Refer to Appendix. 2 : External memory area The area at addresses 00FFD616 to 00FFFF16 is the interrupt vector table area. Be sure to set ROM to this area. h Memory allocation of the 7735 Group differs from that of the 7733 Group. (For the memory allocation of the 7735 Group, refer to section “Appendix 1 in part 2.”) h Fig. 4 Memory allocation of M37733S4BFP, M37733S4LHP Appendix 1. Memory allocation of 7733 Group

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Fig. 5 Memory allocation in SFR area (1) Appendix 2. Memory allocation in SFR area Figures 5 to 8 show the memory allocation in SFR area. The signals used in Figures 5 to 8 are shown below. : “0” immediately after reset. : “1” immediately after reset. : Undefined immediately after reset. : Always “0” at reading 0 : Always undefined at reading : “0” immediately after reset. Must be fixed to “0.” : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Not implemented. It is impossible to read the bit state. The written value becomes invalid. RW RO WO Abbreviations which represent access characteristics 1016 1116 1216 1316 Port P8 direction register1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 016 116 216 316 416 516 616 716 816 916 B16 C 16 D 16 E16 F16 A16 Address Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register 0 A-D control register 1 Port P0 register Port P1 register Port P2 register Port P3 register Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Register name Access characteristics State immediately after reset RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0016 0016 0016 0016 0016 00 0 0 00 0 0 00 0 0 0016 0 0 00 0 ? 0 0 11 b7 b0 b7 b0 n SFR area (addresses 016 to 7F16) RW 0016 h Do not write to the reserved area. (For the M37733S4BFP, M37733S4LHP, M37735S4BFP, M37735S4LHP, refer to Figure 20.8.1.) RW RW ?? 0 ? ?? ? 0016 (Reserved area)h (Reserved area)h Appendix 2. Memory allocation in SFR area

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Fig. 6 Memory allocation in SFR area (2) UART0 transmit/receive control register 0 UART0 transmit/receive mode register UART0 baud rate register UART0 transmission buffer register UART1 receive buffer register Register name UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register UART1 transmission buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 2816 2916 2B16 2C 16 2D 16 2E16 2F16 2A16 2016 2116 2216 2316 2416 2516 2616 2716 3F16 Address Access characteristics RW WO WO RO RO b7 b0 WO RWRO RO RORW RW RO RO RW WO WO WO RWRO RO RORW RW State immediately after reset 00 1 00 0 0016 0 00 0 00 0 ? b7 b0 0016 00 0 0 0 0 1 0 00 0 0 00 0 00 1 00 0 00 0 0 0 0 1 0 A-D register 5 A-D register 1 A-D register 3 A-D register 2 A-D register 4 A-D register 0 A-D register 6 A-D register 7 RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW 00 ? ? Appendix 2. Memory allocation in SFR area

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Fig. 7 Memory allocation in SFR area (3) Timer B2 register 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 4B16 4C 16 4D 16 4E16 4F16 4A16 Address Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Processor mode register 0 One-shot start flag Timer A0 register Up-down flag Timer A1 register Register name Count start flag Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Access characteristics WO RW b7 b0 RW RW RW RW RW RW RW WO RW State immediately after reset 0016 0016 0016 0016 0016 b7 b0 0016 00 0 00 0 0 0 0 0 0 0 WO RW RW RW Timer A0 mode register Timer A4 mode register RW RW RW 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 0RWRW 0Processor mode register 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 1 h 2 h 2 h 2 h 3 h 3 h 1 Access characteristics at addresses 4616 to 5516 vary according to the timer’s operating mode. (Refer to chapter “6. TIMER A,” and chapter “7. TIMER B.”) h 2 Access characteristics for bit 5 at addresses 5B16 to 5D16 vary according to the timer B’s operating mode. (Refer to chapter “7. TIMER B.”) h 3 Access characteristics for bit 1 at address 5E16 and its state immediately after reset vary according to the voltage level applied to pin CNVSS . (Refer to section “2.5 Processor modes.”) Appendix 2. Memory allocation in SFR area

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Fig. 8 Memory allocation in SFR area (4) RO O UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address Oscillation circuit control register 0 Serial transmit control register A-D / UART 2 trans./rece. interrupt control register UART0 transmission interrupt control register UART1 transmission interrupt control register INT2/Key input interrupt control register Watchdog timer frequency selection flag Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW( h 2) RW RW RW RW b7 b0 WO RW RW RW RW RW RW RW RW RW RW State immediately after reset 0 00 0 ? 0 ? (h 1) b7 b0 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 Port function control register UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register RW RW WO RW RW RW 00 0 0 0 1 00 00 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 00 0 0 0 0 00 0 0 0 0 A value of “FFF 16” is set to the watchdog timer. (Refer to chapter “10. WATCHDOG TIMER. ”) For access characteristics at address 6C16, also refer to Figure 14.3.2. Fix this bit to “1” in the One Time PROM version and EPROM version. (However, fix this bit to “0” in the 7735 Group.) Do not write to the reserved area. (Refer to Figure 20.8.1 for the M37733S4BFP, M37733S4LHP, M37735S4BFP, 37735S4LHP.) n Internal RAM area (M37733MHBXXXFP: addresses 8016 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset. When the stop or wait mode is terminated (when the hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. RW h 3 00 0 h 1 h 2 h 3 h 4 (Reserved area) h 4 Memory allocation control register UART 2 transmit/receive mode register UART 2 baud rate register (BRG2) UART 2 transmission buffer register UART 2 transmit/receive control register 0 UART 2 transmit/receive control register 1 UART 2 receive buffer register Oscillation circuit control register 1 RW 0? 0 00 0 RW ? 00 0 0 0 00 WO WO WO RWRO 1 00 0 RW RORO 00 0 0 00 10 RO 00 0 000 ? RW ?? 0 00 0 0 00 0 Appendix 2. Memory allocation in SFR area RW

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Appendix 3. Control registers Appendix 3. Control registers The control registers allocated in the SFR area are shown on the following pages. Below is the structure diagram for all registers. XXX register (address XX16) b1 b0b2b3b4b5b6b7 ]2 ]3 1 : ... 1 : ... The value is “0” at reading. 0 : ... 1 : ... Fix this bit to “0.” 7 to 5 Not implemented. RW WO RO RW RW Bit Bit name This bit is ignored in ... mode. Functions At reset RW ... flag Undefined Undefined Blank : Set to “0” or “1” according to the usage. 0 : Set to “0” at writing. 1 : Set to “1” at writing. 5 : Ignored depending on the mode or state. It may be “0” or “1.” : Not implemented. 0 : “0” immediately after reset. 1 : “1” immediately after reset. Undefined : Undefined immediately after reset. RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be “0” or “1.” WO : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading] is indicated in the “Function” or “Note” column, the bit is always “0” at reading.(See to ]4 above.) — : It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading] is indicated in the “Function” or “Note” column, the bit is always “0” at reading.(See to ]4 above.) The written value becomes invalid. Accordingly, the written value may be “0” or “1.”

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Appendix 3. Control registers Port Pi register Port Pi direction register Data is input from or output to a pin by reading from or writing to the corresponding bit. Port Pi register (i = 0 to 8) (addresses 216,316,616,716,A16,B16,E16,F16,1216) b1 b0b2b3b4b5b6b7 Note: Writing to bits 4 to 7 of the port P3 register is invalid and these bits are fixed to “0” when they are read. 0: “L” level 1: “H ” level

7 Port Pi7’s pin Undefined RW

Bit Bit name Functions At reset RW

0 Port Pi0’s pin RWUndefined

1 Port Pi1’s pin RWUndefined

2 Port Pi2’s pin RWUndefined

3 Port Pi3’s pin RWUndefined

4 Port Pi4’s pin RWUndefined

5 Port Pi5’s pin RWUndefined

6 Port Pi6’s pin RWUndefined

0: Input mode (The port functions as an input port.) 1: Output mode (The port functions as an output port.) Port Pi direction register (i = 0 to 8) (addresses 416,516,816,916,C16,D16,1016,1116,1416) b1 b0b2b3b4b5b6b7 At reset RW Note: Writing to bits 4 to 7 of the port P3 direction register is invalid and these bits are fixed to “0” when they are read.

0 Port Pi0 direction selection bit 0 RW

1 Port Pi1 direction selection bit 0 RW

2 Port Pi2 direction selection bit 0 RW

3 Port Pi3 direction selection bit 0 RW

4 Port Pi4 direction selection bit 0 RW

5 Port Pi5 direction selection bit 0 RW

6 Port Pi6 direction selection bit 0 RW

7 Port Pi7 direction selection bit 0 RW

pin Pi6 Pi5 Pi4 Pi3 Pi2 Pi1 Pi0

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Appendix 3. Control registers A-D control register 0 A-D control register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (address 1F16) Bit Bit name At reset RWFunctions 0 0: Pins AN0 and AN1 (2 pins) 0 1: Pins AN0 to AN3 (4 pins) 1 0: Pins AN0 to AN5 (6 pins) (Note 2) 1 1: Pins AN0 to AN7 (8 pins) b1 b0 Not implemented. Undefined These bits are ignored in the one-shot and repeat modes. (They may be “0” or “1.”) When an external trigger is selected, pin AN5 cannot be used as an analog input pin. Writing to each bit of the A-D control register 1 must be performed while the A-D converter stops operating. When the VREF connection selection bit is cleared from “1” to “0,” wait for an interval of 1 µs or more passed, and then start A-D conversion. 3 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution A-D sweep pin selection bits (Valid in the single sweep and repeat sweep modes.) (Note 1) 4 Must be fixed to “0.” bit (Note 4) 0: Pin VREF is connected. 1: Pin VREF is disconnected. (High impedance) 6 Not implemented. Undefined RW RW RW RW RW Notes 1: b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 0 (address 1E16) Bit A-D conversion frequency (fAD ) selection flag A-D conversion start flag Trigger selection bit A-D operation mode selection bits Bit name At reset Undefined Undefined Undefined RWFunctions 0 0 0: AN0 is selected. 0 0 1: AN1 is selected. 0 1 0: AN2 is selected. 0 1 1: AN3 is selected. 1 0 0: AN4 is selected. 1 0 1: AN5 is selected. (Note 2) 1 1 0: AN6 is selected. 1 1 1: AN7 is selected. f2]: Refer to chapter “14. CLOCK GENERATING CIRCUIT. ” b2 b1 b0 0: Internal trigger 1: External trigger 0: f2/4] 1: f2/2 00: One-shot mode 01: Repeat mode 10: Single sweep mode 11: Repeat sweep mode 0: A-D conversion is stopped. 1: A-D conversion is started. b4b3 These bits are ignored in the single sweep and repeat sweep modes. (They may be “0” or “1.”) When an external trigger is selected, pin AN5 cannot be used as an analog input pin. Writing to each bit (except bit 6) of the A-D control register 0 must be performed while the A-D converter stops operating. Analog input selection bits (Valid in the one-shot and repeat modes.) (Note 1) Notes 1: RW RW RW RW RW RW RW RW

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Appendix 3. Control registers A-D register i b7 b0 A-D register 0 (addresses 2116 and 2016) A-D register 1 (addresses 2316 and 2216) A-D register 2 (addresses 2516 and 2416) A-D register 3 (addresses 2716 and 2616) A-D register 4 (addresses 2916 and 2816) A-D register 5 (addresses 2B16 and 2A16) A-D register 6 (addresses 2D16 and 2C16) A-D register 7 (addresses 2F16 and 2E16) Bit “0” at reading. The A-D conversion result is read out. Functions At reset Undefined RO RO RW b7 b0 (b15) (b8) l When resolution = 10 bits 15 to 10 9 to 0 b7 b0 A-D register 0 (addresses 2116 and 2016) A-D register 1 (addresses 2316 and 2216) A-D register 2 (addresses 2516 and 2416) A-D register 3 (addresses 2716 and 2616) A-D register 4 (addresses 2916 and 2816) A-D register 5 (addresses 2B16 and 2A16) A-D register 6 (addresses 2D16 and 2C16) A-D register 7 (addresses 2F16 and 2E16) Bit “0” at reading. The A-D conversion result is read out. Functions At reset Undefined RO RW b7 b0 (b15) (b8) l When resolution = 8 bits 7 to 0 15 to 8 RO

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Appendix 3. Control registers UART0, UART1 transmit/receive mode register Bit (Valid in the UART mode.) (Note) (Valid in the UART mode.) (Note) (Valid in the UART mode when the parity enable bit = “1.”) (Note) (Valid in the UART mode.) (Note) 0 0 0: Serial I/O is disabled. (P8 functions as a programmable I/O port.) 0 0 1: Clock synchronous serial I/O mode 0 1 0: Do not select. 0 1 1: Do not select. 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Do not select. UART0 transmit/receive mode register (address 3016) UART1 transmit/receive mode register (address 3816) Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be “0” or “1.”) Fix bit 7 to “0.” b2 b1 b0 0: Odd parity 1: Even parity 0: Parity is disabled. 1: Parity is enabled. 0: The sleep mode is terminated. (Ignored.) 1: The sleep mode is selected. 0: Internal clock 1: External clock 0: One stop bit 1: Two stop bits RW RW RW RW RW RW RW RW UARTi baud rate register (BRGi) b7 b0 UART0 baud rate register (address 3116) UART1 baud rate register (address 3916) UART2 baud rate register (address 6516) FunctionsBit At reset RW 7 to 0Values 0016 to FF16 can be set. Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Un- defined WO

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Appendix 3. Control registers UARTi transmission buffer register b7 b0 (b15) (b8) b7 b0 UART0 transmission buffer register (addresses 3316, 3216) UART1 transmission buffer register (addresses 3B16, 3A16) UART2 transmission buffer register (addresses 6716, 6616) Bit Not implemented. The transmit data is set. At reset Un- defined RWFunctions 8 to 0 15 to 9 Un- defined WO UART0, UART1 transmit/receive control register 0 0: At the falling edge of the transfer clock, transmit data is output; at the rising edge of the transfer clock, receive data is input. When not in transferring, pin CLKi’s level is “H.” 1: At the rising edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. When not in transferring, pin CLKi’s level is “L.” 0: The CTS /RTS function is enabled. 1: The CTS /RTS function is disabled. (P80 and P84 function as programmable I/O ports.) (Valid when the CTS /RTS enable bit is “0.”) 0: Data is present in the transmission register. (Transmission is in progress.) 1: No data is present in the transmission register. (Transmission is completed.) RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) b1 b0 0: The CTS function is selected. 1: The RTS function is selected. Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT. ” Note: Fix bits 6 and 7 to “0” in the UART mode. 5 Data output selection bit 0: Pin TxDi is set for CMOS output. 1: Pin TxDi is set for N-channel open- drain output. 6 0 7 0: LSB (Least Significant Bit) first 1: MSB (Most Significant Bit) first CLK polarity selection bit (This bit is used in the clock synchronous serial I/O mode.) (Note) Transfer format selection bit (This bit is used in the clock synchronous serial I/O mode.) (Note) RW RW RW RO RW RW RW RW

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Appendix 3. Control registers UARTi transmit/receive control register 1 At resetBit Bit name (Valid in the UART mode.) 00: No framing error is detected. 1: Framing error is detected. RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) Notes 1: Bits 4 to 7 are cleared to “0” when the serial I/O mode selection bits (bits 2 to 0 at addresses 3016, 3816) are cleared to “0002” or when the receive enable bit is cleared to “0.” (Bit 7 is cleared to “0” when all of bits 4 to 6 are “0.”) Note also that bits 5 and 6 are cleared to “0” when the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16, 6A16) is read out. 2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode. 0 Transmit enable bit 00: Transmission is disabled. 1: Transmission is enabled. buffer register. 1: No data is present in the transmission buffer register. 2 Receive enable bit 00: Reception is disabled. 1: Reception is enabled. buffer register. 1: Data is present in the receive buffer register. 4 Overrun error flag (Note 1) 00: No overrun error is detected. 1: Overrun error is detected. (Valid in the UART mode.) 00: No parity error is detected. 1: Parity error is detected. (Valid in the UART mode.) 00: No error is detected. 1: Error is detected. RW RO RW RO RO RO RO RO UARTi receive buffer register b7 b0 (b15) (b8) b7 b0 UART0 receive buffer register (addresses 3716, 3616) UART1 receive buffer register (addresses 3F16, 3E16) UART2 receive buffer register (addresses 6B16, 6A16) Bit Not implemented. A value of “0” is read out from here. The receive data is read out from here. At reset Un- defined RWFunctions 8 to 0 15 to 9 RO

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Appendix 3. Control registers Count start flag Bit Count start flag (address 4016) 0: Counting is stopped. 1: Counting is started. RW RW RW RW RW RW RW RW One-shot start flag Bit 7 to 5 Not implemented. One-shot start flag (address 4216) 1: One-shot pulse output is started. (Valid when the internal trigger is selected.) “0” at reading. WO WO WO WO WO Up-down flag Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Up-down flag (address 4416) 0: Countdown 1: Countup This bits is valid when the contents of the up-down flag is selected as the up-down switching factor. 0: Two-phase pulse signal processing function is disabled. 1: Two-phase pulse signal processing function is enabled. When not using the two-phase pulse signal processing function, be sure to set this bit to “0.” This bit is “0” at reading. RW RW RW RW RW WO WO WO Note: When writing to bits 5 to 7, use the LDM or STA instruction.

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Appendix 3. Control registers Timer Ai mode register Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) 0 0: Timer mode 0 1: Event counter mode 1 0: One-shot pulse mode 1 1: Pulse width modulation (PWM) mode b1 b0 2 These bits have different functions according to the operating mode. (b15) (b8) Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Undefined RW

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Appendix 3. Control registers n Timer mode Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT. ” Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) 0 0: Timer mode 0: No pulse is output. (Pin TAiOUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TAiOUT functions as a pulse output pin.) 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b66 Count source selection bits b1 b0 b4 b3 5 Must be fixed to “0” in the timer mode. 00 0 (Pin TAiIN functions as a programmable I/O port.) 1 0: Counter counts only while pin TAiIN’s input signal level is “L.” 1 1: Counter counts only while pin TAiIN’s input signal level is “H.” Bit At reset RW b7 b0 b7 b0 (b15) (b8) Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Undefined RW RW RW RW RW RW RW RW RW

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Appendix 3. Control registers n Event counter mode Timer A0 mode register (address 5616) Timer A1 mode register (address 5716) b7 b6 b5 b4 b3 b2 b1 b0 5 00 1 Bit 6 These bits are ignored in the event counter mode. 5 Must be fixed to “0” in the event counter mode. Functions 0: Counts at falling edge of external signal 1: Counts at rising edge of external signal 0: Contents of the up-down flag 1: A signal which is input to pin TA0OUT or TA1OUT At reset RW 0: No pulse is output. (Pin TA0OUT or TA1OUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TA0OUT or TA1OUT functions as a pulse output pin.) 0 1: Event counter mode b1 b0 b7 b0 b7 b0 (b15) (b8) Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) RW 15 to 0Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (FFFF16 – n + 1) in up- counting. At reading this register, the counter value is read out. Undefined Bit Functions At reset RW RW RW RW RW RW RW RW RW

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Appendix 3. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Timer A2 mode register (address 5816) Timer A3 mode register (address 5916) Timer A4 mode register (address 5A16) 00 1 Bit 5 Must be fixed to “0” in the event counter mode. Note: This bit is valid only for the timer A3 mode register. For the timer A2 and A4 mode registers, this bit is ignored. (It may be “0” or “1.”) bit (Note) Functions 0 1: Event counter mode b1 b0 0: Contents of the up-down flag 1: A signal which is input to pin TA2OUT , TA3OUT , or TA4OUT At reset RW 0: No pulse is output. (Pin TA2OUT , TA3OUT , or TA4OUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TA2OUT , TA3OUT , or TA4OUT functions as a pulse output pin.) the external signal. 1: Counting is performed at the rising edge of the external signal. 0: Reload count type 1: Free-run count type 0: Normal processing 1: Quadruple processing b7 b0 b7 b0 (b15) (b8) FunctionsBit At reset RW 15 to 0Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (FFFF16 – n + 1) in up-counting. At reading this register, the counter value is read out. Undefined Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) RW RW RW RW RW RW RW RW RW

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Appendix 3. Control registers n One-shot pulse mode b7 b0 b7 b0 (b15) (b8) Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, “H ” level width of the one-shot pulse output from pin TAiOUT is n/fi. Undefined fi: Frequency of the count source (f2, f16, f64, or f512) 2 Must be fixed to “1” in the one-shot pulse mode. Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) 1 0: One-shot pulse mode 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b6 5 Must be fixed to “0” in the one-shot pulse mode. 10 1 Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT. ” TAiIN functions as a programmable I/O @@ port.) 1 0: Falling edge of the pin TAiIN’s input signal 1 1: Rising edge of the pin TAiIN’s input signal Bit At reset RW RW RW RW RW RW RW RW RW WO

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Appendix 3. Control registers n Pulse width modulation (PMW) mode b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b6 Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT. ” At reset RW 2 Must be fixed to “1” in the PWM mode. 1 1: PWM mode b1 b0 b4 b3 5 16/8-bit PWM mode selection bit functions as a programmable I/O port.) 1 0: Falling edge of the pin TAiIN’s input signal 1 1: Rising edge of the pin TAiIN’s input signal Bit 0: The counter operates as a 16-bit pulse width modulator. 1: The counter operates as an 8-bit pulse width modulator. n When operating as an 8-bit pulse width modulator (b15) b7 b0 b7 b0 (b8) Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) FunctionsBit At reset RW 7 to 0 Values 0016 to FF16 can be set. Assuming that the set value = m, period of the PWM pulse which is output from pin TAiOUT is (m + 1)(28 – 1)/fi. fi: Frequency of the count source (f2, f16, f64, or f512) 15 to 8Values 0016 to FE16 can be set. Assuming that the set value = n, “H ” level width of the PWM pulse which is output from pin TAiOUT is n(m +1)/fi. Un- defined Un- defined b7 b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0Values 000016 to FFFE16 can be set. Assuming that the set value = n, “H ” level width of the PWM pulse which is output from pin TAiOUT is n/fi. Un- defined fi: Frequency of the count source (f2, f16, f64, or f512) n When operating as a 16-bit pulse width modulator (b15) (b8) RW RW RW RW RW RW RW RW WO WO WO

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Appendix 3. Control registers Timer Bi mode register Timer Bi register b7 b0 b7 b0 (b15) (b8) Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) FunctionsBit At reset RW 15 to 0Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Un- defined RW RW RW RW RW RW RW RW Bit 4 Must be fixed to “0” (i = 0). Bit name At reset Un- defined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) 0 0: Timer mode 0 1: Event counter mode 1 0: Pulse period/Pulse width measurement mode 1 1: Do not select. b1 b0 2 These bits have different functions according to the operating mode. Note: In the timer and event counter modes, bit 5 is ignored and undefined at reading. 5 These bits have different functions according to the operating mode. Not implemented (i = 1, 2). Un- defined RO (Note)

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Appendix 3. Control registers n Timer mode At reset Un- defined Un- defined RWBit Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) b1 b0 b4 b3 00XXX 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b66 Count source selection bits 5 This bit is ignored in the timer mode and is undefined at reading. Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT. ” b7 b0 b7 b0 (b15) (b8) Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) FunctionsBit At reset RW 15 to 0Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Un- defined 2 These bits are ignored in the timer mode. 0 0: Timer mode 4 •Timer B0 mode register Must be fixed to “0.”

• Timer B1 and B2 mode registers Not implemented. RW RW RW RW RW RO RW RW RW

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Appendix 3. Control registers n Event counter mode 0 0: Counting is performed at the falling edge of the external signal. 0 1: Counting is performed at the rising edge of the external signal. 1 0: Counting is performed at both falling and rising edges of the external signal. 1 1: Do not select. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit 5 This bit is ignored in the event counter mode and is undefined at reading. 4 •Timer B0 mode register Must be fixed to “0.” 0 1: Event counter mode b1 b0 b3 b2 X 01 6 These bits are ignored in the event counter mode. At reset Un- defined Un- defined RW

• Timer B1 and B2 mode registers Not implemented. b7 b0 b7 b0 (b15) (b8) Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) FunctionsBit At reset RW 15 to 0Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Un- defined XX RW RW RW RW RW RO RW RW RW

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Appendix 3. Control registers n Pulse period/Pulse width measurement mode b7 b0 b7 b0 (b15) (b8) Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) FunctionsBit At reset RW 15 to 0The result of the pulse period or pulse width measurement is read out. Un- defined 0 0: Pulse period m easurem ent Interval betw een falling edges of the m easurem ent pulse) 0 1: Pulse period m easurem ent Interval betw een rising edges of the m easurement pulse) 1 0: Pulse width m easurem ent Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of the measurement pulse) 1 1: Do not select. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit

5 Timer Bi overflow flag (Note)

• Timer B0 mode register Must be fixed to “0.”

2 Measurement mode selection

1 0: Pulse period/pulse width m easurem ent m ode b1 b0 0: No overflow 1: Overflow b3 b2 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b6 At reset Un- defined RW

• Timer B1 and B2 mode registers Not implemented. Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT. ” Note: Timer Bi overflow flag is cleared to “0” when writing to the timer Bi mode register is performed with the count start flag = “1.” This flag cannot be set to “1” by software. RW RW RW RW RW RO RW RW RO

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Appendix 3. Control registers n Clock timer At resetFunctions Un- defined Un- defined RWBit 3 Must be fixed to “0” for the clock timer. b7 b6 b5 b4 b3 b2 b1 b0 Timer B2 mode register (address 5D16) 1010 06 These bits are ignored for the clock timer. 5 This bit is ignored for the clock timer. b7 b0 b7 b0 (b15) (b8) Timer B2 register (addresses 5516 and 5416) FunctionsBit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Un- defined 2 Must be fixed to “1” for the clock timer. 1 Must be fixed to “0” for the clock timer. 0 Must be fixed to “1” for the clock timer. 4 Not implemented. X XX RW RW RW RW RO RW RW RW

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Appendix 3. Control registers Processor mode register 0 Bit Bit name Functions At reset RW Processor mode bits Wait bit Software reset bit Must be fixed to “0.” Clock f1 output selection bit (Note 2) 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Microprocessor mode 1 1: Do not select. 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. Microcomputer is reset by setting this bit to “1.” This bit is “0” at reading. 0 0: 7 cycles of f 0 1: 4 cycles of f 1 0: 2 cycles of f 1 1: Do not select. 0: Clock f1 output is disabled. (P42 functions as a programmable I/O port.) 1: Clock f1 output is enabled. 2 functions as a clock f1 output pin.) b1 b0 b5 b4 Processor mode register 0 (address 5E16) (Note 1) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to “1” after reset. (At reading, this bit is always “1.”) 2: This bit is ignored in the microprocessor mode. (It may be “0” or “1.”) b1 b0b2b3b4b5b6b7 RW RW RW WO RW RW RW RW Interrupt priority detection time selection bits Processor mode register 1 b2b3b4b5b6b7 b1 Processor mode register 1 (address 5F16) Bit Bit name Function At reset 7 to1 Wait selection bit 0 : Wait 0 1 : Wait 1 0 Not implemented. Un- defined RW RW (Port P4

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Appendix 3. Control registers Watchdog timer register b7 b0 Watchdog timer register (address 6016) Bit 7 to 0 Watchdog timer is initialized. By writing dummy data to this register, watchdog timer’s value is initialized to “FFF 16” (Dummy data: 0016 to FF16). At reset Un- defined WO RWFunctions Watchdog timer frequency selection flag 0 : Clock f512 1 : Clock f32 At reset Un- defined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency selection flag (address 6116) Bit 7 to 1 Not implemented. Clocks f32, f512 : Refer to chapter “14. CLOCK GENERATING CIRCUIT. ” RW

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Appendix 3. Control registers Memory allocation control register ROM size ROM size 7 to 5 Not implemented. Notes 1: The case where value “5516” is written in À of the procedure listed below is not included. 2: When changing these bits, this change must be performed in an area which is internal ROM area before and after this change, for example addresses 00C00016 to 00FFFF16. Also, when changing these bits, be sure to follow the procedure listed below. 3: This figure is applied only to the M37733MHBXXXFP. For the other microcoputers, please refer to the latest datasheets on the English document CD-ROM or our Web site. Bit Bit name Functions At reset RW Memory allocation selection bits (Notes 1 and 2) 0 0 0: 124 Kbytes, 3968 bytes 0 0 1: 120 Kbytes, 3968 bytes 0 1 0: 60 Kbytes, 2048 bytes 0 1 1: Do not select. 1 0 0: 32 Kbytes, 2048 bytes 1 0 1: 16 Kbytes, 2048 bytes 1 1 0: 96 Kbytes, 3968 bytes 1 1 1: Do not select. b2b1b0 Memory allocation control register (address 6316) (Note 3) b1 b0b2b3b4b5b6b7 RW RW RW RW RW Un- defined | Note: When changing bits 2 to 0, be sure to follow this procedure. Procedure À By using the LDM instruction, write value “5516” to address 6316. (By this, writing to the memory allocation selection bits is enabled.) \` By using the LDM instruction, write value “00000XXX2” to address 6316. (Values of b2, b1, and b0 shown in the above Figure) Writing is performed by the next instruction. Must be fixed to “0.” (Note 1)

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Appendix 3. Control registers UART2 transmit/receive mode register Bit 7 Not implemented. (Valid in the UART mode.) (Note 2) (Valid in the UART mode when the parity enable bit = “1”.) (Note 2) (Valid in the UART mode.) (Note 2) 2 @ 1 @ (Note 1) Bit name At reset Un- defined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0 0: Serial I/O is ignored. (P7 functions as a programmable I/O port) 0 0 1: Clock synchronous serial I/O mode 0 1 0: 0 1 1: 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Do not select. UART2 transmit/receive mode register (address 64 16) Notes 1: By specifying these bits, an A-D conversion interrupt or a UART2 transmit/receive interrupt is selected. When bits 2 to 0 = “0002,” an A-D conversion interrupt is selected. When bits 2 to 0 = “0012” or “1002 to 1112,” a UART2 transmit/receive interrupt is selected. 2: In the clock synchronous serial I/O mode, bits 4 to 6 are ignored. (They may be “0” or “1.”) b2 b1 b0 0: Odd parity 1: Even parity 0: Parity is disabled. 1: Parity is enabled. 0: Internal clock 1: External clock 0: One stop bit 1: Two stop bits RW RW RW RW RW RW RW Do not select. UART2 transmit/receive control register 0 1 @ 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 UART2 transmit/receive control register 0 (address 6816) b1 b0 0: The CTS function is enabled. 1: The CTS function is disabled. (P80 and P84 function as programmable I/O ports.) Not implemented. 7 to 4 RW RW RW RW RO 0: Data is present in the transmission register. (Transmission is in progress.) 1: No data is present in the transmission @ @ register. (Transmission is completed.) Un- defined Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

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Appendix 3. Control registers Oscillation circuit control register 0 Bit Bit name Functions At reset RW XCOUT drivability selection bit Main clock stop bit System clock selection bit P ort-X c selection bit Not implemented. Un- defined 0: Drivability “LOW” 1: Drivability “HIGH” When the port-Xc selection bit = “0,” 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = “1,” 0: Main clock 1: Sub clock Un- defined Oscillation circuit control register 0 (address 6C16) b1 b0b2b3b4b5b6b7 Notes 0: Main clock oscillation or external clock input is available. 1: Main clock oscillation or external clock input is stopped. RW RW Not implemented. – RW (Note 1) 0: Operate as I/O ports (P77, P76). 1: Operate as pins XCIN and XCOUT . RW (Notes 2 and 3) RW (Note 2) System clock stop bit at wait state (Note 4) 0: Output is enabled. 1: Output is disabled. (Refer to Tables 12.1.2 and 12.1.5) 0: Operates in the wait mode. 1: Stopped in the wait mode. Signal output disable selection bit RW (Note 1) 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = “1.” 2: When selecting the sub clock as the system clock, set bit 3 to “1” after setting bit 4 to “1.” If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to “1.” 3: Although this bit can be set to “1,” it cannot be cleared to “0” after this bit is once set to “1.” 4: When setting the system clock stop bit at wait state to “1,” perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to “0” immediately after the wait mode is terminated.

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Appendix 3. Control registers Port function control register Bit Functions b7 b6 b5 b4 b3 b2 b1 b0 Port function control register (address 6D16) Bit name 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. Timer B2 clock source selection bit 0: No internal connection 1: Internal connection with timer B2 0: No pull-up for pins P54/TA2OUT /KI0 to P57/TA3IN/KI3 1: With pull-up for pins P54/TA2OUT /KI0 to P57/TA3IN/KI3 1: Key input interrupt 4 Must be fixed to “0.” At reset RW RW RW RW0 RW0 RW0 RW0 RW0 RW0 0•Port-XC selection bit] = “0” (when the sub clock is not used) Timer B2 (event counter mode) clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer)

• Port-XC selection bit = “1” (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/ SUB functions as a programmable I/O port. 1: Sub clock SUB is output from pin P67/TB2IN/ SUB . (Note 2) Notes 1: When the port-Xc selection bit = “0” and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid.
• Key input interrupt selection bit = “0” 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2
• Key input interrupt selection bit = “1” 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up and is used for the key input interrupt. 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 Port-Xc selection bit] : Bit 4 of the oscillation circuit control register 0 (address 6C16)

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Appendix 3. Control registers Serial transmit control register Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Serial transmit control register (address 6E16) h When using multiple transfer clock output pins, satisfy the following conditions: l Serial I/O mode selection bits (bits 2 to 0 at address 3016) = “0012” l Internal/external clock selection bit (bit 3 at address 3016) = “0” l CTS /RTS enable bit (bit 4 at address 3416) = “1” l Receive enable bit (bit 2 at address 3516) = “0” (for cases À and \` in Table 8.3.4) l Transmission clock output pin selection bits = “012”, “102”, or “112” (Refer to Table 8.3.3.) Note: Bits 4 and 5 are ignored in the UART mode. (They may be “0” or “1.”) Not implemented. Un- defined (Valid only in the clock synchronous serial I/O mode.) (Note) 00 0: One transfer clock output pin (CLK0) 0 1: 1 0: 1 1: 5 0 3 to 0 7, 6 Not implemented. Value “0” is read out from here. b5 b4 Multiple transfer clock output pins RW RW

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Appendix 3. Control registers Oscillation circuit control register 1 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Bit Bit name Functions At reset RW Main clock division selection bit Sub clock external input selection bit Must be fixed to “1” in the one time PROM and EPROM versions (Notes 1 and 2). Must be fixed to “0” (Note 2). Clock prescaler reset bit Undefined Oscillation circuit control register 1 (address 6F16) 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT . Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. RW RW RW RW WO —Not implemented. Not implemented. /LiteDiagLines /LiteDiagLines b1 b0b2b3b4b5b6b7 Notes 1: When writing to this register, follow the procedure shown in Figure 10.2.3. By writing “1” to this bit, clock prescaler is initialized. RW (Note 3) Undefined Main clock external input selection bit 0: Main clock is divided by 2. 1: Main clock is not divided by 2. Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. Ignored in the mask ROM and external ROM versions. 2: The case where data “010101012” is written with the procedure shown in Figure 10.2.3 is not included. 3: In the 7735 Group, fix this bit to “0.” (Note 1) (Note 1) (Note 1) Write data “010101012.” (LDM instruction)

• When writing to bits 0 to 3 Write data “00001XXX2.” (LDM instruction) Next instruction (b3 in Figure 10.2.2) (b2 to b0 in Figure 10.2.2) Write data “8016.” (LDM instruction)
• When performing clock prescaler reset

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Appendix 3. Control registers Interrupt control register INT0, INT1, and INT2/Key input interrupt control registers (addresses 7D16 to 7F16) b2b1b0 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 RW0 A-D/UART2 trans./rece., UART0 and 1 transmission, UART0 and 1 receive, Timers A0 to A4, Timers B0 to B2 interrupt control registers (addresses 7016 to 7C16) b7 b6 b5 b4 b3 b2 b1 b0 Bit Bit name Functions At reset RW b2b1b0 0 0 0 : Level 0 (Interrupt is disabled.) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 Not implemented. Interrupt priority level selection bits Interrupt request bit Un- defined 0: No interrupt request has occurred. 1: Interrupt request has occurred. 0: Interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1: Interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when level sense is selected. b7 b6 b5 b4 b3 b2 b1 b0 Bit Bit name Functions RW RW0 RW0 Interrupt priority level selection bits Interrupt request bit (Note) 0: No interrupt request has occurred. 1: Interrupt request has occurred. 0 RW Polarity selection bit Level sense/Edge sense selection bit 0: Edge sense 1: Level sense RW0 At reset Un- defined Not implemented. Note: The interrupt request bits of INT0 to INT2/Key input interrupts are ignored when the level sense is selected. RW RW RW RW RW RW

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Appendix 4. Package outlines Appendix 4. Package outlines

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Appendix 4. Package outlines

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Appendix 4. Package outlines

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Appendix 5. Hexadecimal instruction code table Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE-1 D 3–D 0 D 7–D 4 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

0123456789 B C D EF

A,(DIR,X) ORA A,(DIR),Y AND A,(DIR,X) EOR A,(DIR,X) EOR A,(DIR),Y ADC A,(DIR,X) ADC A,(DIR),Y STA A,(DIR,X) LDA A,(DIR,X) AND A,(DIR),Y STA A,(DIR),Y LDA A,(DIR),Y CMP A,(DIR),Y CMP A,(DIR,X) SBC A,(DIR,X) SBC A,(DIR),Y ORA A,(DIR) JSR ABL AND A,(DIR) Note 1 EOR A,(DIR) PER ADC A,(DIR) STA A,(DIR) LDA A,(DIR) CMP A,(DIR) SBC A,(DIR) BRA REL LDX IMM CLP IMM SEP IMM ORA A,SR A ORA A,DIR SEB DIR,b ASL DIR ORA A,L(DIR) ORA A,IMM ORA A,ABS PHP PHD ASL A SEB ABS,b ASL ABS ORA A,(SR),Y ORA A,L(DIR),Y CLB DIR,b ORA A,DIR,X ASL DIR,X CLC TAS ORA A,ABS,Y DEC A CLB ABS,b ORA A,ABS,X ASL ABS,X AND A,SR BBS DIR,b,R AND A,DIR ROL DIR AND A,L(DIR) PLP PLD AND A,IMM ROL A BBS ABS,b,R AND A,ABS ROL ABS AND A,(SR),Y BBC DIR,b,R AND A,DIR,X ROL DIR,X AND A,L(DIR),Y SEC AND A,ABS,Y INC A TSA BBC ABS,b,R AND A,ABS,X ROL ABS,X EOR A,SR MVP EOR EOR EOR EOR A,DIR LSR DIR A,L(DIR) PHA A,IMM LSR A PHG JMP ABS A,ABS LSR ABS EOR A,(SR),Y A,(SR),Y A,(SR),Y A,(SR),Y A,(SR),Y A,(SR),Y MVN EOR EOR EOR EOR LSRLSR CLI TAD PHY JMP A,DIR,X A,DIR,X A,DIR,X A,DIR,X A,DIR,X A,DIR,X DIR,X DIR,X DIR,Y DIR,Y DIR,X DIR,X A,L(DIR),Y A,L(DIR),Y A,L(DIR),Y A,L(DIR),Y A,L(DIR),Y A,L(DIR),Y A,ABS,Y A,ABS,Y A,ABS,Y A,ABS,Y A,ABS,Y A,ABS,Y ABL (ABS) ABS ABS ABS ABS A,ABS,X A,ABS,X A,ABS,X A,ABS,X A,ABS,X A,ABS,X ABS,X ABS,X ABS,X ABS,Y ABS,X ABS,X ADC ADC ADC ADC ADC ROR ROR ROR JMP RTLPLA LDM A,SR A,SR A,SR A,SR A,SR DIR DIR DIR DIR DIR A,DIR A,DIR A,DIR A,DIR A,DIR DIR DIR DIR DIR DIR A,L(DIR) A,L(DIR) A,L(DIR) A,L(DIR) A,L(DIR) A,IMM A,IMM A,IMM A,IMM A A,ABS ABS A,ABS ABS A,ABS ABS A,ABS ABS A,ABS ABS ADC ADC ADC ADC ADCJMP RORRORLDM DIR,X DIR,X DIR,X SEI TDA PLY (ABS,X) STA STY STA STA STA STX STY STX DEY TXA PHTNote 2 STASTASTASTASTA STY STX TXS TXYTYA LDM LDM LDA LDALDY LDA LDA LDALDX LDX LDY PLTTAXTAY LDA LDALDY LDA LDX LDA TYXTSXCLV ABS,X LDA LDXLDY CMP CMP CMP CMP CMPCPY DEC CPY DEC CMP DEC INY DEX WIT CMP CMP CMP DEC CLM CMP PHX STP JMP L(ABS) PEI SBC SBC SBC SBC SBC ORA A,ABL ORA A,ABL,X AND A,ABL AND A,ABL,X EOR A,ABL EOR A,ABL,X A,ABL,X A,ABL,X A,ABL,X A,ABL,X A,ABL,X ADC A,ABL A,ABL A,ABL A,ABL A,ABL ADC STA STA LDA LDA CMP CMP SBC SBCSBCSBC CPX CPX INC INC INX INC SBC PEA SBC SBC INC SEM PLX NOP PSH PUL JSR ABS (ABS,X) Notes 1: 4216 specifies the contents of the INSTRUCTION CODE TABLE-2. About the second word’s codes, refer to the INSTRUCTION CODE TABLE-2. 2: 8916 specifies the contents of the INSTRUCTION CODE TABLE-3. About the second word’s codes, refer to the INSTRUCTION CODE TABLE-2.

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Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE-2 (The first word’s code of each instruction is 4216) D 3–D 0 D 7–D 4 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

0123456789 B C D E F

B,(DIR,X) ORA B,(DIR),Y AND B,(DIR,X) EOR B,(DIR,X) EOR B,(DIR),Y ADC B,(DIR,X) ADC B,(DIR),Y STA B,(DIR,X) LDA B,(DIR,X) AND B,(DIR),Y STA B,(DIR),Y LDA B,(DIR),Y CMP B,(DIR),Y CMP B,(DIR,X) SBC B,(DIR,X) SBC B,(DIR),Y ORA B,(DIR) AND B,(DIR) EOR B,(DIR) ADC B,(DIR) STA B,(DIR) LDA B,(DIR) CMP B,(DIR) SBC B,(DIR) ORA B,SR A ORA B,DIR ORA B,L(DIR) ORA B,IMM ORA B,ABS ASL B ORA B,(SR),Y ORA B,L(DIR),Y ORA B,DIR,X TBS ORA B,ABS,Y DEC B ORA B,ABS,X AND B,SR AND B,DIR AND B,L(DIR) AND B,IMM ROL B AND B,ABS AND B,(SR),Y AND B,DIR,X AND B,L(DIR),Y AND B,ABS,Y INC B TSB AND B,ABS,X EOR B,SR EOR EOR EOR EOR B,DIR B,L(DIR) PHB B,IMM LSR B B,ABS EOR B,(SR),Y B,(SR),Y B,(SR),Y B,(SR),Y B,(SR),Y B,(SR),Y EOR EOR EOR EOR TBD B,DIR,X B,DIR,X B,DIR,X B,DIR,X B,DIR,X B,DIR,X B,L(DIR),Y B,L(DIR),Y B,L(DIR),Y B,L(DIR),Y B,L(DIR),Y B,L(DIR),Y B,ABS,Y B,ABS,Y B,ABS,Y B,ABS,Y B,ABS,Y B,ABS,Y B,ABS,X B,ABS,X B,ABS,X B,ABS,X B,ABS,X B,ABS,X ADC ADC ADC ADC ADC ROR PLB B,SR B,SR B,SR B,SR B,SR B,DIR B,DIR B,DIR B,DIR B,DIR B,L(DIR) B,L(DIR) B,L(DIR) B,L(DIR) B,L(DIR) B,IMM B,IMM B,IMM B,IMM B B,ABS B,ABS B,ABS B,ABS B,ABS ADC ADC ADC ADC ADC TDB STA STA STA STA TXB STASTASTASTASTA TYB LDA LDA LDA LDA LDA TBXTBY LDA LDA LDA LDA LDA CMP CMP CMP CMP CMP CMPCMP CMP CMP CMP SBC SBC SBC SBC SBC ORA B,ABL ORA B,ABL,X AND B,ABL AND B,ABL,X EOR B,ABL EOR B,ABL,X B,ABL,X B,ABL,X B,ABL,X B,ABL,X B,ABL,X ADC B,ABL B,ABL B,ABL B,ABL B,ABL ADC STA STA LDA LDA CMP CMP SBC SBCSBCSBCSBC SBC SBC

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Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE-3 (The first word’s code of each instruction is 8916) D 3–D 0 D 7–D 4 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 (DIR,X) MPY (DIR),Y DIV (DIR,X) DIV (DIR),Y MPY (DIR) DIV (DIR) MPY SR A MPY DIR MPY L(DIR) MPY IMM MPY ABS MPY (SR),Y MPY L(DIR),Y MPY DIR,X MPY ABS,Y MPY ABS,X DIV SR DIV DIR DIV L(DIR) DIV IMM DIV ABS DIV (SR),Y DIV DIR,X DIV L(DIR),Y DIV ABS,Y DIV ABS,X RLA IMM IMM LDT MPY ABL MPY ABL,X DIV ABL DIV ABL,X XAB

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A CC ,C← A CC +M+C A CC ← A CC ∧ M Symbol Functions Details Adds the carry, the accumulator and the memory contents.The result is entered into the accumulator. When the D flag is “0,” binary additions is done, and when the D flag is “1,” decimal addition is done. Obtains the logical product of the contents of the accumu- lator and the contents of the memory . The result is en- tered into the accumulator. Shifts the accumulator or the memory contents one bit to the left. “0” is entered into bit 0 of the accumulator or the memory. The contents of bit 15 ( bit 7 when the m flag is “1”) of the accumulator or memory before shift is entered into the C flag. Tests the specified bit of the memory. Branches when all the contents of the specified bit is “0.” Tests the specified bit of the memory. Branches when all the contents of the specified bit is “1.” Branches when the contents of the C flag is “0.” Branches when the contents of the C flag is “1.” Branches when the contents of the Z flag is “1.” Branches when the contents of the N flag is “1.” Branches when the contents of the Z flag is “0.” Branches when the contents of the N flag is “0.” Jumps to the address indicated by the program counter plus the offset value. Executes software interruption. Branches when the contents of the V flag is “0.” Branches when the contents of the V flag is “1.” Makes the contents of the specified bit in the memory “0.” Makes the contents of the C flag “0.” Makes the contents of the I flag “0.” Specifies the bit position in the processor status register by the bit pattern of the second byte in the instruction, and sets “0” in that bit. Makes the contents of the V flag “0.” Compares the contents of the accumulator with the con- tents of the memory. Mb=0? Mb=1? C=0? C=1? Z=1? N=1? Z=0? N=0? PC ← PC ±offset PG ← PG+1 when carry occurs) PG ← PG–1 (when borrow occurs) PC ← PC+2 M(S)← PG S ← S–1 M(S)← PC H S ← S–1 M(S)← PC L S ← S–1 M(S)← PS H S ← S–1 M(S)← PS L S ← S–1 I← 1 PC L← AD L PC H ← AD H PG ← 0016 V=0? V=1? C ← 0 Mb ← 0 Makes the contents of the m flag “0.” I← 0 m ← 0 PSb ← 0 V ← 0 A CC –M IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y op n n op Addressing modes AND (Notes 1,2) ADC (Notes 1,2) ASL (Note 1) BBC (Notes 3,5) BBS (Notes 3,5) BCC (Note 3) BCS (Note 3) BEQ (Note 3) BMI (Note 3) BNE (Note 3) BPL (Note 3) BRA (Note 4) BRK BVC (Note 3) BVS (Note 3) CLB (Note 5) CLC CLI CLM CLV CMP (Notes 1,2) CLP n n op n 22 2 61 72 71 2 3 42 3 42 3 42 3 42 2 35 32 2 21 31 82 43 3 42 3 42 72 16 72 C1 D1 342 m=0 m=1 C ← b7 ··· b0 ← 0 # op n# op n# op n# 69 2 65 24 43 42 75 72 22 25 47 2 3 42 6 42 0A 2 06 00 15 2 14 8 18 2 4C5 D2 7 Appendix 6. Machine instructions Appendix 6. Machine instructions

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Processor status registerAddressing modes L(DIR) L(DIR),Y ABL,X (ABS) STK REL SR (SR),Y BLKABS,b ABS,X ABS,Y DIR,b,R ABS,b,R (ABS,X ) 30 op op op nnnnnnnn ABS IPL N V m C 285 64 DIZn op op opn n nop op nop 10 2 3 42 4 42 4 42 5 42 op 63 5 10 3 10 2 37 12 3 42 0E 3 66 3 2F 64 3F 74 4 42 84 42 58 42 1E 83

• • N V• x
• • • Z C 53C 847 90 42 24 74 2C 85 24D0 10 42 50 42 IC 94
• ••• C Z
• C3 52 8D3 2 3103742 C7 10 2 D7 11 2 CD 3 DD 63 3 13 34 D9 63 84 84 CF 64 DF 74 85 9 542 DF L(ABS)ABL #nn 77 11 2 6D 4 7D 679 6F 7F 28 3612 27 11 2 2D 3 3D 39 23 3 42 12 42 CD 6 42 DD CF 910 Specified flag be- comes “0.” N Appendix 6. Machine instructions

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Symbol Functions Details IMP IMM DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y nop op op n nn op n op Addressing modes Compares the contents of the index register X with the contents of the memory. Compares the contents of the index register Y with the contents of the memory. Decrements the contents of the accumlator or memory by Decrements the contents of the index register X by 1. Decrements the contents of the index register Y by 1. The numeral that places the contents of accumlator B to the higher order and the contents of accumulator A to the lower order is divided by the contents of the memory. The quotient is entered into accumula- tor A and the remainder into accumulator B. Logical exclusive sum is obtained of the contents of the accumulator and the contents of the memory. The result is placed into the accumulator. Increments the contents of the accumulator or memory by Increments the contents of the index register X by 1. Increments the contents of the index register Y by 1. Places a new address into the program counter and jumps to that new address. X–M Y–M A CC ← A CC –1 or M ← M–1 X ← X–1 Y ← Y–1 A(quotient)← B,A/M B(remainder) A CC ← A CC ∨ M A CC ← A CC +1 or M ← M+1 X ← X+1 Y ← Y+1 ABS PC L← AD L PC H ← AD H ABL PC L← AD L PC H ← AD H PG ← AD G (ABS) PC L← (ADH , ADL) PC H ← (ADH ,ADL+1) L(ABS) PC L← (ADH , ADL) PC H ← (AD H , ADL+1) PG ← (AD H , ADL+2) (ABS, X) PC L← (ADH , ADL+X) PC H ← (AD H , ADL+X +1) ABS M(S)← PC H S ← S–1 M(S)← PC L S ← S–1 PC L← AD L PC H ← AD H ABL M(S)← PG S ← S–1 M(S)← PC H S ← S–1 M(S)← PC L S ← S–1 PC L← AD L PC H ← AD H PG ← AD G (ABS, X) M(S)← PC H S ← S–1 M(S)← PC L S ← S–1 PC L← (ADH , ADL+X) PC H ← (AD H , ADL+X +1) CPX (Note 2) CPY (Note 2) DEC (Note 1) DEX DEY DIV (Notes 2,10) EOR (Notes 1,2) INC (Note 1) INX JMP INY JSR Saves the contents of the program counter (also the con- tents of the program bank register for ABL) into the stack, and jumps to the new address. n op nn op op n op op n E0 2 E4 42 C4 4 2 1A 21 C6 72 D6 3 89 3 89 3 89 32 3 89 49 2 45 42 55 52 62 72 51 82 63 42 73 42 83 42 93 10 3 3A 21 E6 77 C8 21 A C0 22 CA 327 4152 Appendix 6. Machine instructions

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Processor status registerAddressing modes L(DIR),Y ABL ABL,X (ABS) L(ABS) STK REL (SR),Y BLKABS,Y DIR,b,R ABS,b,R(ABS,X ) 30 op #op op op nnnnop nnn ABS op IPL N V m C 285 6410 9 DIZn nn op op nopn op nop op n nop op

• • N •• x
• • • Z4 op 336 EE 31 89 31 5 89 32 589 31 4 5D 63 FE 38 4F 64 5C 44 22 84 DC33 86 7C 3 3FC 8 30 3 89 333 Z L(DIR) ABS,b ABS,X SR ## ## C CC EC CE 73 DE 29 89 344D 324C 46C Appendix 6. Machine instructions

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Symbol Functions Details IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y #nop n op n op n op Addressing modes A CC ← M M ← IMM DT ← IMM X ← M Y ← M m=0 m=1 0 → b7 ··· b0 → C Enters the contents of the memory into the accummulator. Enters the immediate vaiue into the memory. Enters the immediate value into the data bank regiater. Enters the contents of the memory into index register X. Enters the contents of the memory into index register Y. Shifts the contents of the accumulator or the contents of the memory one bit to the right. The bit 0 of the accumu- lator or the memory is entered into the C flag. “0” is en- tered into bit 15 (bit 7 when the m flag is “1.”) B, A← A ] M Mn+i← Mm+i Mn–i← Mm–i PC ← PC+1 A CC ← A CC VM M(S)← IMM 2 S ← S–1 M(S)← IMM 1 S ← S–1 M(S)← M((DPR)+IMM +1) S ← S–1 M(S)← M((DPR)+IMM) S ← S–1 EAR ← PC+IMM 2,IMM1 M(S)← EAR H S ← S–1 M(S)← EAR L S ← S–1 m=0 M(S)← A H S ← S–1 M(S)← A L S ← S–1 m=1 M(S)← A L S ← S–1 m=0 M(S)← B H S ← S–1 M(S)← B L S ← S–1 m=1 M(S)← B L S ← S–1 Transmits the data block. The transmission is done from the lower order address of the block. Advances the program counter, but pertorms nothing else. Logical sum per bit of the contents of the accumulator and the contents of the memory is obtained. The result is en- tered into the accumulator. The 3rd and the 2nd bytes of the instruction are saved into the stack, in this order. Specifies 2 sequential bytes in the direct page in the 2nd byte of the instruction, and saves the contents into the stack. Regards the 2nd and 3rd bytes of the instruction as 16-bit numerals, adds them to the program counter, and saves the result into the stack. Saves the contents of accumulator A into the stack. Saves the contents of accumuator B into the stack. LDA (Notes 1,2) LDM (Note 5) LDT LDX (Note 2) LDY (Note 2) LSR (Note 1) MPY (Notes 2,11) MVN (Note 8) MVP (Note 9) NOP ORA (Notes 1,2) PEA PEI PER PHA PHB n op nn op op op n n op op n 25 2 B2 62 2 43 74 53 A6 42 2

2 A4 42 5 2

Multiplies the contents of accumulator A and the contents of the memory. The higher order of the result of operation are entered into accumulator B, and the lower order into accumulator A. Transmits the data block. Transmission is done form the higher order address of the data block. A9 22 A5 4 B5 72 B1 B6 5 B4A0 A2 2 2289 2118 EA Appendix 6. Machine instructions

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Processor status registerAddressing modes ABL ABL,X (ABS) STK (SR),YABS,X ABS,Y ABS,b,R(ABS,X ) 30 op nopnnnnn ABS IPL N V m C 287 5 6410 9 DIZn nop nop nop nopop

• N• x opop n op op opop op n op op op n op A7 2 B7 11 2 AD 43 3 B9 63 AF 64 BF 7 n A3 52 B3 3 13 3 42 AD BD 4 42 84 42 AF 85 42 BF 5 42 73 42 10 3 9C 54 4

43 BE 63

1D 63 19 63 0F 64 1F 74 03 52 13 82 3 42 3 42 64 42 84 42 84 42 85 42 95 42 73 42 F4 53 D4 62 62 53 48 41 54 73 i 5 72 i 5 72

• • • • Z N
• • Z•
• Z•• N Z Z C
• ••• Z N BLKSRDIR,b,R RELL(ABS)ABS,bL(DIR),YL(DIR) n BD n 69E BC AE 25 18 89 20 3 Appendix 6. Machine instructions

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Symbol Functions Details IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y opnop n nn n nn n n Addressing modes PHD M(S)← DPR H S ← S–1 M(S)← DPR L S ← S–1 Saves the contents of the direct page register into the stack. M(S)← PG S ← S–1 M(S)← PS H S ← S–1 M(S)← PS L S ← S–1 M(S)← DT S← S–1 x=0 M(S)← XH S ← S–1 M(S)← X L S ← S–1 x=1 M(S)← X L S ← S–1 x=0 M(S)← YH S ← S–1 M(S)← Y L S ← S–1 x=1 M(S)← Y L S ← S–1 m=0 S ← S+1 A L← M(S) S ← S+1 A H ← M(S) m=1 S ← S+1 A L← M(S) m=0 S ← S+1 B L← M(S) S ← S+1 B H ← M(S) m=1 S ← S+1 B L← M(S) S ← S+1 DPR L← M(S) S ← S+1 DPR H ← M(S) S ← S+1 PS L← M(S) S ← S+1 PS H ← M(S) S ← S+1 DT ← M(S) x=0 S ← S+1 X L← M(S) S ← S+1 X H ← M(S) x=1 S ← S+1 X L← M(S) PHG PHP PHT PHX PHY Saves the contents of the program bank register into the stack. Saves the contents of the program status register into the stack. Saves the contents of the data bank register into the stack. Saves the contents of the index register X into the stack. Saves the contents of the index register Y into the stack. PLA Restores the contents of the stack on the accumulator A. Restores the contents of the stack on the accumulator B. Restores the contents of the stack on the direct page reg- ister. Restores the contents of the stack on the processor status register. Restores the contents of the stack on the data bank reg- ister. Restores the contents of the stack on the index register X. PLB PLD PLP PLT PLX Appendix 6. Machine instructions

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Processor status registerAddressing modes L(DIR) L(DIR),Y ABL ABL,X (ABS) L(ABS) STK SR (SR),Y BLKABS,b ABS,X ABS,Y DIR,b,R ABS,b,R (ABS,X ) 10 98 76 5 2 30 op nop op op op op op op nop nop op op op op n nnnop nnopop nnnnop nnnnn ABS 408 1 8B 3 1 5A 41 68 51 42 72 2B 1 1628 AB 61 FA 51 IPL N V m x D I C Z Value saved in stack. DA REL Appendix 6. Machine instructions

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Symbol Functions Details IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y opnop op n op nn op op n op nn op op n op Addressing modes PLY x=0 S ← S+1 Y L← M(S) S ← S+1 Y H ← M(S) x=1 S ← S+1 Y L← M(S) Restores the contents of the stack on the index register Y. M(S)← A, B, X··· Saves the registers among accumulator, index register, direct page register, data bank register, program bank register, or processor status register, specified by the bit pattern of the second byte of the instruction into the stack. Restores the contents of the stack to the registers among accumulator, index register, direct page register, data bank register, or processor status register, specified by the bit pattern of the second byte of the instruction. m=0 n bit rotate left b15 ··· b0 ← m=1 n bit rotate left b7 ··· b0 ← A, B, X···← M(S) PSH (Note 6) PUL (Note 7) RLA (Note 13) Rotates the contents of the accumulator A, n bits to the left.m=0 m=1 ROL (Note 1) Links the accumulator or the memory to C flag, and rotates result to the left by 1 bit. m=0 m=1 → C → b7 ··· b0 → ROR (Note 1) Links the accumulator or the memory to C flag, and rotates result to the right by 1 bit. S ← S+1 PS L← M(S) S ← S+1 PS H ← M(S) S ← S+1 PC L← M(S) S ← S+1 PC H ← M(S) S ← S+1 PG ← M(S) S ← S+1 PC L← M(S) S ← S+1 PC H ← M(S) S ← S+1 PG ← M(S) S ← S+1 PC L← M(S) S ← S+1 PC H ← M(S) A CC , C← A CC –M–C RTI RTL RTS SBC (Notes 1,2) Returns from the interruption routine. Returns from the subroutine. The contents of the program bank register are also restored. Returns from the subroutine. The contents of the program bank register are not restored. Subtracts the contents of the memory and the borrow from the contents of the accumulator. 816B 60 51 40 11 1 6A 21 66 72 42 4 2 12 26 72 36 7 2 42 42 89 63

22 E5 4 2 F5 5 26 F2 2 E1 7 2 F1 2

i 1042 Appendix 6. Machine instructions

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Processor status registerAddressing modes L(DIR) L(DIR),Y ABL ABL,X (ABS) L(ABS) STK REL SR (SR),Y BLKABS,b ABS,X ABS,Y DIR,b,R ABS,b,R (ABS,X ) 10 98 76 5 2 30 op nop op op op op op op op op op op op op n nnnopnopop nnnop nnnnn ABS IPL V m x D I C Z N If restored the contents of PS, it becomes its value. And the other cases are no change. Value saved in stack. EB 12 2 214FB 3i1+4i2 3E 83 6E 387E 2E 73 52E3 EDE7 F7

2 F7 11 210 ED 43

FD 63 F9 63 EF 6 FF 74 82F3 42 73 42 10 3 E3 F3 FD C 2i1+i2 Appendix 6. Machine instructions

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Symbol Functions Details IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y opnop op n op nn op op n op nn op op op Addressing modes Makes the contents of the specified bit in the memory “1.” Makes the contents of the I flag “1.” Makes the contents of the m flag “1.” Set the specified bit of the processor status register's lower byte (PS L) to “1.” Stores the contents of the accumulator into the memory. Stops the oscillation of the oscillator. Stores the contents of the index register X into the memory. Stores the contents of the index register Y into the memory. Transmits the contents of the accumulator A to the direct page register. Transmits the contents of the accumulator A to the stack pointer. Transmits the contents of the accumulator A to the index register X. Transmits the contents of the accumulator A to the index register Y. Transmits the contents of the accumulator B to the direct page register. Transmits the contents of the accumulator B to the stack pointer. Transmits the contents of the accumulator B to the index register X. Transmits the contents of the accumulator B to the index register Y. Transmits the contents of the direct page register to the accumulator A. Transmits the contents of the direct page register to the accumulator B. Makes the contents of the C flag “1.” SEB (Note 5) Mb ← 1 SEC SEI SEM SEP STA (Note 1) STP STX STY TAD TAS C ← 1 I← 1 m ← 1 PSb ← 1 M ← A CC M ← X M ← Y DPR ← A S ← A X ← A Y ← A DPR ← B S ← B TAX TAY TBD TBS TDB X ← BTBX TBY TDA Y ← B A ← DPR B ← DPR 04 83 38 21 78 21 2F8 1 DB 31 2485 42 6 3 39423942742 2595 72 81 72 91 72 819295 2486 2484 5296 94 25 5B 21 1B 21 AA 21 A8 21 442 2 42 42 AA 42 4 7B 21 42 4 Transmits the contents of the stack pointer to the accumulator A. Transmits the contents of the stack pointer to the accu- mulator B. A ← S B ← S TSA TSB 3B 21 42 42 Transmits the contents of the stack pointer to the index register X. Transmits the contents of the index register X to the ac- cumulator A. X ← S A ← X TSX TXA Transmits the contents of the index register X to the ac- cumulator B. Transmits the contents of the index register X to the stack pointer. B ← X S ← X TXB TXS Transmits the contents of the index register X to the index register Y. Y ← XTXY Transmits the contents of the index register Y to the ac- cumulator A. A ← YTYA TYB B ← Y Transmits the contents of the index register Y to the index register X. Stops the internal clock. Exchanges the contents of the accumulator A and the con- tents of the accumulator B. TYX WIT XAB X ← Y A B←→ BA 21 42 24 9A 21 9B 21 98 21 42 42 Transmits the contents of the index register Y to the ac- cumulator B. BB 21 CB 31 2689 9 3 42 Appendix 6. Machine instructions

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L(DIR) L(DIR),Y ABL ABL,X (ABS) L(ABS) STK SR (SR),Y BLKABS,b ABS,X ABS,Y DIR,b,R ABS,b,R (ABS,X ) 10 98 76 5 2 30 op nop op op op op op op nop nop op op op op n nnnop nnopop nnnnop nnnn ABS IPL V m x D I C Z N 40C 9 97 353 3 54 4 7 342 474 74 75 85 9 97 9F Processor status register 22 6 “1.” 13 42 59D 99 8F 9F 5 42 10 REL 4242 8F8D 1087 Appendix 6. Machine instructions

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The number of cycles shown in the table is described in the case of the fastest mode for each instruction. The number of cycles shown in the table is calculated for DPRL=0. The number of cycles in the addressing mode concerning the DPR when DPRL≠0 must be incremented by 1. The number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer, or according to whether the memory read/write address is odd or even. It also differs when the external region memory is accessed by BYTE=“H.” Notes 1. The operation code at the upper row is used for accumulator A, and the operation at the lower row is used for accumulator 2. When setting flag m=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 3. The number of cycles increments by 2 when branching. 4. The operation code on the upper row is used for branching in the range of –128 to +127, and the operation code on the lower row is used for branching in the range of –32768 to +32767. 5. When handling 16-bit data with flag m=0, the byte in the table is incremented by 1. The number of cycles corresponding to the register to be pushed are added. The number of cycles when no pushing is done is 12. i 1 indicates the number of registers among A, B, X, Y, DPR, and PS to be saved, while i2 indicates the number of registers among DT and PG to be saved. The number of cycles corresponding to the register to be pulled are added. The number of cycles when no pulling is done is 14. i 1 indicates the number of registers among A, B, X, Y, DT, and PS to be restored, while i2=1 when DPR is to be restored. 8. The number of cycles is the case when the number of bytes to be transferred is even. When the number of bytes to be transferred is odd, the number is calculated as; 7 + (i/2) 5 7 + 4 Note that, (i/2) shows the integer part when i is divided by 2. 9. The number of cycles is the case when the number of bytes to be transferred is even. When the number of bytes to be transferred is odd, the number is calculated as; 9 + (i/2) 5 7 + 5 Note that, (i/2) shows the integer part when i is divided by 2. 10. The number of cycles is the case in the 16-bit ÷ 8-bit operation. The number of cycles is incremented by 16 for 32-bit ÷ 16- bit operation. 11. The number of cycles is the case in the 8-bit 5 8-bit operation. The number of cycles is incremented by 8 for 16-bit 5 16- bit operation. 12. When setting flag x=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 13. When flag m is 0, the byte in the table is incremented by 1. B A X Y DPR DT PS A B X Y DPR DT PG PS Type of register Number of cycles Type of register Number of cycles Appendix 6. Machine instructions

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Symbols in machine instructions table Description Symbol DescriptionSymbol IMP IMM A DIR DIR, b DIR, X DIR, Y (DIR) (DIR,X) (DIR), Y L (DIR) L (DIR),Y ABS ABS, b ABS, X ABS, Y ABL ABL, X (ABS) L (ABS) (ABS, X) STK REL DIR, b, REL ABS, b, REL SR (SR), Y BLK C Z I D x m V N IPL Implied addressing mode Immediate addressing mode Accumulator addressing mode Direct addressing mode Direct bit addressing mode Direct indexed X addressing mode Direct indexed Y addressing mode Direct indirect addressing mode Direct indexed X indirect addressing mode Direct indirect indexed Y addressing mode Direct indirect long addressing mode Direct indirect long indexed Y addressing mode Absolute addressing mode Absolute bit addressing mode Absolute indexed X addressing mode Absolute indexed Y addressing mode Absolute long addressing mode Absolute long indexed X addressing mode Absolute indirect addressing mode Absolute indirect long addressing mode Absolute indexed X indirect addressing mode Stack addressing mode Relative addressing mode Direct bit relative addressing mode Absolute bit relative addressing mode Stack pointer relative addressing mode Stack pointer relative indirect indexed Y addressing mode Block transfer addressing mode Carry flag Zero flag Interrupt disable flag Decimal operation mode flag Index register length selection flag Data length selection flag Overflow flag Negative flag Processor interrupt priority level Addition Subtraction Multiplication Division Logical AND Logical OR A CC ACCH ACCL A A H AL B B H BL X X H XL Y Y H YL S PC PC H PC L PG DT DPR DPR H DPR L PS PS H PS L PS b M(S) Mb AD G AD H AD L op n i i 1, i2 Exclusive OR Negation Movement to the arrow direction Accumulator Accumulator’s upper 8 bits Accumulator’s lower 8 bits Accumulator A Accumulator A’s upper 8 bits Accumulator A’s lower 8 bits Accumulator B Accumulator B’s upper 8 bits Accumulator B’s lower 8 bits Index register X Index register X’s upper 8 bits Index register X’s lower 8 bits Index register Y Index register Y’s upper 8 bits Index register Y’s lower 8 bits Stack pointer Program counter Program counter’s upper 8 bits Program counter’s lower 8 bits Program bank register Data bank register Direct page register Direct page register’s upper 8 bits Direct page register’s lower 8 bits Processor status register Processor status register’s upper 8 bits Processor status register’s lower 8 bits Processor status register’s b-th bit Contents of memory at address indicated by stack pointer b-th memory location Value of 24-bit address’s upper 8-bit (A23–A 16) Value of 24-bit address’s middle 8-bit (A15–A 8) Value of 24-bit address’s lower 8-bit (A7–A 0) Operation code Number of cycle Number of byte Number of transfer byte or rotation Number of registers pushed or pulled Appendix 6. Machine instructions

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Appendix 7. Examples of handling unused pins The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user’s application. 1. In single-chip mode Table 1 Examples of handling unused pins in single-chip mode Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). Leave this pin open. Connect this pin to pin Vcc. Connect these pins to pin Vss. Pins P0 –P8 E X OUT (Note 2) AVcc AVss, VREF , BYTE Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 2: This is applied when an external clock is input to pin XIN. Appendix 7. Examples of handling unused pins P0–P8 AVss VREF BYTE M37733MHBXXXFP Vss AVcc E XOUT Left open n When setting ports to input mode VCC P0–P8 AVss VREF BYTE M37733MHBXXXFP Vss AVcc E XOUT Left open n When setting ports to output mode Left open Vcc Fig. 9 Examples of handling unused pins in single-chip mode

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1. In memory expansion mode Table 2 Examples of handling unused pins in memory expansion mode Pins P4 2–P4 7, P5–P8 ____ BHE (Note 3) ALE (Note 4) HLDA X OUT (Note 6) HOLD , RDY AVcc AVss, VREF Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1, 2, and 7). Leave this pin open. (Note 5) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: This is applied when “H ” level is input to pin BYTE. 4: This is applied when “H ” level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: this pin functions as an input port from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. 7: Set pin P42/φ1 as pin P42. (Clock φ1 output is disabled.) And then, for this pin, do the same handling as that for pins P43 to P47 and P5 to P8. Fig. 10 Examples of handling unused pins in memory expansion mode P42–P47, P5–P8 AVss VREF HOLD RDY Left open M37733MHBXXXFP HLDA Vcc Vss AVcc XOUT n When setting ports to input mode Left open P42–P47, P5–P8 AVs s VREF Left open Vss AVcc XOUT n When setting ports to output mode Left open Left open Vcc M37733MHBXXXFP BHE ALE HOLD RDY BHE ALE HLDA Appendix 7. Examples of handling unused pins

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1. In microprocessor mode Table 3 Examples of handling unused pins in microprocessor mode Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1 and 2). Leave this pin open. (Note 5) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: This is applied when “H ” level is input to pin BYTE. 4: This is applied when “H ” level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: this pin functions as an input port from reset until the processor mode is switched to the microprocessor mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. Pins P4 3–P4 7, P5–P8 ____ BHE (Note 3) ALE (Note 4) HLDA , φ1 X OUT (Note 6) HOLD , RDY AVcc AVss, VREF Fig. 11 Examples of handling unused pins in microprocessor mode P43–P47, P5–P8 AVss VREF HOLD RDY Left open M37733MHBXXXFP HLDA Vcc Vss AVcc XOUT n When setting ports to input mode Left open P43–P47, P5–P8 AVs s VREF Left open Vss AVcc XOUT n When setting ports to output mode Left open Left open Vcc M37733MHBXXXFP BHE ALE HOLD RDY BHE ALE HLDA φ1 φ1 Appendix 7. Examples of handling unused pins

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Appendix 8. Countermeasure examples against noise General countermeasure examples against noise are described below. Although the effect of these countermeasures depends on each system, refer to the following when a noise-related problem occurs. 1. Shortest wiring length The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer. (1) Wiring for pin RESET Make the length of wiring connected to pin RESET as short as possible. In particular, connect a capacitor between pin RESET and pin Vss with the shortest possible wiring (within 20 mm). Reason If noise is input to pin RESET, the microcomputer restarts operation before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Fig. 12 Wiring for pin RESET RESETReset circuit Noise VssVss Vss M37733MHBXXXFP Not acceptable Reset circuit RESET VSS M37733MHBXXXFP Acceptable Appendix 8. Countermeasure examples against noise

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(2) Wiring for clock I/O pins l Make the length of wiring connected to clock I/O pins as short as possible. l Make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator and pin Vss of the microcomputer, as short as possible (within 20 mm). l Separate the Vss pattern only for oscillation from all other Vss patterns. (Refer to Figure 21.) Reason The microcomputer’s operation synchronizes with a clock generated by the oscillation circuit. If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or a program runaway. Also, if the noise causes a potential difference between the Vss level of the microcomputer and the Vss level of an oscillator, the correct clock will not be input in the microcomputer. (3) Wiring for pin CNVss Connect pin CNVss to pin Vss with the shortest possible wiring. Reason The processor mode of the microcomputer is influenced by a potential at pin CNVss when pin CNV SS and pin VSS are connected. If the noise causes a potential difference between the two pins, the processor mode may become unstable. This may cause a malfunction or a program runaway. Fig. 13 Wiring for clock I/O pins Fig. 14 Wiring for pin CNVss Noise CNVss Vss CNVss Vss Not acceptable Acceptable M37733MHBXXXFP M37733MHBXXXFP Noise XIN XOUT Vss XIN XOUT Vss Not acceptable Acceptable M37733MHBXXXFP M37733MHBXXXFP Appendix 8. Countermeasure examples against noise

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(4) Wiring to pin CNVss [In single-chip and memory expansion modes] l Connect pin CNVss to pin Vss of the microcomputer with the shortest possible wiring. l If the above countermeasure cannot be taken, insert an approximate 5 kΩ resistor between pins CNVss and Vss and, again, make the distance between the resistor and pin CNVss as short as possible. [In microprocessor mode] l Connect pin CNVss to pin Vcc with the shortest possible wiring. Reason Pin CNVss is connected to the internal ROM in the low-impedance state. (Noise is easily to be fed to the pin in this condition.) If noise enters pin CNVss, incorrect instruction codes or data are fetched from the built-in PROM. This may cause a program runaway. Fig. 15 Built-in PROM version: Wiring for pin CNVss Microprocessor mode CNV SS VCC Shortest possible wiring Approx. 5 KΩ Pin CNVss is connected to pin Vss with the shortest possible wiring. CNV SS VSS Single-chip and Memory expansion modes M37733EHBXXXFP h The above countermeasure is not necessary for pin BYTE. M37733EHBXXXFP Pin CNVss is connected to pin Vcc with the shortest possible wiring. Shortest possible wiring Appendix 8. Countermeasure examples against noise

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1. Connection of bypass capacitor between Vss line and Vcc line Connect an approximate 0.1 µF bypass capacitor as follows: l Connect a bypass capacitor between pin Vss and pin Vcc, at equal lengths. l The wiring connecting the bypass capacitor between pin Vss and pin Vcc should be as short as possible. l Use thicker wiring for the Vss and Vcc lines than for the other signal lines. Bypass capacitor VccVss M37733MHBXXXFP Wiring pattern Wiring pattern Fig. 16 Bypass capacitor connection Appendix 8. Countermeasure examples against noise

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Appendix 8. Countermeasure examples against noise 3. Wiring for analog input pins, analog power source pins, etc. (1) Processing analog input pins l Connect a resistor to the analog signal line, which is connected to an analog input pin, in series. Additionally, connect the resistor to the microcomputer as close as possible. l Connect a capacitor between pin AVss and the analog input pin, as close to pin AVss as possible. Reason A signal which is input to the analog input pin is usually an output signal from a sensor. The sensor, which detects changes in status, is installed far from the printed circuit board. Therefore, this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer. If a capacitor between an analog input pin and pin AVss is grounded far away from pin AVss, noise on the GND line may enter the microcomputer through the capacitor. Fig. 17 Countermeasure example against noise for analog input pin using thermistor AN i AVss Thermistor Noise M37733MHBXXXFP RI CI Reference values@ RI: Approximate 100 Ω to 1000 Ω CI: Approximate 100 pF to 1000 pF Notes 1: Design an external circuit for pin ANi so that charge/discharge is available within 1 cycle of AD . 2: This resistor and the thermistor are used to divide resistance. (Note 2j Not acceptable Acceptable Acceptable

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(2) Processing for analog power source pins, etc. l Use independent power sources for pins Vcc, AVcc and VREF . l Insert capacitors between pins AVcc and AVss, and between pins VREF and AVss, respectively. Reasons: Prevents noise from affecting the A-D converter on the Vcc line. AVcc AVss M37733MHBXXXFP Reference values C1 0.47 F C2 0.47 F Note : Connect capacitors using the thickest, shortest wiring possible. VREF AN i C1 C2 (sensor, etc.) Fig. 18 Processing for analog power source pins, etc. Appendix 8. Countermeasure examples against noise

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1. Oscillator protection The oscillator, which generates the basic clock for the microcomputer operations, must be protected from the affect of other signals. (1) Distance oscillator from signal lines with large current flows l Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. Reason The microcomputer is used in systems which contain signal lines for controlling motors, LEDs, thermal heads, etc. Noise occurs due to mutual inductance when a large current flows through the signal lines. (2) Distance oscillator from signal lines with frequent potential level changes l Install an oscillator and a connecting pattern away from signal lines in which potential levels change frequently. l Do not cross these signal lines over clock- related or noise-sensitive signal lines. Reason Signal lines with frequently changing potential levels may affect other signal lines at the rising or falling edge. In particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. Fig. 19 Wiring for signal lines with large current flows Fig. 20 Wiring for signal lines with frequent potential level changes XIN XOUT Vss M M37733MHBXXXFP Mutual inductance Large current GND XIN XOUT Vss hDo not cross. h I/O pin for signal with frequently changing potential levels. M37733MHBXXXFP Appendix 8. Countermeasure examples against noise

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(3) Oscillator protection using Vss pattern Print a Vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. Connect the Vss pattern to pin Vss of the microcomputer with the shortest possible wiring, separating it from other Vss patterns. Fig. 21 Vss pattern underneath mounted oscillator XIN XOUT Vss An example of Vss pattern on the underside of an oscillator Mounted pattern example of an oscillator unit Separate Vss lines for oscillation and supply. M37733MHBXXXFP Appendix 8. Countermeasure examples against noise

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1. Setup for I/O ports Setup for I/O ports is follows: <Hardware> l Connect a resistor of 100 Ω or more to an I/O port in series. <Software> l Read the data of an input port several times to confirm that input levels are equal. l Periodically rewrite data to the output port’s Pi register, as the data may reverse due to noise. l Rewrite data to port Pi direction registers periodically. Noise Direction register Port latch Data bus Port Fig. 22 Setup for I/O ports Appendix 8. Countermeasure examples against noise

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1. Reinforcement of the power source line l For the Vss and Vcc lines, use thicker wiring than that of other signal lines. l When using a multilayer printed circuit board, the Vss pattern and the Vcc pattern must each be one of the middle layers. l The following is necessary for double-sided printed circuit boards:

• On one side, the microcomputer is installed at the center, and the Vss line is looped or meshed around it. The vacant area is filled with the Vss line.
• On the opposite side, the Vcc line is wired the same as the Vss line.
• The power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputer’s power source lines with the shortest possible wiring. Reasons With external devices connected to the microcomputer, the levels of many of the signal lines (total external address buses: 24 bits) may change simultaneously, causing noise on the power source line. Appendix 8. Countermeasure examples against noise

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Appendix 9. Q & A Information which may be helpful in fully utilizing the 7733 Group is provided in Q & A format. In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each page is a question, and a box below the question is its answer. (If a question or an answer extends to two or more pages, there is a page number at the lower right corner.) At the upper right corner of each page, the main function related to the contents of description in that page is listed. Appendix 9. Q & A

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Q (1/2) If an interrupt request (b) occurs while an interrupt routine (a) is executed, is it true that the main routine is not executed at all from when the execution of the interrupt routine (a) is completed until the execution of the INTACK sequence for the next interrupt (b) starts? Conditions: l I = 0 by executing the RTI instruction l Interrupt priority level of interrupt (b) is higher than IPL of main routine. l Interrupt priority level detection time = 2 cycles of φ A An interrupt request is sampled by detecting a sampling pulse which is generated synchronously with the CPU ’s op-code fetch cycle. (1) If the next interrupt request (b) occurs before sampling pulse À of the RTI instruction is generated, sampling for this interrupt request is completed while the RTI instruction is executed. Therefore, the INTACK sequence for (b) is executed without executing the main routine. (Even one instruction is not executed.) Interrupt routine (a) Main routine INTACK sequence(b) S equence of execution ?RTI instruction INTACK sequence for (b) Interrupt request (b) Interrupt routine (a) Sampling pulse RTI instruction Appendix 9. Q & A À

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A (2) If the next interrupt request (b) occurs immediately after sampling pulse À is generated, this interrupt request is sampled when sampling pulse \` for the next instruction is generated. There- fore, one instruction in the main routine is executed, and then the INTACK sequence for (b) is executed. (2/2) Main routine Interrupt request (b) Sampling pulse INTACK sequence for (b) One instruction is executed. À Interrupt routine (a) RTI instruction Appendix 9. Q & A

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Suppose that there is a routine where a certain interrupt request should not be accepted. (The other interrupt requests are acceptable.) Although when the interrupt priority level selection bits for the above interrupt are set to “0002,” in other words, when this interrupt is set to be disabled, this interrupt request is actually accepted immediately after the change of the priority level. Why did this occur and what should I do about it? Interrupt request is accepted in this interval CLB #07H, XXXIC ;The interrupt priority level selection bits are set to “0002” ; or the interrupt request bit is set to “0.” LDA A,DATA ; The first instruction of a routine where a certain interrupt request should not be accepted As for the change of the interrupt priority level, when the following are met, the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled:

• The next instruction (in the above example, it is the LDA instruction) is already stored into a instruc- tion queue buffer for the BIU.
• Conditions for accepting the instruction which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed. When writing to the memory • I/O, the CPU transfers an address and data to the BIU. And then, the CPU executes the next instruction in the instruction queue buffer while the BIU is writing the data into the actual address. Interrupt priority level is determined at the start of each instruction. In the above case, the CPU executes the next instruction before the BIU completes the change of the interrupt priority level. Therefore, when the interrupt priority level is detected synchronously with the execution of the next instruction, the interrupt priority level before the change is detected and its interrupt request is accepted. Q A (1/2) Previous instruction is executed. (Instruction is prefetched.) CPU operation BIU operation Interrupt priority detection time Sequence of execution Interrupt priority level selection bits are set. Change of interrupt priority levels is completed Interrupt request is accepted. Interrupt request is generated. CLB instruction is executed. LDA instruction is executed. Appendix 9. Q & A

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A To solve this problem, make sure that, by software, the execution of a routine where a certain interrupt request should not be accepted starts after the change of the interrupt level is completed. The following lists a sample program. [Sample program] After an instruction which writes value “0002” to the interrupt priority level selection bits, fill the instruction queue buffer with several NOP instructions and make the next instruction not to be ex- ecuted until the writing is completed. CLB #07H, XXXIC ; The interrupt priority level selection bits are set to “0002.” NOP ; NOP ; NOP ; LDA A,DATA ; The first instruction of a routine where a certain interrupt request should not be accepted (2/2) Appendix 9. Q & A

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Q (1) If the edge sense or level sense is selected, an external interrupt request occurs when the level ____ of an input signal on the INTi pin changes. This is independent of clock φ1. At this time, if the edge sense is selected, the interrupt request bit is set to “1,” also. (2) There are two methods: one is the method to use the external interrupt’s level sense; the other one is the method to use the timer’s event counter mode. À Method to use the external interrupt’s level sense As for hardware, input a logical sum of several interrupt signals (for example, ‘a’, ‘b’, and ‘c’) ____ to the INTi pin and input each signal to the corresponding port. ____ As for software, check the ports’ input levels in an INTi interrupt routine in order to detect a signal (one of signals ‘a,’ ‘b,’ and ‘c’) which is input. A (1) ____ At what timing of clock φ1 is an external interrupt (an input signal on the INTi pin) detected? (2) ____ Suppose that more than three external interrupt input pins (INTi) are necessary, what should I do? \` Method to use the timer’s event counter mode As for hardware, input an interrupt signal to the TAi IN or TBiIN pin. As for software, set the timer’s operating mode to the event counter mode and set value “000016” to the timer. Furthermore, select a valid edge. The timer’s interrupt request occurs when an interrupt signal (selected valid edge) is input. Note : The same process can be realized by using the key input interrupt function, also. M37733MHBXXXFP Port Port Port INTi a b c Appendix 9. Q & A

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Serial I/O (UART mode) Q ____ If the CTS function is selected in UART (clock asynchronous serial I/O) mode, at what timing should ____ the CTS input’s level be checked by the transmitter? A Checked near the middle of the stop bit (if two stop bits are selected, the second stop bit). D 6Transmit data n: 1-bit length Input level on CTS i pin is checked near this timing. nn n n/2 n/2 D 6Transmit data Input level on CTS i pin is checked near this timing. nn n/2 n/2 Appendix 9. Q & A

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If “L” level is input to the HOLD pin, when is a bus actually opened? A Q Interval while bus is open Clock 1 HOLD HLDA tpxz(HOLD-PZ): Maximum of 50 ns When interval 50 ns (max.) has passed since clock φ1 is risen immediately after the HLDA pin’s output becomes “L,” a bus is opened. Appendix 9. Q & A

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A Although when the processor mode bits are set in order to switch the processor mode, as described above, the mode is not switched until the write cycle for the processor mode bits is completed. (The processor mode is actually switched simultaneously with the write cycle’s completion.) At this time, the program counter indicates the address which is next to the address (address XXXX16) where the write instruction for the processor mode bits is stored. Also, access to the internal ROM area is disabled. Note that there is a possibility that less than four bytes of instructions are prefetched into instruction queue buffers. Therefore, the address which resides in the external ROM area and is accessed first after the mode is switched is one of addresses “XXXX 16 + 1” to “XXXX16 4.” Note also that instructions at addresses “XXXX16 1” to “XXXX16 3” in the internal ROM area may be executed. To solve this problem, do the following processes by software. [Process À ] Program a write instruction for the processor mode bits and the following instructions (at least three bytes) to the same addresses of the internal ROM and external ROM areas. (See below.) [Process \` ] Transfer a write instruction for the processor mode bits to an internal RAM area and make the program branch to the address in order to execute the write instruction. And then, make the program branch to the program address in the external ROM area. (Contents of instruction queue buffers are initialized by a branch instruction.) LD M , B #00000010B, PM R NO P NO P NO P LD M , B #00000010B, PM R NO P NO P NO P XXXX 16 External ROM areaInternal ROM area XXXX 16 At least three When the processor mode is switched, as described below, by setting the processor mode bits (bits 1 and 0 at address 5E16) while a program is executed, is there any precaution on software? Single-chip mode Å Microprocessor mode Memory expansion mode Microprocessor mode Q Appendix 9. Q & A + +

7733 Group User’s Manual21-80

Appendix 9. Q & A À Use the STA and LDM instructions for setting the registers or the bits listed below. Do not use read-modify-write instructions (for example, CLB, SEB, INC, DEC, ASL, LSR, ROL, and ROR ). UART0 baud rate register (address 3116) UART1 baud rate register (address 3916) UART2 baud rate register (address 6516) UART0 transmission buffer register (addresses 3316, 3216) UART1 transmission buffer register (addresses 3B16, 3A16) UART2 transmission buffer register (addresses 6716, 6616) Timer A4 two-phase pulse signal processing selection bit (bit 7 at address 4416) Timer A3 two-phase pulse signal processing selection bit (bit 6 at address 4416) Timer A2 two-phase pulse signal processing selection bit (bit 5 at address 4416) \` When writing data to the oscillation circuit control register 1 (address 6F16), be sure to follow the procedure shown below.

• When initializing the clock prescaler Write data “8016.” (LDM instruction) Clock prescaler is reset.
• When writing to bits 0 to 2 Write data “010101012.” (LDM instruction) Write data “00001555 2.” (LDM instruction) (Note) Bits 0 to 2 are set. Note: In the case of the 7735 Group, write data “00000555 2.” ´ When writing data to the memory allocation control register (address 6316), be sure to follow the procedure shown below. Write data “010101012.” (LDM instruction) Write data “00000555 2.” (LDM instruction) Bits 0 to 2 are set. SFR Q Is there any SFR where a certain write instruction can not be used? A Next instruction Next instruction

7733 Group User’s Manual 21-81

Q Is there any precaution when debugging? A Some functions of the 7733 Group cannot be evaluated by a debugger. For the operations listed below, use the built-in PROM version to make full evaluation. When debugging, be sure to read the user’s manual supplied with the debugger. <<Operation examples that cannot be evaluated by a debugger>> À Operation when the signal output disable selection bit (bit 6 at address 6C16) = “1” \` Operation when the stand-by state selection bit (bit 0 at address 6D16) = “1” ´ Operations for reading from and writing to addresses 0216 to 0916 in the memory expansion or microprocessor mode Appendix 9. Q & A

7733 Group User’s Manual21-82

Appendix 9. Q & A Q Questions about the memory allocation selection function are described below: À For what purpose is this function used? \ Is there any precaution on use of this function? Memory À This function is used in order to secure an external memory area to bank 016 in the memory expansion mode. If there is an external device which is frequently accessed, this device’s memory allocation in bank 16 is effective for accessing this device, as well as internal RAM and SFR, with using DPR and DT efficiently. In the M37733MHBXXXFP, all of bank 016 is specified as an area for internal resources. Therefore, this function is used to secure an external memory area in bank 016. Note that the memory allocation selection bits are valid in the single-chip mode, also. In the single- chip mode, the memory allocation selection function is valid only for reduction of usable ROM area. Therefore, in the single-chip mode, we recommend to set these bits to “000 2” (the state immedi- ately after reset) and not to change them. \ Note the following:

• When changing the memory allocation selection bits, follow the procedure in Figure 2.4.1.
• When changing the memory allocation selection bits, make sure that the change is done within an area which is in the internal ROM area both of after and before the change, for example addresses 00C000 16 to 00FFFF16.
• We recommend to set the memory allocation selection bits only when a processor mode is set after reset and not to change them after this setting.
• When programming to the EPROM and one time PROM versions, program to addresses listed in Table 19.1.3.
• As for debugging for an area in bank 016 or 116 which is specified as an external area, some considerations may be necessary. For details concerning the development support tools, refer to the respective operation manuals. A

CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) CHAPTER 3 PROGRAMMABLE I/O PORTS CHAPTER 4 INTERRUPTS CHAPTER 5 KEY INPUT INTERRUPT FUNCTION CHAPTER 6 TIMER A CHAPTER 7 TIMER B CHAPTER 8 SERIAL I/O CHAPTER 9 A-D CONVERTER CHAPTER 10 WATCHDOG TIMER CHAPTER 11 STOP AND WAIT MODES CHAPTER 12 CONNECTING EXTERNAL DEVICES CHAPTER 13 RESET CHAPTER 14 CLOCK GENERATING CIRCUIT CHAPTER 15 ELECTRICAL CHARACTERISTICS CHAPTER 16 STANDARD CHARACTERISTICS CHAPTER 17 APPLICATIONS CHAPTER 18 LOW VOLTAGE VERSION CHAPTER 19 BUILT-IN PROM VERSION CHAPTER 20 EXTERNAL ROM VERSION APPENDIX

7735 Group User’s Manual2

The differences between the 7735 Group and the 7733 Group are mainly described below. For the 7733 Group, refer to part “1. 7733 Group.” The 7735 Group differs from the 7733 Group in the following:

• External bus mode in the memory expansion mode and the microprocessor mode
• External memory area (The 7735 Group has the maximum of 1-Mbyte external memory area.)
• Setting conditions for bit 3 of the oscillation circuit control register 1 (In the 7735 Group, this bit must be “0.” Note that, in the one time PROM version and the EPROM version, this bit is automatically set to “1” after reset. Therefore, be sure to clear this bit to “0.”)
• Functions of pin E/RDE

1–2 7735 Group User’s Manual Concerning chapter “1. OVERVIEW,” the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter:

• “1.1 Performance overview”
• “1.2 Pin configuration”
• “1.3 Pin description” The following section of the 7735 Group is the same as that of the 7733 Group. Therefore, for this section, refer to part 1:
• “1.4 Block diagram” (page 1-11 in part 1)

Concerning section “1.1 Performance overview,” the 7735 Group differs from the 7733 Group in the following:

• Description of the memory expansion in Table 1.1.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “1.1 Performance overview” (page 1-3 in part 1) Table 1.1.1 M37735MHBXXXFP’s performance overview

Possible (Maximum of 1 Mbytes) Items Memory expansion

1–37735 Group User’s Manual Figure 1.2.1 shows the M37735MHBXXXFP pin configuration. Note: For the low voltage version, refer to chapter “18. LOW VOLTAGE VERSION.” Fig. 1.2.1 M37735MHBXXXFP pin configuration (Top view) 25 2726 28 3429 30 31 32 33 35 36 37 38 39 40 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 0/HOLDBYTECNV SS 4/AN 4/R XD 5/AN 5/AD TRG XD 6/AN 6/X COUT 7/AN 7/X CIN V SS AV SS V REF AV CC V CC 0/CTS 0/RTS 0/CLKS 1/CLK 2/R XD 0/CLKS 3/T XD P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 P00/CS0 P01/CS1 P02/CS2 P03/CS3 P04/CS4 P05/RSMP P06/A16 P07/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 80 79 78 77 76 75 74 73 72 71 69 68 67 66 6570 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A0/D0 P21/A1/D1 P22/A2/D2 P23/A3/D3 M37735MHBXXXFP 24P41/RDY P47 P46 P45 P44 P43 P42/ 1 1/AN 2/AN 2/CTS 3/AN 3/CLK RESET X IN X OUT E/RDE V SS 3/HLDA 2/ALE 1/WEH 0/WEL 7/A 7/D 6/A 6/D 5/A 5/D 4/A 4/D Outline 80P6N-A

1–4 7735 Group User’s Manual Concerning section “1.3 Pin description,” the 7735 Group differs from the 7733 Group in the following: ___

• “Description of pin E in Table 1.3.1”
• “Description of pins P00–P0 7, P20–P2 7 and P30–P3 3 in Table 1.3.2”
• “1.3.1 Examples of handling unused pins” The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “1.3 Pin description” (page 1-5 in part 1) Table 1.3.1 Pin description (1) Functions [Single-chip Mode] This pin outputs internal enable signal E . When E ’s level is “L,” the microcomputer reads data and instruction codes or writes data. Also, output of internal enable signal E can be stopped by software. [Memory Expansion Mode] [Microprocessor Mode] This pin outputs read enable signal RDE . This signal’s level is “L” in the data read period of the read cycle. Pin E Name Internal enable output Input/Output Output

1–57735 Group User’s Manual Input/Output I/O Output I/O I/O Output Pin P0 0–P0 7 CS 0–CS 4, RSMP , A16, A17 P2 0–P2 7 A 0/D0– A 7/D7 P3 0–P3 3 WEL , WEH , ALE, HLDA Table 1.3.2 Pin description (2) Functions [Single-chip Mode] Same as the 7733 Group. [Memory Expansion Mode] [Microprocessor Mode] These pins respectively output signals CS 0–CS 4, RSMP , and address’s high-order 2 bits (A16 and A17). l Signal CS 0–CS 4 These signals are the chip select signals. When the microcomputer accesses a certain area, the corresponding pin outputs “L” level. (Refer to Table 2.5.3.) l Signal RSMP This signal is the ready sampling signal and is used to generate signal RDY for accessing external memory area. [Single-chip Mode] Same as the 7733 Group. [Memory Expansion Mode] [Microprocessor Mode] Input/Output of data (D 0–D 7) and output of address’s low-order 8 bits (A0–A 7) are performed with the time sharing method. [Single-chip Mode] Same as the 7733 Group. [Memory Expansion Mode] [Microprocessor Mode] These pins respectively output signals WEL , WEH , ALE, and HLDA . l Signal WEL , WEH ____ Signal WEL is the write enable low signal. ____ Signal WEH is the write enable high signal. These signals’ levels are “L” in the data write period of the write cycle. The operations of these signals depend on the level of pin BYTE. (Refer to Table 12.1.1.) l Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. l Signal HLDA This signal informs the external whether the microcomputer enters the Hold state or not. In Hold state, pin HLDA outputs “L” level. Name I/O port P0 I/O port P2 I/O port P3

1–6 7735 Group User’s Manual The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user’s system. (1) In single-chip mode Table 1.3.4 Examples of handling unused pins in single-chip mode Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until the they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these ports function as input ports. Software reliability can be enhanced when the contents of the above ports ’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 2: This is applied when an external clock is input to pin X IN. Pins P0–P8 E X OUT (Note 2) AVcc AVss, VREF , BYTE Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). Leave this pin open. Connect this pin to pin Vcc. Connect these pins to pin Vss. Fig. 1.3.1 Examples of handling unused pins in single-chip mode P0–P8 AVss VREF BYTE M37735MHBXXXFP Vss AVcc E XOUT Left open When setting ports to input mode Vcc P0–P8 AVss VREF BYTE M37735MHBXXXFP Vss AVcc E XOUT Left open When setting ports to output mode Left open Vcc

1–77735 Group User’s Manual (2) In memory expansion mode Table 1.3.5 Examples of handling unused pins in memory expansion mode Pins P4 2–P4 7, P5–P8 (Note 5) WEH , WEL , RDE , HLDA, CS 0–CS 4, RSMP X OUT (Note 4) HOLD , RDY AVcc AVss, VREF Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open. (Note 3) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 4: This is applied when an external clock is input to pin X IN. 5: Set pin P42/φ1 as pin P42. (Clock φ1 output is disabled.) And then, for this pin, do the same handling as that for pins P43 to P47 and P5 to P8. Fig. 1.3.2 Examples of handling unused pins in memory expansion mode P42–P47, P5–P8 HOLD RDY M37735MHBXXXFP Vcc Vss AVcc XOUT CS 0–CS 4 P42–P47, P5–P8 HOLD RDY Vss AVcc XOUT CS 0–CS 4 Vcc M37735MHBXXXFP When setting ports to input mode When setting ports to output mode Left open Left open Left open Left open Left open AVss VREF AVss VREF WEH WEL RDE HLDA RSMP WEH WEL RDE HLDA RSMP

1–8 7735 Group User’s Manual (3) In microprocessor mode Table 1.3.6 Examples of handling unused pins in microprocessor mode Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open. (Note 3) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Pins P4 3–P4 7, P5–P8 WEH , WEL , RDE HLDA , φ1, CS 0–CS 4, RSMP X OUT (Note 4) HOLD , RDY AV CC AV SS , VREF Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the microprocessor mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. 4: This is applied when an external clock is input to pin XIN. Fig. 1.3.3 Examples of handling unused pins in microprocessor mode P43–P47, P5–P8 RSMP HOLD RDY M37735MHBXXXFP WEH WEL RDE HLDA Vcc Vss AVcc XOUT CS 0–CS 4 P43–P47, P5–P8 RSMP HOLD RDY Vss AVcc XOUT CS 0–CS 4 Vcc M37735MHBXXXFP When setting ports to input mode When setting ports to output mode Left open Left open Left open Left open Left open AVss VREF AVss VREF WEH WEL RDE HLDA

(CPU)

CENTRAL PROCESSING UNIT (CPU)

7735 Group User’s Manual2–2

Concerning chapter “2. CENTRAL PROCESSING UNIT (CPU),” the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter:

• “2.2 Bus interface unit”
• “2.3 Accessible area”
• “2.5 Processor modes” The following sections of the 7735 Group are the same as those of the 7733 Group. Therefore, for these section, refer to part 1:
• “2.1 Central processing unit” (page 2–2 in part 1)
• “2.4 Memory allocation” (page 2–18 in part 1)

Concerning section “2.2 Bus interface unit,” the 7735 Group differs from the 7733 Group in the following.

• External buses in Figure 2.2.1
• Signal names in Figure 2.2.3 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “2.2 Bus interface unit” (page 2–10 in part 1)

CENTRAL PROCESSING UNIT (CPU)

7735 Group User’s Manual 2–3

Fig. 2.2.1 Buses and bus interface unit (BIU) M37735MHBXXXFP A and A A to A 8/D A 7/D 7 to A 0/D Internal bus D to D Central processing unit (CPU) SFR : Special Function Register Notes 1: CPU bus, internal bus, and external bus are independent of each other. For details about signals on the external buses, refer to chapter “12. CONNECTING EXTERNAL DEVICES.” Internal bus A to A External devices Internal control signals CPU bus Internal bus Internal bus D 7 to D Internal memory Internal peripheral devices(SFR) External busControl signals Bus interface unit(BIU) Bus conversion circuit

CENTRAL PROCESSING UNIT (CPU)

7735 Group User’s Manual2–4

Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU) RDE (a) RDE (b) AddressInternal address bus (A0 to A17) Data (Even address)Internal data bus (D0 to D 7) Data (Odd address) Internal data bus (D8 to D 15) Address (Odd address) Address (Even address) Data (Even address) Data (Odd address) Invalid data Invalid data Internal address bus (A0 to A17) Internal data bus (D0 to D 7) Internal data bus (D8 to D 15)

CENTRAL PROCESSING UNIT (CPU)

7735 Group User’s Manual 2–5

Concerning section “2.3 Accessible area,” the 7735 Group differs from the 7733 Group in the following:

• Accessible area which is allocated to addresses 016 to 0FFFFF16 (Maximum of 1 Mbytes)
• Figure 2.3.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “2.3 Accessible area” (page 2–16 in part 1)

Fig. 2.3.1 M37735MHBXXXFP’s accessible area 00000016 00008016 00FFFF 16 01000016 FE0000 16 FF000016 FFFFFF 16 00100016 02000016 000FFF 16 00007F16 01FFFF 16

• SFR : Special Function Register Notes 1: Banks 1016 to FF16 cannot be accessed. 2: Memory allocation of internal area in bank 016 depends on the microcomputer’s type and settings of the memory allocation selection bits. The above diagram shows the M37735MHBXXXFP’s accessible area immediately after reset. For the other microcomputers of the 7735 Group, refer to “Appendix 1. Memory allocation of 7735 Group.” For settings of the memory allocation selection bits, refer to section “2.4 Memory allocation.” SFR area Internal RAM area Bank 016 Internal ROM area Bank 116 Bank FF16 Bank FE16 represents the memory allocation of internal areas. indicates that nothing is allocated.

“Appendix 1. This applies when the contents of memory allocation selection bits (bits 2 to 0 at CENTRAL PROCESSING UNIT (CPU)

7735 Group User’s Manual2–6

Concerning section “2.5 Processor modes,” the 7735 Group differs from that of the 7733 Group in the following:

• “Fig. 2.5.1 Memory map in each processor mode ”
• “Fig. 2.5.2 Pin configuration in each processor mode (Top view)”
• “Table 2.5.1 Relationship between processor modes and functions of P0 to P4”
• “2.5.4 Relationship between access addresses and chip select signals (CS 0–CS 4) (This section is added in part 2.) The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “2.5 Processor modes ” (page 2–24 in part 1)

Fig. 2.5.1 Memory map in each processor mode (M37735MHBXXXFP ) Notes 1: represents external area. By accessing this area, an external device connected to the M37735MHBXXXFP can be accessed. address 6316) = “0002.” 3: For the other microcomputers of the 7735 Group, refer to section Memory allocation of 7735 Group.” 4: Banks 1016 to FF16 cannot be accessed. 00000016 01FFFF 16 00008016 02000016 FFFFFF 16 000FFF 16 00100016 0FFFFF 16 10000016 SFR area Internal ROM area Single-chip mode Internal RAM area SFR area Memory expansion mode SFR area Microprocessor mode Internal RAM area Internal RAM area Internal ROM area (Note 4) (Note 4)

CENTRAL PROCESSING UNIT (CPU)

7735 Group User’s Manual 2–7

Fig. 2.5.2 Pin configuration in each processor mode (Top view) : These pins’ functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. P24 P25 P26 P27 P30 P31 P32 P33 VSS E XOUT XIN RESET CNV SS BYTE P40 P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P41 P70/AN0 P67/TB2IN / SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN /KI3 P56/TA3OUT /KI2 P55/TA2IN /KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 14 325 P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 6789 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 M37735MHBXXXFP 22 23 24 P47 P46 P45 P44 P43 P42/ 1 ]1 Connect this pin to Vss in the single-chip mode. <Single-chip mode> A4/D4 A5/D5 A6/D6 A7/D7 WEL WEH ALE HLDA VSS RDE XOUT XIN RESET CNV SS BYTE HOLD RDY A11 /D11 A12 /D12 A13 /D13 A14 /D14 A15 /D15 A0/D0 A1/D1 A2/D2 A3/D3 P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 CS 0 CS 1 CS 2 CS 3 CS 4 RSMPA16 A17 A8/D8 A9/D9 14 32 56789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN / SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN /KI3 P56/TA3OUT /KI2 55/TA2IN /KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 40P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 M37735MHBXXXFP P47 P46 P45 P44 P43 P42/ 1 A10 /D10 <Memory expansion and Microprocessor modes> ]2 1 in the microprocessor mode : These pins’ functions in the single-chip mode differ from those in the memory expansion or microprocessor mode.

In the memory expansion mode, this pin functions as a programmable I/O port. Furthermore, it can be switched to be a clock These signals are affected by the signal output disable selection bit (bit 6 at address 6C CENTRAL PROCESSING UNIT (CPU)

7735 Group User’s Manual2–8

Table 2.5.1 Relationship between processor modes and functions of P0 to P4 Notes 1: When an internal area is accessed, signals CS 0 to CS 4 are not output. (The output level is fixed to “H.”) 2: 16). (Refer to chapter “12. CONNECTING EXTERNAL DEVICES.” ) 3: Pin P42 can also function as a clock 1 output pin. (Refer to chapter “12. CONNECTING EXTERNAL DEVICES.” ) 4: 1 output pin when selected by software. In the microprocessor mode, this pin is affected by the signal output disable selection bit (bit 6 at address 6C16). (Refer to chapter “12. CONNECTING EXTERNAL DEVICES.” ) D(even): Data at even address P05 HLDA P32 P33 A8 to A15 A16, A17P06 and P07 A8 to A15 A0 to A7 A0 to A7 D ALE HLDA P31 P33 (“H” level output) RSMP P RDYP41 E/RDE E RDE (Note 2) P P P P P P00 to P04 CS 0 to CS 4 (Note 1) P30 WEL (Note 2) P31 WEH (Note 2) P30 WEL (Note 2) P32 ALE HOLDP40 P42 1 (Note 4) (Note 2) D(odd): Data at odd address P43 to P47 Pin name Single-chip mode Memory expansion and Microprocessor modes Processor mode n When external data bus is 16 bits wide (BYTE = “L”) n When external data bus is 8 bits wide (BYTE = “H”) n When external data bus is 16 bits wide (BYTE = “L”) n When external data bus is 8 bits wide (BYTE = “H”) P: Functions as a programmable I/O port. P: Functions as a programmable I/O port. P: Functions as a programmable I/O port. P: Functions as a programmable I/O port. P: Functions as a programmable I/O port (Note 3). P: Functions as a programmable I/O port. n When external data bus is 16 bits wide (BYTE = “L”) n When external data bus is 8 bits wide (BYTE = “H”) D(odd) D(even) D: Data

CENTRAL PROCESSING UNIT (CPU)

7735 Group User’s Manual 2–9

2.5.4 Relationship between access addresses and chip select signals CS 0 to CS 4

Table 2.5.3 lists the relationship between access addresses and chip select signals CS 0 to CS 4. Table 2.5.4 lists the relationship between the memory allocation selection bits and addresses for chip select signals CS 0, CS 1 in the memory expansion mode. Table 2.5.3 Relationship between access addresses and chip select signals CS 0 to CS 4

03 FFFF 16

07 FFFF 16

The former half of bank 0016 except for internal memory area

• The latter half of bank 0016 except for internal memory area
• Banks 0116 to 0316 Banks 0416 to 0716 Banks 0816 to 0B16 Banks 0C 16 to 0F16 Memory expansion mode (Note) 02 0000 16 (Note) to

Note: This applies when each of bits 1 and 0 of the memory allocation control register (address 6316) = “0.” For details, refer to Table 2.5.4. Table 2.5.4 Relationship between memory allocation selection bits and addresses for chip select signals CS 0, CS 1 in memory expansion mode Access addresses CS 1 020000 16 to 03FFFF16 020000 16 to 03FFFF16 020000 16 to 03FFFF16 010000 16 to 03FFFF16 Memory allocation selection bits] Memory allocation selection bits] : Bits 0 to 2 of the memory allocation control register (address 6316) Internal ROM area 001000 16 to 01FFFF16 (124 Kbytes) 002000 16 to 01FFFF16 (120 Kbytes) 008000 16 to 01FFFF16 (96 Kbytes) 008000 16 to 00FFFF16 (32 Kbytes) CS 0 001000 16 to 001FFF16 001000 16 to 007FFF16 001000 16 to 007FFF16 Access addresses

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7735 Group User’s Manual2–10

3.4 Internal peripheral devices’ I/O functions (Ports P42 and P5 to P8)

7735 Group User’s Manual3–2

Concerning chapter “3. PROGRAMMABLE I/O PORTS,” the 7735 Group differs from the 7733 Group in the following section. Therefore, only the difference is described in this chapter:

• 3.2 Port peripheral circuits The following sections are the same as those of the 7733 Group. Therefore, for these sections, refer to part
• “3.1 Programmable I/O ports” (page 3-2 in part 1)
• “3.3 Pull-up function” (page 3-8 in part 1)
• “3.4 Internal peripheral devices’ I/O functions (Ports P42 and P5 to P8)” (page 3-10 in part 1)

Concerning section “3.2 Port peripheral circuits,” the 7735 Group differs from the 7733 Group in the follow- ing:

• Pin E /RDE in Figure 3.2.2 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “3.2 Port peripheral circuits” (page 3-6 in part 1) Fig. 3.2.2 Port peripheral circuits (2)
• E / RDE Hold acknowledge

4.7 How interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) ____ interrupt)

4–2 Interrupts of the 7735 Group are the same as those of the 7733 Group. Therefore, for interrupts, refer to the corresponding sections in part 1:

• “4.1 Overview (page 4-2 in part 1)
• “4.2 Interrupt sources (page 4-4 in part 1)
• “4.3 Interrupt control (page 4-6 in part 1)
• “4.4 Interrupt priority level (page 4-10 in part 1)
• “4.5 Interrupt priority level detection circuit (page 4-11 in part 1)
• “4.6 Interrupt priority level detection time (page 4-13 in part 1)
• “4.7 How interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) (page 4-14 in part 1)
• “4.8 Return from interrupt routine (page 4-17 in part 1)
• “4.9 Multiple interrupts (page 4-17 in part 1) ____
• “4.10 External interrupts (INTi interrupt) (page 4-19 in part 1)
• “4.11 Precautions for interrupts (page 4-23 in part 1)

7735 Group User’s Manual5-2

KEY INPUT INTERRUPT FUNCTION The key input interrupt function of the 7735 Group is the same as that of the 7733 Group. Therefore, the key input interrupt function, refer to the corresponding sections in part 1:

• “5.1 Overview (page 5-2 in part 1)
• “5.2 Block description (page 5-3 in part 1)
• “5.3 Initial setting example for related registers (page 5-7 in part 1)

(PWM) mode

7735 GROUP USER’S MANUAL6-2

Timer A of the 7735 Group is the same as that of the 7733 Group. Therefore, for timer A, refer to the corresponding sections in part 1:

• “6.1 Overview” (page 6-2 in part 1)
• “6.2 Block description” (page 6-3 in part 1)
• “6.3 Timer mode” (page 6-9 in part 1)
• “6.4 Event counter mode” (page 6-19 in part 1)
• “6.5 One-shot pulse mode” (page 6-32 in part 1)
• “6.6 Pulse width modulation (PWM) mode” (page 6-41 in part 1)

7735 GROUP USER’S MANUAL7-2

Timer B of the 7735 Group is the same as that of the 7733 Group. Therefore, for timer B, refer to the corresponding sections in part 1:

• “7.1 Overview” (page 7-2 in part 1)
• “7.2 Block description” (page 7-3 in part 1)
• “7.3 Timer mode” (page 7-10 in part 1)
• “7.4 Event counter mode” (page 7-17 in part 1)
• “7.5 Pulse period/Pulse width measurement mode” (page 7-25 in part 1)
• “7.6 Clock timer” (page 7-34 in part 1)

I/O (UART) mode

7735 Group User’s Manual8–2

The serial I/O of the 7735 Group is the same as that of the 7733 Group. Therefore, for serial I/O, refer to the corresponding sections in part 1:

• “8.1 Overview” (page 8-2 in part 1)
• “8.2 Block description” (page 8-4 in part 1)
• “8.3 Clock synchronous serial I/O mode” (page 8-21 in part 1)
• “8.4 Clock asynchronous serial I/O (UART) mode” (page 8-44 in part 1)

Differential non-linearity error 9.9 Precautions for A-D converter

7735 Group User’s Manual9–2

The A-D converter of the 7735 Group is the same as that of the 7733 Group. Therefore, for the A-D converter, refer to the corresponding sections in part 1:

• “9.1 Overview” (page 9-2 in part 1)
• “9.2 Block description” (page 9-3 in part 1)
• “9.3 A-D conversion method” (page 9-11 in part 1)
• “9.4 Absolute accuracy and Differential non-linearity error” (page 9-14 in part 1)
• “9.5 One-shot mode” (page 9-17 in part 1)
• “9.6 Repeat mode” (page 9-20 in part 1)
• “9.7 Single sweep mode” (page 9-23 in part 1)
• “9.8 Repeat sweep mode” (page 9-27 in part 1)
• “9.9 Precautions for A-D converter” (page 9-31 in part 1)

10.3 Precautions for watchdog timer

7735 Group User’s Manual10-2

Concerning chapter “10. WATCHDOG TIMER,” the 7735 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter:

• “10.2 Operation description” The following sections are the same as those of the 7733 Group. Therefore, for these sections, refer to part
• “10.1 Block description” (page 10-2 in part 1)
• “10.3 Precautions for watchdog timer” (page 10-10 in part 1)

Concerning section “10.2 Operation description,” the 7735 Group differs from the 7733 Group in the following:

• Figures 10.2.2 and 10.2.3 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “10.2 Operation description” (page 10-5 in part 1)

7735 Group User’s Manual 10-3

Fig. 10.2.2 Structure of oscillation circuit control register 1 Fig. 10.2.3 Procedure for writing data to oscillation circuit control register 1 In the M37735MHBXXXFP, set bit 3 of the oscillation circuit control register 1 to “0.” Write data “010101012.” (LDM instruction)

• When writing to bits 0 to 3 Write data “00000XXX2.” (LDM instruction) Next instruction (b3 in Figure 10.2.2) (b2 to b0 in Figure 10.2.2) 2: Because this bit is “1” at reset, clear this bit to “0” with the initial setting program after reset. 3: The case where data “010101012” is written with the procedure shown below is not included. 4: For the 7733 Group, refer to Figure 14.3.3 in part 1. 5: represents that bits 3 to 7 are not used for the watchdog timer. /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Bit Bit name Functions At reset RW Main clock division selection bit Sub clock external input selection bit Must be fixed to “0” in the one time PROM and EPROM versions (Notes 1 and 2). Must be fixed to “0” (Note 3). Clock prescaler reset bit Undefined Oscillation circuit control register 1 (address 6F16) 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT . Watchdog timer is used when terminating stop mode. 1: Sub clock is input fro m the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. RW RW RW RW WO —Not implemented. Not implemented. /LiteDiagLines b1 b0b2b3b4b5b6b7 Notes 1: When writing to this register, follow the procedure shown below. By writing “1” to this bit, clock prescaler is initialized. RW (Note 4) Undefined Main clock external input selection bit 0: Main clock is divided by 2. 1: Main clock is not divided by 2. 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. Must be fixed to “0” in the mask ROM and external ROM versions (Note 1). (Note 1) (Note 1) (Note 1)

7735 Group User’s Manual10-4

7735 Group User’s Manual11–2

Concerning chapter “11. STOP AND WAIT MODES,” the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter:

• “11.2 Clock generating circuit”
• “11.3 Stop mode”
• “11.4 Wait mode” The following section of the 7735 Group is the same as that of the 7733 Group. Therefore, for this section, refer to part 1:
• “11.1 Overview” (page 11-2 in part 1)

Concerning section “11.2 Clock generating circuit,” the 7735 Group differs from the 7733 Group in the following:

• Figures 11.2.3 and 11.2.4 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “11.2 Clock generating circuit” (page 11-3 in part 1) In the M37735MHBXXXFP, be sure to set bit 3 of the oscillation circuit control register 1 to “0.” Fig. 11.2.3 Structure of oscillation circuit control register 1 2: Because this bit is “1” at reset, clear this bit to “0” with the initial setting program after reset. 3: The case where data “010101012” is written with the procedure shown in Figure 11.2.4. is not included. 4: For the 7733 Group, refer to Figure 11.2.3 in part 1. 5: represents that bits 3 to 7 are not used for the stop and wait modes. Bit Bit name Functions At reset RW Main clock division selection bit Sub clock external input selection bit Must be fixed to “0” in the one time PROM and EPROM versions (Notes 1 and 2). Must be fixed to “0” (Note 3). Clock prescaler reset bit Undefined Oscillation circuit control register 1 (address 6F16) 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT . Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. RW RW RW RW WO —Not implemented. Not implemented. b1 b0b2b3b4b5b6b7 Notes 1: When writing to this register, follow the procedure shown in Figure 11.2.4. By writing “1” to this bit, clock prescaler is initialized. RW (Note 4) Undefined Main clock external input selection bit 0: Main clock is divided by 2. 1: Main clock is not divided by 2. 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. Must be fixed to “0” in the mask ROM and external ROM versions (Note 1). (Note 1) (Note 1) (Note 1)

7735 Group User’s Manual 11–3

Fig. 11.2.4 Procedure for writing data to oscillation circuit control register 1 Concerning section “11.3 Stop mode,” the 7735 Group differs from the 7733 Group in the following:

• Table 11.3.2 and Figure 11.3.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “11.3 Stop mode” (page 11-6 in part 1) Write data “010101012.” (LDM instruction)
• When writing to bits 0 to 3 Write data “00001XXX2.” (LDM instruction) Next instruction (b3 in Figure 11.2.3) (b2 to b0 in Figure 11.2.3)

7735 Group User’s Manual11–4

Table 11.3.2 Pin state in stop mode State Single-chip mode Memory expansion Microprocessor mode mode Pins When the standby state selection bit∗1 = “0” When the standby state selection bit ∗1 = “1” n When the signal output disable selection bit = “0,” “H” level is output n When the signal output disable selection bit = “1,” “L” level is output. n When the signal output disable selection bit = “0,” “H” level is output. n When the signal output disable selection bit = “1,” “L” level is output. Same as in the micro- processor mode “H” level is output. E ____ RDE, ____ WEL, ____ WEH, CS 0–CS 4, RSMP, HLDA ALE A 0/D0–A 15/D15, A 16, A17 Output levels can be set. (Refer to section “11.3.1 Output levels of external bus and bus control signals in stop mode.”) “L” level is output. n When the clock φ1 output selection bit*2 = “1” φ1: “L” level is output. n When the clock φ1 output selection bit = “0” P42: Retains the same state in which the STP instruction is executed. Retains the same state in which the STP instruction is executed. n When the signal output disable selection bit *3 = “0” φ1: “L” level is output. n When the signal output disable selection bit = “1” 2: Bit 2’s value of the port P4 register is output (Note). P0 to P8 (not including P42) :Retains the same state in which the STP instruction is executed. P4 3 to P47, P5 to P8 :Retains the same state in which the STP instruction is executed. Ports P42/φ1 Standby state selection bit*1: Bit 0 at address 6D16 (Refer to Figure 11.3.1.) Clock φ1 output selection bit*2: Bit 7 at address 5E16 (Refer to section “12.1 Signals required for accessing external devices.”) Signal output disable selection bit*3: Bit 6 at address 6C16 (Refer to section “12.1 Signals required for accessing external devices.”) Note: Make sure to set bit 2 of the port P4 direction register to “1.”

7735 Group User’s Manual 11–5

Fig. 11.3.1 Output level setting example in stop mode (Memory expansion or Microprocessor mode) executed. Note 2: This bit’s value also affects the pin state in the wait mode. (Refer to Figure 11.4.1.) Setting of the output levels for the external bus, chip select signals, and bus control signals (not including RDE ) b7 b0 Port P0 direction register (address 416) Port P1 direction register (address 516) Port P2 direction register (address 816) Port P3 direction register (address 916) Must be fixed to “FF16.” 1 1 11111 1 b7 b0 Set output level by the bit which corresponds to each pin. 0: “L” level output 1: “H” level output Note 3: This bit's value also affects the following:

• Output state of bus control signals and others after the stop mode is terminated (Refer to chapter “12. CONNECTING EXTERNAL DEVICES”)
• Pin state in the wait mode. (Refer to Figure 11.4.1.) Furthermore, description of pin P42/ 1 is applied only in the microprocessor mode. Setting of RDE signal’s output level (Setting of pin P42/ 1’s state) b7 b0 Oscillation circuit control register 0 (address 6C16) Signal output disable selection bit (Note 3) 0: In the stop mode, pin E/RDE outputs “H” level, and pin P42/ 1 outputs “L” level. 1: In the stop mode, pin E/RDE outputs “L” level, and pin P42/ 1 outputs bit 2’s value of port P4 register. Port function control register (address 6D16) Standby state selection bit (Note 2) b7 b0 Setting of the standby state selection bit to “1” b7 b0 Port P4 direction register (address C16)1 b7 b0 Port P4 register (address A16) 0: “L” level output 1: “H” level output
• When setting the signal output disable selection bit to “1” in the microprocessor mode
• When setting the clock 1 output selection bit to “0” in the memory expansion mode
• When setting the signal output disable selection bit to “0” in the microprocessor mode
• When setting the clock 1 output selection bit to “1” in the memory expansion mode Note 1: This is applied only in the microprocessor mode. In the memory expansion mode, it may be “0” or “1” because the I/O port function is selected. (Note 1) Port P0 register (address 216) Port P1 register (address 316) Port P2 register (address 616) Port P3 register (address 716)

7735 Group User’s Manual11–6

Concerning section “11.4 Wait mode,” the 7735 Group differs from the 7733 Group in the following:

• Table 11.4.2 and Figure 11.4.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “11.4 Wait mode” (page 11-13 in part 1)

7735 Group User’s Manual 11–7

Table 11.4.2 Pin state in wait mode State Single-chip mode Memory expansion Microprocessor mode mode Pins When the standby state selection bit∗1 = “0” When the standby state selection bit ∗1 = “1” n When the signal output disable selection bit = “0,” “H” level is output. n When the signal output disable selection bit = “1,” “L” level is output. n When the signal output disable selection bit = “0,” “H” level is output. n When the signal output disable selection bit = “1,” “L” level is output. Same as in the micro- processor mode “H” level is output. E ____ RDE, ____ WEL, ____ WEH, CS 0–CS 4, RSMP, HLDA ALE A 0/D0–A 15/D15, A 16, A17 Output level can be set. (Refer to section “11.4.2 Output levels of external bus and bus control signals in wait mode”) “L” level is output. Retains the same state in which the WIT instruction is ex- ecuted. n When the signal output disable selection bit *3 = “0” φ1: Stopped when the system clock stop bit at wait state = “0.” “L” level is output when the system clock stop bit at wait state = “1.” n When the signal output disable selection bit = “1” P4 2: Bit 2’s value of port P4 register is output (Note). n When the clock φ1 output selection bit*2 = “1” φ1: Operating when the system clock stop bit at wait state*4 = “0.” “L” level is output when the system clock stop bit at wait state = “1.” n When the clock φ1 output selection bit = “0” P4 2: Retains the same state in which the WIT instruction is executed. P42/φ1 P0 to P8 (not including P4 : Retains the same state in which the WIT instruction is executed. 3 to P47, P5 to P8 : Retains the same state in which the WIT instruction is executed. Ports Standby state selection bit*1: Bit 0 at address 6D16 (Refer to Figure 11.4.1.) Clock φ1 output selection bit*2: Bit 7 at address 5E16 (Refer to section “12.1 Signals required for accessing external devices.”) Signal output disable selection bit*3: Bit 6 at address 6C16 (Refer to section “12.1 Signals required for accessing external devices.”) System clock stop bit at wait state*4: Bit 5 at address 6C16 (Refer to section “11.4.1 State of clocks f2 to f512 in wait mode.”) Note: Make sure to set bit 2 of the port P4 direction register to “1.”

7735 Group User’s Manual11–8

Fig. 11.4.1 Output level setting example in wait mode (Memory expansion or Microprocessor mode)

• When setting the signal output disable selection bit to “1” in the microprocessor mode
• When setting the clock 1 output selection bit to “0” in the memory expansion mode Note 2: This bit’s value also affects the pin state in the stop mode. (Refer to Figure 11.3.1.) Setting of the output levels for the external bus, chip select signals, and bus control signals (not including RDE) b7 b0 Port P0 direction register (address 416) Must be fixed to “FF16.” 11 11 11 11 Port P1 direction register (address 516) Port P2 direction register (address 816) Port P3 direction register (address 916) b7 b0 Port P0 register (address 216) Set output level by bit which corresponds to each pin. 0: “L” level output 1: “H” level output Port P1 register (address 316) Port P2 register (address 616) Port P3 register (address 716) Setting of E/RDE signal’s output level (Setting of pin P42/ 1’s state) b7 b0 Oscillation circuit control register 0 (address 6C16) Signal output disable selection bit (Note 3) 0: In the wait mode, pin E/RDE outputs “H” level. Pin P42/ 1 operates when system clock stop bit at wait state = “0” and outputs “L” level when this bit = “1.” 1: In the wait mode, pin E/RDE outputs “L” level. Pin P42/ 1 outputs bit 2’s value of port P4 register. Port function control register (address 6D16) Standby state selection bit (Note 2) b7 b0 Setting of standby state selection bit to “1” b7 b0 Port P4 direction register (address C16)1 b7 b0 Port P4 register (address A16) 0: “L” level output 1: “H” level output WIT instruction is executed. Note 3: This bit’s value also affects the following:
• Output state of bus control signals and others after the wait mode is terminated (Refer to chapter “12. CONNECTING EXTERNAL DEVICES.” )
• Pin state in the stop mode. (Refer to Figure 11.3.1.) Furthermore, description of pin P42/ 1 is applied only in the microprocessor mode.
• When setting the signal output disable selection bit to “0” in the microprocessor mode
• When setting the clock 1 output selection bit to “1” in the memory expansion mode Note 1: This is applied only in the microprocessor mode. In the memory expansion mode, it may be “0” or “1” because the I/O port function is selected. (Note 1)

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual12–2

Functions for connecting external devices are described in this chapter. Reading or writing data from or to external devices are performed by the bus interface unit (BIU). (Refer to section “2.2 Bus interface unit.”) The BIU operates on the basis of internal enable signal E (usually, internal clock φ divided by 2) but does not output internal enable signal E to the external. The BIU outputs signals RDE , WEL , and WEH . Signals RDE , WEL , and WEH are generated from internal enable signal E and are output at the same timing as that of internal enable signal E . When external devices are accessed, the BIU outputs some of these signals, in other words, outputs only signals which are required for the access at that time.

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual 12–3

Functions and operations of signals required for accessing external devices are described below. When connecting external devices which require a long access time, refer to sections “12.2 Software wait,” “12.3 Ready function,” and “12.4 Hold function,” also. When connecting external devices, make sure that the microcomputer operates in the memory expansion or microprocessor mode. (Refer to section “2.5 Processor modes.”) When the microcomputer operates in these modes, ports P0 to P4 and pin E/RDE function as I/O pins of signals required for accessing external devices. lists the functions of ports P0 to P4 and pin E/RDE in the memory expansion or microprocessor mode.

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual12–4

Fig. 12.1.1 Pin configuration in memory expansion or micropr ocessor mode (Top view) A4/D4(P24) A5/D5(P25) A6/D6(P26) A7/D7(P27) WEL(P3 0) WEH(P3 1) ALE(P32) HLDA(P3 3) Vss RDE XOUT XIN RESET CNV SS BYTE HOLD A11 /D11 (P13) A12 /D12 (P14) A13 /D13 (P15) A14 /D14 (P16) A15 /D15 (P17) A0/D0(P20) A1/D1(P21) A2/D2(P22) A3/D3(P23) RDY P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 CS 0(P00) CS 1(P01) CS 2(P02) CS 3(P03) CS 4(P04) RSMP(P0 5) A16 (P06) A17 (P07) A8/D8(P10) A9/D9(P11) A10 /D10 (P12) P70/AN0 P67/TB2IN SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN /KI3 P56/TA3OUT /KI2 P55/TA2IN /KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 14 325 P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 678 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 M37735 MHBXXXFP 22 23 24 P47 P46 P45 P44 P43 *1 P42/ A4/D4(P24) A5/D5(P25) A6/D6(P26) A7/D7(P27) WEL(P3 0) WEH(P3 1) ALE(P32) HLDA(P3 3) Vss RDE XOUT XIN RESET CNV SS BYTE HOLD RDY A11 (P13) A12 (P14) A13 (P15) A14 (P16) A15 (P17) A0/D0(P20) A1/D1(P21) A2/D2(P22) A3/D3(P23) P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 CS 0(P00) CS 1(P01) CS 2(P02) CS 3(P03) CS 4(P04) RSMP(P0 5) A16 (P06) A17 (P07) A8(P10) A9(P11) A10 (P12) 14 32 56789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN /KI3 P56/TA3OUT /KI2 55/TA2IN /KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 40P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 M37735 MHBXXXFP P47 P46 P45 P44 P43 P42/ When external data bus is 8 bits wide (BYTE = “H”) : External address bus, external data bus, chip select signals, and bus control signals h 1 in the microprocessor mode When external data bus is 16 bits wide (BYTE = “L”) : External address bus, external data bus, chip select signals, and bus control signals h 1 in the microprocessor mode By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin’s level can be fixed in the stop or wait mode. By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin’s level can be fixed in the stop or wait mode. h "H"level is output

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual 12–5

A8 to A15 D(odd) ALE A0/D0 to A7/D7 A8 to A15 A 0 to A7 D(even) A0 to A7 D D : Data ALE ALE RSMP P E/RDE RDE (Note 2) A8/D8 to A15/D15 P43 to P47 A0/D0 to A7/D7 A8 to A15 A0/D0 to A7/D7 (Note 3) ALE HLDA WEL HLDA P43 to P47 A 16, A17A 16, A17A16, A17 CS 0 to CS4 CS 0 to CS4 (Note 1)CS 0 to CS4 WEL WEL (Note 2) WEL (Note 2)WEL HLDAHLDA HLDA WEH WEH (Note 2) (“H” level output)WEHWEH RDYRDYRDY HOLDHOLDHOLD Pin name 16 bits (BYTE = “L”) 8 bits (BYTE = “H”) External data bus width Notes 1: When the internal area is accessed, signals CS 0 to CS 4 are not output. (Output levels are fixed to “H.”) 2: These signals are affected by the signal output disable selection bit (bit 6 at address 6C16). (Refer to Table 12.1.4.) 3: In the memory expansion mode, this pin functions as a programmable I/O port. Furthermore, it can be switched to be a clock 1 output pin when selected by software. In the microprocessor mode, this signal is affected by the signal output disable selection bit (bit 6 at address 6C16). (Refer to Table 12.1.3.) P : Functions as programmable I/O port D(odd) : Data at odd address D(even) : Data at even address Table 12.1.1 Functions of ports P0 to P4 and pin E/RDE in memory expansion or microprocessor mode

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual12–6

12.1.1 External bus (A0/D0 to A15/D15, A16 and A17) and chip select signals (CS 0 to CS 4)

The address (A0 to A 17) and chip select signals are output and specify the external area. Figures 12.1.2 and 12.1.3 show the external areas specified by these signals. An area specified by a chip select signal does not the internal area. (When the internal area is accessed, the chip select signal is not output.) Pins A8 to A15 of the external address bus and pins D0 to D15 of the external data bus share the same pins. When pin BYTE’s level, which is described later, is “L” (in other words, when the external data bus is 16 bits wide), pins A0/D0 to A15/D15 perform address output and data input/output with the time-sharing method. When pin BYTE’s level is “H” (in other words, when the external data bus is 8 bits wide), pins A0/ D 0 to A7/D7 perform address output and data input/output with the time-sharing method and pins A8 to A15 output the address. Fig. 12.1.2 External area (Memory expansion mode) : External area specified by address and chip select signal 00000016 00100016 Memory expansion mode (for M37735MHBXXXFP) 02000016 0FFFFF 16 04000016 08000016 0C0000 16 CS 1 CS 2 CS 3 CS 4 00008016 Memory allocation selection bits (b2,b1,b0) = 00000016 00100016 02000016 0FFFFF 16 04000016 08000016 0C0000 16 CS 1 CS 2 CS 3 CS 4 00008016 00200016 CS 0 (0,0,1) 00000016 00100016 02000016 0FFFFF 16 04000016 08000016 0C0000 16 CS 1 CS 2 CS 3 CS 4 00008016 00800016 CS 0 (1,1,0) 00000016 00100016 0FFFFF 16 04000016 08000016 0C0000 16 CS 1 CS 2 CS 3 CS 4 00008016 00800016 CS 0 (1,1,1)(0,0,0) h The memory allocation selection bits must be set as above. 01000016 Internal RAM area SFR area Internal ROM area Internal RAM area SFR area Internal ROM area Internal RAM area SFR area Internal ROM area Internal RAM area SFR area Internal ROM area

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: External area specified by address and chip select signal Microprocessor mode (for M37735MHBXXXFP) CS 1 CS 2 CS 3 CS 4 CS 0 00000016 0FFFFF 16 04000016 08000016 0C0000 16 00100016 00800016 00008016 Internal RAM area SFR area Fig. 12.1.3 External area (Microprocessor mode)

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This signal is used to select the external data bus width from 8 bits and 16 bits. When this signal level is “L,” the external data bus is 16 bits wide; when this signal level is “H,” the external data bus is 8 bits This signal is valid only for the external areas. (When the internal area is accessed, the data bus is always 16 bits wide.)

12.1.3 Read enable signal (RDE ) and Write enable signals (WEL , WEH )

These signals are output when data is read or written from or to the external area. When the internal area is accessed, these signals are stopped at “H” level by setting the signal output disable selection bit (bit 6 at address 6C16) to “1.” (Refer to Table 12.1.4.) Table 12.1.2 Functions of read enable signal and write enable signals External data bus state Data is read out. 1-byte data is written to even address. 1-byte data is written to odd address. 1-word data is written. Data is read out. Data is written. External data bus width 16 bits (BYTE = “L”) 8 bits (BYTE = “H”) ____ RDE H L H H H H L H ____ WEL H H L H L H H L ____ WEH H H H L L H H H

12.1.4 Address latch enable signal (ALE)

This signal is used to latch an address from a multiplexed signal. This multiplexed signal consists of the address and data and is input or output to or from pins A 0/D0 to A15/D15, A16/D0 to A23/D7. When this signal level is “H,” take the address into a latch and output it simultaneously. When this signal level is “L,” retain the latched address.

12.1.5 Signals related to ready function (RDY , RSMP )

These signals are required to use the ready function. (Refer to section “12.3 Ready function.”)

12.1.6 Signals related to hold function (HOLD , HLDA )

These signals are required to use the hold function. (Refer to section “12.4 Hold function.”)

12.1.7 Clock φ1

This signal has the same period as internal clock φ. Whether clock φ1 is output or stopped can be selected by software. However, the method of this selection depends on the processor mode. Table 12.1.3 lists the method to select whether to output or stop clock φ1. Figure 12.1.4 shows the clock φ1 output start timing.

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Table 12.1.3 Method to select whether to output or stop clock φ1 Clock φ1 output Clock φ1 stopped Remark Processor mode Single-chip or Memory expansion mode Microprocessor mode Clear the signal output disable selection bit*2 to “0.” Set the signal output disable selection bit to “1.” (Note) Clock φ1 is output after reset. The clock φ1 output selection bit is ignored. Set the clock φ1 output selection bit*1 to “1.” Clear the clock φ1 output selection bit to “0.” (Pin P42 functions as a programmable I/O port.) Clock φ1 is stopped after reset. The signal output disable selection bit is ignored. Clock φ1 output selection bit*1: Bit 7 at address 5E16 Signal output disable selection bit*2: Bit 6 at address 6C16 (Refer to Table 12.1.4.) Note: When bit 2 at address C16 (Port P4 direction register) is set to “1,” bit 2 of the port P4 register is output. Table 12.1.4 Functions of signal output disable bit Processor mode Conditions Signal output disable selection bit Memory expansion or Microprocessor mode Signals ____ RDE, ____ WEL, ____ WEH ____ RDE, ____ WEL, ____ WEH ____ RDE, ____ WEL, ____ WEH Clock φ1 When the external area is accessed When the internal area is accessed When the standby state selection bit = “1” in the stop or wait mode When the standby state selection bit = “0” in the stop or wait mode Operating Operating Stopped at “H” level Stopped at “H” levelStopped at “L” level Stopped at “H” level Stopped (Output levels can be set.) Stopped (Note)Microprocessor mode Enable signal E When not in the stop or wait modeSingle-chip mode When in the stop or wait mode Operating Stopped at “H” levelStopped at “L” level Stopped at “L” level h All functions listed in Table 12.1.4 are not emulated by a debugger. h For the stop and wait modes and the standby state selection bit, refer to chapter “11. STOP AND WAIT MODES.” Note: When bit 2 at address C16 (Port direction register) is set to “1,” bit 2 of the port P4 register is output. :Not affected by the signal output disable selection bit. Each signal’s state Operating (independent of the φ1 output selection bit)

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Fig. 12.1.4 Clock φ1 output start timing (when clock φ1 output selection bit is set from “0” to “1”) Fig. 12.1.5 Structure of oscillation circuit control register 0 Clock 1 E : There is a possibility that the first cycle of clock 1 output is not an exact square; the shaded section may be lost. : This is applied when “1” is written to the clock 1 output selection bit while pin P42 outputs “L” level. The clock 1 output selection bit is set to “1.” Bit Bit name Functions At reset RW XCOUT drivability selection bit Main clock stop bit System clock selection bit Port-Xc selection bit Not implemented. Un- defined 0: Drivability “LOW” 1: Drivability “HIGH” When the port-Xc selection bit = “0,” 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = “1,” 0: Main clock 1: Sub clock Un- defined Oscillation circuit control register 0 (address 6C16) b1 b0b2b3b4b5b6b7 Notes 0: Main clock oscillation or external clock input is available. 1: Main clock oscillation or external clock input is stopped. RW RW Not implemented. – RW (Note 1) 0: Operate as I/O ports (P77, P76). 1: Operate as pins XCIN and XCOUT . RW (Notes 2 and 3) RW (Note 2) System clock stop bit at wait state (Note 4) 0: Output is enabled. 1: Output is disabled. (Refer to Tables 12.1.3 and 12.1.4) 0: Operates in the wait mode. 1: Stopped in the wait mode. Signal output disable selection bit RW (Note 1) 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = “1.” 2: When selecting the sub clock as the system clock, set bit 3 to “1” after setting bit 4 to “1.” If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to “1.” 3: Although this bit can be set to “1,” it cannot be cleared to “0” after this bit is once set to “1.” 4: When setting the system clock stop bit at wait state to “1,” perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to “0” immediately after the wait mode is terminated. 5: represents that bits 0 to 5 and 7 are not used for access control of external area. (Functions of these bits are valid.)

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Fig. 12.1.6 Relationship between setting of signal output disable selection bit and stop timing of each signal WEH WEL RDE Clock 1 (in the microprocessor mode) Note: These signals can be stopped only when accessing internal area (in the memory expansion and microprocessor modes). Internal enable signal E (in single-chip mode) “H” (Note) (Note) (Note) Value “1” is written to the signal output disable selection bit. Signal is stopped.

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12.1.8 Operation of bus interface unit (BIU)

Figures 12.1.7 to 12.1.9 show operating waveform examples of signals which are input to or output from the external when accessing external devices. These waveforms are described in relation to the basic operating waveforms. (Refer to section “2.2.3 Operation of bus interface unit (BIU).”) (1) When fetching an instruction into an instruction queue buffer À When an instruction which is next fetched resides at an even address When the external data bus is 16 bits wide, the BIU fetches two bytes of the instruction at a time with waveform (a). When the external data bus is 8 bits wide, the BIU fetches only one byte of the instruction with the first half of waveform (i). \ When an instruction which is next fetched resides at an odd address When the external data bus is 16 bits wide, the BIU fetches only one byte of the instruction with waveform (g). When the external data bus is 8 bits wide, the BIU fetches only one byte of the instruction with the first half of waveform (i). When branched to an odd address by executing a branch instruction or others with the 16-bit external data bus, at first, the BIU fetches one byte of an instruction with waveform (g) and then fetches instructions by the two bytes with waveform (a). (2) When reading or writing data from or to memory • I/O À When accessing 16-bit data which starts from an even address, waveform (a), (b), (i) or (j) is applied. \ When accessing 16-bit data which starts from an odd address, waveform (c), (d), (i) or (k) is applied. ´ When accessing 8-bit data which resides at an even address, waveform (e), (f) or the first half of waveform (i) or (j) is applied. ˆ When accessing 8-bit data which resides at an odd address, waveform (g), (h) or the first half of waveform (k) is applied. For instructions which are affected by data length flag (m) and index register length flag (x), an operation is applied as follows.:

• When “m” or “x” = “0,” operation À or \` is applied.
• When “m” or “x” = “1,” operation ´ or ˆ is applied. Settings of flags “m” and “x” and selection of the external data bus width do not affect each other.

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Data (even) Data (odd) Address Address RDE ALE CS 0 to CS4 A16, A17 WEH WEL “H” AddressA 0/D0 to A 7/D7 A 8/D8 to A15/D15 Address Address Address Address (Note 3) RDE ALE CS 0 to CS4 A16, A17 WEH WEL “H” Address (Note 3) AddressA0/D0 to A 7/D7 A 8/D8 to A15/D15 Address Address Address Address RDE ALE CS 0 to CS4 A16, A17 WEH WEL “H” Address (Note 2) AddressA0/D0 to A7/D7 A8/D8 to A 15/D15 “H” (Note 1) (Note 2) (Note 1) RDE (a) Read starting from even address ALE CS 0 to CS4 A0/D0 to A7/D7 A 16, A17 Address A8/D8 to A15/D15 Address WEH WEL “H” “H” Address (Note 1) Notes 1: These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is fetched into the data buffer of the BIU. 2 : These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is not fetched fetched into the data buffer of the BIU. 3 : Invalid data (Undefined value) “H” “H” l When external data bus is 16 bits wide (BYTE = “L” ) <16-bit data access> (b) Write starting from even address (c) Read starting from odd address (d) Write starting from odd address (Note 1) Data (even) Data (odd) Fig. 12.1.7 Operating waveform example of signals which are input to or output from the external (1)

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A 16, A17 Address A8/D8 to A15/D15 Address WEH WEL “H” “H” Address (Note 2) (Note 1) Address Address (Note 3) RDE ALE CS 0 to CS4 A16, A17 WEH WEL “H” Address Data (even)A0/D0 to A7/D7 A8/D8 to A15/D15 “H” Address Address (Note 3) RDE ALE CS 0 to CS4 A16, A17 WEH WEL “H” Address Data (odd) A0/D0 to A7/D7 A8/D8 to A15/D15 “H” RDE ALE CS 0 to CS4 A0/D0 to A7/D7 A 16, A17 Address A8/D8 to A15/D15 Address WEH WEL “H” “H” Address (Note 1) (Note 2) (e) Read starting from even address l When external data bus is 16 bits wide (BYTE = “L” ) <8-bit data access> (f) Write starting from even address (g) Read starting from odd address (h) Write starting from odd address Notes 1: These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is fetched into the data buffer of the BIU. 2: These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is not fetched into the data buffer of the BIU. 3: Invalid data (Undefined value) Fig. 12.1.8 Operating waveform example of signals which are input to or output from the external (2)

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A16, A17 WEH WEL “H” A 0/D0 to A7/D7 A 8 to A15 Address Data (even) Address Data (odd) Address Address (i) Read starting from even or odd address RDE ALE CS 0 to CS4 A0/D0 to A7/D7 A 16, A17 Address A8 to A15 Address WEH WEL “H” “H” Address Address (Note) (Note) Address Address Address Address RDE ALE CS 0 to CS4 A16, A17 WEH WEL “H” A0/D0 to A7/D7 A 8 to A15 Address Data (odd) Address Data (even) Address Address l When external data bus is 8 bits wide (BYTE = “H” ) <8/16-bit data access> h When 16-bit data is accessed, the low-order 8 bits of data are accessed first, and then, the high-order 8 bits are accessed. 8-bit data access 16-bit data access (j) Write starting from even address (k) Write starting from odd address 8-bit data access 16-bit data access 8-bit data access 16-bit data access Note: These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is fetched into the data buffer of the BIU. Fig. 12.1.9 Operating waveform example of signals which are input to or output from the external (3)

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The software wait facilitates access to external devices which require a long access time. There are two types of software waits: wait 0 and wait 1. The software wait is set by the wait bit (bit 2 at address 5E16) and the wait selection bit (bit 0 at address 5E 16) and processor mode register 1 (address 5F16). Figure 12.2.2 shows bus timing examples when the software wait is used. The software wait is valid only for the external area. (Access to the internal areas is always performed with no wait.) For external devices which can not be accessed even when using the software wait, by using the ready function (signal RSMP ), a wait which is equivalent to 1 cycle of clock φ1 can furthermore be generated. (Refer to section “12.3 Ready function.” Table 12.2.1 Setting method of software wait Wait bit Wait selection bit Software wait Bus cycle Invalid (No wait) Wait 0 Wait 1 Cycle of “internal clock φ divided by 2” (clock φ1’s cycle 5 2) “Cycle in the no-wait state” 5 2 (clock φ1’s cycle 5 4 ) “Cycle in the no-wait state” 5 1.5 (clock φ1’s cycle 5 3 )

of the external area. CONNECTING EXTERNAL DEVICES

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Fig. 12.2.1 Structures of processor mode register 0 and processor mode register 1 b2b3b4b5b6b7 b1 Processor mode register 1 (address 5F16) Bit Bit name Function At reset 7 to1 Wait selection bit 0 : Wait 0 1 : Wait 1 0 Not implemented. Un- defined RW RW Bit Bit name Functions At reset RW Processor mode bits Wait bit Software reset bit Interrupt priority detection time selection bits Must be fixed to “0.” Clock f1 output selection bit (Note 2) 00: Single-chip mode 01: Memory expansion mode 10: Microprocessor mode 11: Do not select. 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. Microcomputer is reset by setting this bit to “1.” This bit is “0” at reading. 00: 7 cycles of f 01: 4 cycles of f 10: 2 cycles of f 11: Do not select. 0: Clock f1 output is disabled. (P42 functions as a programmable /O port.) 1: Clock f1 output is enabled. (Port P42 functions as a clock f1 output pin.) b1 b0 b5 b4 Processor mode register 0 (address 5E16) (Note 1) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to “1” after reset. (At reading, this bit is always “1.”) 2: This bit is ignored in the microprocessor mode. (It may be “0” or “1.”) 3: represents that bits 3 to 6 are not used for access control (Functions of these bits are valid.) b1 b0b2b3b4b5b6b7 RW RW RW WO RW RW RW RW

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Fig. 12.2.2 Bus timing examples when software wait is used (BYTE = “L” ). <<No wait>> Clock 1 RSMP CS 0 to CS4 A16, A17 A 0/D0 to A15/D15 h ALE 1-bus cycle (Note) <<Wait 0>> Clock 1 RSMP CS 0 to CS4 A16, A17 A 0/D0 to A15/D15 h ALE 1-bus cycle (Note) <<Wait 1>> Clock 1 RSMP CS 0 to CS4 A16, A17 A 0/D0 to A15/D15 h ALE Data 1-bus cycle (Note) Address l This waveform is always applied when the internal area is accessed. Note: When the external data bus is 8 bits wide (BYTE = “H” ), operating waveform of A8/D8 to A15/D15 is the same as that of A16 and A17. Address Address Address Data Address Data Address Address Address Data Address Data Address Address Address Data h One of the following is applied.:

• One of signals RDE, WEL, and WEH
• Signals WEL and WEH

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P4 2/φ1 Timers A and B, Serial I/O, A-D converter, Watchdog timer Item State The ready function facilitates access to external devices which require a long access time. ____ By applying “L” level to pin RDY in the memory expansion or microprocessor mode, the microcomputer ____ enters the ready state. While pin RDY ’s level is “L,” this state is retained. Table 12.3.1 lists the microcomputer’s state in the ready state. In the ready state, oscillation of the oscillator does not stop. Therefore, the internal peripheral devices can operate even in the ready state. The ready function is valid for the internal and external areas. Table 12.3.1 Microcomputer’s state in ready state Clock φ1 output selection bit*1: Bit 7 at address 5E16 Signal output disable selection bit*2: Bit 6 at address 6C16 ____ Notes 1: When “L” level which was input to pin RDY is sampled at one of the following timings, this signal is not accepted. (Note that φCPU is stopped at “L” level.) l When the levels of signals RDE , WEL , and WEH are “H” while the bus is in use (Refer to \` in Figure 12.3.2.) l Immediately before a wait generated by the software wait (Refer to ˜ in Figure 12.3.2.) 2: This is applied when these pins function as programmable I/O ports. Oscillation φCPU Operating Stopped at “L” level ____ Retains the same state in which RDY was accepted. In the memory expansion mode n When the clock φ1 output selection bit*1 = “1” Outputs clock φ1. n When the clock φ1 output selection bit = “0” ____ Retains the same state in which RDY was accepted. In the microprocessor mode n When the signal output disable selection bit*2 = “1” ____ Retains the same state in which RDY was accepted. n When the signal output disable selection bit = “0” Outputs clock φ1. Operating RDE , WEL , WEH , CS 0 to CS 4, HLDA , ALE, A0/D0 to A15/D15, A 16, A17 P4 3 to P47, P5 to P8 (Note 2)

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n : 0 to 4 Chip select signal Fig. 12.3.1 Connection example when signal RSMP is used ____ When “L” level is input to pin RDY , this signal is accepted at the falling edge of clock φ1 and the microcomputer ____ enters the ready state. The ready state can be terminated by setting pin RDY ’s level to “H” again. When ____ “H” level is input to pin RDY , this signal is also accepted at the falling edge of clock φ1 and the ready state is terminated. Figure 12.3.2 shows timings when the ready state is accepted and terminated. When generating a wait which is equivalent to 1 cycle of clock φ1 by using the ready function, use signals RSMP and CS n (n = 0 to 4). These signals facilitate to generate a signal input to pin RDY . Figure 12.3.1 shows a connection example when signal RSMP is used. Note that signal RSMP is affected by the software wait. Figure 12.3.3 shows the relationship between the software wait and signal RSMP . Refer to section “17.1 Memory expansion” for the way to use the ready function.

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: Ready state : Software wait

• One of signals RDE, WEL, and WEH
• Signals WEL and WEH h One of the following is applied.:<<No wait>> Sampling timing Clock 1 CPU RDY ALE ˆÀ\ ´ Bus is not in use. Bus is in use. ˆ Ready state is terminated. À “L” level which is input to pin RDY is accepted, so that signal h is stopped at “H” level for 1cycle of clock1 (area ), andCPU is stopped at “L” level. \ “L” level which is input to pin RDY is not accepted, butCPU is stopped at “L” level. ´ “L” level which is input to pin RDY is accepted, so that signal h is stopped at “L” level for 1cycle of clock1 (area ), andCPU is stopped at “L” level. ˜ “L” level which is input to pin RDY is not accepted because it is sampled immediately before a wait generated by software wait (area ), butCPU is stopped at “L” level. Sampling timing Clock 1 CPU RDY ALE <<Wait 0>> Bus is in use. Sampling timing Clock 1 CPU RDY ALE <<Wait 1>> Bus is in use. ˜ˆ ´ ˜ˆ ´ h h h Fig. 12.3.2 Timings when ready state is accepted and terminated (when not using signal RSMP )

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h One of the following is applied.: : Ready state : Software wait <<No wait>> h CPU ALE RDY Clock 1 RSMP CS 0 to CS4 <<Wait 1>> RDY ALE Clock 1 CPU h RSMP CS 0 to CS4 Clock 1 ALE CPU h <<Wait 0>> RDY CS 0 to CS4 RSMP

• One of signals RDE, WEL, and WEH
• Signals WEL and WEH Fig. 12.3.3 Relationship between software wait and signal RSMP

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When an external circuit which accesses the bus without using the central processing unit (CPU), for example DMA, is used, it is necessary to generate a timing for transferring the right to use of the bus from the CPU to the external circuit. The hold function is used to generate this timing. By applying “L” level to pin HOLD in the memory expansion or microprocessor mode, the microcomputer enters the hold state. While pin HOLD ’s level is “L,” this state is retained. Table 12.4.1 lists the microcomputer’s state in the hold state. In the hold state, oscillation of the oscillator does not stop. Therefore, the internal peripheral devices can operate even in the hold state. (Note that the watchdog timer stops.) Table 12.4.1 Microcomputer’s state in hold state Item State Operating Stopped at “L” Floating Oscillation φCPU RDE , WEL , WEH , CS 0 to CS 4, RSMP , A0/D0 to A15/D15, A16, A 17 Outputs “L” level. HLDA , ALE P4 2/φ1 P4 3 to P47, P5 to P8 (Note) Timers A and B, Serial I/O, A-D converter Watchdog timer In the memory expansion mode n When the clock φ1 output selection bit*1 = “1” Outputs clock φ1. n When the clock φ1 output selection bit = “0” Retains the same state in which HOLD was accepted. In the microprocessor mode n When the signal output disable selection bit*2= “1” Retains the same state in which HOLD was accepted. n When the signal output disable selection bit = “0” Outputs clock φ1. Re tains the same state in which HOLD was accepted. Operating Stopped Clock φ1 output selection bit*1: Bit 7 at address 5E16 Signal output disable selection bit*2: Bit 6 at address 6C16 Note: This is applied when these pins function as programmable I/O ports.

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A Clock 1 ALE At reading At writing RDE l Determination timing of pin HOLD ’s input level A Not determined Determined Word data is accessed by the two bus cycles. (in this case, no wait) A AWW When “L” level is input to pin HOLD while the bus is not in use, this signal is accepted at the falling edge of clock φ1. When “L” level is input to pin HOLD while the bus is in use, this signal is accepted at the clock φ1’s falling edge which precedes the rising edge of signal RDE , WEL , or WEH by the clock φ1’s cycle divided accessed by the two bus cycles, determination is performed only in the second bus cycle. (Refer to Figure 12.4.1.) When “L” level which was input to pin HOLD is accepted, φCPU is stopped at the next rising edge of clock φ1. At this time, pin HLDA outputs “L” level, and so the external is informed that the microcomputer is in the hold state. After one cycle of clock φ1 has passed since pin HLDA ’s level becomes “L,” pins RDE , WEL , WEH , CS 0 to CS 4, RSMP and the external bus enter the floating state. The hold state can be terminated by setting pin HOLD ’s level to “H” again. When “H” level is input to pin HOLD , this signal is accepted at the falling edge of clock φ1. When “H” level which was input to pin HOLD is accepted, pin HLDA ’s level goes from “L” to “H.” And then, the hold state is terminated after one cycle of clock φ1 has passed. h In the ready state, determination of pin HOLD ’s input level is not performed. Fig.12.4.1 Determination when word data which starts from odd address is accessed by the two bus cycles

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À Because the bus is not in use, the address which was output immediately before is output again, instead of a new address. HLDA HOLD BHE ALE h External address bus/ External data bus Sampling timing Note: The same operation is performed independent of the software wait (no wait, wait 0, or wait 1). This diagram shows the operation when no wait is selected. CS 0 to CS4 Clock 1 External data bus Data length External data bus width Software wait 8, 16 No wait, Not in use l State when “L” level is input to pin HOLD Wait 1, Wait 08, 16 <<When “L” level is input to pin HOLD while bus is not in use>> Address B 1 5 1 1 5 1 À Bus is in use.Bus is not in use. Address A Data Address A Floating Floating Bus is in use. Hold state h RDE, WEL, WEH Fig. 12.4.2 Timing when hold state is accepted and terminated (1)

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External data bus Data length 8, 16 (When accessed starting from even address) No waitIn use State when “L” level is input to pin HOLD External data bus width Software wait ALE h HLDA HOLD CS 0 to CS4 Address A 1 5 1 1 5 1 Hold state Sampling timing <<When “L” level is input to pin HOLD while bus is in use (1)>> External address bus/ External data bus External address bus Clock 1 Data Floating BHE Address A Floating Address B Floating À Bus is not in use. À When “L” level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. Bus is in use. h RDE, WEL, WEH Bus is in use. Fig. 12.4.3 Timing when hold state is accepted and terminated (2)

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External data bus Data length External data bus width Software wait 8, 16 (When accessed starting from even address) Wait 1In use l State when “L” level is input to pin HOLD ALE h HLDA HOLD CS 0 to CS4 Address A Address B 1 5 1 1 5 1 Hold state À Sampling timing <<When “L” level is input to pin HOLD while bus is in use (2)>> External address bus Clock 1 Data Floating Floating Floating BHE Bus is in use. Bus is in use.Bus is not in use. À When “L” level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. h RDE, WEL, WEH Fig. 12.4.4 Timing when hold state is accepted and terminated (3)

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual12–28

External data bus Data length External data bus width Software wait 8, 16 (When accessed starting from even address) Wait 0In use l State when “L” level is input to pin HOLD ALE HLDA HOLD Address A Address B 1 5 1 1 5 1 Hold state Data Sampling timing <<When “L” level is input to pin HOLD while bus is in use (3)>> External address bus/ External data bus External address bus Clock 1 Address A Floating Floating Floating BHE À h CS 0 to CS4 Bus is in use. Bus is in use.Bus is not in use. À When “L” level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. h RDE, WEL, WEH Fig. 12.4.5 Timing when hold state is accepted and terminated (4)

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual 12–29

À When “L” level which is input to pin HOLD is the accepted, the address which was output immediately before is output again, instead of a new address. \ Sampling is not performed until 16-bit data input/output is finished. ( “L” level which is input to pin HOLD is not accepted.) External address bus/ External data bus ALE HLDA HOLD Address 1 5 1 1 5 1 Hold state Not sampled\ External data bus Data length External data bus width Software wait (When accessed starting from even address) No wait In use l State when “L” level is input to pin HOLD Sampling timing Bus is in use. <<When “L” level is input to pin HOLD while bus is in use (4)>> External address bus Clock 1 Data High-order address Floating Floating Floating À Bus is in use. BHE Data Low-order address h CS 0 to CS4 h RDE, WEL, WEH Bus is not in use. Fig. 12.4.6 Timing when hold state is accepted and terminated (5)

CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual12–30

7735 Group User’s Manual13–2

Concerning chapter “RESET,” the 7735 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter:

• “13.1 Hardware reset” The following section of the 7735 Group is the same as that of the 7733 Group. Therefore, for this section, refer to part 1:
• “13.2 Software reset” (page 13-12 in part 1)

Concerning section “13.1 Hardware reset,” the 7735 Group differs from the 7733 Group in the following:

• “Table 13.1.1 Pin state while pin RESET is at “L” level”
• “Figure 13.1.6 State of SFR area and internal RAM area immediately after reset (4)” The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “13.1 Hardware reset” (page 13-2 in part 1)

Pin CNV SS ’s level V SS or VCC VSS V CC V CC Pin state Floating “H” level is output. Floating “H” level is output. Floating

• Floating when “H” level is applied to both or one of pins P51 and P52
• “H” or “L” level is output when “L” level is applied to both of pins P51 and P52. “H” level is output. “H” or “L” level is output. “H” level is output. “L” level is output. 1 (operating) is output. Floating Table 13.1.1 Pin state while pin RESET is at “L” level Pin (Port) name P0 to P8 E/RDE P0 to P8 E/RDE P0, P1, P3 to P8 E/RDE A0/D0 to A7/D7, A8/D8 to A15/D15, A16, A17 CS 0 to CS4, WEL, WEH, HLDA, E/RDE ALE HOLD, RDY, P4 3 to P47, P5 to P8

7735 Group User’s Manual 13–3

Figure 13.1.6 for the 7735 Group differs from that for the 7733 Group only in ] 3. Fig. 13.1.6 State of SFR area and internal RAM area immediately after reset (4) RO UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address Oscillation circuit control register 0 Serial transmit control register A-D / UART2 trans./rece. interrupt control register UART0 transmission interrupt control register UART1 transmission interrupt control register INT2/Key input interrupt control register Watchdog timer frequency selection flag Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW( ]2) RW RW RW RW b7 b0 WO RW RW RW RW RW RW RW RW RW RW State immediately after reset 0 00 0 ? 0 ? (h1) b7 b0 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 Port function control register UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register RW RW WO RW RW RW 00 0 0 0 1 00 00 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 00 0 0 0 0 00 0 0 0 0 Value “FFF16” is set to the watchdog timer. (Refer to section Chapter “10. WATCHDOG TIMER.” ) For access characteristics at address 6C16, also refer to Figure 14.3.2 in part 1. State immediately after reset for bit 3 at address 6F16 vary according to the microcomputer. (Refer to Figure 14.3.3 in part 2 ; This bit’s function of the 7735 Group differs from that of the 7733 Group.) This bit must be fixed to “0” in the 7735 Group. Do not write data to address 6216. n Internal RAM area (M37735MHBXXXFP: addresses 8016 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset. When the stop or wait mode is terminated (when hardware reset is applied)...Retains the state immediately before the STP or WIT instruction is executed. RW ]3 00 0 (Reserved area) ]4 Memory allocation control register UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Oscillation circuit control register 1 RW 0? 0 00 0 RW ? 00 0 0 0 00 WO WO WO RWRO 1 00 0 RW RWRORO 00 0 0 00 10 RO 00 0 000 ? RW ?? 0 00 0 0 00 0

7735 Group User’s Manual13–4

7735 Group User’s Manual14-2

Concerning chapter “14. CLOCK GENERATING CIRCUIT,” the 7735 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter:

• “14.3 Clock control” The following sections are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1:
• “14.1 Overview” (page 14-2 in part 1)
• “14.2 Oscillation circuit example” (page 14-3 in part 1)

Concerning section “14.3 Clock control,” the 7735 Group differs from the 7733 Group in the following:

• Figures 14.3.3 and 14.3.4 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “14.3 Clock control” (page 14-5 in part 1)

7735 Group User’s Manual 14-3

Fig. 14.3.3 Structure of oscillation circuit control register 1 Fig. 14.3.4 Procedure for writing data to oscillation circuit control register 1 In the M37735MHBXXXFP, set bit 3 of the oscillation circuit control register 1 to “0.” Notes 1: When writing to this register, follow the procedure shown in Figure 14.3.4. 2: Because this bit is “1” at reset, clear this bit to “0” with the initial setting program after reset. 3: The case where data “010101012” is written with the procedure shown in Figure 14.3.4 is not included. 4: For the 7733 Group, refer to Figure 14.3.3 in part 1. 5: represents that bits 3 to 7 are not used for the clock generating circuit. Bit Bit name Functions At reset RW Main clock division selection bit Sub clock external input selection bit Must be fixed to “0” in the one time PROM and EPROM versions (Notes 1 and 2). Must be fixed to “0” (Note 3). Clock prescaler reset bit Undefined Oscillation circuit control register 1 (address 6F16) 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT . Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. RW RW RW RW WO —Not implemented. Not implemented. b1 b0b2b3b4b5b6b7 By writing “1” to this bit, clock prescaler is initialized. RW (Note 4) Undefined Main clock external input selection bit 0: Main clock is divided by 2. 1: Main clock is not divided by 2. 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. Must be fixed to “0” in the mask ROM and external ROM versions (Note 1). (Note 1) (Note 1) (Note 1) Write data “010101012.” (LDM instruction)

• When writing to bits 0 to 3 Write data “00000XXX2.” (LDM instruction) Next instruction (b3 in Figure 14.3.3)(b2 to b0 in Figure 14.3.3)

7735 Group User’s Manual14-4

15.8 Memory expansion mode and Microprocessor mode : with no wait Microprocessor mode : with wait 1 Microprocessor mode : with wait 0 P0 to P8 and pins φ1 and E

7735 Group User’s Manual15–2

Electrical characteristics of the M37735MHBXXXFP are described in this chapter. For the low voltage version, refer to section “18.4 Electrical characteristics.” Concerning chapter “15. ELECTRICAL CHARACTERISTICS,” the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter:

• “15.6 Ready and Hold”
• “15.8 Memory expansion mode and Microprocessor mode : with no wait”
• “15.9 Memory expansion mode and Microprocessor mode : with wait 1”
• “15.10 Memory expansion mode and Microprocessor mode : with wait 0” The following sections are the same as those of the 7733 Group. Therefore, refer to part 1:
• “15.1 Absolute maximum ratings” (page 15-2 in part 1)
• “15.2 Recommended operating conditions” (page 15-3 in part 1)
• “15.3 Electrical characteristics” (page 15-4 in part 1)
• “15.4 A-D converter characteristics” (page 15-5 in part 1)
• “15.5 Internal peripheral devices” (page 15-6 in part 1)
• “15.7 Single-chip mode” (page 15-13 in part 1)
• “15.11 Measuring circuit for ports P0 to P8 and pins φ1 and E ” (page 15-21 in part 1)

7735 Group User’s Manual 15–3

Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. HOLD input setup time RDY input hold time HOLD input hold time Limits tsu(RDY– φ1) tsu(HOLD– φ1) th(φ1–RDY) th(φ1–HOLD) RDY input setup time Max. ns ns ns ns Min. ParameterSymbol Unit Note: This is applied when the main clock division selection bit = “0” and f(f 2) = 12.5 MHz. Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) HLDA output delay timetd(φ1–HLDA) ns Min. Max. Limits UnitConditionsParameter Fig. 15.11.1 in part 1 Symbol

7735 Group User’s Manual15–4

WEL, WEH, RDE output WEL, WEH, RDE output RDY input tsu(RDY– 1) th( 1–RDY) tsu(RDY– 1) th( 1–RDY) Measuring conditions

• VCC = 5 V ± 10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage: VOL = 0.8 V, VOH = 2.0 V HOLD input HLDA output th( 1–HOLD) td( 1–HLDA) tsu(HOLD– 1) Hold td( 1–HLDA)

7735 Group User’s Manual 15–5

2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) Symbol td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th(φ 1–RSMP) td(WE– φ 1) td(RDE– φ 1) Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. tc tw(H) tw(L) tr tf tsu(D–RDE) th(RDE–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 80 ns. 3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LimitsData formula (Min.) Max. 1 5 109 2•f(f2) 2 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 2 5 109 2•f(f2) 1 5 109 2•f(f2) Parameter Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL, WEH pulse width Floating start delay time Floating release delay time ____ RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time – 22 – 30 – 20 – 32 – 30 Conditions Fig. 15.11.1 in part 1 Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. – 28 – 28 – 22 – 18 – 35 – 28 Min.

7735 Group User’s Manual15–6

th(WE–DQ) tsu(A–ALE)Address/Data output A0/D0–A15/D15 (BYTE = “L”) A0/D0–A7/D7 (BYTE = “H ”) td(WE– 1) td(CS–WE) td(WE– 1) tw(WE) td(RSMP–WE) XIN CS 0–CS 4 output WEL output WEH output RDE output With no wait (Wait bit = “1”) td(RDE– 1) Memory expansion mode and Microprocessor mode : td(An–WE) ALE output tw(H)tw(L) tf tr tc th(ALE–A) tw(H)tw(L) tf tr tc th(WE–CS) Address output A8–A15 (BYTE = “H ”) A16, A17 tw(ALE) Address Address td(A–WE) td(WE–DQ) Data input D 0–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H ”) RSMP output td(ALE–WE) th(WE–An) td(RDE– 1) th(RDE–CS)td(CS–RDE) Address th(RDE–An)td(An–RDE) Address Address AddressData tpzx(RDE–DZ)td(A–RDE) tsu(D–RDE) th(RDE–D) td(RSMP–RDE) Measuring conditions (CS0–CS 4, A0/D0–A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP)

• VCC = 5 V ± 10 %
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : VIL = 0.8 V, VIH = 2.5 V Port Pi output (i = 4–8) Port Pi input (i = 4–8) Measuring conditions (Ports P4–P8)
• VCC = 5 V ± 10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V td(WE–PiQ) tsu(PiD–RDE) th(RDE–PiD) Data tsu(A–ALE) tw(ALE) th(ALE–A) tpxz(RDE–DZ) td(ALE–RDE) tw(RDE) Data Address 1–RSMP)th( 1–RSMP)th(

7735 Group User’s Manual 15–7

td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th(φ 1–RSMP)

15.9 Memory expansion mode and Microprocessor mode : with wait 1

Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. tc tw(H) tw(L) tr tf tsu(D–RDE) th(RDE–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 80 ns. 3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data formula (Min.) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) Parameter Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL, WEH pulse width Floating start delay time Floating release delay time ____ RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time Conditions Fig. 15.11.1 in part 1 – 28 – 28 – 28 – 22 – 18 – 35 1 5 109 2•f(f2) 4 5 109 2•f(f2) 1 5 109 2•f(f2) 4 5 109 2•f(f2) 1 5 109 2•f(f2) – 22 – 30 – 20 – 32 – 30 td(WE– φ 1) td(RDE– φ 1) Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. Min. 130 128 Max. Limits

7735 Group User’s Manual15–8

th(ALE–A) td(WE–DQ) td(An–RDE) th(WE–DQ)tsu(A–ALE)Address/Data output A0/D0–A15/D15 (BYTE = “L”) A0/D0–A7/D7 (BYTE = “H”) td(WE– 1) td(CS–WE) td(WE– 1) tw(WE) td(RSMP–WE) XIN CS 0–CS 4 output WEL output WEH output RDE output When external memory area is accessed With wait 1 (Wait bit = “0” and Wait selection bit = “1”) td(RDE– 1) Memory expansion mode and Microprocessor mode : td(An–WE) ALE output tw(H)tw(L) tf tr tc th(ALE–A) th(WE–CS) Address output A8–A15 (BYTE = “H”) A16, A17 Address tw(ALE) Data td(A–WE) Data input D 0–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H”) RSMP output td(ALE–WE) th(WE–An) td(RDE– 1) th(RDE–CS)td(CS–RDE) th(RDE–An) td(ALE–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ)td(A–RDE) tsu(D–RDE) th(RDE–D) tw(RDE) td(RSMP–RDE) Measuring conditions (CS0–CS 4, A0/D0–A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP)

• VCC = 5 V ± 10 %
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : VIL = 0.8 V, VIH = 2.5 V Port Pi output (i = 4–8) Port Pi input (i = 4–8) Measuring conditions (Port P4–P8)
• VCC = 5 V ± 10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V td(WE–PiQ) tsu(PiD–RDE) th(RDE–PiD) Address Address tw(H)tw(L) tf tr tc Address Address Address Data tw(ALE) tsu(A–ALE) Address th( 1–RSMP) th( 1–RSMP) Address

7735 Group User’s Manual 15–9

td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) td(φ 1–RSMP)

15.10 Memory expansion mode and Microprocessor mode : with wait 0

Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. tc tw(H) tw(L) tr tf tsu(D–RDE) th(RDE–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 80 ns. 3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LimitsData formula (Min.) 3 5 109 2•f(f2) 3 5 109 2•f(f2) 3 5 109 2•f(f2) 1 5 109 2•f(f2) 2 5 109 2•f(f2) 2 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) – 33 – 33 – 45 – 22 – 23 – 35 – 25 – 30 Parameter Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL, WEH pulse width Floating start delay time Floating release delay time ____ RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time 1 5 109 2•f(f2) 4 5 109 2•f(f2) 1 5 109 2•f(f2) 4 5 109 2•f(f2) 1 5 109 2•f(f2) Conditions Fig. 15.11.1 in part 1 – 22 – 30 – 20 – 32 – 30 td(WE– φ 1) td(RDE– φ 1) Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. Max.Min. 130 128

7735 Group User’s Manual15–10

td(WE–DQ) td(WE–PiQ) td(An–RDE) tsu(A–ALE)Address/Data output A0/D0–A15/D15 (BYTE = “L”) A0/D0–A7/D7 (BYTE = “H”) td(CS–WE) td(WE– 1) tw(WE) td(RSMP–WE) XIN CS 0–CS 4 output WEL output WEH output RDE output When external memory area is accessed with wait 0 (Wait bit = “0” and Wait selection bit = “0”) Memory expansion mode and Microprocessor mode : td(An–WE) ALE output tw(H)tw(L) tf tr tc th(WE–CS) Address output A8–A15 (BYTE = “H”) A16, A17 tw(ALE) Address Data td(A–WE) Data input D 0–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H”) RSMP output td(ALE–WE) th(WE–An) td(RDE– 1) th(RDE–CS)td(CS–RDE) th(RDE–An) td(ALE–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ) td(A–RDE) tsu(D–RDE) th(RDE–D) tw(RDE) td(RSMP–RDE) Measuring conditions (CS0–CS 4, A0/D0–A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP)

• VCC = 5 V ± 10 %
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : V IL = 0.8 V, VIH = 2.5 V Port Pi output (i = 4–8) Port Pi input (i = 4–8) Measuring conditions (Ports P4–P8)
• VCC = 5 V ± 10 %
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V tsu(PiD–RDE) th(RDE–PiD) Address Address th(WE–DQ) tw(H)tw(L) tf tr tc Data Data Address tw(ALE) th(ALE–A) tsu(A–ALE) Address th(ALE–A) th( 1–RSMP) th( 1–RSMP) 1)1)td(WE– td(RDE–

7735 Group User’s Manual16–2

Concerning chapter “16. STANDARD CHARACTERISTICS,” the 7735 Group is the same as the 7733 Group. Therefore, for this chapter, refer to part 1:

• “16 STANDARD CHARACTERISTICS” (part 1)

7735 Group User’s Manual17–2

Concerning chapter “17. APPLICATIONS,” the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter:

• “17.1 Memory expansion”
• “17.4 Power saving” The following sections of the 7735 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1:
• “17.2 Serial I/O” (page 17-28 in part 1)
• “17.3 Watchdog timer” (page 17-41 in part 1)
• “17.5 Timer B” (page 17-54 in part 1)

Memory • I/O expansion examples of the M37735MHBXXXFP are described below.

• For functions and operations of pins used in memory • I/O expansion, refer to chapter “12. CONNECTING EXTERNAL DEVICES.”
• For timing characteristics, refer to chapter “15. ELECTRICAL CHARACTERISTICS.”

Memory expansion to the external is available in the memory expansion or microprocessor mode. In the M37735MHBXXXFP, the desired memory expansion model can be selected from two models listed in Table 17.1.1. This selection depends on the level of the external data bus width selection signal (BYTE). (1) 8-bit external data bus model The external data bus is 8 bits wide and the accessible area can be expanded up to 1 Mbytes. The low-order 8 bits of the external address bus (A 7 to A0) are multiplexed with the external data bus. Therefore, one 8-bit address latch is necessary in order to latch A7 to A0. (2) 16-bit external data bus model The external data bus is 16 bits wide and the accessible area can be expanded up to 1 Mbytes. The low-order 16 bits of the external address bus (A 15 to A0) are multiplexed with the external data bus. Therefore, two 8-bit address latches are necessary in order to latch A7 to A0 and A15 to A8.

7735 Group User’s Manual 17–3

Table 17.1.1 Memory expansion models External data bus BYTE M37735MHBXXXFP BYTE M37735MHBXXXFP 8 bits wide BYTE = “H” 16 bits wide BYTE = “L” A0 to A15+n D 0 to D78 16 + n E (n ≤ 2) D Q Latch Latch Latch E A0 to A15+n D 0 to D15 n 16 + n D Q E D Q ALE ALE P2 8 n (n ≤ 2) h For functions and operations of pins used in memory expansion, refer to chapter “12. CONNECTING EXTERNAL DEVICES.” For timing characteristics, refer to chapter “15. ELECTRICAL CHARACTERISTICS.” h In memory expansion, the address bus can be expanded up to 18 bits wide. Accordingly, be sure to strengthen the 7735 Group’s Vss line on the system. (Refer to section “Appendix 8. Countermeasure examples against noise.”)

7735 Group User’s Manual17–4

When expanding memory, use a memory of which specifications satisfy the following timing requirements: address access time (t a(AD)) and data setup time for writing data (tsu(D)). Calculation ways for ta(AD) and tsu(D) are described below. À Address access time of external memory [ta(AD)] ta(AD) = td(A-RDE) + tw(RDE) – tsu(D-RDE) – (address decode time] 1 + address latch delay time] 2) address decode time] 1: time necessary for validating a chip select signal after an address is decoded address latch delay time] 2: delay time necessary for latching an address \` Data setup time of external memory for writing data [tsu(D)] tsu(D) = tw(WE) – td(WE-DQ) Table 17.1.2 lists the calculation formulas and constants for each parameter in the above formulas. Figure 17.1.1 shows bus timing diagrams. Table 17.1.2 Calculation formulas and constants for each parameter (Unit: ns) Software wait Wait bit Wait selection bit t d(A-RDE) tw(RDE) tw(WE) tsu(D-RDE) td(WE-DQ) Wait 1 Wait 0 – 322 5 109 2•f(f2) 1 5 109 2•f(f2) – 28 3 5 109 2•f(f2) – 45 4 5 109 2•f(f2) – 30 4 5 109 2•f(f2) – 30– 302 5 109 2•f(f2) Wait bit: Bit 2 at address 5E Wait selection bit: Bit 0 at address 5F16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = “0.” No wait 0 or 1

7735 Group User’s Manual 17–5

Fig. 17.1.1 Bus timing diagrams ALE High-order address td(An-RDE) td(An-RDE) tsu(A-ALE) td(ALE-RDE) tsu(D-RDE) tw(RDE) Port P0 (A16, A17) Port P1 (A8 to A15) Port P2 (A0/D0 to A7/D7) Data td(WE-DQ) High-order address tw(ALE) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines ta(AD) tsu(D) RDE WEL, WEH tw(WE) CS 4 to CS0 td(CS-RDE) td(CS-WE) Data (odd address) ALE Low-order address High-order address td(An-RDE) tsu(A-ALE) tsu(A-ALE) td(ALE-RDE) tsu(D-RDE) tw(RDE) Port P0 (A16, A17) Port P2 (A0/D0 to A7/D7) Data (even address) td(WE-DQ) High-order address tw(ALE) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines ta(AD) tsu(D) RDE WEL, WEH tw(WE) CS 4 to CS0 td(CS-RDE) td(CS-WE) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port P1 (A8/D8 to A15/D15) tsu(D-RDE) td(WE-DQ) External memory’s output data When BYTE = “L” (External data bus = 16 bits wide) When BYTE = “H” (External data bus = 8 bits wide) : Specifications of the 7735 Group (The others are specifications of external memory.) When data is written When data is read Middle-order address Middle-order address When data is written When data is read External memory’s output data Low-order address Low-order address Low-order address Middle-order address Middle-order address External memory’s output data

7735 Group User’s Manual17–6

Figure 17.1.2 shows the relationship between ta(AD), tsu(D) and the system clock frequency. For ta(AD) in Figure 17.1.2, an address decode time and an address latch delay time are not considered. The actual ta(AD) is a value obtained by subtracting the above times from the value shown in Fig.17.1.2. Data setup time t su(D) [MHz] [ns] 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 200 300 400 500 175 147 496 425 369 325 288 258 232 210 191 175 160 147 135 125 115 106 98 91 85 210 125 106 78 67 58 50 42 36 30 25 20 15 11 8 5 [MHz] [ns] 7 8 9 591 10 11 12 13 14 15 16 17 18 19 20 21 135 125 23 24 25 100 200 283 300 400 500 600 700 766 800 900 1000 668 527 241 180 158 138 463 533 408 362 241 208 891 429 391 357 328 302 279 259 224 209 195 182 171 622 324 292 265 241 220 202 185 171 158 146 116 108 336 122 108 95 84 74 65 58 50 44 38 33 28 No wait Wait 1 is valid. Wait 0 is valid. Address access time t a(AD) h System clock (Main clock) frequency f(XIN) h Address decode time and address latch delay time are not considered. No wait System clock (Main clock) frequency f(XIN) Wait 1 or Wait 0 is valid. Fig. 17.1.2 Relationship between ta(AD), tsu(D) and f(XIN)

7735 Group User’s Manual 17–7

(1) Timing for reading data Figure 17.1.3 shows the timing at which data is read from an external memory. When data is read, the external data bus enters a floating state and reads data from an external memory. The floating state of the external data bus is retained from when an interval of t pxz(RDE-DZ) ____ has passed after signal RDE’s falling edge until an interval of tpzx(RDE-DZ) has passed after signal ____ RDE’s rising edge. tpxz(RDE-DZ) is a constant which is independent of f(XIN); tpzx(RDE-DZ) is a constant which is dependent on f(XIN). Table 17.1.3 lists the value of tpxz(RDE-DZ) and the calculation formula for tpzx(RDE-DZ) . Note that the external data bus is multiplexed with the external address bus. Therefore, when reading data, it is necessary to consider timing to avoid collision between data being read-in and an address which is output preceding or following the data. (Refer to “(3) Precautions on memory expansion.”) Fig. 17.1.3 Timing at which data is read from external memory ten(OE) Address Address tpzx(RDE-DZ) tsu(D-RDE) ta(OE) ta(CE), ta(S) tDF , tdis(OE) h 2 h 3 tw(RDE) Data tpxz(RDE-DZ) ten(CE), ten(S) External memory data output h 1 This is applied when the external data bus = 16 bits wide (BYTE = “L”). External memory output enable signal (Read signal) OE RDE External memory chip select signalsCE, S h 2 When the external memory’s specifications are smaller than tpxz(RDE-DZ), there is a possibility that the tail of an address collides with the head of data. → Refer to “(3) Precautions on memory expansion.” h 3 When the external memory’s specifications are greater than tpzx(RDE-DZ), there is a possibility that the tail of data collides with the head of an address. → Refer to “(3) Precautions on memory expansion.” Address output A0/D 0 to A7/D7 A8/D8 to A15/D15 h 1 : Specifications of the 7735 Group (The others are specifications of external memory.)

7735 Group User’s Manual17–8

Table 17.1.3 Value of tpxz(RDE-DZ) and calculation formula for tpzx(RDE-DZ) (Unit: ns) Wait 0 Wait 1 1 5 109 2•f(f2) – 20 Software wait Wait bit Wait selection bit t pxz(RDE-DZ) tpzx(RDE-DZ) No wait 0 or 1 Wait bit: Bit 2 at address 5E16 Wait selection bit: Bit 0 at address 5F16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = “0.”

7735 Group User’s Manual 17–9

(2) Timing for writing data Figure 17.1.4 shows the timing for writing data to an external memory. When data is written, the data is output from when an interval of td(WE-DQ ) has passed after signal WEL/WEH’s falling edge until an interval of th(WE-DQ ) has passed after signal WEL/WEH’s rising edge. td(WE-DQ ) is a constant which is independent of f(XIN); th(WE-DQ ) is a constant which is dependent on f(XIN). Table 17.1.4 lists the value of td(WE-DQ ) and the calculation formula for th(WE-DQ ). Make sure that the data output timing for writing data satisfies the following specifications of the external memory: data setup time (tsu(D )) and data hold time (th(D )) for writing data. Fig. 17.1.4 Timing at which data is written to external memory Table 17.1.4 Value of td(WE-DQ) and calculation formula for th(WE-DQ) (Unit: ns) Wait 0 Wait 1 – 221 5 109 2•f(f2) No wait 0 or 1 Wait bit: Bit 2 at address 5E16 Wait selection bit: Bit 0 at address 5F16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = “0.” Software wait Wait bit Wait selection bit t d(WE-DQ ) th(WE-DQ ) External memory write signals W, WE External memory chip select signalsCE, S (The others are specifications of external memory.) : Specifications of the 7735 Grouph This is applied when the external data bus = 16 bits wide (BYTE = “L” ). WEL, WEH Address and data output hA0/D0 to A7/D7 A8/D 8 to A15/D15 tsu(D) th(D) AddressDataAddress tw(WE) th(WE-DQ) td(WE-DQ)

7735 Group User’s Manual17–10

(3) Precautions on memory expansion When specifications of the 7735 Group do not match those of an external memory as described in the following À to ´ , some considerations about the circuit are necessary: À When using an external memory which requires a long address access time (ta(AD)) \` When using an external memory which outputs data within an interval of tpxz(RDE-DZ) after signal ____ RDE’s falling edge ´ When using an external memory which outputs data for more than an interval of tpzx(RDE-DZ) ____ after signal RDE’s rising edge À When using an external memory which requires a long address access time (ta(AD)) When an external memory requires a long address access time (ta(AD)) which does not satisfy the 7735 Group’s tsu(D-RDE), try to lower f(XIN) or extend a bus cycle by inserting a wait. There are two methods for insertion of a wait: the software wait and the ready function. For the software wait, refer to section “12.2 Software wait”; for the ready function, refer to section “12.3 Ready function.” l Wait 1 (Software wait) Insert a wait equivalent to one cycle of clock φ1 while signal RDE /WEL /WEH is at “L”-level. l Wait 0 (Software wait) Insert a wait equivalent to one cycle of clock φ1 while signal RDE /WEL /WEH is at “H”- and “L”- levels. l Ready function Insert a wait in an arbitrary duration. ____ f(XIN) > 20.7 MHz, the setup time for the RDY input (tsu(RDY- φ1)) is insufficient. In this case, refer to tsu(RDY-φ1) is satisfied when f(XIN) ≤ 25 MHz. Note that a wait generated by the ready function is also is inserted are specified by using signals RSMP and CS 0.

7735 Group User’s Manual 17–11

Fig. 17.1.5 Ready generating circuit example (with no wait) M37735MHBXXXFP CS 0 RDY AC32 CS 0 RSMP RDE CS 0 RSMP RDY td(RDE- 1) td(RSMP-RDE) tc tsu(RDY- 1) h Wait generated by the ready function is inserted only to an area where accessed by signal CS 2. Circuit conditions: f(XIN) ≤ 21.3 MHz, no wait, Propagation delay time of AC32 (Max.: 8.5 ns) h Condition to satisfy the relationship of tsu(RDY- 1) ≥ 55 ns is tc+td(RSMP-RDE) ≥ 63.5 ns. Accordingly, when f(XIN) ≤ 21.3 MHz, this example satisfies the relationship of tsu(RDY- 1) ≥ 55 ns. : Wait generated by the ready function 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN) or

7735 Group User’s Manual17–12

Fig. 17.1.6 Ready generating circuit example (with wait 1) Wait generated by the ready function is inserted only to an area where accessed by signal CS2. M37735MHBXXXFP th( 1-RDY)tsu(RDY- 1) CS 0 RDY HC32 CS 0 RSMP h td(RDE- 1) Propagation delay time of HC32 RDE RDY CS 0 RSMP td(RSMP-RDE) : Wait generated by the ready function : Software wait h Make sure that the propagation delay time is within (when f(XIN) = 25 MHz, 75 ns). 3 5 10 f(XIN) + td(RSMP–RDE ) – tsu(RDY– 1 ) Circuit conditions: f(XIN) ≤ 25 MHz, wait 1 is valid, 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN)or

7735 Group User’s Manual 17–13

\` When using an external memory which outputs data within an interval of tpxz(RDE-DZ) after signal ____ RDE’s falling edge When there is a possibility that the tail of an address collides with the head of data because the ____ external memory outputs data within an interval of tpxz(RDE-DZ) after signal RDE’s falling edge, delay ____ only the signal RDE ’s front falling edge and realize the relationship of tpxz(RDE-DZ) -d < ten(OE). In this case, the falling edge of the read signal (OE ) for the memory, which is generated from signal RDE , is delayed. (Refer to Figure 17.1.7.) Fig. 17.1.7 Timing example when data output is delayed External memory output enable signal (Read signal) Address output External memory data output tpxz(RDE-DZ) RDE OE d Address Address Data ten(OE ) ta(OE ) When ten(OE) ≤ tpxz(RDE-DZ)(= 5 ns), make sure that signal RDE’s falling edge precedes signal OE’s falling edge (Refer to “d”) and the relationship of tpxz(RED-DZ)-d ≤ ten(OE) is realized. Note:

7735 Group User’s Manual17–14

´ When using an external memory which outputs data for more than an interval of tpzx(RDE-DZ) ____ after signal RDE ’s rising edge When there is a possibility that the tail of data collides with the head of an address because the ____ external memory outputs the data for more than an interval of tpzx(RDE-DZ) after signal RDE’s rising edge, try to carry out the following: l By using bus buffers and others, delete the tail of data which is output from the memory. l Use a memory which is made by MITSUBISHI ELECTRIC CORPORATION and can be connected without bus buffers. Table 17.1.5 lists memories which can be connected without bus buffers (made by MITSUBISHI ELECTRIC CORPORATION). The reason why these memories do not need buffers is that timing parameters t DF or tdis(OE) is guaranteed. (Make sure that the read signal rises within 5 ns after signal ____ RDE’s rising edge.) Table 17.1.5 Memories which can be connected without bus buffers (made by MITSUBISHI ELECTRIC CORPORATION) M5M27C256AK-85, -10, -12, -15 M5M27C512AK-10, -12, -15 M5M27C100K-12, -15 M5M27C101K-12, -15 M5M27C102K-12, -15 M5M27C201K, JK-10, -12, -15 M5M27C202K, JK-10, -12, -15 M5M27C256AP, FP, VP, RV-12, -15 M5M27C512AP, FP-15 M5M27C100P-15 M5M27C101P, FP, J, VP, RV-15 M5M27C102P, FP, J, VP, RV-15 M5M27C201P, FP, J, VP, RV-12, -15 M5M27C202P, FP, J, VP, RV-12, -15 M5M28F101P, FP, J, VP, RV-10, -12, -15 M5M28F102FP, J, VP, RV-10, -12, -15 M5M5256CP, FP, KP, VP, RV-55LL, -55XL, -70LL, -70XL, -85LL, -85XL, -10LL, -10XL M5M5278CP, FP, J-20, -20L M5M5278CP, FP, J-25, -25L M5M5278DP, J-12 M5M5278DP, FP, J-15, -15L M5M5278DP, FP, J-20, -20L Type Usage conditiontDF /tdis(OE) (Max.) 8 ns 10 ns 6 ns 7 ns 8 ns 2 • f(f 2) ≤ 20 MHz 2 • f(f2) ≤ 25 MHz EPROM One time PROM Frash memory SRAM Note: Specifications of the above memories are available if a comment “t DF/tdis = 15 ns, microcomputer and kit” is added. 15 ns (When guaranteed as kit) (Note)

7735 Group User’s Manual 17–15

Fig. 17.1.8 Bus buffer usage example (1) f(XCIN) DIR F245 BYTE A8/D8 to A15/D15 E DQ OC ALS573 OCDIR BA E DQ OC ALS573 ALE A16, A17 Address bus M37735MHBXXXFP OC BA RDE WEH F11 RD WO WE XIN XOUT F245 h 1 h 1 A0/D0 to A0/D7 CNV SS WEL h 2 Data bus (even) Data bus (odd) h 1, h 2 Make sure that the following relationships are satisfied: l The sum of output disable time of h 1 and propagation delay time of h 2 is 20 ns or less. l The sum of output enable time of h 1 and propagation delay time of h 2 is 5 ns or more. Circuit conditions: Wait 1 is valid, 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) 2 ,or

7735 Group User’s Manual17–16

5 (max.) 128 (min.) 20 (min.) F11 (tPHL ) F11 (t PLH ) D AA F245 (tPHZ /tPLZ ) WEH, WEL 130 (min.) F11 (tPLH ) D AA D F245 PHL /tPLH ) F245 PHZ /tPLZ ) F245 PZH /tPZL ) OC 45 (max.) A8/D8 to A15/D15 A0/D0 to A7/D7 A8/D8 to A15/D15 A0/D0 to A7/D7 Data output (B) from external memory <At reading> Data output (A) to external memory <At writing> (Unit: ns) Fig. 17.1.9 Timing diagram for bus buffer usage example (1)

7735 Group User’s Manual 17–17

Fig. 17.1.10 Bus buffer usage example (2) (when a memory which requires a long data hold time for writing is connected) DIR ALS245A BYTE E D Q OC ALS573 OCDIR AB E DQ OC ALS573 ALE A16, A17 OC AB 1D 1Q 2Q2T

1 F74

Data bus (even) Data bus (odd) Address bus These circuits make the rising edge of the write signal earlier by 1/2 1, so that the write hold time is extended. h 1 Make sure that the propagation delay time is 20 ns or less. Circuit conditions: Wait 1 is valid, 1= 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN)or 2 h 1, h 2 Make sure that the following relationships are satisfied: l The sum of propagation delay time of h 1 and output disable time of h 2 is 42.5 ns or less. l The sum of propagation delay time of h 1 and output enable time of h 2 is 5 ns or more.

7735 Group User’s Manual17–18

Fig. 17.1.11 Timing diagram for bus buffer usage example (2) A8/D8 to A15/D15 A0/D0 to A7/D7 Data output B from external memory 5 (max.) 42.5 (min.) D A <At reading> ALS245A (tPHZ /tPLZ ) OC ALS245A (tPZH /tPZL ) <At writing> D A D F32(tPLH ) ALS245A (tPHZ /tPLZ ) A8/D8 to A15/D15 A0/D0 to A7/D7 Data output A to external memory WO, WE WEL, WEH 45 (max.) ALS245A (tPHL /tPLH ) 220(min.) 218(min.) RDE F11 (tPHL ) F11 (tPLH ) OC F04 (tPHL )+F74 (tPLH ) F11(tPLH ) (Unit: ns) Write hold time A

7735 Group User’s Manual 17–19

Figure 17.1.12 shows a memory expansion example (with one 128-Kbyte ROM and two 32-Kbyte SRAMs, microprocessor mode). Figure 17.1.13 shows the corresponding timing diagram. E RD D0 to D15 WO M5M27C102K-15 D 0 to D15 OE A0 to A15 CE A1 to A16 S S A0 to A14 A0 to A14 DQ 1 to DQ8 DQ 1 to DQ8 OE W OE W A1 to A15 A1 to A15 D0 to D7 M5M5256P-15 D8 to D15 WE Address bus A16 A0/D0 to A7/D7 ALE RDE WEH h WEL CS 1 CS 2 Data bus (even) Data bus (odd) 000016 008016 087F16 800016 1FFFF 1 4000016 4FFFF 16 External ROM area (M5M27C102K-15) SFR area Internal RAM area External RAM area (M5M5256P-15 5 2) Memory map Not used Not used A8/D8 to A15/D15 AC573 DQ E h Circuit conditions: Wait 0 is valid, 1 = 2 , f(XIN) 8 , f(XIN) 16 , f(XIN) f(XCIN) h Make sure that the propagation delay time is 33 ns or less. or Fig. 17.1.12 ROM and SRAM expansion example

7735 Group User’s Manual17–20

Fig. 17.1.13 Timing diagram for ROM and SRAM expansion example <At reading> 128 (min.) 75(min.) 5 (max.) ta (A), ta(AD) tsu (D-RDE) ta (S) ta (OE) A A 130 (min.) WEL, WEH, W RDE, OE 20 (min.) A0/D 0 to A15/D 15 A D A A16 A CE, S, CS 1, CS2 Address output (A0 to A15) to external memory AC573 (tPHL ) <At wriring> A0/D 0 to A15/D 15 AA D 45 (max.) 75(min.) S, CS2 tsu (D) External Memory data output (Unit: ns) 15 (max.) (Guaranteed as kit.)

7735 Group User’s Manual 17–21

I/O expansion is realized with the memory-mapped method. The method and points in I/O expansion are the same as those in memory expansion. Figure 17.1.15 shows a port expansion example using the M5M81C55P-2. In this example, the M5M81C55P- 2 is connected to the external data bus and programmable I/O ports expand by 22 bits. A reset signal for an external device is supplied from port P43 and IO/M is supplied from port P44. Note that, when f(XIN) > 10 MHz, bus buffer ALS245A or others is necessary. Fig. 17.1.14 Port expansion example where M5M81C55P-2 is used CNVss BYTE A0/D0 to A7/D7 ALE M37735MHBXXXFP WEL Circuit condition: Wait 0 is valid. CE AD 0 to AD7 Port C Port B Port A M5M81C55P-2 WR P44

7735 Group User’s Manual17–22

Concerning section “17.4 Power saving,” the 7735 Group differs from the 7733 Group in the following:

• Bit 3 of the oscillation circuit control register 1 (address 6F16) must be fixed to “0.”
• External bus pins’ functions for ports P0 to P3 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “17.4 Power saving” (page 17-44 in part 1)

7735 Group User’s Manual18-2

Concerning chapter “18. LOW VOLTAGE VERSION,” the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter:

• “18.1 Performance overview”
• “18.2 Pin configuration”
• “18.3 Functional description”
• “18.4 Electrical characteristics”
• “18.6 Applications” The following section is the same as that of the 7733 Group. Therefore, refer to part 1:
• “18.5 Standard characteristics” (page 18-27 in part 1)

Concerning section “18.1 Performance overview,” the 7735 Group differs from the 7733 Group in the following:

• Description of the memory expansion in Table 18.1.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “18.1 Performance overview” (page 18-3 in part 1.) Table 18.1.1 M37735MHLXXXHP performance overview Items Memory expansion Performance Possible (Maximum of 1 Mbytes)

7735 Group User’s Manual 18-3

Figure 18.2.1 shows the M37735MHLXXXHP pin configuration. Fig. 18.2.1 M37735MHLXXXHP pin configuration (Top view) 2/AL E P31/WE H P33/HL DA XOU T E/RDE CNV SS R ESET P40/HO LD P8 6/R xD 1 P8 7/TxD1 P0 0/CS 0 P0 1/CS 1 P0 2/CS 2 P0 3/CS 3 P0 4/CS 4 P0 5/RS M P P0 6/A16 P0 7/A17 P1 0/A8/D 8 P11/A9/D 9 P12/A10/D 10 P13/A11/D 11 P14/A12/D 12 P15/A13/D 13 P16/A14/D 14 P17/A15/D 15 P20/A0/D 0 P21/A1/D 1 75 74 73 72 71 69 68 67 66 657080 79 78 77 76 64 63 62 61 3026 27 28 29 31 32 33 34 35 3621 2322 24 25 37 38 39 40 P41/RDY P42/ 1 BYT E X IN V SS P30/WE L 7/A 7/D 6/A 6/D 5/A 5/D 4/A 4/D 3/A 3/D 2/A 2/D P6 6/TB 1IN P6 5/TB 0IN P6 4/INT 2 P6 3/INT 1 P6 2/INT 0 P6 1/TA 4IN P6 0/TA 4OU T P5 7/TA 3IN /KI3 P5 6/TA 3OU T/KI2 P5 5/TA 2IN /KI1 P5 4/TA 2OU T/KI0 P5 3/TA 1IN P52 /TA 1OU T P51/TA 0IN P50/TA 0OU T P4 7 5/CL K P8 4/CT S1/RT S1 3/T XD 2/R XD 0/CL KS0 1/CL K P8 0/CT S0/RT S0/CL K S1 V CC AV CC V RE F AV SS V SS 7/AN 7/XCIN 6/AN 6/XCO UT 5/AN 5/AD TR G /TxD 2 4/AN 4/RxD 2 3/AN 3/CL K2 2/AN 2/CT S2 1/AN 1 0/AN 0 7/TB 2IN/ SUB M 37735M H LXXXH P P4 3 P4 4 P4 5 P4 6 Outline 80P6D-A

7735 Group User’s Manual18-4

The M37735MHLXXXHP has the same functions as the M37735MHBXXXFP except for the power-on reset conditions. For power-on reset conditions, refer to section “18.3.1 Power-on reset conditions” in part 1. For the other functions, refer to the following: l PART 1. 7733 GROUP

• “4. INTERRUPTS”
• “5. KEY INPUT INTERRUPT FUNCTION”
• “6. TIMER A”
• “7. TIMER B”
• “8. SERIAL I/O”
• “9. A-D CONVERTER” l PART 2. 7735 GROUP
• “2. CENTRAL PROCESSING UNIT (CPU)”
• “3. PROGRAMMABLE I/O PORTS”
• “10. WATCHDOG TIMER”
• “11. STOP AND WAIT MODES”
• “12. CONNECTING EXTERNAL DEVICES”
• “13. RESET”
• “14. CLOCK GENERATING CIRCUIT”

7735 Group User’s Manual 18-5

Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Concerning section “18.4 Electrical characteristic,” the 7735 Group differs from the 7733 Group in the following sections:

• “18.4.6 Ready and Hold”
• “18.4.8 Memory expansion mode and Microprocessor mode : with no wait”
• “18.4.9 Memory expansion mode and Microprocessor mode : with wait 1”
• “18.4.10 Memory expansion mode and Microprocessor mode : with wait 0” The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “18.4 Electrical characteristics” (page 18-7 in part 1)

tsu(RDY– φ1) tsu(HOLD– φ1) th(φ1–RDY) th(φ1–HOLD) Max. ns ns ns ns Min. ParameterSymbol Unit ____ RDY input setup time HOLD input setup time ____ RDY input hold time HOLD input hold time Note: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. td(φ1–HLDA) ns Min. Max. 120 Limits UnitConditionsParameterSymbol HLDA output delay time Fig. 18.4.1 Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz, unless otherwise noted)

7735 Group User’s Manual18-6

RDE, WEL, WEH output RDE, WEL, WEH output RDY input tsu(RDY– 1) th( 1–RDY) tsu(RDY– 1) th( 1–RDY) Measuring conditions

• VCC = 2.7 to 5.5 V
• Input timing voltage : VIL = 0.2 VCC , VIH = 0.8 VCC
• Output timing voltage: VOL = 0.8 V, VOH = 2.0 V HOLD input HLDA output th( 1–HOLD) td( 1–HLDA) tsu(HOLD– 1) Hold td( 1–HLDA)

7735 Group User’s Manual 18-7

td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th(φ 1–RSMP) td(WE– φ 1) td(RDE– φ 1) td(φ 1–HLDA) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) Parameter Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL, WEH pulse width Floating start delay time Floating release delay time ____ RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time HLDA output delay time Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz, unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data formula (Min.) – 63 – 63 – 63 – 43 – 43 – 73 Conditions Fig. 18.4.1 tc tw(H) tw(L) tr tf tsu(D–RDE) th(RDE–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 166 ns. 3: When the main clock division selection bit = “1,” values of tw (H)/tc and tw (L)/tc must be set to values from 0.45 through 0.55. 120 1 5 109 2•f(f2) 2 5 109 2•f(f2) 1 5 109 2•f(f2) 2 5 109 2•f(f2) 1 5 109 2•f(f2) – 43 – 35 – 30 – 38 – 58 Note: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1 in part 1. Max.Min. 131 128

7735 Group User’s Manual18-8

th(WE–DQ) tsu(A–ALE)Address/Data output A0/D0–A15/D15 (BYTE = “L”) A0/D0–A7/D7 (BYTE = “H”) td(WE– 1) td(CS–WE) td(WE– 1) tw(WE) td(RSMP–WE) XIN CS 0–CS 4 output WEL output WEH output RDE output With no wait (Wait bit = “1”) td(RDE– 1) Memory expansion mode and Microprocessor mode : td(An–WE) ALE output tw(H)tw(L) tf tr tc th(ALE–A) tw(H)tw(L) tf tr tc th(WE–CS) Address output A8–A15 (BYTE = “H”) A16, A17 tw(ALE) td(A–WE) td(WE–DQ) Data input D 0–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H”) RSMP output td(ALE–WE) th(WE–An) td(RDE– 1) th(RDE–CS)td(CS–RDE) th(RDE–An)td(An–RDE) tpzx(RDE–DZ)td(A–RDE) tsu(D–RDE) th(RDE–D) td(RSMP–RDE) Measuring conditions (CS0–CS 4, A0/D0–A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP)

• VCC = 2.7–5.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : VIL = 0.16 VCC , VIH = 0.5 VCC Port Pi output (i = 4–8) Port Pi input (i = 4–8) Measuring conditions (Ports P4–P8)
• VCC = 2.7–5.5 V
• Input timing voltage : VIL = 0.2 VCC , VIH = 0.8 VCC
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V td(WE–PiQ) tsu(PiD–RDE) th(RDE–PiD) tsu(A–ALE) tw(ALE) th(ALE–A) td(ALE–RDE) tw(RDE) Address Address Address Address Data Address Data Address Address Data tpxz(RDE–DZ) 1–RSMP)th( 1–RSMP)th(

7735 Group User’s Manual 18-9

td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th(φ 1–RSMP) td(WE– φ 1) td(RDE– φ 1) td(φ 1–HLDA) 1 5 109 2•f(f2) 4 5 109 2•f(f2) 1 5 109 2•f(f2) Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz, unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LimitsData formula (Min.) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) tc tw(H) tw(L) tr tf tsu(D–RDE) th(RDE–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 166 ns. 3: When the main clock division selection bit = “1,” values of tw (H)/tc and tw (L)/tc must be set to values from 0.45 through 0.55. Parameter Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL, WEH pulse width Floating start delay time Floating release delay time ____ RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time HLDA output delay time 120 1 5 109 2•f(f2) 4 5 109 2•f(f2) Note: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1 in part 1. – 43 – 35 – 30 – 38 – 58 – 63 – 63 – 63 – 43 – 43 – 73 Conditions Fig. 18.4.1 Max.Min. 298 295

7735 Group User’s Manual18-10

th(ALE–A) td(WE–DQ) td(An–RDE) th(WE–DQ)tsu(A–ALE)Address/Data output A0/D0–A15/D15 (BYTE = “L”) A0/D0–A7/D7 (BYTE = “H”) td(WE– 1) td(CS–WE) td(WE– 1) tw(WE) td(RSMP–WE) XIN CS 0–CS 4 output WEL output WEH output RDE output When external memory area is accessed with wait 1 (Wait bit = “0” and Wait selection bit = “1”) td(RDE– 1) Memory expansion mode and Microprocessor mode : td(An–WE) ALE output tw(H)tw(L) tf tr tc th(ALE–A) th(WE–CS) Address output A8–A15 (BYTE = “H”) A16, A17 tw(ALE) td(A–WE) Data input D 0–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H”) RSMP output td(ALE–WE) th(WE–An) td(RDE– 1) th(RDE–CS)td(CS–RDE) th(RDE–An) td(ALE–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ)td(A–RDE) tsu(D–RDE) th(RDE–D) tw(RDE) td(RSMP–RDE) Measuring conditions (CS0–CS 4, A0/D0–A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP)

• VCC = 2.7–5.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input IL = 0.16 VCC , VIH = 0.5 VCC Port Pi output (i = 4–8) Port Pi input (i = 4–8) Measuring conditions (Ports P4–P8)
• VCC = 2.7–5.5 V
• Input timing voltage : VIL = 0.2 VCC , VIH = 0.8 VCC
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V td(WE–PiQ) tsu(PiD–RDE) th(RDE–PiD) tw(H)tw(L) tf tr tc tw(ALE) tsu(A–ALE) Address Address Address Address Address Data Address Address Address Data 1–RSMP)th( 1–RSMP)th(

: V

7735 Group User’s Manual 18-11

2•f(f2) 4 5 109 2•f(f2) 1 5 109 2•f(f2) 3 5 109 2•f(f2) 3 5 109 2•f(f2) 3 5 109 2•f(f2) 1 5 109 2•f(f2) 2 5 109 2•f(f2) 2 5 109 2•f(f2) 1 5 109 2•f(f2) 1 5 109 2•f(f2) Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) h The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz, unless otherwise noted) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LimitsData formula (Min.)Parameter Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL, WEH pulse width Floating start delay time Floating release delay time ____ RDE pulse width RSMP output delay time RSMP hold time φ 1 output delay time HLDA output delay time tc tw(H) tw(L) tr tf tsu(D–RDE) th(RDE–D) Min. ns ns ns ns ns ns ns Limits Unit External clock input cycle time (Note 2) External clock input high-level pulse width (Note 3) External clock input low-level pulse width (Note 3) External clock rise time External clock fall time Data input setup time Data input hold time Parameter Max. Symbol Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2: When the main clock division selection bit = “1,” the minimum value of tc = 166 ns. 3: When the main clock division selection bit = “1,” values of tw (H)/tc and tw (L)/tc must be set to values from 0.45 through 0.55. 1 5 109 2•f(f2) 4 5 109 2•f(f2) – 43 – 35 – 30 – 38 – 58 – 68 – 68 – 88 – 43 – 43 – 73 – 43 – 43 Symbol td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th(φ 1–RSMP) td(WE– φ 1) td(RDE– φ 1) th(φ 1–HLDA) Conditions Fig. 18.4.1 120 Max.Min. 182 182 162 123 298 295

7735 Group User’s Manual18-12

td(WE–DQ) td(WE–PiQ) td(An–RDE) tsu(A–ALE) Address/Data output A0/D0–A15/D15 (BYTE = “L”) A0/D0–A7/D7 (BYTE = “H”) td(CS–WE) td(WE– 1) tw(WE) td(RSMP–WE) XIN CS 0–CS 4 output WEL output WEH output RDE output When external memory area is accessed with wait 0 (Wait bit = “0” and Wait selection bit = “0”) Memory expansion mode and Microprocessor mode : td(An–WE) ALE output tw(H)tw(L) tf tr tc th(WE–CS) Address output A8–A15 (BYTE = “H”) A16, A17 tw(ALE) td(A–WE) Data input D 0–D 15 (BYTE = “L”) D 0–D 7 (BYTE = “H”) RSMP output td(ALE–WE) th(WE–An) td(RDE– 1) th(RDE–CS)td(CS–RDE) th(RDE–An) td(ALE–RDE) tpxz(RDE–DZ) td(A–RDE) tsu(D–RDE) th(RDE–D) tw(RDE) td(RSMP–RDE) Measuring conditions (CS0–CS 4, A0/D0–A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP)

• VCC = 2.7–5.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input IL = 0.16 VCC , VIH = 0.5 VCC Port Pi output (i = 4–8) Port Pi input (i = 4–8) Measuring conditions (Ports P4–P8)
• VCC = 2.7–5.5 V
• Input timing voltage : VIL = 0.2 VCC , VIH = 0.8 VCC
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V tsu(PiD–RDE) th(RDE–PiD) th(WE–DQ) tw(H)tw(L) tf tr tc tw(ALE) th(ALE–A) tsu(A–ALE)th(ALE–A) Address Address Address Data Data Address Address Data tpzx(RDE–DZ) 1)td(WE– 1)td(RDE– 1–RSMP)th( 1–RSMP)th(

: V

7735 Group User’s Manual 18-13

Some application examples of connecting external memorys for the low voltage version are described below. For the basic description of the memory expansion, refer to chapter “17. APPLICATIONS. ” Applications shown here are just examples. Modify the desired application to suit the user’s need and make sufficient evaluations before actually using it. The following items of the 7735 Group’s low voltage version are the same as section “17.1 Memory expansion ” in part 1, but a part of the caluculation way and constants for each parameter is different:

• Memory expansion model
• Caluculation way for address access time of external memory
• Bus timing
• Memory expansion way À Address access time of external memory ta(AD) ta(AD) = td(A-RDE) + tw(RDE) – tsu(D-RDE) – (address decode time] 1 + address latch delay time] 2) address decode time] 1 : time necessary for validating a chip select signal after an address is decoded address latch delay time] 2 : time necessary for latching an address \` Data setup time of external memory for writing data tsu(D) tsu(D) = tw(WE) – td(WE–DQ) Table 18.6.1 lists the caluculation formulas and constants for each parameter of the low voltage version. between tsu(D) and 2•f(f2). Table 18.6.1 Caluculation formulas and constants for each parameter (Unit : ns) Wait 1 Wait 0 No wait 0 or 1 4 5 109 2•f(f2) Wait bit : Bit 2 at address 5E16 Wait selection bit : Bit 0 at address 5F16 Note: This is applied to the case where the system clock selection bit (bit 3 at address 6C16) = “0.” – 63 – 38 – 35 – 35 –38 – 883 5 109 2•f(f2) 1 5 109 2•f(f2) Software wait Wait bit Wait selection bit td(A-RDE) tw(RDE) tw(WE) tsu(D-RDE) td(WE-DQ) 2 5 109 2•f(f2) 2 5 109 2•f(f2) 4 5 109 2•f(f2)

MHz] LOW VOLTAGE VERSION

7735 Group User’s Manual18-14

Fig. 18.6.2 Relationship between tsu(D) and 2•f(f2) Fig. 18.6.1 Relationship between ta(AD) and 2•f(f2) [ns] 2 3 4 5 6 7 8 9 10 11 12 152 500 1000 1500 2000 2500 3000 3500 3294 2127 1194 960 794 669 571 430 377 2319 1485 1069 819 652 533 235 1319 569 247 194 819 319 119 91 273 494 1544 319 374444 419 No wait Wait 1 is valid. Wait 0 is valid. Address access time ta (AD) External clock input frequency 2•f(f2) ] Address decode time and address latch delay time are not idd [MHz] [ns] 2 3 4 5 6 7 8 9 10 11 12 500 1000 1500 2000 208 541 875 675 541 1875 1208 319 275 238 875 275 208 160 125 97 75 56 375 446 375 No wait Wait 1 or Wait 0 is valid. External clock input frequency 2•f(f2) Data setup time tsu(D)

7735 Group User’s Manual 18-15

18.6.2 Memory expansion example

Figure 18.6.3 shows a memory expansion example and Figure 18.6.4 shows the corresponding timing diagram. In this example, an Atmel company’s EPROM (AT27LV256R) is used as the external ROM. Fig. 18.6.3 Memory expansion example XIN XOUT M37735MHLXXXHP BYTE Data bus H C573 DQ E RD D0 to D7 AT27LV256R-15DI D 0 to D7 OE A0 to A14 CE A0 to A14 A0 to A16 DQ 1 to DQ 8 OE W A0 to A16 D0 to D7 M5M51008AFP-15VLL WR Address bus A0/D0 to A7/D7 ALE RDE CNV SS WEL CS1 CS2 000016 008016 087F16 800016 FFFF 16 4000016 5FFFF 16 External ROM area (AT27LV256R-15DI) SFR area Internal RAM area External RAM area (M5M51008AFP-15VLL) Memory map Not used Not used A8 to A16 h Circuit conditions : Wait 1 h Make sure that the propagation delay time is 85 ns (max.) or less. 1 = , , , or 2 f(XIN) f(XIN) f(XIN) f(XCIN) Supply voltage : Vcc = 3.0 to 5.5 V (Can operate with no wait when f(XIN) £ 8.0 MHz.)

7735 Group User’s Manual18-16

Fig. 18.6.4 Timing diagram RDE, OE 295 (min.) tsu(D-RDE) 298 (min.) (Unit : ns) WEL, W 20 (min.) CE, S1, 4 (min.) CS 2, S1 20 (min.) A8 to A16 A A A0/D 0 to A7/D 7 A A 90 (min.) A Extermal memory data output A D 10 (max.) ta(A), tACC ta(S1),tCE ta(OE),tOE HC573 (tPHL/PLH) A8 to A16 A A0/D 0 to A7/D 7 53 (min.) tdis(OE),tDF tdis(S1) A CS 1, CS2 tsu(D) l At writing At reading A D

7735 Group User’s Manual 18-17

18.6.3 Ready generating circuit example

When validating “wait” only for a certain area (for example, ROM area) in Figure 18.6.3, use the ready function. Figure 18.6.5 shows a ready generating circuit example. M37735MHLXXXHP CS 0 RDY AC32 CS 0 RSMP RDE CS 0 RSMP RDY td(RDE- 1) td(RSMP-RDE) tc tsu(RDY- 1) Wait generated by the ready function is inserted only to an area where accessed by signal CS0. Circuit conditions : f(XIN) £ 12 MHz, no wait, Propagation delay time of AC32 (max. : 28 ns) ] Condition to satisfy the relationship t tc+td(RSMP-RDE) ‡ 108 ns Accordingly, when f(XIN) £ 12 MHz, this example satisfies the relationship t : Wait generated by the ready function 1 = , , , or 2 f(XIN) f(XIN) f(XIN) f(XCIN) su(RDY- 1) ‡ 80 ns is su(RDY- 1) ‡ 80 ns. Fig. 18.6.5 Ready generating circuit example

7735 Group User’s Manual18-18

7735 Group User’s Manual19-2

Concerning chapter “19. BUILT-IN PROM VERSION,” the 7735 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter:

• “19.1 EPROM mode” The following section of the 7735 Group is the same as that of the 7733 Group. Therefore, for this section, refer to part 1:
• “19.2 Usage precaution” (page 19-10 in part 1)

Concerning section “19.1 EPROM mode,” the 7735 Group differs from the 7733 Group in the following:

• Figures 19.1.1 and 19.1.2
• Bit 3 of the oscillation circuit control register 1 (address 6F 16) is “1” at reset. After reset, this bit must be cleared to “0” in the single-chip mode. This writing must be performed with the procedure shown in Figure 14.3.4. The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “19.1 EPROM mode” (page 19-3 in part 1)

7735 Group User’s Manual 19-3

Fig. 19.1.1 Pin connections in EPROM mode (M37735EHBFP) 2/RxD 0/CLKS 1/CLK P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P41/RDY

60 P00/CS0

59 P01/CS1

58 P02/CS2

57 P03/CS3

56 P04/CS4

55 P05/RSMP

54 P06/A16

53 P07/A17

44 P20/A0/D0

43 P21/A1/D1

42 P22/A2/D2

41 P23/A3/D3

/TxD 6/AN 6/X COUT 7/AN 7/X CIN V SS AV SS V REF AV CC V CC 0/CTS 0/RTS 0/CLKS 3/TxD 5/A 5/D 6/A 6/D 0/HOLD BYTE CNV SS RESET X IN X OUT E/RDE V SS 3/HLDA 2/ALE 1/WEH 0/WEL 7/A 7/D 4/A 4/D M37735EHBFP A10 A11 A12 A13 A14 D 0 D 1 D 2 D 3 OE CE V PP D D D D VSS A15 PGM VCC P70/AN0 P67/TB2IN/ SUB A Outline 80P6N-A * : Connect these pins to a resonator or an oscillator. : EPROM pin.

7735 Group User’s Manual19-4

Fig. 19.1.2 Pin connections in EPROM mode (M37735EHLHP) X OUT 2/ALE 0/WEL 1/WEH D A14 P86/RXD 1 P87/TXD 1 P00/CS0 P01/CS1 P02/CS2 P03/CS3 P04/CS4 P05/RSMP P06/A16 P07/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A0D 0 P21/A1/D1 75 74 73 72 71 69 68 67 66 657080 79 78 77 76 64 63 62 61 3026 27 28 29 31 32 33 34 35 3621 2322 24 25 37 38 39 40 1/RDY 0/HOLDBYTECNV SS RESET X IN E/RDE V SS 3/HLDA 7/A 7/D 6/A 6/D 5/A 5/D 4/A 4/D P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 5/CLK 4/CTS 1/RTS 3/T XD 2/R XD 0/CLKS 1/CLK 0/CTS 0/RTS 0/CLKS V CC AV CC V REF AV SS V SS 7/AN 7/X CIN 6/AN 6/X COUT 5/AN 5/AD TRG /TxD 4/AN 4/RxD 3/AN 3/CLK 2/AN 2/CTS 1/AN 0/AN 7/TB2 IN SUB M 37735E H LH P P43 P44 P45 P46 3/A 3/D 2/A 2/D VCC A15 A13 A12 A10 A11 D 0 D 1 D D D D D V PP VSS CE PGM OE A Outline 80P6D-A * : Connect these pins to a resonator or an oscillator. : EPROM pin.

7735 Group User’s Manual20–2

The external ROM version can operate only in the microprocessor mode. Functions of the external ROM version differ from those of the mask ROM version in the following. Therefore, only the differences are described in this chapter:

• Memory allocation
• Operation is available only in the microprocessor mode
• ROM area change function is not available.
• Timer A has the pulse output port mode.
• Power source current and Current consumption For the other functions, refer to the following:
• Chapters “4. INTERRUPTS” to “9. A-D CONVERTER” in part 1
• Chapter “2. CENTRAL PROCESSING UNIT (CPU)” in part 2
• Chapter “3. PROGRAMMABLE I/O PORT” in part 2
• Chapters “10. WATCHDOG TIMER” to “17. APPLICATIONS” in part 2 h For product expansion information of the 7735 Group, contact the appropriate office, as listed in “CONTACT ADDRESSES FOR FURTHER INFORMATION.”

7735 Group User’s Manual 20–3

Performance overview of the external ROM version differs from that of the mask ROM version in the following: memory size and current consumption. For the other items, refer to section “1.1 Performance overview” in part 2. Table 20.1.1 lists the M37735S4BFP’s performance overview. Table 20.1.1 M37735S4BFP’s performance overview Items Memory size Current consumption RAM Performance 2048 bytes 57 mW (When f(X IN) = 25-MHz external square wave input, Vcc = 5 V, and the main clock is the system clock, Typ.) 300 µW (When f(X CIN ) = 32 kHz, Vcc = 5 V, the sub clock is the system clock, and the main clock is stopped, Typ.)

7735 Group User’s Manual20–4

Figure 20.2.1 shows the M37735S4BFP pin configuration. Note: For the low voltage version, refer to section “20.10 Low voltage version.” Fig. 20.2.1 M37735S4BFP pin configuration (Top view) 25 2726 28 3429 30 31 32 33 35 36 37 38 39 40 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3/RTP13 P56/TA3OUT /KI2/RTP12 P55/TA2IN/KI1/RTP11 P54/TA2OUT /KI0/RTP10 P53/TA1IN/RTP03 P52/TA1OUT /RTP02 P51/TA0IN/RTP01 P50/TA0OUT /RTP00 HOLD BYTE CNV SS RESET XIN XOUT RDE Vss (P33)HLDA (P32)ALE (P31)WEH (P30)WEL (P27)A7/D7 (P26)A6/D6 (P25)A5/D5 (P24)A4/D4 P74/AN4/RXD 2 P75/AN5/ADTRG /TXD 2 P76/AN6/XCOUT P77/AN7/XCIN VSS AV SS VREF AV CC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD 0/CLKS0 P83/TXD 0 P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 CS 0(P00) CS 1(P01) CS 2(P02) CS 3(P03) CS 4(P04) RSMP(P0 5) A16(P06) A17(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) 80 79 78 77 76 75 74 73 72 71 69 68 67 66 6570 Outline 80P6N-A A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A0/D0(P20) A1/D1(P21) A2/D2(P22) A3/D3(P23) M37735S4BFP 24RDY P47 P46 P45 P44 P43 (P42)/ 1 P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin’s level can be fixed in the stop or wait mode.

7735 Group User’s Manual 20–5

To pin Vcc, apply 5 V±10% (When the main clock is the system clock) or 2.7 V to 5.5 V (When the sub- clock is the system clock). To pin Vss, apply 0 V. Connect to pin Vcc. The microcomputer is reset when “L” level is input to this pin. Pins X IN and X OUT are the I/O pins of the clock generating circuit, respectively. Connect these pins via a ceramic resonator or a quartz-crystal oscillator. When an external clock is used, the clock should be input to pin X IN, and pin XOUT should be left open. This pin outputs read enable signal RDE . RDE ’s level is “L” in the data read period of the read cycle. Input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. A 16-bit width is selected when the level is “L,” and an 8-bit width is selected when the level is “H.” Power source input for the A-D converter. Connect to pin Vcc. Power source input for the A-D converter. Connect to pin Vss. This is the reference voltage input pin for the A-D converter. These pins respectively output signals CS 0–CS 4, RSMP , and high-order 2 bits (A16, A17) of address. l Signals CS 0–CS 4 These signals are the chip-select signals. When the microcomputer accesses a certain area, the corresponding pin outputs “L“ level. (Refer to Figure 12.1.3.) l Signal RSMP This signal is the ready sampling signal and is used ____ to generate signal RDY for accessing the external memory area. l When the external data bus width = 8 bits (Pin BYTE is at “H” level) Address’s middle-order 8 bits (A 8–A 15) are output. l When the external bus width = 16 bits (Pin BYTE pin is at “L” level) Input/Output of data (D 8–D 15) and output of address’s middle-order 8 bits (A8–A 15) are performed with the time sharing system. Name Power source input CNVss Reset input Clock input Clock output Read enable output External data bus width selection input Analog power source input Reference voltage input Chip select output, Ready sampling output, Address (high-order) output Address (middle-order) output/Data I/O Table 20.3.1 Pin description (1) Pin Vcc, Vss CNVss RESET X IN X OUT ____ RDE BYTE AVcc AVss V REF ____ CS 0 (P00)– ____ CS 4 (P04), RSMP (P05), A 16 (P06), A 17 (P07) A 8/D8 (P10) – A 15/D15 (P17) Input/Output Input Input Input Output Output Input Input Output I/O

7735 Group User’s Manual20–6

Table 20.3.2 Pin description (2) Input/Output I/O Output Input Input Output I/O I/O I/O I/O I/O Functions Input/Output of data (D0–D 7) and output of address’s low-order 8 bits (A0–A 7) are performed with the time sharing system. These pins respectively output signals WEL , WEH , ALE, and HLDA . l Signals WEL, WEH ____ Signal WEL is the write enable low signal. ____ Signal WEH is the write enable high signal. These signals’ levels are “L” in the data write period of the write cycle. The operations of these signals depend on the level of pin BYTE. (Refer to Table 12.1.1.) l Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and data. l Signal HLDA This signal informs the external whether this microcomputer enters the Hold state or not. In Hold state, pin HLDA outputs “L” level. The microcomputer is in Hold state while pin HOLD ’s ____ input level is “L” and is in Ready state while pin RDY ’s input level is “L.” The clock φ1 output can be stopped by software. (Refer to chapter “14. CLOCK GENERATING CIRCUIT.” ) P4 3–P4 7 function as I/O ports with the same functions as port P5. P5 is a CMOS 8-bit I/O port and has an I/O direction register. Each pin can be programmed for input or output. It can be programmed as I/O pins for timers A0–A3, input pins (KI0–KI3) for the key input interrupt and output pins (RTP00–RTP1 3) for the pulse output. P6 is an 8-bit I/O port with the same function as port P5 and can be programmed as I/O pins for timer A4, external interrupt input pins, and input pins for timers B0–B2. P6 7 also functions as an output pin for the sub clock (φSUB ). P7 is an 8-bit I/O port with the same function as port P5 and can be programmed as analog input pins for the A-D converter. P7 6 and P77 can be programmed as I/O pins (XCOUT , XCIN ) for the sub-clock (32 kHz) oscillation circuit. When using P76 and P77 as pins XCOUT and XCIN , connect a quartz-crystal oscillator between them. P72–P7 5 also function as UART2’s I/O pins. P8 is an 8-bit I/O port with the same function as port P5 and can be programmed as serial I/O’s I/O pins. Name Address (low-order) output/Data (low-order) I/O Write enable low output, Write enable high output, Address latch enable output, Hold acknowledge output Hold request input, Ready input, Clock output, I/O port P4 I/O port P5 I/O port P6 I/O port P7 I/O port P8 Pin A 0/D0 (P2 0) –A 7/D7 (P27) ____ WEL (P30), ____ WEH (P31), ALE (P3 2), HLDA (P33) HOLD , ____ RDY , φ1(P42), P4 3–P4 7 P5 0–P5 7 P6 0–P6 7 P7 0–P7 7 P8 0–P8 7

7735 Group User’s Manual 20–7

Figure 20.4.1 shows the M37735S4BFP block diagram. Fig.20.4.1 M37735S4BFP block diagram XIN XOUT RESET VREF CNVss BYTEAV SS (0V) AV CC (0V) VSSVCC XCIN XCOUT

1 RDY HOLD HLDA ALE WEH WEL RDE RSMP

UART1 (9) UART0 (9) UART2 (9) Clock input Clock output Reset input Reference voltage input Clock Generating Circuit Data Buffer DBH (8) Data Buffer DBL(8) Instruction Queue Buffer Q0 (8) Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8) Data Bank Register DT(8) Program Counter PC(16) Incrementer/Decrementer(24) Program Bank Register PG(8) Input Buffer Register IB(16) Direct Page Register DPR(16) Stack Pointer S(16) Index Register Y(16) Index Register X(16) Anthmetic Logic Unit(16) Accumulator B(16) Accumulator A(16) Instruction Register(8) Data Bus(Even) Data Bus(Odd) Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Watchdog Timer External data bus width selection input Timer TB1(16) Timer TB2(16) Address bus/ Data bus Timer TB0(16) Timer TA1(16) Timer TA2(16) Timer TA3(16) Timer TA4(16) Timer TA0(16) RAM 2048 bytes Central Processing Unit (CPU) Incrementer(24) Program Address Register PA(24) Data Address Register DA(24) Address Bus Bus Interface Unit (BIU) Processor Status Register PS(11) A-D Converter(10) Address (18) / data (16) Chip select

7735 Group User’s Manual20–8

The internal area’s memory allocation is described below. For details, refer to section “2.4 Memory allocation” M37735S4BFP’s memory map and Figure 20.5.2 shows the SFR area’s memory map.

7735 Group User’s Manual 20–9

Fig. 20.5.1 M37735S4BFP’s memory map 01FFFF 16 10000016 00000016 00007F16 00008016 00087F16 FFFFFF 16 00080016 00FFFF 16 01000016 00000016 00007F16 INT1 INT0 DBC RESET 00FFD6 16 00FFFE 16 0FFFFF 16 (Note) Timer A4 SFR area Internal RAM area 2048 bytes Bank 016 Bank 116 A-D/UART2 trans./rece. UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A3 Timer A2 Timer A1 Timer A0 INT 2/Key input Watchdog timer BRK instruction Zero divide Interrupt vector table Peripheral device control registers (SFR) UART1 transmission UART0 transmission Refer to Figure 20.5.2. : External memory area For the 7735 Group’s microcomputers other than the M37735S4BFP, refer to section “Appendix 1. 773 5 Group memory allocation .” h

• RAM size: 2 Kbytes Note: Banks 1016 to FF16 cannot be accessed.

These registers are used when outputting an arbitrary data in the stop or wait mode. EXTERNAL ROM VERSION

7735 Group User’s Manual20–10

Fig. 20.5.2 SFR area’s memory map UART 0 transmission interrupt control register UART 1 transmission interrupt control register INT2/Key input interrupt control register Port P1 direction register (Note 3) UART 0 transmit/receive mode register UART 0 baud rate register (BRG0) UART 0 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 0 transmission buffer register UART 1 transmit/receive control register 0 UART 1 transmit/receive mode register UART 1 baud rate register (BRG1) UART 1 transmit/receive control register 1 UART 0 receive buffer register UART 1 transmission buffer register UART 1 receive buffer register Port P0 register (Note 3) A-D register 0 A-D register 2 Port P1 register (Note 3) Port P0 direction register (Note 3) Port P2 register (Note 3) Port P3 register (Note 3) Port P4 register (Note 3) Port P5 register Port P6 register Port P7 register Port P8 register A-D control register 0 A-D control register 1 A-D register 1 A-D register 3 A-D register 4 A-D register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001A 00001B 00001C 00001D 00001E 00001F 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002A 00002B 00002C 00002D 00002E 00002F 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003A 00003B 00003C 00003D 00003E 00003F 00000B 00000C 00000D 00000E 00000F 00000A 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F 00004B 00004C 00004D 00004E 00004F 00004A 000044 Address (Hexadecimal notation) Address (Hexadecimal notation) Timer A1 register Timer A4 register Timer A2 register Timer A3 register Timer B0 register Timer B1 register Timer B2 register Count start flag One-shot start flag Up-down flag Timer A0 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Watchdog timer register Watchdog timer frequency selection flag A-D/UART2 trans./rece. interrupt control register UART 0 receive interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register Processor mode register 1 Oscillation circuit control register 1 Serial transmit control register Port function control register Oscillation circuit control register 0 Timer A3 mode register Port P2 direction register (Note 3) Port P3 direction register (Note 3) Port P4 direction register (Note 3) Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Pulse output data register 1 (Note 1) A-D register 6 A-D register 7 UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Waveform output mode register (Note 1) Notes 1: Memory map of the M37735S4BFP differs from that of the M37735MHBXXXFP in addresses 1C 16, 1D16, 6216, and 6316. 2: Writing to the reserved area is disabled. Pulse output data register 0 (Note 1) Reserved area (Notes 1, 2) A-D control register 1

7735 Group User’s Manual 20–11

The M37735S4BFP can operate only in the microprocessor mode. For the processor mode, refer to the description of the microprocessor mode in section “2.5 Processor modes” in part 1. Also, be sure to set as follows:

• Connect pin CNVss to Vcc.
• Fix the processor mode bit to “102.“ Figure 20.6.1 shows the structure of the processor mode register 0. Fig. 20.6.1 Structure of processor mode register 0 Bit Bit name Functions At reset RW Processor mode bits Wait bit Software reset bit Interrupt priority detection time selection bits Must be fixed to “0.” This bit is ignored. (it may be “0” or “1.”) 0 0: Do not select. 0 1: Do not select. 1 0: Microprocessor mode 1 1: Do not select. Microcomputer is reset by setting this bit to “1.” This bit is “0” at reading. 0 0: 7 cycles of 0 1: 4 cycles of 1 0: 2 cycles of 1 1: Do not select. b1 b0 b5 b4 Processor mode register 0 (address 5E16) represents that bits 2 to 7 are not used for setting the processor mode. b1 b0b2b3b4b5b6b7 RW RW RW WO RW RW RW RW 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area.

7735 Group User’s Manual20–12

20.7 Timer A, 20.8 Reset The timer A description of the M37735S4BFP is the same as that of the 7733 Group. For timer A description of the M37735S4BFP, refer to the following:

• “6. TIMER A” (page 6-2 in part 1)
• “20.7 Timer A” (page 20-12 in part 1)

The reset description of the M37735S4BFP differs from that of the mask ROM version in the state immediately after reset. The state immediately after reset of the M37735S4BFP differs from that of the mask ROM version in the following addresses: addresses 1C 16, 1D16, 6216 and 6316. Figures 20.8.1 and 20.8.2 show the state of SFR area and internal RAM area immediately after reset (1) in part 1. For the other descriptions, refer to chapter “13. RESET.” For the pin state while pin RESET is at “L” level, refer to Table 13.1.1.

7735 Group User’s Manual 20–13

Fig. 20.8.1 State of SFR area and internal RAM area immediately after reset (1) : “0” immediately after reset. : “1” immediately after reset. : Undefined immediately after reset. : Always “0” at reading 0 : Always undefined at reading : “0” immediately after reset. Must be fixed to “0.” 1016 1116 1216 1316 Port P8 direction register1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 016 116 216 316 416 516 616 716 816 916 B16 C 16 D 16 E16 F16 A16 Address Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register 0 A-D control register 1 Port P0 register Port P1 register Port P2 register Port P3 register Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Register name Access characteristics State immediately after reset RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0016 0016 0016 0016 0016 00 0 0 0 0 000 0 00 0016 0 0 000 ? 00 11 b7 b0 b7 b0 n SFR area (addresses 016 to 7F16) RW 0016 h The contents of addresses 1C16 and 1D16 of the M37735S4BFP differ from those of the M37735MHBXXXFP. Abbreviations which represent access characteristics RW RW ?? 0 ? ?? ? 0016 Pulse output data register 1 Pulse output data register 0 WO WO h h : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Not implemented. It is impossible to read the bit state. The written value becomes invalid. RW RO WO

7735 Group User’s Manual20–14

Fig. 20.8.2 State of SFR area and internal RAM area immediately after reset (4) RO UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address Oscillation circuit control register 0 Serial transmit control register A-D / UART 2 trans./rece. interrupt control register UART0 transmission interrupt control register UART1 transmission interrupt control register INT2/Key input interrupt control register Watchdog timer frequency selection flag Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW( h 2) RW RW RW RW b7 b0 WO RW RW RW RW RW RW RW RW RW RW State immediately after reset 0 00 0 ? 0 ? (h 1) b7 b0 0 0 0 0 0 00 0 00 00 00 0 00 0 Port function control register UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register RW RW WO RW RW RW 00 0 0 0 1 00 00 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 0 0 0 0 00 0 0 00 0 0 00 0 00 0 00 0 00 0 00 0 A value of “FFF16” is set to the watchdog timer. (Refer to Chapter “10. WATCHDOG TIMER” in part 1.) For access characteristics at address 6C16, also refer to Figure 14.3.2 in part 1. The contents of addresses 6216 and 6316 of the M37735S4BFP differ from those of the M37735MHBXXXFP. Do not wirte to address 6316. n Internal RAM area (M37735S4BFP: addresses 8016 to 87F16) l At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. l At software reset...Retains the state immediately before reset. l When the stop or wait mode is terminated (when hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. RW 00 0 h 1 h 2 h 3 h 4 Waveform output mode register h 3 (Reserved area) h 4 UART 2 transmit/receive mode register UART 2 baud rate register (BRG2) UART 2 transmission buffer register UART 2 transmit/receive control register 0 UART 2 transmit/receive control register 1 UART 2 receive buffer register Oscillation circuit control register 1 RW ? 00 0 00 00 WO WO WO RWRO 1 00 0 RW RWRORO 00 0 0 00 10 RO 00 0 000 ? RW ?? 0 00 0 0 00 0 RWRWRW 0 ? 0 00 ?

7735 Group User’s Manual 20–15

Except for “Icc,” the electrical characteristics of the M37735S4BFP are the same as those of the M37735MHBXXXFP in the microprocessor mode. For the others, refer to chapter “15. ELECTRICAL CHARACTERISTICS.” ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Max. 22.8 3.2 120 Limits Vcc = 5 V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 12.5 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 5V, f(X IN) = 25 MHz (Square waveform), f(XCIN) : Stopped, in operating (Note 1) Vcc = 5V, f(X IN) = 25 MHz (Square waveform), f(XCIN) = 32.768 kHz, when the WIT instruction is executed (Note 2) Vcc = 5 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 5 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped Unit Measuring conditionsSymbol Parameter Icc Power source current Min. Typ. 11.4 1.6 mA mA µA µA µA µA µA External bus is operating, output pins are open, and the other pins are con- nected to Vss. Notes 1: This is applied when the main clock external input selection bit = “1,” the main clock division selection bit = “0,” and the signal output disable selection bit = “1.” 2: This is applied when the main clock external input selection bit = “1” and the system clock stop selection bit at wait state = “1.” 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the X COUT drivability selection bit = “0” and the system clock stop bit at wait state = “1.”

7735 Group User’s Manual20–16

Differences from the M37735S4BFP are mainly described below. The performance overview of the low voltage version differs from that of the M37735S4BFP in the following: memory size and current consumption. For the other items, refer to section “18.1 Performance overview.” Table 20.10.1 shows the M37735S4LHP’s performance overview. Items Memory size Current consumption Performance 2048 bytes 10.8 mW (When f(XIN) = 12-MHz square wave input, Vcc = 3 V, and the main clock is the system clock, Typ.) 120 µW (When f(XCIN) = 32 kHz, Vcc = 3 V, the sub clock is the system clock, and the main clock is stopped, Typ.) Table 20.10.1 M37735S4LHP’s performance overview RAM

7735 Group User’s Manual 20–17

Figure 20.10.1 shows the M37735S4LHP pin configuration. Fig. 20.10.1 M37735S4LHP pin configuration (Top view) (P32)ALE (P31)WEH (P33)HLDA XOUT RDE CNV SS RESET HOLD P86/RxD1 P87/TxD 1 CS 0(P00) CS 1(P01) CS 2(P02) CS 3(P03) CS 4(P04) RSMP(P0 5) A16(P06) A17(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A0/D0(P20) A1/D1(P21) 75 74 73 72 71 69 68 67 66 657080 79 78 77 76 64 63 62 61 3026 27 28 29 31 32 33 34 35 3621 2322 24 25 37 38 39 40 RDY (P42)/ 1 BYTE XIN VSS (P30)WEL (P27)A7/D7 (P26)A6/D6 (P25)A5/D5 (P24)A4/D4 (P23)A3/D3 (P22)A2/D2 P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3/RTP13 P56/TA3OUT /KI2/RTP12 P55/TA2IN/KI1/RTP11 P54/TA2OUT /KI0/RTP10 P53/TA1IN/RTP03 P52/TA1OUT /RTP02 P51/TA0IN/RTP01 P50/TA0OUT /RTP00 P47 P85/CLK1 P84/CTS1/RTS1 P83/TXD 0 P82/RXD 0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AV CC VREF AV SS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 P70/AN0 P67/TB2IN/ SUB M37735S4LHP P43 P44 P45 P46 Outline 80P6D-A By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin’s level can be fixed in the stop or wait mode.

7735 Group User’s Manual20–18

Except for the power-on reset conditions, the M37735S4LHP has the same functions as the M37735S4BFP For the other functions, refer to the following: “4. INTERRUPTS” to “9. A-D CONVERTER” in part 1, “2. CENTRAL PROCESSING UNIT (CPU)” in part 2, “3. PROGRAMMABLE I/O PORTS” in part 2, and “10. WATCHDOG TIMER” to “17. APPLICATIONS” in part 2. The power-on reset condition of the M37735S4LHP is the same as that of the M37735MHLXXXHP. For the power-on reset condition, refer to section “18.3 Functional description” in part 1. Except for “Icc,” the electrical characteristics of the M37735S4LHP are the same as those of the M37735MHLXXXHP in the microprocessor mode. For the others, refer to section “18.4 Electrical characteristics” in part 2. Limits Vcc = 5 V, f(X IN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(X IN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(X IN) = 12 MHz (Square waveform), (f(f2) = 0.75 MHz), f(XCIN) : Stopped, in operating (Note 1) Vcc = 3V, f(X IN) = 12 MHz (Square waveform), f(XCIN) = 32.768 kHz, when the WIT instruction is executed (Note 2) Vcc = 3 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 3 V, f(X IN) : Stopped, f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Unit Measuring conditionsSymbol Parameter ICC Power source current Min. Typ. 5.4 3.6 0.5 mA mA mA µA µA µA µA µA Max. 10.8 7.2 1.0 Notes 1: This is applied when the main clock external input selection bit = “1,” the main clock division selection bit = “0,” and the signal output disable selection bit = “1.” 2: This is applied when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1.” 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1.” External bus is operating, output pins are open, and the other pins are connected to Vss.

Appendix 1.Memory allocation of 7735 Group Appendix 2.Memory allocation in SFR area Appendix 3. Control registers Appendix 4. Package outlines Appendix 5.Hexadecimal instruction code table Appendix 6. Machine instructions Appendix 7. Examples of handling unused pins Appendix 8.Countermeasure examples against noise Appendix 9. Q & A

7735 Group User’s Manual21-2

Concerning chapter “APPENDIX,” the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter:

• “Appendix 1. Memory allocation of 7735 Group”
• “Appendix 2. Memory allocation in SFR area”
• “Appendix 3. Control registers”
• “Appendix 7. Examples of handling unused pins” Note: The following sections of the 7735 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1:
• “Appendix 4. Package outlines” (page 21-38 in part 1)
• “Appendix 5. Hexadecimal instruction code table” (page 21-41 in part 1)
• “Appendix 6. Machine instructions” (page 21-44 in part 1)
• “Appendix 8. Countermeasure examples against noise” (page 21-61 in part 1)
• “Appendix 9. Q & A” (page 21-71 in part 1)

7735 Group User’s Manual 21-3

Appendix 1. Memory allocation of 7735 Group 1. M37735MHBXXXFP, M37735EHBXXXFP, M37735EHBFS, M37735MHLXXX HP, M37735EHLXXXHP Fig. 1 Memory allocation of M37735MHBXXXFP, M37735EHBXXXFP, M37735EHBFS, M37735MHLXXXHP, M37735EHLXXXHP (1) Appendix 1. Memory allocation of 7735 Group 01FFFF 16 10000016 00000016 00007F16 00008016 000FFF 16 FFFFFF 16 00100016 00FFFF 16 01000016 00200016 00000016 00007F16 00008016 000FFF 16 00FFFF 16 01000016 01FFFF 16 FFFFFF 16 00000016 00007F16 INT 1 INT 0 DB C R ESET 00FFD 616 00FFFE 16 0FFFFF 16 SFR area Internal RAM area 3968 bytes Bank 016 Bank 116 Bank FF16 Internal ROM area (4 Kbytes) A-D/UART2 trans./rece. UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input Watchdog timer BRK instruction Zero divide Interrupt vector table SFR area Internal RAM area 3968 bytes Internal ROM area (SFR)

• Memory allocation selection bits (b2, b1, b0)=(0, 0, 0)
• ROM size: 124 Kbytes
• RAM size: 3.9 Kbytes
• Memory allocation selection bits (b2, b1, b0)=(0, 0, 1)
• ROM size: 120 Kbytes
• RAM size: 3.9 Kbytes UART1 transmission UART0 transmission : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Notes 1: Access to internal ROM area is disabled in the microprocessor mode. “2.5 Processor modes” in part 1.) 2: In the 7735 Group, banks 1016 to FF16 cannot be accessed. Refer to Appendix 2. Bank 1016 (Refer to section

7735 Group User’s Manual21-4

Fig. 2 Memory allocation of M37735MHBXXXFP, M37735EHBXXXFP, M37735EHBFS, M37735MHLXXXHP, M37735EHLXXXHP (2) Appendix 1. Memory allocation of 7735 Group 00FFFF 16 01000016 UART1 transmission 01FFFF 16 FF000016 00000016 00007F16 00008016 00087F16 FFFFFF 16 00100016 00000016 00007F16 00008016 00087F16 00FFFF 16 01000016 FFFFFF 16 00000016 RESET 00007F16 00FFD6 16 00FFFE 16 A-D/UART2 trans./rece. 02000016 00800016 SFR area Internal RAM area 2048 bytes Bank 016 Bank 116 Bank FF16 Internal ROM area (29.9 Kbytes) UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT 2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide Interrupt vector table SFR area Internal RAM area 2048 bytes Peripheral device control registers (SFR) : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode

• Memory allocation selection bits (b2, b1, b0)=(0, 1, 0)
• ROM size: 60 Kbytes
• RAM size: 2048 bytes
• Memory allocation selection bits (b2, b1, b0)=(1, 0, 0)
• ROM size: 32 Kbytes
• RAM size: 2048 bytes (1.9 Kbytes) UART0 transmission Refer to Appendix 2. 02FFFF 16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section “2.5 Processor modes.”) 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Internal ROM area

7735 Group User’s Manual 21-5

Appendix 1. Memory allocation of 7735 Group Fig. 3 Memory allocation of M37735MHBXXXFP, M37735EHBXXXFP, M37735EHBFS, M37735MHLXXXHP, M37735EHLXXXHP (3) 00FFFF 16 01000016 02000016 UART1 transmission 01FFFF 16 FF000016 00000016 00007F16 00008016 00087F16 FFFFFF 16 00C000 16 00000016 00007F16 00008016 000FFF 16 00FFFF 16 01000016 FFFFFF 16 00000016 RESET 00007F16 00FFD6 16 00FFFE 16 A-D/UART2 trans./rece. 00800016 SFR area Internal RAM area 2048 bytes Bank 016 Bank 116 Bank FF16 Internal ROM area (28 Kbytes) UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT 2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide Interrupt vector table SFR area Internal RAM area 3968 bytes Peripheral device control registers (SFR) : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode

• Memory allocation selection bits (b2, b1, b0)=(1, 0, 1)
• ROM size: 16 Kbytes
• RAM size: 2048 bytes
• Memory allocation selection bits (b2, b1, b0)=(1, 1, 0)
• ROM size: 96 Kbytes
• RAM size: 3968 bytes (45.9 Kbytes) UART0 transmission Refer to Appendix 2. 02FFFF 16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section “2.5 Processor modes.”) 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Internal ROM area

7735 Group User’s Manual21-6

1. M37735S4BFP, M37735S4LHP Appendix 1. Memory allocation of 7735 Group Fig. 4 Memory allocation of M37735S4BFP, M37735S4LHP R ESET DB C INT 0 INT 1 FFFFFF 16 00000016 00007F16 00008016 00FFFF 16 01000016 01FFFF 16 00000016 00007F16 00FFD 616 00FFFE 16 10000016 0FFFFF 16 Timer A4 SFR area Internal RAM area 2048 bytesBank 016 Bank 116 Bank 1016 A-D/UART2 trans./rece. UART1 reception UART0 reception Timer B2 Timer B1 Timer B0 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input Watchdog timer BRK instruction Zero divide Interrupt vector table Peripheral device control registers (SFR) UART1 transmission UART0 transmission Refer to Appendix. 2 : External memory area Bank FF16 Notes 1: Addresses 00FFD616 to 00FFFF16 are the interrupt vector table. Be sure to set ROM to this area. 2 : In the 7735 Group, banks 1016 to FF16 cannot be accessed. 00087F16

7735 Group User’s Manual 21-7

Appendix 2. Memory allocation in SFR area Concerning section “Appendix 2. Memory allocation in SFR area,” the 7735 Group differs from the 7733 Group in the following:

• Address 6F 16 (Refer to Figure 8.) The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “Appendix 2. Memory allocation in SFR area” (page 21-6 in part 1) Appendix 2. Memory allocation in SFR area

7735 Group User’s Manual21-8

Fig. 8 Memory allocation in SFR area (4) Figure 8 differs from that of the 7733 Group only in h 3. RO UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address Oscillation circuit control register 0 Serial transmit control register A-D / UART 2 trans./rece. interrupt control register UART0 transmission interrupt control register UART1 transmission interrupt control register INT2/Key input interrupt control register Watchdog timer frequency selection flag Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW( h 2) RW RW RW RW b7 b0 WO RW RW RW RW RW RW RW RW RW RW State immediately after reset 0 00 0 ? 0 ? (h1) b7 b0 0 0 0 0 0 0 0 0 0 00 0 00 0 0 0 0 Port function control register UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register RW RW WO RW RW RW 00 0 0 0 1 00 00 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 00 0 0 0 0 00 0 0 0 0 A value of “FFF 16” is set to the watchdog timer. (Refer to chapter “10. WATCHDOG TIMER. ”) For access characteristics at address 6C16, also refer to Figure 14.3.2 in part 1. The state of bit 3 at address 6F16 immediately after reset depends on the product. (Refer to Figure 14.3.3 in part 2 : refer to this part because bit 3 at address 6F16 of the 7735 Group differs from that of the 7733 Group. Fix this bit to “0” in the 7735 Group. Do not wirte to the reserved area. (Refer to Figure 20.8.1 for the M37733S4BFP, M37733S4LHP, M37735S4BFP, 37735S4LHP.) n Internal RAM area (M37735MHBXXXFP: addresses 8016 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset. When the stop or wait mode is terminated (when the hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. RW h 3 00 0 h 1 h 2 h 3 h 4 (Reserved area) h 4 Memory allocation control register UART 2 transmit/receive mode register UART 2 baud rate register (BRG2) UART 2 transmission buffer register UART 2 transmit/receive control register 0 UART 2 transmit/receive control register 1 UART 2 receive buffer register Oscillation circuit control register 1 RW 0? 0 00 0 RW ? 00 0 0 0 00 WO WO WO RWRO 1 00 0 RW RORO 00 0 0 00 10 RO 00 0 000 ? RW ?? 0 00 0 0 00 0 Appendix 2. Memory allocation in SFR area RW

7735 Group User’s Manual 21-9

Appendix 3. Control registers Concerning section “Appendix 3. Control registers,” the 7735 Group differs from the 7733 Group in the following:

• Oscillation circuit control register 1 The other control registers are the same as those of the 7733 Group. Therefore, for the other control registers, refer to part 1:
• “Appendix 3. Control registers” (page 21-10 in part 1) Appendix 3. Control registers

7735 Group User’s Manual21-10

Oscillation circuit control register 1 2: Because this bit is “1” at reset, clear this bit to “0” with the initial setting program after reset. 3: The case where data “010101012” is written with the procedure shown below is not included. 4: For the 7733 Group, refer to Figure 14.3.3 in part 1. Bit Bit name Functions At reset RW Main clock division selection bit Sub clock external input selection bit Must be fixed to “0” in the one time PROM and EPROM versions (Notes 1 and 2). Must be fixed to “0” (Note 3). Clock prescaler reset bit Undefined Oscillation circuit control register 1 (address 6F16) 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT . Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. RW RW RW RW WO —Not implemented. Not implemented. b1 b0b2b3b4b5b6b7 Notes 1: When writing to this register, follow the procedure shown below. By writing “1” to this bit, clock prescaler is initialized. RW (Note 4) Undefined Main clock external input selection bit 0: Main clock is divided by 2. 1: Main clock is not divided by 2. 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. Must be fixed to “0” in the mask ROM and external ROM versions (Note 1). (Note 1) (Note 1) (Note 1) Write data “010101012.”(LDM instruction)

• When writing to bits 0 to 3 Write data “00000XXX 2.” (LDM instruction) Next instruction (b2 to b0 in the above Figure) Write data “8016.” (LDM instruction)
• When performing clock prescaler reset Appendix 3. Control registers

7735 Group User’s Manual 21-11

Appendix 7. Examples of handling unused pins The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user’s application. 1. In single-chip mode Table 1 Examples of handling unused pins in single-chip mode Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these ports function as input ports. Software reliability can be enhanced when the contents of the above ports ’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 2: This is applied when an external clock is input to pin XIN. Pins P0 –P8 E X OUT (Note 2) AVcc AVss, VREF , BYTE Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). Leave this pin open. Connect this pin to pin Vcc. Connect these pins to pin Vss. Fig. 9 Examples of handling unused pins in single-chip mode P0–P8 AVss VREF BYTE M37735MHBXXXFP Vss AVcc E XOUT Left open When setting ports to input mode Vcc P0–P8 AVss VREF BYTE M37735MHBXXXFP Vss AVcc E XOUT Left open When setting ports to output mode Left open Vcc Appendix 7. Examples of handling unused pins

7735 Group User’s Manual21-12

1. In memory expansion mode Table 2 Examples of handling unused pins in memory expansion mode Pins P4 2–P4 7, P5–P8 (Note 5) WEH , WEL , RDE , HLDA, CS 0–CS 4, RSMP X OUT (Note 4) HOLD , RDY AVcc AVss, VREF Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open. (Note 3) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 4: This is applied when an external clock is input to pin XIN. 5: Set pin P42/φ1 as pin P42. (Clock φ1 output is disabled.) And then, for this pin, do the same handling as that for pins P43 to P47 and P5 to P8. Fig. 10 Examples of handling unused pins in memory expansion mode P42–P47, P5–P8 HOLD RDY M37735MHBXXXFP Vcc Vss AVcc XOUT CS 0–CS 4 P42–P47, P5–P8 HOLD RDY Vss AVcc XOUT CS 0–CS 4 Vcc M37735MHBXXXFP When setting ports to input mode When setting ports to output mode Left open Left open Left open Left open Left open AVss VREF AVss VREF WEH WEL RDE HLDA RSMP WEH WEL RDE HLDA RSMP Appendix 7. Examples of handling unused pins

7735 Group User’s Manual 21-13

1. In microprocessor mode Table 3 Examples of handling unused pins in microprocessor mode Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open. (Note 3) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Pins P4 3–P4 7, P5–P8 WEH , WEL , RDE HLDA , φ1, CS 0–CS 4, RSMP X OUT (Note 4) HOLD , RDY AV CC AV SS , VREF Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the microprocessor mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. 4: This is applied when an external clock is input to pin XIN. Fig. 11 Examples of handling unused pins in microprocessor mode P43–P47, P5–P8 RSMP HOLD RDY M37735MHBXXXFP WEH WEL RDE HLDA Vcc Vss AVcc XOUT CS 0–CS 4 P43–P47, P5–P8 RSMP HOLD RDY Vss AVcc XOUT CS 0–CS 4 Vcc M37735MHBXXXFP When setting ports to input mode When setting ports to output mode Left open Left open Left open Left open Left open AVss VREF AVss VREF WEH WEL RDE HLDA Appendix 7. Examples of handling unused pins

Appendix 7. Examples of handling unused pins

7735 Group User’s Manual21–14

CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) CHAPTER 3 PROGRAMMABLE I/O PORTS CHAPTER 4 INTERRUPTS CHAPTER 5 KEY INPUT INTERRUPT FUNCTION CHAPTER 6 TIMER A CHAPTER 7 TIMER B CHAPTER 8 SERIAL I/O CHAPTER 9 A-D CONVERTER CHAPTER 10 WATCHDOG TIMER CHAPTER 11 STOP AND WAIT MODES CHAPTER 12 CONNECTING EXTERNAL DEVICES CHAPTER 13 RESET CHAPTER 14 CLOCK GENERATING CIRCUIT CHAPTER 15 ELECTRICAL CHARACTERISTICS CHAPTER 16 STANDARD CHARACTERISTICS CHAPTER 17 APPLICATIONS CHAPTER 18 LOW VOLTAGE VERSION CHAPTER 19 BUILT-IN PROM VERSION APPENDIX

7736 Group User’s Manual2

The differences between the 7736 Group and the 7733 Group are mainly described below. For the 7733 Group, refer to part “1. 7733 Group.” For the 7735 Group, refer to part “2. 7735 Group.” The 7736 Group differs from the 7733/7735 Group in the following:

• External bus mode in the memory expansion mode and the microprocessor mode (In the 7736 Group, pin BSEL’s level determines the external bus mode, which is A or B.)
• Output port P9 and I/O port P10 (Ports P9 and P10 are assigned only for the 7736 Group.)
• Pin assignment for the key input interrupt (In the 7736 Group, the pins are assigned to pins P10 4 to P107.)
• Pin assignment for UART2 (In the 7736 Group, the pins are assigned to pins P9 0 to P93.)
• External ROM version (In the 7736 Group, there is no external ROM version.)
• Package (In the 7736 Group, the 100-pin QFP is used.)

7736 Group User’s Manual1–2

• External bus mode A: Maximum of 16 Mbytes
• External bus mode B: Maximum of 1 Mbytes 100-pin plastic molded QFP Ports P0–P2, P4–P8, P10 Port P3 Port P9 Concerning chapter “1. OVERVIEW,” the 7736 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter:
• “1.1 Performance overview”
• “1.2 Pin configuration”
• “1.3 Pin description”
• “1.4 Block diagram”

Concerning section “1.1 Performance overview,” the 7736 Group differs from the 7733 Group in the following:

• Description of the programmable I/O ports, memory expansion, and package in Table 1.1.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “1.1 Performance overview” (page 1-3 in part 1) Table 1.1.1 M37736MHBXXXGP’s performance overview

7736 Group User’s Manual 1–3

Fig. 1.2.1 M37736MHBXXXGP pin configuration (Top view) P46 P45 P44 P43 P42/ 1 P47 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 4/AN 5/AN 5/AD TRG 6/AN 6/X COUT 7/AN 7/X CIN V SS AV SS V REF AV CC V CC 0/CTS 0/RTS 0/CLKS 1/CLK 2/R XD 0/CLKS 3/T XD P00/A0/CS0 P01/A1/CS1 P02/A2/CS2 P03/A3/CS3 P04/A4/CS4 P05/A5/RSMP 100 99 98 97 96 95 94 93 92 91 89 88 87 86 8590 Outline 100P6S-A M37736MHBXXXGP P107/KI3 P106/KI2 P105/KI1 P104/KI0 P103 P102 P101 P100 0/AN 1/AN 2/AN 3/AN 1/RDY 0/HOLDBYTE P06/A6/A16 P07/A7/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 31 3332 34 4035 36 37 38 39 41 42 43 44 45 46 47 48 49 50 84 83 82 81 CNV SS BSELRESET X IN X OUT E/RDE V SS V CC EVL1EVL0 3/HLDA 2/ALE 1/BHE/WEH 0/R/W/WEL 7/A 7/D 6/A 6/D 5/A 5/D P17/A15/D15 P20/A16/A0/D0 P21/A17/A1/D1 P22/A18/A2/D2 P23/A19/A3/D3 P24/A20/A4/D4 P87/TXD 1 P90/CTS2 P91/CLK2 P92/RxD2 P93/TxD2 P94 P95 P96 P97 4/CTS 1/RTS 5/CLK 6/R XD Figure 1.2.1 shows the M37736MHBXXXGP pin configuration. Note: For the low voltage version, refer to chapter “18. LOW VOLTAGE VERSION.”

7736 Group User’s Manual1–4

E BSEL External bus modes A B A, B Processor modes Single-chip mode Memory expansion or Microprocessor mode Single-chip mode Memory expansion or Microprocessor mode I/O Output Output Output Input Input Functions Same as the 7733 Group. This pin outputs internal enable signal E. This pin outputs read enable signal RDE . RDE’s level is “L” in the data read period of the read cycle. The level of a signal which is input to this pin may be “H” or “L.” The signal which is input to this pin determines the external bus mode. When this signal’s level is “H,” external bus mode A is selected; when this signal’s level is “L,” external bus mode B is selected. Name Enable output Bus select input Concerning section “1.3 Pin description,” the 7736 Group differs from the 7733 Group in the following: ___

• “Description of pins E and BSEL in Table 1.3.1”
• “Description of pins P00–P0 7, P20–P2 7 and P30–P3 3 in Tables 1.3.2 and 1.3.3”
• “Description of pins P50–P5 7, P70–P7 7, P90–P9 7, P100–P10 7, EVL0 and EVL1 in Table 1.3.4”
• “1.3.1 Examples of handling unused pins” The other description is the same as that of the 7733 Group. Therefore, refer to part 1:
• “1.3 Pin description” (page 1-5 in part 1) Table 1.3.1 Pin description (1)

7736 Group User’s Manual 1–5

Table 1.3.2 Pin description (2) Pin FunctionsI/ONameProcessor mode A B A B I/O port P0 I/O port P2 Same as the 7733 Group. Address’s low-order 8 bits (A0–A 7) are output. ____ These pins respectively output signals CS 0–CS 4, RSMP , and address’s high-order 2 bits (A16 and A17). l Signals CS 0–CS 4 These signals are the chip select signals. When the microcomputer accesses a certain area, the corresponding pin outputs “L” level. (Refer to Table 2.5.4.) l Signal RSMP This signal is the ready sampling signal and is used to generate signal RDY for accessing external memory area. Same as the 7733 Group. Input/Output of data (D0–D 7) and output of address’s high-order 8 bits (A16–A 23) are performed with the time sharing method. Input/Output of data (D0–D 7) and output of address’s low-order 8 bits (A0–A7) are performed with the time sharing method. P0 0–P0 7 A 0–A 7 CS 0–CS 4, RSMP, A 16, A17 P2 0–P2 7 A 16/D0– A23/D7 A 0/D0– A7/D7 Single-chip mode Memory expansion or Microprocessor mode Single-chip mode Memory expansion or Microprocessor mode I/O Output Output I/O Output Output External bus mode

7736 Group User’s Manual1–6

A B I/O port P3 I/O Output Output Same as the 7733 Group. These pins respectively output signals R/W , BHE , ALE, and HLDA . l Signal R/W This signal indicates the data bus state. When this signal level is “H,” a data bus is in the read state. When this signal level is “L,” a data bus is in the write state. ____ l Signal BHE This signal’s level is “L” when the microcomputer accesses an odd address. l Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. l Signal HLDA This signal informs the external whether this microcomputer enters the Hold state or not. In Hold state, pin HLDA outputs “L” level. These pins respectively output signals WEL , WEH , ALE, and HLDA . l Signal WEL , WEH ____ Signal WEL is the write enable low signal. ____ Signal WEH is the write enable high signal. These signals’ levels are “L” in the data write period of the write cycle. The operations of these signals depend on the level of pin BYTE. (Refer to Table 12.1.1 in part 2.) l Signal ALE This signal is the same as that in external bus mode A. l Signal HLDA This signal is the same as that in external bus mode A. Table 1.3.3 Pin description (3) Pin FunctionsI/ONameProcessor mode Single-chip mode Memory expansion or Microprocessor mode External bus mode P3 0–P3 3 R/W, ____ BHE, ALE, HLDA ____ WEL, ____ WEH, ALE, HLDA

7736 Group User’s Manual 1–7

Table 1.3.4 Pin description (4) Pin FunctionsI/ONameProcessor mode External bus mode P5 0–P5 7 P7 0–P7 7 P9 0–P9 7 I/O I/O Output A, B A, B A, B I/O port P5 I/O port P7 Output port P9 P5 is an 8-bit I/O port with the same function as port P0 and can be programmed as I/O pins for timers A0–A3. P7 is an 8-bit I/O port with the same function as port P0 and can be programmed as analog input pins for the A-D converter. P76 and P77 can be programmed as I/O pins (XCOUT , XCIN) for the sub-clock (32 kHz) oscillation circuit. When using P7 6 and P77 as pins XCOUT and XCIN, connect a quartz-crystal oscillator between them. When inputting an external clock, input the clock from pin XCIN . P9 is an 8-bit output-only port. After reset, P9 enters a floating state. When data is written to the port P9 register, P9 starts outputting (Note). P9 0–P9 3 also function as UART2’s I/O pins. P10 is an 8-bit I/O port with the same function as port P0. Pins 104–107 can be programmed as input pins (KI0–KI3) for the key input interrupt. Leave these pins open. Single-chip mode Memory expansion or Microprocessor mode Single-chip mode Memory expansion or Microprocessor mode Single-chip mode Memory expansion or Microprocessor mode Single-chip mode Memory expansion or Microprocessor mode Single-chip mode Memory expansion or Microprocessor mode P10 0–P10 7 EVL0, EVL1 I/O port P10 I/O Output–– A, B A, B Note: After reset, be sure to write data to the port P9 latch.

7736 Group User’s Manual1–8

The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user’s application. (1) In single-chip mode Table 1.3.5 Examples of handling unused pins in single-chip mode Fig. 1.3.1 Examples of handling unused pins in single-chip mode Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). Leave these pins open after writing data to the port P9 register (Note 3). Leave this pin open. Connect this pin to pin Vcc. Connect these pins to pin Vss. Connect this pin to pin Vcc or Vss. Pins P0–P8, P10 E , RDE EVL0, EVL1 X OUT (Note 2) AVcc AVss, VREF , BYTE BSEL P0–P8 , P10 AV SS VREF BYTE BSEL M37736MHBXXXGP VSS AV CC E/RDE XOUT EVL0 EVL1 Left open n When setting ports to input mode VCC P0–P10 AV SS VREF BYTE BSEL M37736MHBXXXGP VSS AV CC E/RDE XOUT EVL0 EVL1 Left open n When setting ports to output mode Left open VCC Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until the they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these ports function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 2: This is applied when an external clock is input to pin XIN. 3: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state.

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(2) In memory expansion mode (External bus mode A) Table 1.3.6 Examples of handling unused pins in memory expansion mode (External bus mode A) Pins P4 2–P4 7, P5–P8, P10 (Note 7) BHE ( Note 3), ALE (Note 4), HLDA X OUT (Note 6) HOLD , RDY AVcc AVss, VREF EVL0, EVL1 Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open after writing data to the port P9 register (Note 8). Leave these pins open. (Note 5) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Leave these pins open. Fig. 1.3.2 Examples of handling unused pins in memory expansion mode (External bus mode A) Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: This is applied when “H” level is input to pin BYTE. 4: This is applied when “H” level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. 7: Set pin P42/φ1 as pin P42. (Clock φ1 output is disabled.) And then, for this pin, do the same handling as that for pins P43 to P47, P5 to P8 and P10. 8: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. P42–P47, P5–P8, P10 AV SS VREF HOLD RDY Left open M37736MHBXXXGP VCC VSS AV CC XOUT EVL0 EVL1 n When setting ports to input mode BHE ALE HLDA Left open P42–P47, P5–P10 AV SS VREF HOLD RDY Left open VSS AV CC XOUT EVL0 EVL1 n When setting ports to output mode BHE ALE HLDA Left open Left open VCC M37736MHBXXXGPP9

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