7721

Renesas Technology Corp

16-BIT SINGLE-CHIP MICROCOMPUTER

Manufacturer: Renesas Technology Corp

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Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER

7700 FAMIL Y / 7700 SERIES

User’s Manual

keep safety first in your circuit designs ! l Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials l These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. l Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. l Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. l If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. l Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

Rev. Rev. No. date

1.0 First Edition 970926

REVISION DESCRIPTION LIST 7721 Group User’s Manual (1/1) Revision Description

This manual describes the hardware of the Mitsubishi CMOS 16-bit microcomputers 7721 Group. After reading this manual, the user will be able to understand the functions, so that their capabilities can fully be utilized. Preface

Constitution This user’s manual consists of the following chapters. Refer to the chapters relevant to the products. l Chapter 1. DESCRIPTION through Chapter 16. APPLICATION Functions which are common to the M37721S1BFP and the M37721S2BFP are explained, using the M37721S2BFP as an example. Differences between the M37721S1BFP and the M37721S2BFP are described as notes. l Appendix Practical information for using the 7721 Group is described. 2. Remark l Product expansion Refer to the latest catalog and data book, or contact the appropriate office, as listed in “CONTACT ADDRESSES FOR FURTHER INFORMATION” on the last page. l Electrical characteristics Refer to the latest data book. l Software Refer to “7700 Family Software Manual.” l Development support tools Refer to the latest data book of the development support tools. 3. Signal levels in Figure As a rule, signal levels in each operation example and timing diagram are as follows.

Signal levels The upper line indicates “1,” and the lower line indicates “0.”
Input/output levels of pin The upper line indicates “H,” and the lower line indicates “L.” For the exception, the level is shown on the left side of a signal.

Register structure Below is the structure diagram for all registers: XXX register (Address XX16) b1 b0b2b3b4b5b6b7 ] 1 ]2 ]3 1 : ... 1 : ... The value is “0” at reading. 0 : ... 1 : ... Fix this bit to “0.” 7 to 5 Nothing is assigned. RW WO RO RW RW Bit Bit name This bit is invalid in ... mode. Functions At reset RW ... flag Undefined Undefined Blank : Set to “0” or “1” according to the usage. 0 : Set to “0” at writing. 1 : Set to “1” at writing. 5 : Invalid depending on the mode or state. It may be “0” or “1.” : Nothing is assigned. 0 : “0” immediately after reset. 1 : “1” immediately after reset. Undefined : Undefined immediately after reset. RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be “0” or “1.” WO : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at reading. (See ]4 above.) — : It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at reading. (See ]4 above.) The written value becomes invalid. Accordingly, the written value may be “0” or “1.” ] 4

7721 Group User’s Manual i

CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES

7721 Group User’s Manualii

CHAPTER 5 CLOCK GENERATING CIRCUIT CHAPTER 6 INPUT/OUTPUT PINS CHAPTER 7 INTERRUPTS

7.7 Sequence from acceptance of interrupt request until execution of interrupt

7721 Group User’s Manual iii

7721 Group User’s Manualiv

CHAPTER 10 REAL-TIME OUTPUT CHAPTER 11 SERIAL I/O

7721 Group User’s Manual v

7721 Group User’s Manualvi

CHAPTER 14 DRAM CONTROLLER

7721 Group User’s Manual vii

7721 Group User’s Manualviii

DESCRIPTION

1.1 Performance overview

1.2 Pin configuration

1.3 Pin description

1.4 Block diagram

7721 Group User’s Manual1–2

Table 1.1.1 lists the performance overview of the M37721. Table 1.1.1 M37721 performance overview ROM RAM P5–P10 TA0–TA4 TB0–TB2 UART0, UART1 M37721S2BFP M37721S1BFP Parameters Number of basic instructions Instruction execution time External clock input frequency f(X IN) Memory sizes Programmable Input/Output ports Multifunctional timers Serial I/O A-D converter Watchdog timer DMA controller DRAM controller Real-time output Interrupts Clock generating circuit Supply voltage Power dissipation Port Input/Output characteristics Memory expansion Operating temperature range Device structure Package Input/Output withstand voltage Output current Functions 103 160 ns (the minimum instruction at f(XIN) = 25 MHz)

25 MHz (maximum)

(UART or clock synchronous serial I/O) 5 2 8-bit successive approximation method 5 1 (8 channels) 12 bits 5 1 4 channels Maximum transfer rate : 12.5 Mbytes/sec. (at f(X IN) = 25 MHz, 1-bus cycle transfer) Maximum transfer rate : 6.25 Mbytes/sec. (at f(XIN) = 25 MHz, 2-bus cycle transfer) CAS before RAS refreshing method 4 bits 5 2 channels or 6 bits 5 1 channel + 2 bits 5 1 channel 3 external, 20 internal (priority levels 0 to 7 can be set for each interrupt with software) Built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator)

5 V ±10 %

135 mW (at f(X IN) = 25 MHz, typ.) 5 V 5 mA Maximum 16 Mbytes –20°C to 85°C CMOS high-performance silicon gate process 100-pin plastic molded QFP

7721 Group User’s Manual 1–3

Figure 1.2.1 shows the M37721S2BFP pin configuration. Fig. 1.2.1 M37721S2BFP pin configuration (top view) 3431 32 33 35 36 37 38 39 40 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 P57/TB1IN P56/TB0IN P55/TA4IN P54/TA4OUT P53/TA3IN P52/TA3OUT P51/TA2IN P50/TA2OUT P107/MA9 P106/MA8 P105/RAS P104/CAS P103/TC P102/INT2 P101/INT1 P100/INT0 P47 P46 P45 P44 P43 P87/TXD 1 P90/DMAACK0 P91/DMAREQ0 P92/DMAACK1 P93/DMAREQ1 P94/DMAACK2 P95/DMAREQ2 P96/DMAACK3 P97/DMAREQ3 A0/MA0 A1/MA1 A2/MA2 A3/MA3 A4/MA4 A5/MA5 A6/MA6 A7/MA7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A A A R/WBHEBLEALEST0ST1V CC V SS EX OUT X IN RESETRESET OUT CNV SS BYTEHOLDRDY 50494847464544434241 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 6/R XD 5/CLK 4/CTS 1/RTS 3/T XD 2/R XD 1/CLK 0/CTS 0/RTS V CC AV CC V REF AV SS V SS 7/AN 7/AD TRG 6/AN 5/AN 4/AN 3/AN 2/AN 1/AN 0/AN Outline 100P6S-A M37721S2BFP

7721 Group User’s Manual1–4

Table 1.3.1 Pin description (1) Vcc, Vss CNVss RESET RESET OUT X IN X OUT E BYTE ST0 ST1 AVcc AVss V REF Input/Output Input Input Output Input Output Output Input Output Input ST1 ST0 Bus use state DRAM refresh Hold DMA CPU Functions Supply 5 V ±10 % to Vcc pin and 0 V to Vss pin. Connect to Vss or Vcc pin. The microcomputer is reset when supplying “L” level to this pin. When input to RESET pin is “L,” this pin outputs “L.” Output from this pin returns “H” after the release of reset. When writing “1” to the software reset bit, this pin outputs “L.” These are I/O pins of the internal clock generating circuit. Connect a ceramic resonator or quartz-crystal oscillator between pins XIN and XOUT . When using an external clock, the clock source should be input to XIN pin and XOUT pin should be left open. Data/instruction code read or data write is performed when output from this pin is “L” level. Input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. The width is 16 bits when the level is “L”, and 8 bits when the level is “H”. The bus use state is output in 2-bit code. The power supply pin for the A-D converter. Connect AVcc to Vcc pin. Connect AVss to Vss pin. This is a reference voltage input pin for the A-D converter. Name Power supply CNVss Reset input Reset output Clock input Clock output Enable output Exernal data bus width selection input Status signal output Analog supply input Reference voltage input

7721 Group User’s Manual 1–5

Table 1.3.2 Pin description (2) Low-order 8 bits (A0–A 7) of the address are output. When the DRAM is accessed, the row and column addresses are output with the time-sharing. l External data bus width = 8 bits (When the BYTE pin is “H” level) Middle-order 8 bits (A 8–A15) of the address are output. l External data bus width = 16 bits (When the BYTE pin is “L” level) Data (D 8–D 15) input/output and output of the middle- order 8 bits (A8–A 15) of the address are performed with the time-sharing. Data (D0–D 7) input/output and output of the high-order 8 bits (A16–A 23) of the address are performed with the time-sharing. l R/W The Read/Write signal indicates the data bus state. The state is read while this signal is “H” level, and write while this signal is “L” level. ____ l BHE “L” level is output when an odd-numbered address is accessed. ____ l BLE “L” level is output when an even-numbered address is accessed. l ALE This is used to obtain only the address from address and data multiplex signals. The microcomputer is in Hold state while “L” level is input to the HOLD pin. The microcomputer is in Ready state while “L” level is ____ input to the RDY pin. This is the φ1 output pin. Input/Output Output I/O I/O Output Input Input Output Name Address low-order/ DRAM address Address middle-order/ data high-order Address high-order/ data low-order Memory control signal output Hold input Ready input Clock φ1 output Pin A 0/MA 0– A 7/MA 7 A 8/D8– A 15/D15 A 16/D0– A 23/D7 R/W, ____ BHE, ____ BLE, ALE HOLD ____ RDY

7721 Group User’s Manual1–6

Table 1.3.3 Pin description (3) Pin P4 3–P4 7 P5 0–P5 7 P6 0–P6 7 P7 0–P7 7 P8 0–P8 7 P9 0–P9 7 P10 0– P10 7 Functions Port P4 is a 5-bit CMOS I/O port. This port has an I/O direction register and each pin can be programmed for input or output. Port P5 is an 8-bit I/O port with the same function as P4. These pins can be programmed as I/O pins for Timers A2–A4 and I/O pins for Timers B0, B1. Port P6 is an 8-bit I/O port with the same function as P4. These pins can be programmed as output pins for the real-time output. Port P7 is an 8-bit I/O port with the same function as P4. These pins can be programmed as input pins for A-D converter. Port P8 is an 8-bit I/O port with the same function as P4. These pins can be programmed as I/O pins for Serial I/O. Port P9 is an 8-bit I/O port with the same function as P4. These pins can be programmed as I/O pins for DMA controller. Port P10 is an 8-bit I/O port with the same function as P4. These pins can be programmed as I/O pin for TC and output pins for DRAM controller. P10 0–P10 2 also function as input pins for INT0–INT2. Name I/O port P4 I/O port P5 I/O port P6 I/O port P7 I/O port P8 I/O port P9 I/O port P10 Input/Output I/O I/O I/O I/O I/O I/O I/O

7721 Group User’s Manual

1–7 Figure 1.4.1 shows the M37721 block diagram. L (8) Instruction Queue Buffer Q (8) Data Bank Register DT (8) Program Counter PC (16) Incrementer/Decrementer (24) Program Bank Register PG (8) Input Buffer Register IB (16) Direct Page Register DPR (16) Stack Pointer S (16) Index Register Y (16) Index Register X (16) Arithmetic Logic Unit (16) Accumulator A (16) Instruction Register (8) Data Bus (Odd) Central Processing Unit (CPU) Incrementer (24) Program Address Register PA (24) Data Address Register DA (24) Address Bus Bus Interface Unit (BIU) Processor Status Register PS (11) A-D Converter (8) UART1 (9) UART0 (9) Watchdog Timer Timer TA4 (16) ROM

1024 Bytes

Address/Data (16) Address/Data Address (8) P5 (8) P6 (8) P7 (8) Input/Output port P4 P4 (5) Reset input RESET (0V) V SS CNVss Reference voltage input V REF (0V) AV SS AV CC V CC External data bus width selection input BYT E Clock Generating Circuit Clock input X IN Enable output E DMA0 (16) DMA1 (16) DMA2 (16) DMA3 (16) DRAM Controller RDY HOLD R/W BHE Clock output BLE ALE ST0 Status signal output Memory control signal output ST1 Note: For the M37721S1BFP, the RAM size is 512 bytes. Clock output X OUT Accumulator B (16) Instruction Queue Buffer Q (8) Instruction Queue Buffer Q (8) Data Buffer DB H (8) Timer TA3 (16) Timer TA2 (16) Timer TA1 (16) Timer TA0 (16) Timer TB2 (16) Timer TB1 (16) Timer TB0 (16) Data Bus (Even) Input/Output port P5 Input/Output port P6 Input/Output port P7 P8 (8) Input/Output port P8 Input/Output port P9 P9 (8) P10 (8) Input/Output port P10 Fig. 1.4.1 M37721 block diagram

7721 Group User’s Manual1–8

(CPU)

2.1 Central processing unit

2.2 Bus interface unit

2.3 Access space

2.4 Memory assignment

2.5 Bus access right

CENTRAL PROCESSING UNIT (CPU) 2–2 7721 Group User’s Manual The CPU (Central Processing Unit) has the ten registers as shown in Figure 2.1.1. Fig. 2.1.1 CPU registers structure b0b7b8b15 AH AL b0b7b8b15 BH BL b0b7b8b15 XH XL b0b7b8b15 YH YL b0b7b8b15 SH SL b0b7b8b15 b7 b0 b8b23 b16 b15 b7 b0 PC H PC LPG b0b7 DT b0b7b8b15 b0b1b2b3b4b5b6b7b8b10

00000 C ZIDxmVNIPL

Accumulator A (A) Accumulator B (B) Index register X (X) Index register Y (Y) Stack pointer (S) Data bank register (DT) Program counter (PC) Program bank register (PG) Direct page register (DPR) Processor status register (PS) Processor interrupt priority level Carry flag Zero flag Interrupt disable flag Index register length flag Decimal mode flag Data length flag Overflow flag Negative flag DPR LDPR H PS LPS H b15

CENTRAL PROCESSING UNIT (CPU) 2–3

2.1.1 Accumulator (Acc)

Accumulators A and B are available. (1) Accumulator A (A) Accumulator A is the main register of the microcomputer. The transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits, and the low-order 8 bits can also be used separately. The data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. When an 8-bit register is selected, only the low-order 8 bits of accumulator A are used and the contents of the high-order 8 bits is unchanged. (2) Accumulator B (B) Accumulator B is a 16-bit register with the same function as accumulator A. Accumulator B can be used instead of accumulator A. The use of accumulator B, however except for some instructions, requires more instruction bytes and execution cycles than that of accumulator A. Accumulator B is also controlled by the data length flag (m) just as in accumulator A.

2.1.2 Index register X (X)

Index register X consists of 16 bits and the low-order 8 bits can also be used separately. The index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. When an 8-bit register is selected, only the low-order 8 bits of index register X are used and the contents of the high-order 8 bits is unchanged. In an addressing mode in which index register X is used as an index register, the address obtained by adding the contents of this register to the operand’s contents is accessed. In the MVP or MVN instruction, a block transfer instruction, the contents of index register X indicate the low-order 16 bits of the source address. The third byte of the instruction is the high-order 8 bits of the source address. Note: Refer to “7700 Family Software Manual” for addressing modes.

2.1.3 Index register Y (Y)

Index register Y is a 16-bit register with the same function as index register X. Just as in index register X, the index register length flag (x) determines whether this register is used as a 16-bit register or as an 8-bit register. In the MVP or MVN instruction, a block transfer instruction, the contents of index register Y indicate the low-order 16 bits of the destination address. The second byte of the instruction is the high-order 8 bits of the destination address.

CENTRAL PROCESSING UNIT (CPU) 2–4 7721 Group User’s Manual

2.1.4 Stack pointer (S)

The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when addressing modes using the stack are executed. The contents of S indicate an address (stack area) for storing registers during subroutine calls and interrupts. Stack area is selected by the stack bank select bit described later (bit 7 at address 5E 16). The stack area is specified to bank 016 when the stack bank select bit is “0,” and the stack area is specified to bank FF16 when it is “1.” When an interrupt request is accepted, the microcomputer stores the contents of the program bank register (PG) at the address indicated by the contents of S and decrements the contents of S by 1. Then the contents of the program counter (PC) and the processor status register (PS) are stored. The contents of S after accepting an interrupt request is equal to the contents of S decremented by 5 before the accepting of the interrupt request. (Refer to “Figure 2.1.2.”) When completing the process in the interrupt routine and returning to the original routine, the contents of registers stored in the stack area are restored into the original registers in the reverse sequence (PS→ PC → PG) by executing the RTI instruction. The contents of S is returned to the state before accepting an interrupt request. The same operation is performed during a subroutine call, however, the contents of PS is not automatically stored. (The contents of PG may not be stored. This depends on the addressing mode.) The user should store registers other than those described above with software when the user needs them during interrupts or subroutine calls. Additionally, initialize S at the beginning of the program because its contents are undefined at reset. The stack area changes when subroutines are nested or when multiple interrupt requests are accepted. Therefore, make sure of the subroutine’s nesting depth not to destroy the necessary data. Note: Refer to “7700 Family Software Manual” for addressing modes. Fig. 2.1.2 Stored registers of the stack area l “S” is the initial address that the stack pointer (S) indicates at accepting an interrupt request. The S’s contents become “S–5” after storing the above registers. Address S–4 S–3 S–2 S–1 S Stack area S–5 Processor status register’s low-order byte (PSL) Processor status register’s high-order byte (PSH ) Program counter’s low-order byte (PCL) Program counter’s high-order byte (PCH ) Program bank register (PG)

CENTRAL PROCESSING UNIT (CPU) 2–5

2.1.5 Program counter (PC)

The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. The contents of the high-order program counter (PC H ) become “FF16,” and the low-order program counter (PCL) becomes “FE16” at reset. The contents of the program counter becomes the contents of the reset’s vector address (addresses FFFE16, FFFF16) immediately after reset. Figure 2.1.3 shows the program counter and the program bank register. Fig. 2.1.3 Program counter and program bank register

2.1.6 Program bank register (PG)

The access space is divided in units of 64 Kbytes. This unit is called “bank.” (Refer to section “2.3 Access space.”) The program bank register is an 8-bit register. This register indicates the high-order 8 bits (bank) of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. These 8 bits are called bank. When a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others, the contents of the program bank register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the program counter, the contents of the program bank register is automatically decremented by 1. Accordingly, there is no need to consider bank boundaries in programming, usually. This register is cleared to “00 16” at reset.

2.1.7 Data bank register (DT)

The data bank register is an 8-bit register. In the following addressing modes using the data bank register, the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed. Use the LDT instruction to set a value to this register. This register is cleared to “0016” at reset. l Addressing modes using data bank register

Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Absolute
Absolute bit
Absolute indexed X
Absolute indexed Y
Absolute bit relative
Stack pointer relative indirect indexed Y PC H PC L b7 b0 b15 b8 b7 b0 (b16)(b23) PG

CENTRAL PROCESSING UNIT (CPU) 2–6 7721 Group User’s Manual

2.1.8 Direct page register (DPR)

The direct page register is a 16-bit register. The contents of this register indicate the direct page area which is allocated in bank 016 or in the space across banks 016 and 116. The following addressing modes use the direct page register. The contents of the direct page register indicate the base address (the lowest address) of the direct page area. The space which extends to 256 bytes above that address is specified as a direct page. The direct page register can contain a value from “000016” to “FFFF16.” When it contains a value equal to or more than “FF0116,” the direct page area spans the space across banks 016 and 116. When the contents of low-order 8 bits of the direct page register is “0016,” the number of cycles required to generate an address is 1 cycle smaller than the number when its contents are not “0016.” Accordingly, the access efficiency can be enhanced in this case. This register is cleared to “0000 16” at reset. Figure 2.1.4 shows a setting example of the direct page area. l Addressing modes using direct page register

Direct
Direct bit
Direct indexed X
Direct indexed Y
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Direct bit relative Notes 1: The number of cycles required to generate an address is 1 cycle smaller when the low-order 8 bits of the DPR are “0016.” 2: The direct page area spans the space across banks 016 and 116 when the DPR is “FF0116” or more. Fig. 2.1.4 Setting example of direct page area Bank 016 Bank 116 016 FF16 12316 22216 FF1016 1000F16 016 FFFF 16 1000016 Direct page area when DPR = “FF1016” (Note 2) Direct page area when DPR = “0000 16” Direct page area when DPR = “0123 16”(Note 1)

CENTRAL PROCESSING UNIT (CPU) 2–7

2.1.9 Processor status register (PS)

The processor status register is an 11-bit register. Figure 2.1.5 shows the structure of the processor status register. Processor status register (PS) Note: Bits 11–15 is always “0” at reading. Fig. 2.1.5 Processor status register structure (1) Bit 0: Carry flag (C) It retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic operation. This flag is also affected by shift and rotate instructions. When the BCC or BCS instruction is executed, this flag’s contents determine whether the program causes a branch or not. Use the SEC or SEP instruction to set this flag to “1,” and use the CLC or CLP instruction to clear it to “0.” (2) Bit 1: Zero flag (Z) It is set to “1” when a result of an arithmetic operation or data transfer is “0,” and cleared to “0” when otherwise. When the BNE or BEQ instruction is executed, this flag’s contents determine whether the program causes a branch or not. Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” Note: This flag is invalid in the decimal mode addition (the ADC instruction). (3) Bit 2: Interrupt disable flag (I) It disables all maskable interrupts (interrupts other than watchdog timer, the BRK instruction, and zero division). Interrupts are disabled when this flag is “1.” When an interrupt request is accepted, this flag is automatically set to “1” to avoid multiple interrupts. Use the SEI or SEP instruction to set this flag to “1,” and use the CLI or CLP instruction to clear it to “0.” This flag is set to “1” at reset. (4) Bit 3: Decimal mode flag (D) It determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic is performed when this flag is “0.” When it is “1,” decimal arithmetic is performed with 8 bits treated as two digits decimal (the data length flag (m) = “1”) or 16 bits treated as four digits decimal (the data length flag (m) = “0”). Decimal adjust is automatically performed. Decimal operation is possible only with the ADC and SBC instructions. Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” This flag is cleared to “0” at reset. (5) Bit 4: Index register length flag (x) It determines whether each of index register X and index register Y is used as a 16-bit register or an 8-bit register. That register is used as a 16-bit register when this flag is “0,” and as an 8-bit register when it is “1.” Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” This flag is cleared to “0” at reset. Note: When transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the TXA , TYA , TXB , TYB , and TXS instructions. Refer to “7700 Family Software Manual” for details. b15 b8 b7 b0 b1b2b3b4b5b6b14 b9 b10b11b12b13 0N C ZIDxmV0 IPL 000

CENTRAL PROCESSING UNIT (CPU) 2–8 7721 Group User’s Manual (6) Bit 5: Data length flag (m) It determines whether to use a data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16- bit unit when this flag is “0,” and as an 8-bit unit when it is “1.” Use the SEM or SEP instruction to set this flag to “1,” and use the CLM or CLP instruction to clear it to “0.” This flag is cleared to “0” at reset. Note: When transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the TXA , TYA , TXB , TYB , and TXS instructions. Refer to “7700 Family Software Manual” for details. (7) Bit 6: Overflow flag (V) It is used when adding or subtracting with a word regarded as signed binary. When the data length flag (m) is “0,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range between –32768 and +32767, and cleared to “0” in all other cases. When the data length flag (m) is “1,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range between –128 and +127, and cleared to “0” in all other cases. The overflow flag is also set to “1” when a result of division exceeds the register length to be stored in a division instruction DIV. When the BVC or BVS instruction is executed, this flag’s contents determine whether the program causes a branch or not. Use the SEP instruction to set this flag to “1,” and use the CLV or CLP instruction to clear it to “0.” Note: This flag is invalid in the decimal mode. (8) Bit 7: Negative flag (N) It is set to “1” when a result of arithmetic operation or data transfer is negative. (Bit 15 of the result is “1” when the data length flag (m) is “0,” or bit 7 of the result is “1” when the data length flag (m) is “1.”) It is cleared to “0” in all other cases. When the BPL or BMI instruction is executed, this flag determines whether the program causes a branch or not. Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” Note: This flag is invalid in the decimal mode. (9) Bits 10 to 8: Processor interrupt priority level (IPL) These three bits can determine the processor interrupt priority level to one of levels 0 to 7. The interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each interrupt control register, is higher than IPL. When an interrupt request is accepted, IPL is stored in the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request. There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the new IPL into the stack area and updating the processor status register with the PUL or PLP instruction. The contents of IPL is cleared to “0002” at reset.

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A bus interface unit (BIU) is built-in between the central processing unit (CPU) and memory•I/O devices. BIU’s function and operation are described below. When externally connecting devices, refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.”

2.2.1 Overview

Transfer operation between the CPU and memory•I/O devices is always performed via the BIU. À The BIU reads an instruction from the memory before the CPU executes it. \` When the CPU reads data from the memory•I/O device, the CPU first specifies the address from which data is read to the BIU. The BIU reads data from the specified address and passes it to the CPU. ´ When the CPU writes data to the memory•I/O device, the CPU first specifies the address to which data is written to the BIU and write data. The BIU writes the data to the specified address. ˆ To perform the above operations À to ´ , the BIU inputs and outputs the control signals, and control the bus. Figure 2.2.1 shows the bus and bus interface unit (BIU).

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Fig. 2.2.1 Bus and bus interface unit (BIU) M37721 Internal bus D 8 to D Central processing unit (CPU) SFR : Special Function RegisterNotes 1: The CPU bus, internal bus, and external bus are independent of one another. Refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES” about control signals of the external bus. Internal bus A 0 to A External device Internal control signal CPU bus Internal bus Internal bus D 0 to D Internal memory Internal peripheral device(SFR) External busA 0 to A A 0 to A Control signals Bus interface unit(BIU) A 8/D 8 to A Bus conversion circuit

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2.2.2 Functions of bus interface unit (BIU)

of each register. Program address register Instruction queue buffer Data address register Data buffer PA DA Q 0 Q 1 Q 2 DB H DB L b23 b0 b23 b15 Table 2.2.1 Functions of each register Functions Indicates the storage address for the instruction which is next taken into the instruction queue buffer. Temporarily stores the instruction which has been taken in. Indicates the address for the data which is next read from or written to. Temporarily stores the data which is read from the memory•I/O device by the BIU or which is written to the memory•I/O device by the CPU. Name Program address register Instruction queue buffer Data address register Data buffer Fig. 2.2.2 Register structure of bus interface unit (BIU)

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The CPU and the bus send or receive data via BIU because each operates based on different clocks (Note). The BIU allows the CPU to operate at high speed without waiting for access to the memory I/O devices that require a long access time. The BIU’s functions are described bellow. Note: The CPU operates based on φCPU . The period of φCPU is normally the same as that of φ. The internal__ bus operates based on the E signal. The period of the E signal is twice that of φ at a minimum. (1) Reading out instruction (Instruction prefetch) When the CPU does not require to read or write data, that is, when the bus is not in use, the BIU reads instructions from the memory and stores them in the instruction queue buffer. This is called instruction prefetch. The CPU reads instructions from the instruction queue buffer and executes them, so that the CPU can operate at high speed without waiting for access to the memory which requires a long access time. When the instruction queue buffer becomes empty or contains only 1 byte of an instruction, the BIU performs instruction prefetch. The instruction queue buffer can store instructions up to 3 bytes. The contents of the instruction queue buffer is initialized when a branch or jump instruction is executed, and the BIU reads a new instruction from the destination address. When instructions in the instruction queue buffer are insufficient for the CPU’s needs, the BIU extends the pulse duration of clock φCPU in order to keep the CPU waiting until the BIU fetches the required number of instructions or more. (2) Reading data from memory•I/O device The CPU specifies the storage address of data to be read to the BIU’s data address register, and requires data. The CPU waits until data is ready in the BIU. The BIU outputs the address received from the CPU onto the address bus, reads contents at the specified address, and takes it into the data buffer. The CPU continues processing, using data in the data buffer. However, if the BIU uses the bus for instruction prefetch when the CPU requires to read data, the BIU keeps the CPU waiting. (3) Writing data to memory•I/O device The CPU specifies the address of data to be written to the BIU’s data address register. Then, the CPU writes data into the data buffer. The BIU outputs the address received from the CPU onto the address bus and writes data in the data buffer into the specified address. The CPU advances to the next processing without waiting for completion of BIU’s write operation. However, if the BIU uses the bus for instruction prefetch when the CPU requires to write data, the BIU keeps the CPU waiting. (4) Bus control To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses the memory•I/O device is called the bus cycle. Refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES ” about the bus cycle at accessing the external devices.

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2.2.3 Operation of bus interface unit (BIU)

Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU). About signals which are input/output externally when accessing external devices, refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.” (1) When fetching instructions into the instruction queue buffer À When the instruction which is next fetched is located at an even address, the BIU fetches 2 bytes at a time with the timing of waveform (a). However, when accessing an external device which is connected with the 8-bit external data bus width (BYTE = “H”), only 1 byte of the instruction is fetched. \ When the instruction which is next fetched is located at an odd address, the BIU fetches only 1 byte with the timing of waveform (a). The contents at the even address are not taken into the instruction queue buffer. (2) When reading or writing data to and from the memory•I/O device À When accessing a 16-bit data which begins at an even address, waveform (a) is applied. The 16 bits of data are accessed at a time. \ When accessing a 16-bit data which begins at an odd address, waveform (b) is applied. The 16 bits of data are accessed separately in 2 operations, 8 bits at a time. Invalid data is not fetched into the data buffer. ´ When accessing an 8-bit data at an even address, waveform (a) is applied. The data at the odd address is not fetched into the data buffer. ˆ When accessing an 8-bit data at an odd address, waveform (a) is applied. The data at the even address is not fetched into the data buffer. For instructions that are affected by the data length flag (m) and the index register length flag (x), operation À or \` is applied when flag m or x = “0”; operation ´ or ˆ is applied when flag m or x = “1.”

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Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU) Address (a) Data (Even address) Data (Odd address) E Internal address bus (A0 to A23) Internal data bus (D0 to D 7) Internal data bus (D8 to D 15) (b) Address (Odd address) Address (Even address) Data (Even address) Data (Odd address) Invalid data Invalid data Internal address bus (A0 to A23) Internal data bus (D0 to D 7) Internal data bus (D8 to D 15) E

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Figure 2.3.1 shows the M37721’s access space. By combination of the program counter (PC), which is 16 bits of structure, and the program bank register (PG), a 16-Mbyte space from addresses 0 16 to FFFFFF16 can be accessed. For details about access of an external area, refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.” The memory and I/O devices are assigned in the same access space. Accordingly, it is possible to perform transfer and arithmetic operations using the same instructions without discrimination of the memory from I/O devices. Fig. 2.3.1 M37721’s access space : Indicates the memory assignment of the internal areas. : Indicates that nothing is assigned. Note : Memory assignment of internal RAM area varies according to the type of microcomputer. This figure shows the case of the M37721S2BFP. Refer to “Figure 2.4.1” for the M37721S1BFP. SFR :Special Function Register 00000016 00008016 00FFFF 16 01000016 FE0000 16 FF000016 FFFFFF 16 SFR area Internal RAM area Bank 016 SFR area 02000016 00047F16 00007F16 Bank 116 Bank FF16 Bank FE16 001FC0 16 001FFF 16

CENTRAL PROCESSING UNIT (CPU) 2–16

2.3.1 Banks

The access space is divided in units of 64 Kbytes. This unit is called “bank.” The high-order 8 bits of address (24 bits) indicate a bank, which is specified by the program bank register (PG) or data bank register (DT). Each bank can be accessed efficiently by using an addressing mode that uses the data bank register (DT). If the program counter (PC) overflows at a bank boundary, the contents of the program bank register (PG) is incremented by 1. If a borrow occurs in the program counter (PC) as a result of subtraction, the contents of the program bank register (PG) is decremented by 1. Normally, accordingly, the user can program without concern for bank boundaries. SFR (Special Function Register) and internal RAM are assigned in bank 016. For details, refer to section “2.4 Memory assignment.”

2.3.2 Direct page

A 256-byte space specified by the direct page register (DPR) is called “direct page.” A direct page is specified by setting the base address (the lowest address) of the area to be specified as a direct page into the direct page register (DPR). By using a direct page addressing mode, a direct page can be accessed with less instruction cycles than otherwise. Note: Refer also to section “2.1 Central processing unit.”

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This section describes the internal area’s memory assignment. For more information about the external area, refer also to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.” Figure 2.4.1 shows the memory assignment.

2.4.1 Memory assignment in internal area

SFR (Special Function Register) and internal RAM are assigned in the internal area. (1) SFR area The registers for setting internal peripheral devices are assigned at addresses 016 to 7F16 and 1FC016 For each register in the SFR area, refer to each functional description in this manual. For the state of the SFR area immediately after reset, refer to section “4.1.2 State of CPU, SFR area, and internal RAM area.” (2) Internal RAM area The M37721S2BFP ( Note 1) assigns the 1024-byte static RAM at addresses 80 16 to 47F16. 512 bytes of that can be selected either it is used as the internal RAM or it is used as the external area. (Note The internal RAM area is used as a stack area (Note 3), as well as an area to store data. Accordingly, note that set the nesting depth of a subroutine and multiple interrupts’ level not to destroy the necessary data. Notes 1: The M37721S1BFP assigns the 512-byte static RAM at addresses 80 16 to 27F16. 2: The internal RAM area becomes 512 bytes after reset because the internal RAM area select bit is “0.” 3: Either bank 016 or bank FF16 can be selected as the stack area by the stack bank select bit (bit 7 at address 5E16). Figure 2.4.4 shows the structure of the processor mode registers 0, 1.

CENTRAL PROCESSING UNIT (CPU) 2–18

2.4.2 External area

Table 2.4.1 lists the external area. When connecting the external device, follow the procedure described bellow:

Connect the ROM to addresses FFCE16 to FFFF16 because they are interrupt vector table.
Stack area can be assigned to bank 016 or bank FF16. Select the stack area by the stack bank select bit (bit 7 at address 5E16). (Refer to “Figure 2.4.4.”)
When using the DRAM controller, DRAM area can be selected from address FFFFFF16 toward the low- order address in a unit of 1 Mbytes. (Refer to “CHAPTER 14. DRAM CONTROLLER.” ) In the case connecting an external device to the area where overlaps the internal area, when reading out the overlapping area, the central processing unit (CPU) take in data of the internal area and do not take in data of the external area. When writing to the overlapping area, data is written to the internal area. The signal is output to the external at the same timing when data is written to the internal area. Table 2.4.1 External area

Internal RAM area select bit External area M37721S1BFP “0” (Fix this bit to “0.”) 216–916 28016–1FBF 16 200016–FFFFFF 16 216–916 48016–1FBF 16 200016–FFFFFF 16 Internal RAM area select bit : bit 1 at address 5F16

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Fig. 2.4.1 Memory assignment /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Notes 1: Addresses 216 to 916 are the external memory area. 2: For the M37721S1BFP, fix the internal RAM area select bit to “0.” 3: DBC is an interrupt only for debugging; do not use this interrupt. Timer A0 L H L H L H L H L H L H L H H L H Timer A4 L H LTimer A3 H Timer A2 L H Timer A1 L H L H L H L H L H L H Timer B2 L H Timer B1 L H Timer B0 L H A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive INT2 INT1 INT0 Watchdog timer DBC (Note 3) BRK instruction zero divide RESET 00FFD6 16 00FFD8 16 00FFDA 16 00FFDC 16 00FFDE 16 00FFE0 16 00FFE2 16 00FFE8 16 00FFEC 16 00FFE4 16 00FFE6 16 00FFEA 16 00FFEE 16 00FFF0 16 00FFF2 16 00FFF4 16 00FFF6 16 00FFF8 16 00FFFA 16 00FFFC 16 00FFFE 16 Interrupt vector table L 00007F16 00000016 00008016 FFFFFF 16 SFR area (Note 1) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 001FC0 16 00047F16 /LiteDiagLines/LiteDiagLines : The internal memory is not assigned. L H L H L H L H DMA3 DMA2 DMA1 DMA0 00FFCE 16 00FFD0 16 00FFD2 16 00FFD4 16 M37721S2BFP M37721S1BFP 00027F16 Internal RAM area (512 bytes) (512 bytes) SFR area 001FFF 16 00FFCE 16 00FFFF 16 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines SFR area (Note 1) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Internal RAM area (512 bytes) (Note 2) SFR area Case of Internal RAM area select bit = “0” Case of Internal RAM area select bit = “1”

CENTRAL PROCESSING UNIT (CPU) 2–20 Fig. 2.4.2 SFR area’s memory map (1) 00000016 00000116 00000216 00000316 00000416 00000516 00000616 00000716 00000816 00000916 00001016 00001116 00001216 00001316 00001416 00001516 00001616 00001716 00001816 00001916 00001A16 00001B16 00001C 16 00001D 16 00001E16 00001F16 00002016 00002116 00002216 00002316 00002416 00002516 00002616 00002716 00002816 00002916 00002A16 00002B16 00002C 16 00002D 16 00002E16 00002F16 00003016 00003116 00003216 00003316 00003416 00003516 00003616 00003716 00003816 00003916 00003A16 00003B16 00003C 16 00003D 16 00003E16 00003F16 00000B16 00000C 16 00000D 16 00000E16 00000F16 00000A16 Address 00005016 00005116 00005216 00005316 00005416 00005516 00005616 00005716 00005816 00005916 00005A16 00005B16 00005C 16 00005D 16 00005E16 00005F16 00006016 00006116 00006216 00006316 00006416 00006516 00006616 00006716 00006816 00006916 00006A16 00006B16 00006C 16 00006D 16 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C 16 00007D 16 00007E16 00007F16 Address 00004E16 00004F16 00004C 16 00004D 16 00004A16 00004B16 00004816 00004916 00004616 00004716 00004416 00004516 00004216 00004316 00004016 00004116 Port P8 direction register Timer A1 register Timer A4 register Timer A2 register Timer A3 register Timer B0 register Timer B1 register Timer B2 register Count start register One-shot start register Up-down register Timer A0 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Watchdog timer register Watchdog timer frequency select register A-D conversion interrupt control register UART0 receive interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit/receive control register 1 UART0 receive buffer register UART1 transmit buffer register UART1 receive buffer register A-D sweep pin select register A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 UART0 transmit interrupt control register UART1 transmit interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register A-D register 6 A-D register 7 Processor mode register 1 Port P9 register Port P9 direction register Port P10 register Pulse output data register 0 Port P10 direction register Pulse output data register 1 Real-time output control register DRAM control register Refresh timer DMAC control register L DMAC control register H DMA0 interrupt control register DMA1 interrupt control register DMA2 interrupt control register DMA3 interrupt control register

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Fig. 2.4.3 SFR area’s memory map (2) 001FC0 16 001FC1 16 001FC2 16 001FC3 16 001FC4 16 001FC5 16 001FC6 16 001FC7 16 001FC8 16 001FC9 16 001FD0 16 001FD1 16 001FD2 16 001FD3 16 001FD4 16 001FD5 16 001FD6 16 001FD7 16 001FD8 16 001FD9 16 001FDA 16 001FDB 16 001FDC 16 001FDD 16 001FDE 16 001FDF 16 001FE0 16 001FE1 16 001FE2 16 001FE3 16 001FE4 16 001FE5 16 001FE6 16 001FE7 16 001FE8 16 001FE9 16 001FEA 16 001FEB 16 001FEC 16 001FED 16 001FEE 16 001FEF 16 001FF016 001FF116 001FF216 001FF316 001FF416 001FF516 001FF616 001FF716 001FF816 001FF916 001FFA 16 001FFB 16 001FFC 16 001FFD 16 001FFE 16 001FFF 16 001FCB 16 001FCC 16 001FCD 16 001FCE 16 001FCF 16 001FCA 16 Address Source address register 0 L M H L M H L M H L M H L M H Destination address register 0 Transfer counter register 0 DMA0 mode register L DMA0 mode register H DMA0 control register Source address register 1 Destination address register 1 L M H L M H L M H L M H L M H L M H L M H Transfer counter register 1 DMA1 mode register L DMA1 mode register H DMA1 control register Source address register 2 Destination address register 2 Transfer counter register 2 DMA2 mode register L DMA2 mode register H DMA2 control register Source address register 3 Destination address register 3 Transfer counter register 3 DMA3 mode register L DMA3 mode register H DMA3 control register

CENTRAL PROCESSING UNIT (CPU) 2–22 Bit Bit name Functions At reset RW Fix this bit to “0.” Software reset bit Interrupt priority detection time select bits Stack bank select bit The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. 0 : Bank 016 1 : Bank FF16 b5 b4 Processor mode register 0 (Address 5E16) b1 b0b2b3b4b5b6b7 RW WO 0 RW 0 RW Fix this bit to “0.” RW RW Nothing is assigned. The value is “1” at reading. 2 0Wait bit RW0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (Address 5F16) Bit 7 to 2 Bit name At reset RWFunctions Notes 1: For the M37721S1BFP, fix bit 1 to “0.” 2: For the M37721S2BFP, set bit 1 before setting the stack pointer. Nothing is assigned. –Undefined Internal RAM area select bit (Notes 1, 2) 0 : 512 bytes (addresses 8016 to 27F16) 1 : 1024 bytes (addresses 8016 to 47F16) Nothing is assigned. RW0 –Undefined : Bits 0 to 6 are not used for the memory assignment. Fig. 2.4.4 Structure of processor mode registers 0, 1

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The M37721’s bus is used for DRAMC, Hold function, and DMAC besides CPU. When the bus requests of two or more source are detected at the same timing, the highest bus access priority levels get the access right. The bus priority levels are fixed by hardware. Additionally the bus use state is output from the status signal output pins ST0 and ST1. Table 2.5.1 lists the bus use priority levels and the status signals depending on the bus use state. Table 2.5.1 Bus use priority levels and status signals depending on bus use state Status signal ST1 ST0 Bus use priority levels 1 (Highest) 4 (Lowest) Bus use state DRAM refresh Hold DMAC CPU (Including the term that CPU does not use the bus during calculation etc.) For details, refer to section “13.2.1 Bus access control circuit” and chapter for each peripheral devices.

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3.1 Signals required for accessing

3.2 Software Wait

3.3 Ready function

3.4 Hold function

[Precautions for Hold function]

CONNECTION WITH EXTERNAL DEVICES

3.1 Signals required for accessing external devices

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The functions and operations of the signals which are required for accessing the external devices are described below. When connecting an external device that requires long access time, refer to sections “3.2 Software Wait,” “3.3 Ready function,” and “3.4 Hold function,” as well as this section. When the external DRAM is controlled by using DRAM controller, refer to “CHAPTER 14. DRAM CONTROLLER.”

3.1.1 Descriptions of signals

Figure 3.1.1 shows the pin configurations when the external data bus width is 16 bits and 8 bits. (1) External buses (A The external area is specified by the address (A0–A 23) output. The A 8–A 23 pins of the external address bus and the D0–D 15 pins of the external data bus are assigned to the same pins. When the BYTE pin level, described later, is “L” (external data bus width is 16 bits), the A8/D8– A 15/D15 and A16/D0–A 23/D7 pins perform address output and data input/output with time-sharing. When the BYTE pin level is “H” (external data bus width is 8 bits), the A16/D0–A 23/D7 pins perform address output and data input/output with time-sharing, and the A8–A 15 pins output the address. (2) External data bus width switching signal (BYTE pin level) This signal is used to select the external data bus width from 8 bits and 16 bits. The width is 16 bits when the level is “L,” and 8 bits when the level is “H.” Fix this signal to either “H” or “L” level. This signal is valid only for the external area. (When accessing the internal area, the data bus width is always 16 bits.) (3) Enable signal (E) This signal becomes “L” level while reading or writing data from and to the data bus. (Refer to “Table 3.1.1.”) (4) Read/Write signal (R/W) This signal indicates the state of the data bus. This signal becomes “L” level while writing data to__ __ the data bus. Table 3.1.1 lists the state of the data bus indicated with the E and R/W signals. Table 3.1.1 State of data bus indicated with E and__ R/W signals E H L R/W H L H L State of data bus Not used Read data Write data

CONNECTION WITH EXTERNAL DEVICES

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Fig. 3.1.1 Pin configurations when external data bus width is 16 bits and 8 bits (top view) P87/TXD 1 P90/DMAACK0 P91/DMAREQ0 P92/DMAACK1 P93/DMAREQ1 P94/DMAACK2 P95/DMAREQ2 P96/DMAACK3 P97/DMAREQ3 A0/MA0 A1/MA1 A2/MA2 A3/MA3 A4/MA4 A5/MA5 A6/MA6 A7/MA7 A8/D8 A9/D9 A10 /D10 A11 /D11 A12 /D12 A13 /D13 A14 /D14 A15 /D15 A16 /D0 A17 /D1 A18 /D2 A19 /D3 A20 /D4 P86/RXD 1 P85/CLK1 P84/CTS1/RTS1 P83/TXD 0 P82/RXD 0 P81/CLK0 P80/CTS0/RTS0 VCC AV CC VREF AV SS VSS P77/AN7/ADTRG P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 P57/TB1IN P56/TB0IN P55/TA4IN P54/TA4OUT P53/TA3IN P52/TA3OUT P51/TA2IN P50/TA2OUT P107/MA9 P106/MA8 P105/RAS P104/CAS P103/TC P102/INT2 P101/INT1 P100/INT0 P47 P46 P45 P44 P43 A21/D5 A22/D6 A23/D7 R/W BHE BLE ALE ST0 ST1 V CC VSS E X OUT XIN RESET RESET OUT CNV SS BYTE HOLD RDY 35 3736 38 4439 40 41 42 43 45 46 47 48 49 5031 32 33 34 96 9495 93 8792 91 90 89 88 86 85 84 83 82 81100 99 98 97 M37721S2BFP 35 3736 38 4439 40 41 42 43 45 46 47 48 49 5031 32 33 34 96 9495 93 8792 91 90 89 88 86 85 84 83 82 81100 99 98 97 P86/RXD 1 P85/CLK1 P84/CTS1/RTS1 P83/TXD 0 P82/RXD 0 P81/CLK0 P80/CTS0/RTS0 VCC AV CC VREF AV SS VSS P77/AN7/ADTRG P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 P57/TB1IN P56/TB0IN P55/TA4IN P54/TA4OUT P53/TA3IN P52/TA3OUT P51/TA2IN P50/TA2OUT P107/MA9 P106/MA8 P105/RAS P104/CAS P103/TC P102/INT2 P101/INT1 P100/INT0 P47 P46 P45 P44 P43 A21/D5 A22/D6 A23/D7 R/W BHE BLE ALE ST0 ST1 V CC VSS E X OUT XIN RESET RESET OUT CNV SS BYTE HOLD RDY M37721S2BFP l External data bus width = 16 bits (BYTE = “L”) : External address bus, external data bus, bus control signal l External data bus width = 8 bits (BYTE = “H”) Note: For the DRAM control signals, refer to “CHAPTER 14. DRAM CONTROLLER.” : External address bus, external data bus, bus control signal P87/TXD 1 P90/DMAACK0 P91/DMAREQ0 P92/DMAACK1 P93/DMAREQ1 P94/DMAACK2 P95/DMAREQ2 P96/DMAACK3 P97/DMAREQ3 A0/MA0 A1/MA1 A2/MA2 A3/MA3 A4/MA4 A5/MA5 A6/MA6 A7/MA7 A10 A11 A12 A13 A14 A15 A16 /D0 A17 /D1 A18 /D2 A19 /D3 A20 /D4

CONNECTION WITH EXTERNAL DEVICES

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(5) Byte low enable signal (BLE), Byte high enable signal (BHE)____ The BLE signal indicates the access to an even address. This signal becomes “L” level when accessing only an even address or when simultaneously accessing both an even and an odd address.____ The BHE signal indicates the access to an odd address. This signal becomes “L” level when accessing only an odd address or when simultaneously accessing both an odd and an even address. These signals are used to connect memories or I/O devices of which data bus width is 8 bits when the external data bus width is 16 bits. Table 3.1.2 lists levels of the BLE and BHE signals and access addresses. Table 3.1.2 Levels of BLE and BHE signals and access addresses Even and odd addresses (Simultaneous 2-byte access) L L Even address (1-byte access) L H Odd address (1-byte access) H L Access address ____ BLE ____ BHE (6) Address latch enable signal (ALE) This signal is used to latch the address from the multiplexed signal, which consists of the address and data. (This multiplexed signal is input to or output from the A8/D8–A 15/D15 and A16/D0–A 23/D7 pins.) When the ALE signal is “H,” latch the address and simultaneously output the addresses. When this signal is “L,” retain the latched address. (7) ____ Ready function-related signal (RDY) This is the signal to use Ready function (Refer to section “3.3 Ready function.”) (8) Hold function-related signal (HOLD) This is the signal to use Hold function. (Refer to section “3.4 Hold function.”) (9) Status signals (ST0, ST1) These signals indicate the bus use status. Table 3.1.3 lists the bus use status indicated by the ST0 and ST1 signals. (10) Clock This signal has the same period as φ. Table 3.1.3 Bus use status indicated by ST0 and ST1 signals Bus use status DRAM refresh Hold DMA CPU ST1 L L H H ST0 L H L H

CONNECTION WITH EXTERNAL DEVICES

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3.1.2 Operation of bus interface unit (BIU)

Figures 3.1.2 and 3.1.3 show the examples of operating waveforms of the signals input from or output to the external when accessing external devices. The following explains these waveforms, being compared with the basic operating waveform. (Refer to section “2.2.3 Operation of bus interface unit (BIU).”) (1) When fetching instructions into instruction queue buffer À When the instruction which is next fetched is located at an even address When the external data bus width is 16 bits, the BIU fetches 2 bytes of the instruction at a time with waveform (a). When the external data bus width is 8 bits, the BIU fetches only 1 byte of the instruction with the first half of waveform (e). When the instruction which is next fetched is located at an odd address When the external data bus width is 16 bits, the BIU fetches only 1 byte of the instruction with waveform (d). When the external data bus width is 8 bits, the BIU fetches only 1 byte of the instruction with the first half of waveform (f). When a branch to an odd address is caused by a branch instruction etc. with the 16-bit external data bus width, the BIU first fetches 1 byte of the instruction with waveform (d), and after that, fetches instructions in a unit of 2 bytes with waveform (a). (2) When reading or writing data from and to memories or I/O devices À When accessing 16-bit data which begins at an even address, waveform (a) or (e) is applied. \ When accessing 16-bit data which begins at an odd address, waveform (b) or (f) is applied. ´ When accessing 8-bit data at an even address, waveform (c) or the first half of (e) is applied. ˆ When accessing 8-bit data at an odd address, waveform (d) or the first half of (f) is applied. For instructions that are affected by the data length flag (m) and the index register length flag (x), operation À or \ is applied when flag m or x = “0”; operation ´ or ˆ is applied when flag m or x = “1.” The setup of flags m and x and the selection of the external data bus width do not affect each other.

CONNECTION WITH EXTERNAL DEVICES

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Fig. 3.1.2 Examples of operating waveforms of signals input from or output to the external (1) A0 to A7 A16/D0 to A23/D7 E ALE BHE A8/D8 to A15/D15 A0 to A7 A16/D0 to A23/D7 E ALE BHE A8/D8 to A15/D15 A0 to A7 A8/D8 to A15/D15 BHE E ALE A16/D0 to A23/D7 A0 to A7 A8/D8 to A15/D15 BHE E ALE A16/D0 to A23/D7 (a) Access beginning at even address <16-bit data access> l External data bus width = 16 bits (BYTE = “L”) Address Data(odd) Data(even) Address Address (b) Access beginning at odd address Address Address Address Data(odd) Address Address Address Data(even) <8-bit data access> (c) Access to even address Address Address Data(even) Address Address (d) Access to odd address Data(odd)Address Address BLE BLE BLE BLE

CONNECTION WITH EXTERNAL DEVICES

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Fig. 3.1.3 Examples of operating waveforms of signals input from or output to the external (2) E ALE A0 to A7 BHE A8 to A15 A16/D0 to A23/D7 E ALE A0 to A7 BHE A8 to A15 A16/D0 to A23/D7 l External data bus width = 8 bits (BYTE = “H”) <8/16-bit data access> (e) Access beginning at even address Address Address Data Data 8-bit data access 16-bit data access Address Address Address Address DataAddressData Address Address Address Address Address 8-bit data access 16-bit data access (f) Access beginning at odd address Note: When accessing 16-bit data, 2 times of access are performed; the low-order 8 bits are accessed first, and after that, the high- order 8 bits are accessed. BLE BLE

CONNECTION WITH EXTERNAL DEVICES

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Software Wait provides a function to facilitate access to external devices that require long access time. To select the software Wait, use the wait bit (bit 2 at address 5E16). Figure 3.2.1 shows the structure of processor mode register 0 (address 5E16). Figure 3.2.2 shows examples of bus timing when software Wait is used. Software Wait is valid only for the eternal area. The internal area is always accessed with no Wait. Fig. 3.2.1 Structure of processor mode register 0 Bit Bit name Functions At reset RW Fix this bit to “0.” Software reset bit Interrupt priority detection time select bits Stack bank select bit The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. 0 : Bank 016 1 : Bank FF16 b5 b4 Processor mode register 0 (Address 5E16) b1 b0b2b3b4b5b6b7 RW WO 0 RW 0 RW Fix this bit to “0.” RW RW Nothing is assigned. The value is “1” at reading. 2 0Wait bit RW0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. : Bits 0, 1, and 3 to 6 are not used for accessing external area.

CONNECTION WITH EXTERNAL DEVICES

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Fig. 3.2.2 Examples of bus timing when software Wait is used (BYTE = “L”) <No Wait> Clock 1 A0— A7 A8/D8— A15/D15, A16/D0— A23/D7 E ALE Address 1 bus cycle (Note) Note: When the external data bus is 8 bits wide (BYTE = “H”), A8/D8 to A15/D15 operate with the same bus timing as A0 to A7. Address DataData AddressAddress l Internal areas are always accessed with this waveform. <Wait> Clock 1 A0— A7 A8/D8— A15/D15, A16/D0— A23/D7 E ALE (Note) 1 bus cycle Address Address DataData AddressAddress

CONNECTION WITH EXTERNAL DEVICES

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Ready function provides the function to facilitate access to external devices that require long access time.____ The microcomputer enters Ready state by input of “L” level to the RDY pin and retains this state while the____ level of the RDY pin is at “L.” Table 3.3.1 lists the microcomputer’s state in Ready state. In Ready state, the oscillator’s oscillation does not stop. Accordingly, the internal peripheral devices can operate. Ready function is valid for the internal and external areas. Table 3.3.1 Microcomputer’s state in Ready state Item Oscillation φCPU , φ __ _ Pins A0 to A7, A8/D8 to A15/D15, A16/D0 to A23/D7, E, R/W, BHE, BLE, ST0, ST1, ALE Pins P43 to P47, P5 to P10 (Note) Pin φ1 Watchdog timer State Operating Stopped at “L” Retain the state when Ready request was accepted. Outputs clock φ1. Operating Note: This applies when this functions as a programmable I/O port.

CONNECTION WITH EXTERNAL DEVICES

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3.3.1 Operation description____

The input level of the RDY pin is judged at the falling edge of clock φ1. When “L” level is detected at this point, the microcomputer enters Ready state. (This is called “Acceptance of Ready request.”)____ In Ready state, the input level of the RDY pin is judged at every falling edge of clock φ1. When “H” level is detected at this point, the microcomputer terminates Ready state at the next rising edge of clock φ1. Figure 3.3.1 shows timing of acceptance of Ready request and termination of Ready state. Refer also to section “16.1 Memory connection ” for usage of Ready function. ´ The “L” level which is input to th e RDY pin is accepted, so that E stops at “L” level for 1 cycle of clock 1 (indicated by ), and CPU stops at “L” level. \ The “L” level which is input to the RDY pin is not accepted, however CPU stops at “L” level. Clock 1 CPU RDY ALE ˆÀ\ Bus not in use <No Wait> À The “L” level which is input to the RDY pin is accepted, so that E stops at “H ” level for 1 cycle of clock 1 (indicated by ), and CPU stops at “L” level. RDY ALE <Wait> ´˜ˆ CPU E E RDY pin input level sampling timing ˆ ´ Bus in use ˆ Ready state is terminated. ˜ The “L” level which is input to the RDY pin is not accepted because it is sampled immediately before Wait by software Wait (indicated by ), however CPU stops at “L” level. Clock 1 RDY pin input level sampling timing Bus in use Fig. 3.3.1 Timing of acceptance of Ready request and termination of Ready state

CONNECTION WITH EXTERNAL DEVICES

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When composing the external circuit which accesses the bus without using the central processing unit (CPU), Hold function is used to generate a timing for transferring the right to use the bus from the CPU to the external circuit. _____ The microcomputer enters Hold state by input of “L” level to the HOLD pin and retains this state while the_____ level of the HOLD pin is at “L.” Table 3.4.1 lists the microcomputer’s state in Hold state. In Hold state, the oscillation of the oscillator does not stop. Accordingly, the internal peripheral devices can operate. However, Watchdog timer stops operating. Table 3.4.1 Microcomputer’s state in Hold state Item Oscillation φ φCPU E Pins A0 to A7, A8/D8 to A15/D15, A16/D0 to A23/D7, R/W, BHE, BLE Pins ALE, ST1 Pin ST0 Pin φ1 Pins P43 to P47, P5 to P10 (Note) Watchdog timer State Operating Operating Stopped at “L” Stopped at “H” Floating Output “L” level. Outputs “H” level. Outputs clock φ1. Retain the state when Hold request was accepted. Stopped Note: This applies when this functions as a programmable I/O port.

3.4.1 Operation description_____

Judgment of the HOLD pin input level is performed at every falling edge of φ1. When “L” level is detected at judgment of the input level, bus request (Hold) becomes “1,” when “H” level is detected, bus request (Hold) becomes “0.” Bus request (Hold) is sampled within a period when the bus request sampling signal is “1” and bus request is accepted when there is no bus request (DRAMC). (This is called “Acceptance of Hold request.”) For bus request, refer to section “13.2.1 Bus access control circuit.” When Hold request is accepted, φCPU stops at “L” level at the next rising edge of φ and the ST0 pin’s level becomes “H,” the ST1 pin’s level becomes “L.” When 1 cycle of φ has passed after the levels of the ST0__ ____ ____ and ST1 pins are changed, the R/W, BHE, BLE pins and the external bus enter the floating state. In Hold state, when the HOLD pin’s input level becomes “H,” the ST0 and ST1 pins’ levels are changed at the next rising edge of φ. When 1 cycle of φ has passed after the levels of the ST0 and ST1 pins are changed, the microcomputer terminates Hold state. Note: φ has the same polarity and the same frequency as clock φ1. However, φ stops by acceptance of Ready request, or executing the STP or WIT instruction. Accordingly,_____ judgment of the input level of the HOLD pin is not performed during Ready state.

CONNECTION WITH EXTERNAL DEVICES

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Fig. 3.4.1 Timing of acceptance of Hold request and termination of Hold state (1) R/W HOLD ALE Floating ST0 E Address BAddress A Bus request (Hold) ST1 Bus request sampling Transfer of right to use bus <When inputting “L” level to HOLD pin while bus is unused> l State when inputting “L” level to HOLD pin External data bus Data length External data bus width 8, 16 Unused 8, 16 Clock 1 (Note 1) External address bus BLE, BHE External address bus / External data bus Bus not in use Hold state Bus in use À This is the period in which the bus is not used, so that not a new address but the address which was output immediately before is output again. Notes 1: Clock 1 has the same polarity and the same frequency as . Timing of signals to be input from or output to the external is ordained on the basis of clock 1. 2: Bus request (Hold) and bus request sampling are internal signals. Floating Floating À (Note 2) (Note 2) Transfer of right to use bus

CONNECTION WITH EXTERNAL DEVICES

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Fig. 3.4.2 Timing of acceptance of Hold request and termination of Hold state (2) R/W ST1 HOLD ALE ST0 E Bus request (Hold) Bus request sampling <When inputting “L” level to HOLD pin while bus is used; when data access is completed with 1-bus cycle> l State when inputting “L” level to HOLD pin 8, 16 16 (Access beginning at even address) External data bus Data length External data bus width Used Clock 1 (Note 2) Floating Address AÀAddress A Floating Floating Data Address B External address bus External address bus / External data bus BLE, BHE Bus in use Transfer of right to use bus Hold state Bus in use À When a Hold request is accepted, not a new address but the address which was output immediately before is output again. Notes 1: The above diagram shows the case of no Wait. 2: Clock 1 has the same polarity and the same frequency as . Timing of signals to be input from or output to the external is ordained on the basis of clock 1. 3: Bus request (Hold) and bus request sampling are internal signals. (Note 3) (Note 3) Transfer of right to use bus

CONNECTION WITH EXTERNAL DEVICES

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E Address B Address A À When a Hold request is accepted, not a new address but the address which was output immediately before is output again. ST1 ST0 Bus request (Hold) Bus request sampling Transfer of right to use bus <When inputting “L” level to HOLD pin while bus is used; when data access is completed with continuous 2-bus cycle> l State when inputting “L” level to HOLD pin 16 (Access beginning at odd address) Used External data bus Data length External data bus width Clock 1 (Note 2) Floating Address A + 1À À DataExternal address bus / External data bus External address bus BLE, BHE Bus in use Hold state Bus in use Notes 1: The above diagram shows the case of 2- access in low-speed running. 2: Clock 1 has the same polarity and the same frequency as . Timing of signals to be input from or output to the external is ordained on the basis of clock 1. 3: Bus request (Hold) and bus request sampling are internal signals. Floating (Note 3) (Note 3) Transfer of right to use bus Fig. 3.4.3 Timing of acceptance of Hold request and termination of Hold state (3)

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[Precautions for Hold function] When a DRAM refresh request occurs in Hold state, DRAM refresh is performed immediately because the bus use priority level of DRAM refresh is higher than that of Hold function.

4.1 Hardware reset

4.2 Software reset

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When the power source voltage satisfies the microcomputer’s recommended operating conditions, the microcomputer is reset by supplying “L” level to the RESET pin. This is called a hardware reset. Figure 4.1.1 shows an example of hardware reset timing. Fig. 4.1.1 Example of hardware reset timing The following explains how the microcomputer operates in periods À to ˆ above. À After supplying “L” level to the RESET pin, the microcomputer initializes pins within a period of several ten ns. (Refer to “Table 4.1.1.”) While the RESET pin is “L” level and within a period of 4 to 5 cycles of φ after the RESET pin goes from “L” to “H,” the microcomputer initializes the central processing unit (CPU) and SFR area. At this time, the contents of the internal RAM area become undefined (except when Stop or Wait mode is terminated). ´ After \` , the microcomputer performs “Internal processing sequence after reset.” (Refer to “Figure 4.1.10.”) ˆ The microcomputer executes a program beginning with the address set into the reset vector addresses (FFFE 16 and FFFF 16). RESET Program is executed. 2 µs or more Internal processing sequence after reset Note: When the clock is stably supplied. (Refer to section “4.1.4 Time supplying “L” level to RESET pin.”) À 4 to 5 cycles of

4–3 RESET OUT output retaining timing. Table 4.1.1 Pin state while RESET pin is at “L” level Pin state Outputs “H” or “L” level. Outputs “H” level. Outputs “L” level. Outputs φ1. Floating. Pin (Bus, Port) name A 0/MA 0–A 7/MA 7, A8/D8–A 15/D15, A16/D0–A 23/D7, BHE, BLE __ _ R/W, E, ST0, ST1 ALE, RESET OUT HOLD, RDY, P4 3–P4 7, P5–P10 Fig. 4.1.2 RESETOUT output retaining timing RESET RESET OUT When RESET pin input level goes from “L” to “H” in this period 3.5 cycles of1

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4.1.2 State of CPU, SFR area, and internal RAM area

state of the SFR and internal RAM areas immediately after reset. Fig. 4.1.3 State of CPU registers immediately after reset : “0” immediately after reset. : “1” immediately after reset. : Undefined immediately after reset. Data bank register (DT) 0016 b7 b0 Program bank register (PG) 0016 b7 b0 Program counter (PC) Contents at address FFFE16Contents at address FFFF16 b7 b0b15 b8 Direct page register (DPR) 0016 b7 b0 0016 b15 b8 Processor status register (PS)0 0 0 0 00 0 0 00 0 1 b7 b0b15 b8 NV mxD IZ CIPL ??? ? Stack pointer (S) ? b7 b0 b15 b8 Index register Y (Y) ? b7 b0 b15 b8 Index register X (X) ? b7 b0 b15 b8 Accumulator B (B) ? b7 b0 b15 b8 Accumulator A (A) ? b7 b0 b15 b8 Register name State immediately after reset : Always “0” at reading.0

4–5 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? :Underfinedimmediately after reset. : Always “0” at reading. 0 : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” 1016 1116 1216 1316 Port P8 direction register1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 016 116 216 316 416 516 616 716 816 916 B16 C 16 D 16 E16 F16 A16 Address Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register A-D sweep pin select register Register name Access characteristics State immediately after reset RW RW RW RW RW RW RW RW RW RW 0016 0016 0 0 000 ? b7 b0 b7 b0 : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. RW RO WO l SFR area (016 to 7F16, 1FC016 to 1FFF16) RW ? 0016 ??? ? : Always “1” at reading. 1 RW RW RW RW RW WO WO Port P9 register Port P9 direction register Port P10 register Port P10 direction register Pulse output data register 0 Pulse output data register 1 000 00000000 Access characteristics State immediately after reset 0016 0016 Fig. 4.1.4 State of SFR and internal RAM areas immediately after reset (1)

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UART0 transmit/receive control register 0 UART0 transmit/receive mode register UART0 baud rate register UART0 transmit buffer register UART1 receive buffer register Register name UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 2816 2916 2B16 2C 16 2D 16 2E16 2F16 2A16 2016 2116 2216 2316 2416 2516 2616 2716 3F16 Address Access characteristics RW WO WO RO RO b7 b0 WO RWRO RO RORW RW RO RO RW WO WO WO RW RORW RW State immediately after reset 1 000 0016 0 000 00 0 ? b7 b0 0016 00000010 0000 0 0 0 1 000 0000 0 0 1 0 A-D register 5 A-D register 1 A-D register 3 A-D register 2 A-D register 4 A-D register 0 A-D register 6 A-D register 7 RO RO RO RO RO RO RO RO RO RO ??? ? ??? Fig. 4.1.5 State of SFR and internal RAM areas immediately after reset (2)

4–7 (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) b7 b0 RW (Note 2) RW RW RW RW RW RW WO State immediately after reset 0016 0016 0016 0016 b7 b0 WO RW (Note 1) (Note 1) (Note 1) RW Timer A0 mode register Timer A4 mode register (Note 3) 0 00 0 0 0 0 0 0 0 0 0 0 00 0 000 0 0 0 0 0 0 0RWRW Notes 1: The access characteristics at addresses 4A 16 to 4F16 vary according to Timer A’s operating mode. (Refer to “CHAPTER 8. TIMER A.”) 2: The access characteristics at addresses 5016 to 5316 vary according to Timer B’s operating mode. (Refer to “CHAPTER 9. TIMER B.”) 3: The access characteristics for bit 5 at addresses 5B16 and 5C16 vary according to Timer B’s operating mode. Bit 5 at address 5D16 is invalid. (Refer to “CHAPTER 9. TIMER B.”) 4: Bit 1 at address 5F16 becomes “0” immediately after reset. For the M37721S1BFP, fix this bit to “0.” RW(Note 3) RW(Note 3) 00 0 0 00?? 0 0 0 000?? ?Processor mode register 1 RW RW RW RW RW RW RW 00 0 000 0 0 00 0 0000 0 ?(Note 4) Fig. 4.1.6 State of SFR and internal RAM areas immediately after reset (3)

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UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address A-D conversion interrupt control register UART0 transmit interrupt control register UART1 transmit interrupt control register INT2 interrupt control register Watchdog timer frequency select register Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW b7 b0 RW State immediately after reset ?(Note 6) b7 b0 UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register 0 00 0 By writing dummy data to address 6016, the value “FFF16” is set to the watchdog timer. The dummy data is not retained anywhere. The value “FFF16” is set to the watchdog timer. (Refer to “CHAPTER 15. WATCHDOG TIMER .”) It is possible to read the bit state at reading. When writing “0” to this bit, this bit becomes “0.” But when writing “1” to this bit, this bit does not change. RW Notes 5: (Note 5) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 000 Real-time output control register Refresh timer DMAC control register L DMAC control register H DMA0 interrupt control register DMA1 interrupt control register DMA2 interrupt control register DMA3 interrupt control register RW 00000000 RWRWDRAM control register WO RW(Note 7) RW WO RW RW RW RW 00000000 000000 00000000 0 00 0 0 00 0? 0 00 0? 000 Fig. 4.1.7 State of SFR and internal RAM areas immediately after reset (4)

4–9 Fig. 4.1.8 State of SFR and internal RAM areas immediately after reset (5) 1FC0 16 1FC1 16 1FC2 16 1FC3 16 1FC4 16 1FC5 16 1FC6 16 1FC7 16 1FC8 16 1FC9 16 1FD0 16 1FD1 16 1FD2 16 1FD3 16 1FD4 16 1FD5 16 1FD6 16 1FD7 16 1FD8 16 1FD9 16 1FDA 16 1FDB 16 1FDC 16 1FDD 16 1FDE 16 1FDF 16 1FCB 16 1FCC 16 1FCD 16 1FCE 16 1FCF 16 1FCA 16 Address Register name Source address register 0 Access characteristics b7 b0 State immediately after reset b7 b0 RW /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 00 0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 00 0 0 00 0 RW RW /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 0 00 0/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 00 0 000 Destination address register 0 Transfer counter register 0 DMA0 mode register L DMA0 mode register H DMA0 control register Source address register 1 Destination address register 1 Transfer counter register 1 DMA1 mode register L DMA1 mode register H DMA1 control register RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 00 0 0 0 000 0 00 0 0 00 0 0 0??

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Fig. 4.1.9 State of SFR and internal RAM areas immediately after reset (6) 1FE0 16 1FE1 16 1FE2 16 1FE3 16 1FE4 16 1FE5 16 1FE6 16 1FE7 16 1FE8 16 1FE9 16 1FF016 1FF116 1FF216 1FF316 1FF416 1FF516 1FF616 1FF716 1FF816 1FF916 1FFA 16 1FFB 16 1FFC 16 1FFD 16 1FFE 16 1FFF 16 1FEB 16 1FEC 16 1FED 16 1FEE 16 1FEF 16 1FEA 16 Address Register name Source address register 2 Access characteristics b7 b0 State immediately after reset b7 b0 RW /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 00 0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 00 0 0 00 0 RW RW /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 00 0/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 00 0 000 Destination address register 2 Transfer counter register 2 DMA2 mode register L DMA2 mode register H DMA2 control register Source address register 3 Destination address register 3 Transfer counter register 3 DMA3 mode register L DMA3 mode register H DMA3 control register RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 00 0 0 0 000 0 00 0 0 00 0 0 0?? l Internal RAM area (addresses 8016 to 27F16)

At hardware reset
At termination of Stop or Wait mode WIT instruction is executed ] For the M37721S2BFP, the internal RAM area can be assigned to addresses 8016 to 47F16 by setting the internal RAM area select bit (bit 1 at address 5F16). (Refer to section “2.4 Memory assignment.”)

4–11

4.1.3 Internal processing sequence after reset

Figure 4.1.10 shows the internal processing sequence after reset. Fig. 4.1.10 Internal processing sequence after reset (Next op-code or operand) “H” CPU A0–A7 A8/D8–A15/D15 FE 16 AD L E R/W l External bus width = 16 bits (BYTE = “L”) AD H (ADH )0016 FF16 0016 0016 (Next op-code)A16/D0–A23/D7 0016 (ADL)0016 00160016 ALE “H” CPU A0–A7 FE 16 AD L E R/W 0016 A16/D0–A23/D7 0016 (A DH )0016 00160016 ALE FF16 A8–A15 FF16 AD H0016 FF16 0016 (ADL) l External bus width = 8 bits (BYTE = “H”) (Next op-code)

7721 Group User’s Manual4–12

4.1.4 Time supplying “L” level to RESET pin______

Time supplying “L” level to the RESET pin varies according to the state of the clock oscillation circuit. l When the oscillator is stably oscillating or a stable clock is input from the XIN pin, supply “L” level for 2 µs or more. l When the oscillator is not stably oscillating (including the case at power-on reset or in Stop mode), supply “L” level until the oscillation is stabilized. The time required for stabilizing oscillation varies according to the oscillator. For details, contact the oscillator manufacturer. circuit. ] For details about Stop mode, refer to section “5.3 Stop mode.” For details about clocks, refer to “CHAPTER 5. CLOCK GENERATING CIRCUIT.” Fig. 4.1.11 Power-on reset conditions Fig. 4.1.12 Example of power-on reset circuit Vcc RESET Powered on here 4.5V 0.9V IN OUT GND Delay capacity RESET Vcc Vss SWC d GND 5 V M51957AL M37721 27 k 10 k 4 ] The delay time is about 11 ms when Cd = 0.033 µF. td ≈ 0.34 5 C d [ µs], Cd: [ pF ] Vcc

4–13 When the power source voltage satisfies the microcomputer’s recommended operating conditions, the microcomputer is reset by writing “1” to the software reset bit (bit 3 at address 5E16). (This is called “ Software reset.”) In this case, the microcomputer initializes pins, CPU, and SFR area just as in the case of a hardware reset. However, the microcomputer retains the contents of the internal RAM area. (Refer to register 0 (address 5E 16). After completing initialization, the microcomputer performs “internal processing sequence after reset.” (Refer to “Figure 4.1.10.”) After that, it executes a program beginning from the address set into the reset vector addresses (FFFE 16 and FFFF 16). i Bit Bit name Functions At reset RW Software reset bit Interrupt priority detection time select bits Fix this bit to “ 0” Stack bank select bit The microcomputer is reset by writing “1” to this bit. The value of this bit is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. 0 : Bank 0 1 : Bank FF16 b5 b4 Processor mode register 0 (Address 5E16) : Bits 0 to 2 and bits 4 to 7 are not used for software reset. b1 b0b2b3b4b5b6b7 0 0 RW RW WO RW RW RW RW Fix this bit to “0” Nothing is assigned. This bit is “1” at reading. 1 Wait bit 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. Fig. 4.2.1 Structure of processor mode register 0

7721 Group User’s Manual4–14

When the software reset bit is set to “1,” the RESETOUT pin’s output level becomes “L.” In a period of 4.5________ cycles of clock φ1 after the software reset bit is set to “1,” the RESETOUT pin’s output level is “L.” Figure________ 4.2.2 shows the RESETOUT output timing at software reset. Fig. 4.2.2 RESETOUT output timing E RESET OUT Set software reset bit to “1”

5.1 Oscillation circuit examples

5.2 Clocks

5.3 Stop mode

[Precautions for Stop mode]

5.4 Wait mode

[Precautions for Wait mode]

7721 Group User’s Manual5–2

To the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock which is externally generated can be input. Oscillation circuit examples are shown below.

5.1.1 Connection example using resonator/oscillator

Figure 5.1.1 shows an example when connecting a ceramic resonator/quartz-crystal oscillator between pins X IN and XOUT . The circuit constants such as Rf, Rd, CIN, and COUT (shown in “Figure 5.1.1”) depend on the resonator/ oscillator. These values shall be set to the values recommended by the resonator/oscillator manufacturer.

5.1.2 Externally generated clock input example

Figure 5.1.2 shows an input example of the clock which is externally generated. The external clock must be input from the XIN pin, and the XOUT pin must be left open. Fig. 5.1.1 Connection example using resonator/oscillator Fig. 5.1.2 Externally generated clock input example M37721 XIN XOUT R f C IN C OUT R d M37721 XIN XOUT Vcc Vss Externally generated clock Open

7721 Group User’s Manual 5–3

Figure 5.2.1 shows the clock generating circuit block diagram. Fig. 5.2.1 Clock generating circuit block diagram Q XIN XOUT R S Q R S Q R S CPU 1/8 1/2 1/2 1/8 f16 f64 f512 f32 f512 Interrupt request STP instruction Reset WIT instruction Ready request CPU wait request from BIU Operation clock for internal peripheral devices Watchdog timer CPU : Central Processing Unit BIU : Bus Interface Unit Watchdog timer frequency select bit : Bit 0 at address 6116 Note: This signal is generated when the watchdog timer’s most significant bit becomes “0.” (Note) Watchdog timer frequency select bit “0” “1” Bus request DRAMC Hold DMAC

7721 Group User’s Manual5–4

5.2.1 Clocks generated in clock generating circuit

(1) φ It is the operation clock of BIU. It is also the clock source of φCPU . φ stops by acceptance of Ready request or execution of the STP or WIT instruction. It is not stopped by acceptance of bus request. (2) φCPU It is the operation clock of CPU. φCPU stops by the following:

Execution of the STP or WIT instruction, ____
Acceptance of Ready request; “L” level input to the RDY pin
CPU wait request from BIU; Acceptance of bus request is included. (3) Clock φ 1 It has the same period as φ and is output to the external from the φ1 pin. Clock φ1 stops by execution of the STP instruction. It is not stopped by acceptance of Ready or bus request, or execution of the WIT instruction. (4) f2 to f512 Each of them is the internal peripheral devices’ operation clock. Note: Refer to each functional description for details:

7721 Group User’s Manual 5–5

Stop mode is used to stop oscillation when there is no need to operate the central processing unit (CPU). The microcomputer enters Stop mode when the STP instruction is executed. Stop mode can be terminated by an interrupt request occurrence or the hardware reset.

5.3.1 Stop mode

When the STP instruction is executed, the oscillator stops oscillating. This state is called “Stop mode.” In Stop mode, the contents of the internal RAM can be retained intact when Vcc (power source voltage) is 2 V or more. Additionally, the microcomputer’s power consumption is lowered. It is because the CPU and all internal peripheral devices using clocks f 2 to f512 stop the operation. Table 5.3.1 lists the microcomputer’s state and operation in and after Stop mode. Table 5.3.1 Microcomputer’s state and operation in and after Stop mode State and OperationItem Oscillation φCPU , φ Clock φ1, f2 to f512 Timers A, B Serial I/O A-D converter DMA controller DRAM controller Watchdog timer Pins By interrupt request occurrence By hardware reset Internal peripheral devices State in Stop mode Operation after terminating Stop mode Stopped Can operate only in event counter mode Can operate only when an external clock is selected Stopped Stopped (Note) Stopped Retains the same state in which the STP instruction was executed Supply of φCPU and φ starts after a certain time measured by Watchdog timer has passed. Operates in the same way as hardware reset Note: DRAM refresh is not performed because the refresh timer also stops.

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(1) Termination by interrupt request occurrence When terminating Stop mode by interrupt request occurrence, instructions are executed after a certain time measured by the watchdog timer has passed. À When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of clock φ1, f2 to f512 starts. \` The watchdog timer starts counting owing to the oscillation start. The watchdog timer counts f32 regardless of the watchdog timer frequency select bit’s (bit 0 at address 6116) contents. ´ When the watchdog timer’s MSB becomes “0,” supply of φCPU and φ starts. At the same time, the watchdog timer’s count source returns to f32 or f512 that is selected by the watchdog timer frequency select bit. ˆ The interrupt request which occurred in À is accepted. Table 5.3.2 lists the interrupts used to terminate Stop mode. Table 5.3.2 Interrupts used to terminate Stop mode Conditions for using each function to generate interrupt requestInterrupt ____ INTi interrupt (i = 0 to 2) Timer Ai interrupt (i = 2 to 4) Timer Bi interrupt (i = 0, 1) UARTi transmit interrupt (i = 0, 1) UARTi receive interrupt (i = 0, 1) In event counter mode When external clock is selected Notes 1: Since the oscillator has stopped oscillating, interrupts not listed above cannot be used. Also, even the interrupts listed above cannot be used when the above conditions are not satisfied. The A-D converter does not operate, also. 2: When multiple interrupts listed above are enabled, Stop mode is terminated by the interrupt request which occurs first. 3: Refer to “CHAPTER 7. INTERRUPTS” and the description of each internal peripheral device for details about each interrupt. Before executing the STP instruction, interrupts used to terminate Stop mode must be enabled. In addition, the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the processor interrupt priority level (IPL) of the routine where the STP instruction is executed. When multiple interrupts in Table 5.3.2 are enabled, Stop mode is terminated by the first interrupt request. There is a possibility that any of all interrupt requests occurs after the oscillation starts in À and until supply of φCPU and φ starts in ´ . The interrupt requests which occur during this period are accepted in order of priority after the watchdog timer’s MSB becomes “0.” For interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled) before executing the STP instruction.

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Fig. 5.3.1 Stop mode terminating sequence by interrupt request occurrence (2) Termination by hardware reset______ Supply “L” level to the RESET pin by using the external circuit until the oscillation of the oscillator is stabilized. The CPU and the SFR area are initialized in the same way as system reset. However, the internal RAM area retains the same contents as that before executing the STP instruction. The terminating sequence is the same as the internal processing sequence which is performed after reset. Refer to “CHAPTER 4. RESET” for details about reset. “7FF16” “FFF16” Stop mode f(XIN) Operating Stopped Stopped Internal peripheral devices Operating Value of Watchdog timer f32 5 2048 counts Interrupt request used to terminate Stop mode (Interrupt request bit) Stopped Operating Operating Operating l Interrupt request used to terminate Stop mode occurs. l Oscillation starts.(When an external clock is input from the X IN pin, clock input starts.) l Watchdog timer starts counting. l STP instruction is executed l Watchdog timer’s MSB = “0” (However, watchdog timer interrupt request does not occur.) l Supply of CPU , starts. l Interrupt request which has been used to terminate Stop mode is accepted. CPU ,

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[Precautions for Stop mode] When executing the STP instruction after writing to an internal area or an external area, three NOP instructions must be inserted to complete the write operation before the STP instruction is executed. (Refer to “Figure 5.3.2.”) A, 5555 Write instruction NOP instruction inserted STP instruction Fig. 5.3.2 NOP instruction insertion example

7721 Group User’s Manual 5–9

Wait mode is used to stop φCPU and φ when there is no need to operate the central processing unit (CPU). The microcomputer enters Wait mode when the WIT instruction is executed. Wait mode can be terminated by an interrupt request occurrence or the hardware reset.

5.4.1 Wait mode

When the WIT instruction is executed, φCPU and φ stop. The oscillator’s oscillation is not stopped. This state is called “Wait mode.” In Wait mode, the microcomputer’s power consumption is lowered though Vcc (power source voltage) is maintained. Table 5.4.1 lists the microcomputer’s state and operation in and after Wait mode. Table 5.4.1 Microcomputer’s state and operation in and after Wait mode φCPU , φ Clock φ1, f2 to f512 Timer A Timer B Serial I/O A-D converter DMA controller DRAM controller Watchdog timer Pins State in Wait mode Operation after terminating Wait mode Internal peripheral devices By interrupt request occurrence By hardware reset Operating Stopped Operating Operating Stopped Stopped (Note) Operating Retains the same state in which the WIT instruction was executed Supply of φCPU and φ starts just after the termination. Operates in the same way as hardware reset. Note: The refresh timer operates, but DRAM refresh is not performed because the bus request (DRAMC) does not occur. (Refer to section “Appendix 9. 7721 Group Q & A.” )

7721 Group User’s Manual5–10

(1) Termination by interrupt request occurrence À When an interrupt request occurs, supply of φCPU and φ starts. \` The interrupt request which occurred in À is accepted. The following interrupts are used to terminate Wait mode. When a watchdog timer interrupt request occurs, Wait mode is also terminated. ___

INTi interrupt (i = 0 to 2)
Timer Ai interrupt (i = 0 to 4)
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0, 1)
UARTi receive interrupt (i = 0, 1)
A-D converter interrupt Note: Refer to “CHAPTER 7. INTERRUPTS ” and each functional description about interrupts. Before executing the WIT instruction, interrupts used to terminate Wait mode must be enabled. In addition, the interrupt priority level of the interrupt used to terminate Wait mode must be higher than the processor interrupt priority level (IPL) of the routine where the WIT instruction is executed. When multiple interrupts listed above are enabled, Wait mode is terminated by the interrupt request which occurs first. (2) Termination by hardware reset The CPU and the SFR area are initialized in the same way as system reset. However, the internal RAM area retains the same contents as that before executing the WIT instruction. The terminating sequence is the same as the internal processing sequence which is performed after reset. Refer to “CHAPTER 4. RESET” for details about reset.

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[Precautions for Wait mode] When executing the WIT instruction after writing to an internal area or an external area, three NOP instructions must be inserted to complete the write operation before the WIT instruction is executed. (Refer to “Figure 5.4.1.”) A, 5555 ; Write instruction NOP instruction inserted WIT instruction Fig. 5.4.1 NOP instruction insertion example

7721 Group User’s Manual5–12

6.1 Overview

6.2 Programmable I/O ports

6.3 Examples of handling unused pins

6–2 Input/output pins (hereafter called I/O pins) have functions as programmable I/O ports, internal peripheral devices’s I/O pins, external buses, etc. For the basic functions of each I/O pin, refer to section “1.3 Pin description.” For the I/O functions of the internal peripheral devices, refer to relevant sections of each internal peripheral device. For the external address bus, external data bus, bus control signals, etc., refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.” This chapter describes the programmable I/O ports and examples of handling unused pins. The programmable I/O ports have direction registers and port registers in the SFR area. Figure 6.2.1 shows the memory map of direction registers and port registers. 6.1 Overview, 6.2 Programmable I/O ports Fig. 6.2.1 Memory map of direction registers and port registers Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P10 direction register A16 B16 C 16 D 16 E16 F16 1016 1116 1216 1316 1416 Addresses Port P4 register Port P5 register Port P4 direction register Port P5 direction register 1516 1616 1716 1816

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6.2.1 Direction register

This register determines the I/O direction of programmable I/O ports. Each bit of this register corresponds one for one to each pin of the microcomputer. Figure 6.2.2 shows the structure of port Pi (i = 4 to 10) direction register. 0 : Input mode (The port functions as an input port) 1 : Output mode (The port functions as an output port) Port Pi5 direction bit Port Pi direction register (i = 4 to 10) (Addresses C16, D16, 1016, 1116, 1416, 1516, 1816) b1 b0b2b3b4b5b6b7 Port Pi1 direction bit Port Pi7 direction bit At reset RW RW RW RW RW RW RW RW RW Note: For bits 0 to 2 of the port P4 direction register, nothing is assigned and these bits are fixed to “0” at reading. Fig. 6.2.2 Structure of port Pi (i = 4 to 10) direction register

6–4

6.2.2 Port register

Data is input from or output to the external by writing/reading data to/from a port register. A port register consists of a port latch which holds the output data and a circuit which reads the pin state. Each bit of the port register corresponds one for one to each pin of the microcomputer. Figure 6.2.3 shows the structure of the port Pi (i = 4 to 10) register. l When outputting data from programmable I/O port set to output mode À By writing data to the corresponding bit of the port register, the data is written into the port latch. \ The data is output from the pin according to the contents of the port latch. By reading the port register of a port set to the output mode, the contents of the port latch is read out, instead of the pin state. Accordingly, the output data is correctly read without being affected by l When inputting data from programmable I/O port set to input mode À A pin which is set to the input mode enters the floating state. \ By reading the corresponding bit of the port register, the data which is input from the pin can be read out. By writing data to the port register of a programmable I/O port set to the input mode, the data is written only into the port latch and is not output to the external (Note). The pin remains floating. Note: When executing a read-modify-write instruction (CLB, SEB, INC, DEC, ASL, ASR, LSR, ROL, ROR ) to the port register of a programmable I/O port set to the input mode, the instruction is executed to the data which is input from the pin and the result is written into the port register. Fig. 6.2.3 Structure of port Pi (i = 4 to 10) register Bit Bit name Functions Port Pi0’s pin Port Pi2’s pin Port Pi3’s pin Port Pi4’s pin Port Pi6’s pin Data is input from or output to a pin by reading from or writing to the corresponding bit. Port Pi 5’s pin Port Pi register (i = 4 to 10) (Addresses A16, B16, E16, F16, 1216, 1316, 1616) b1 b0b2b3b4b5b6b7 Port Pi1’s pin Port Pi7’s pin At reset RW Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 : “L” level 1 : “H” level RW RW RW RW RW RW RW RW Note: For bits 0 to 2 of the port P4 register, nothing is assigned and these bits are fixed to “0” at reading.

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Fig. 6.2.4 Port peripheral circuits (1) Ports P43 to P46 [Inside dotted-line not included] Data bus Direction register Port latch Ports P83/TxD0, P87/TxD1, [Inside dotted-line not included] Ports P50/TA2OUT , P52/TA3OUT , P54/TA4OUT [Inside dotted-line included] Data bus /LiteDiagLines /LiteDiagLines /LiteDiagLines “1” Output Port latch Direction register P82/RxD0, P86/RxD1, Ports P47, P51/TA2 IN, P53/TA3IN, P55/TA4IN, P56/TB0IN, P57/TB1IN, [Inside dotted-line included] (There is no hysteresis for P82/RxD0 and P86/RxD1.) Ports P60/RTP00 to P67/RTP13 Data bus Direction register Port latch P91/DMAREQ0, P9 3/DMAREQ1, P95/DMAREQ2, P9 7/DMAREQ3, P100/INT0, P101/INT1, P102/INT2, P90/DMAACK0, P9 2/DMAACK1, P94/DMAACK2, P9 6/DMAACK3, P104/CAS, P105/RAS, P106/MA8, P107/MA9 (internal peripheral device) Latch TQ CKTimer underflow signal

6–6 Fig. 6.2.5 Port peripheral circuits (2) Ports P70/AN0 to P76/AN6 [Inside dotted-line not included] Data bus Direction register Port latch Ports P80/CTS0/RTS0, P81/CLK0, Data bus /LiteDiagLines /LiteDiagLines Output Port latch Direction register [Inside dotted-line included] Port P103/TC Data bus Direction register Port latch (internal peripheral device) Port P77/AN7/ADTRG Analog input P84/CTS1/RTS1, P85/CLK1 “0” “1” /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines “0” (TC) E output pin Output

7721 Group User’s Manual 6–7

When unusing an I/O pin, some handling is necessary for the pin. Examples of handling unused pins are described below. The following are just examples. The user shall modify them according to the user’s actual application and test them. Table 6.3.1 Examples of handling unused pins Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor; or set these pins to the output mode and leave them open (Notes 1 and 2). Leave them open. Connect these pins to Vcc via a resistor (pull-up) (Note 2). Connect this pin to Vcc or Vss. Connect this pin to Vcc. Connect these pins to Vss. Pin name P4 3 to P47, P5 to P10 BLE, BHE, ALE, φ1, ST0, ST1 X OUT (Note 3) HOLD, RDY CNVss AVcc AVss, VREF Fig. 6.3.1 Examples of handling unused pins P43–P47, P5–P10 M37721 ST0 ST1 BLE BHE ALE XOUT AV SS VREF HOLD RDY M37721 VCC VSS AV CC l When setting ports to input mode l When setting ports to output mode Left open Left open Left open AV SS VREF HOLD RDY VCC VSS AV CC Left open P43–P47, P5–P10 Left open ST0 ST1 BLE BHE ALE XOUT CNV SS ] CNV SS ] ] CNV SS can be connected to VCC , too. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. After reset, immediately set these ports to the output mode. Software reliability can be enhanced by setting the contents of the above ports’ direction registers periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: This applies when a clock externally generated is input to the XIN pin.

6–8 MEMORANDUM

7.1 Overview

7.2 Interrupt sources

7.3 Interrupt control

7.4 Interrupt priority level

7.5 Interrupt priority level detection circuit

7.6 Interrupt priority level detection time

7.7 Sequence from acceptance of interrupt

request until execution of interrupt routine

7.8 Return from interrupt routine

7.9 Multiple interrupts

____

7.10 External interrupts (INTi interrupt)

7.11 Precautions for interrupts

7–2 The M37721 provides 23 interrupt sources to generate interrupt requests. Figure 7.1.1 shows the interrupt processing sequence. When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set in the interrupt vector table (addresses FFCE16 to FFFF16). Set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table. Fig. 7.1.1 Interrupt processing sequence Interrupt routine Interrupt request is accepted. Processing is resumed. Processing is suspended. Returns to original routine. RTI instruction Interrupt processing Routine in progress Branches to start address of interrupt routine.

7721 Group User’s Manual 7–3

When an interrupt request is accepted, the following registers’ contents just before acceptance of an interrupt request are automatically pushed onto the stack area À → \ → ´ in that order. À Program bank register (PG) \ Program counter (PCL, PCH ) ´ Processor status register (PSL, PSH ) Figure 7.1.2 shows the state of the stack area just before entering the interrupt routine. Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer was executing before the interrupt request was accepted. By executing the RTI instruction, the register contents pushed onto the stack area are pulled ´ → \` → À in that order. Then, the suspended processing is resumed from where it left off. [S] is an initial address that the stack pointer (S) indicates when an interrupt request is accepted. The S’s contents become “[S] – 5” after all of the above registers are pushed. Address [S] – 4 [S] – 3 [S] – 2 [S] – 1 [S]] Processor status register’s low-order byte (PSL) Stack area [S] – 5 Processor status register’s high-order byte (PSH ) Program counter’s low-order byte (PCL) Program counter’s high-order byte (PCH ) Program bank register (PG) Fig. 7.1.2 State of stack area just before entering interrupt routine

7–4 Remarks Non-maskable Non-maskable software interrupt Non-maskable software interrupt Do not use. Non-maskable interrupt Maskable external interrupts Maskable internal interrupts Maskable internal interrupts Maskable internal interrupts Maskable internal interrupt Maskable internal interrupts Table 7.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start address of each interrupt routine at the vector addresses listed in this table. Interrupt vector addresses Table 7.2.1 Interrupt sources and interrupt vector addresses High-order address FFFF 16 FFFD 16 FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 FFDB 16 FFD9 16 FFD7 16 FFD5 16 FFD3 16 FFD1 16 FFCF 16 Interrupt source Reset Zero division BRK instruction ____ DBC (Note) Watchdog timer ____ INT0 ____ INT1 ____ INT2 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 receive UART0 transmit UART1 receive UART1 transmit A-D conversion DMA0 DMA1 DMA2 DMA3 ____ Note: The DBC interrupt is used exclusively for debugger control. l Maskable interrupt: An interrupt of which request’s acceptance can be disabled by software. l Non-maskable interrupt (including Zero division, BRK instruction, Watchdog timer interrupts): An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their interrupt control registers and are not affected by the interrupt disable flag (I). Reference 4. RESET

7700 Family Software

WATCHDOG TIMER

7.10 External interrupts

____ (INTi interrupt) 8. TIMER A 9. TIMER B 11. SERIAL I/O 12. A-D CONVERTER 13. DMA CONTROLLER

7721 Group User’s Manual 7–5

The maskable interrupts are controlled by the following :

Interrupt request bit
Interrupt priority level select bits
Processor interrupt priority level (IPL)
Interrupt disable flag (I) Figure 7.3.1 shows the memory assignment of the interrupt control registers, and Figure 7.3.2 shows their structures. Assigned to the interrupt control register of each interrupt. Assigned to the processor status register (PS).

Fig. 7.3.1 Memory assignment of interrupt control registers DMA3 interrupt control register6F16 UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT 0 interrupt control register INT1 interrupt control register INT2 interrupt control register Address A-D conversion interrupt control register7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 DMA2 interrupt control register6E16 DMA1 interrupt control register6D 16 DMA0 interrupt control register6C 16

7–6 Fig. 7.3.2 Structures of interrupt control register Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected. 0 : Interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1 : Interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when edge sense is selected. 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit Interrupt request bit (Note) Bit name At reset RWFunctions b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW RW0 Polarity select bit 0 : Edge sense 1 : Level sense 7, 6 5 RW Undefined Level sense/Edge sense select bit Nothing is assigned. DMA0 to DMA3, A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 6C16 to 7C16) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned.

7721 Group User’s Manual 7–7

7.3.1 Interrupt disable flag (I)

All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts are disabled; when this flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1” at reset, clear this flag to “0” when enabling interrupts.

7.3.2 Interrupt request bit

When an interrupt request occurs, this bit is set to “1.” This bit remains set to “1” until the interrupt request is accepted; it is cleared to “0” when the interrupt request is accepted. This bit can also be set to “0” or “1” by software. The INTi interrupt request bit (i = 0 to 2) is ignored when the INTi interrupt is used with level sense.

7.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL)

The interrupt priority level select bits are used to determine the priority level of each interrupt. When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition. Accordingly, an interrupt can be disabled by setting its interrupt priority level to 0. Each interrupt priority level > Processor interrupt priority level (IPL) Table 7.3.1 lists the setting of interrupt priority level, and Table 7.3.2 lists the interrupt enabled level corresponding to IPL contents. The interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor interrupt priority level (IPL) are independent of one another; they do not affect one another. Interrupt requests are accepted only when the following conditions are satisfied.

Interrupt disable flag (I) = “0”
Interrupt request bit = “1”
Interrupt priority level > Processor interrupt priority level (IPL)

7–8 Table 7.3.1 Setting of interrupt priority level Level 0 (Interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High Interrupt priority levelInterrupt priority level select bits Priority IPL2 Enabled interrupt priority level Enable level 1 and above interrupts. Enable level 2 and above interrupts. Enable level 3 and above interrupts. Enable level 4 and above interrupts. Enable level 5 and above interrupts. Enable level 6 and level 7 interrupts. Enable only level 7 interrupt. Disable all maskable interrupts. IPL IPL Table 7.3.2 Interrupt enabled level corresponding to IPL contents IPL0: Bit 8 in processor status register (PS) IPL1: Bit 9 in processor status register (PS) IPL2: Bit 10 in processor status register (PS)

7721 Group User’s Manual 7–9

When the interrupt disable flag (I) = “0” (interrupts enabled) and more than one interrupt request is detected at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they are accepted in order of priority levels. In other words, the interrupt request with the highest priority level is accepted first. Among a total of 23 interrupt sources, the user can set the desired priority levels for 20 interrupt sources except software interrupts (zero division and BRK instruction interrupts) and the watchdog timer interrupt. Use the interrupt priority level select bits to set their priority levels. Priority levels of reset, which is handled as the interrupt request with the highest priority, and the watchdog timer interrupt are set by hardware. Figure 7.4.1 shows the interrupt priority set by hardware. Note that software interrupts are not affected by the interrupt priority levels. Whenever the instruction is executed, a program certainly branches to the interrupt routine. 20 interrupt sources except software interrupts and watchdog timer interrupt The user can set the desired priority levels inside of the dotted line. Priority levels determined by hardware HighLow Priority level Fig. 7.4.1 Interrupt priority level set by hardware

7–10

7.5 Interrupt priority level detection circuit

The interrupt priority level detection circuit selects the interrupt with the highest priority level when more than one interrupt request occurs at the same sampling timing. Figure 7.5.1 shows the interrupt priority level detection circuit. Fig. 7.5.1 Interrupt priority level detection circuit Interrupt with the highest priority level Interrupt priority level Level 0 (initial value) A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2 INT1 INT0 IPL Processor interrupt priority level Interrupt disable flag (I) Watchdog timer interrupt Reset Accepting of interrupt request Interrupt priority level DMA1 DMA3 DMA2 DMA0

7721 Group User’s Manual 7–11

The following explains the operation of the interrupt priority detection circuit using Figure 7.5.2. The interrupt priority level of a requested interrupt (Y in Figure 7.5.2) is compared with the resultant priority level which is sent from the preceding comparator (X in Figure 7.5.2); the interrupt with the higher priority level is sent to the next comparator (Z in Figure 7.5.2). (Initial comparison value of “X” is “0.”) For an interrupt which is not requested, the comparison is not performed and the priority level which is sent from the preceding comparator is forwarded to the next comparator as it is. When the two priority levels are found the same by comparison, the priority level which is sent from the preceding comparator is forwarded to the next comparator. Accordingly, when the same priority level is set by software, the interrupt priority levels are handled as follows: DMA3 > DMA2 > DMA1 > DMA0 > A-D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0 receive > Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 > INT2 > INT1 > INT0 Among the multiple interrupt requests sampled at the same time, one request with the highest priority level is detected by the above comparison. Then, this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable flag (I) is “0,” the interrupt request is accepted. A interrupt request which is not accepted here is held until it is accepted or its interrupt request bit is cleared to “0” by software. The interrupt priority is detected when the CPU fetches an op code, which is called the CPU’s op-code fetch cycle. However, when an op-code fetch cycle starts during detection of an interrupt priority, a new interrupt priority detection does not start. (Refer to “Figure 7.6.1.”) Since the state of the interrupt request bit and interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt priority detection is performed for the previous state before the change occurred. The interrupt priority level is detected when the CPU fetches an op code. Therefore, in the following execution or states, after the execution or state is terminated, no interrupt request is accepted until the CPU fetches the op code of the next instruction.

Execution of an instruction which requires many cycles, such as the MVN or MVP instruction
During DRAM refreshment
During Hold state
During DMA transfer

Y X Z Comparator (Priority level comparison) l When X Y then Z = X l When X Y then Z = Y Interrupt source Y X : Priority level sent from the preceding comparator (Highest priority at this point) Y : Priority level of interrupt source Y Z : Highest priority at this point Time Fig. 7.5.2 Interrupt priority level detection model

7–12 When the interrupt priority level detection time has passed after sampling starts, an interrupt request is accepted. The interrupt priority level detection time can be selected by software. Figure 7.6.1 shows the interrupt priority level detection time. Usually, select “2 cycles of φ” as the interrupt priority level detection time. (2) Interrupt priority level detection time Op-code fetch cycle Sampling pulse (a) 7 cycles (b) 4 cycles (c) 2 cycles Interrupt priority level detection time (Note) Note: The pulse resides when “2 cycles of ” is selected. b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 1 1 0 1 1 Processor mode register 0 (Address 5E 16) Processor mode bits Software reset bit Must be fixed to “0.” Clock 1 output select bit 7 cycles of [(a) shown below] 4 cycles of [(b) shown below] 2 cycles of [(c) shown below] Interrupt priority detection time select bits Do not select. (1) Interrupt priority detection time select bits b5, b4 Wait bit Fig. 7.6.1 Interrupt priority level detection time

7–13

7.7 Sequence from acceptance of interrupt request until execution of interrupt routine

The sequence from the acceptance of interrupt request until the execution of the interrupt routine is described below. When an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to “0.” And then, the interrupt processing starts from the cycle just after the completion of the instruction which was executed at accepting the interrupt request. Figure 7.7.1 shows the sequence from acceptance of interrupt request to execution of interrupt routine. After execution of an instruction at accepting the interrupt request is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine allocated in addresses 0 16 to FFFF16. The INTACK sequence is automatically performed in the following order. À The contents of the program bank register (PG) just before performing the INTACK sequence are pushed onto stack. \` The contents of the program counter (PC) just before performing the INTACK sequence are pushed onto stack. ´ The contents of the processor status register (PS) just before performing the INTACK sequence is pushed onto stack. ˆ The interrupt disable flag (I) is set to “1.” ˜ The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL). ¯ The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt vector address are set into the program counter (PC). Performing the INTACK sequence requires at least 13 cycles of internal clock φ. Figure 7.7.2 shows the INTACK sequence timing. After the INTACK sequence is completed, the instruction execution starts from the start address of the interrupt routine. @ : Interrupt priority level detection time Interrupt request occurs. Interrupt request is accepted. Instruction Instruction INTACK sequence Instructions in interrupt routine Interrupt response time Time@ À Time from the occurrence of an interrupt request until the instruction execution which is in progress at that time is completed. \ Time from when execution of an instruction next to À begins (Note) until the instruction execution which is in progress at completion of interrupt priority level detection. Note: At this time, detection of interrupt priority level begins. ´ Time required to execute the INTACK sequence (13 cycles of at minimum) À \ ´ Fig. 7.7.1 Sequence from acceptance of interrupt request until execution of interrupt routine

7–14 Fig. 7.7.2 INTACK sequence timing (at minimum) [S]H l When stack pointer (S)’s contents are even and no Wait PG PC H 00 00 00 00 00 00 00 00 ([S]–1)H FF16 AD HPC H PS HFF16D H AP AH Interrupt disable flag (I) Internal clock CPU PCLPG PS LXX 16D L AD H AD L PC L 00 XX16AL AD L [S]L INTACK sequence Op-code Op-code : Not used [S] XX 16 AD H AD L : Contents of stack pointer (S) : Low-order 8 bits of vector address : Contents of vector address (High-order address) : Contents of vector address (Low-order address) CPU AP AH AL DH D L : CPU standard clock : High-order 8 bits of CPU internal address bus : Middle-order 8 bits of CPU internal address bus : Low-order 8 bits of CPU internal address bus : CPU internal data bus for odd address : CPU internal data bus for even address

7.7.1 Change in IPL at acceptance of interrupt request

When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple interrupts. (Refer to section “7.9 Multiple interrupts.”) At reset or when a watchdog timer interrupt or a software interrupt is accepted, a value listed in Table 7.7.1 is set into the IPL. Table 7.7.1 Change in IPL at acceptance of interrupt request Interrupts Reset Watchdog timer Zero division BRK instruction Other interrupts Change in IPL Level 0 (“0002”) is set. Level 7 (“1112”) is set. Not changed. Not changed. Accepted interrupt priority level is set.

7–15

7.7.2 Push operation for registers

The push operation for registers performed in the INTACK sequence depends on whether the contents of the stack pointer (S) at acceptance of an interrupt request are even or odd. When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the processor status register (PS) are simultaneously pushed in a unit of 16 bits. When the contents of the stack pointer (S) are odd, each of these registers is pushed in a unit of 8 bits. Figure 7.7.3 shows the push operation for registers. In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and processor status register (PS) are pushed onto the stack area. The other necessary registers must be pushed by software at the start of the interrupt routine. By using the PSH instruction, all CPU registers except the stack pointer (S) can be pushed. Fig. 7.7.3 Push operation for registers Pushed in 3 times. ´ Pushed in a unit of 16 bits. À \` Pushed in a unit of 16 bits. (1) When contents of stack pointer (S) are even Low-order byte of processor status register (PSL) Program bank register (PG) Address [S] – 4 (even) [S] – 3 (odd) [S] – 2 (even) [S] – 1 (odd) [S] (even) Order for push[S] – 5 (odd) Address [S] – 4 (odd) [S] – 3 (even) [S] – 2 (odd) [S] – 1 (even) [S] (odd) À ˆ Pushed in a unit of 8 bits. Order for push Pushed in 5 times. [S] – 5 (even) High-order byte of processor status register (PSH ) Low-order byte of program counter (PCL) High-order byte of program counter (PCH ) (2) When contents of stack pointer (S) are odd Low-order byte of processor status register (PSL) Program bank register (PG) High-order byte of processor status register (PSH ) Low-order byte of program counter (PCL) High-order byte of program counter (PCH ) ] [S] is an initial address that the stack pointer (S) indicates when an interrupt request is accepted. The S’s contents become “[S] – 5” after all of the above registers are pushed.

7–16 When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack area just before the INTACK sequence, are automatically pulled. After this, the control returns to the original routine. And then, the suspended processing, which was in progress before the acceptance of the interrupt request, is resumed. Before the RTI instruction is executed, pull registers which were pushed by software in the interrupt routine, using the PUL instruction, etc. Just after a branch is made to an interrupt routine, the following occur:

Interrupt disable flag (I) = “1” (Interrupts are disabled)
Interrupt request bit of accepted interrupt = “0”
Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt Accordingly, as long as the IPL remains unchanged, an interrupt request whose priority level is higher than that of the interrupt which is in progress can be accepted by clearing the interrupt disable flag (I) to “0” in an interrupt routine. In this way, multiple interrupts are processed. Figure 7.9.1 shows the processing for multiple interrupts. An interrupt request which has not been accepted because its priority level is lower is held. When the RTI instruction is executed, the interrupt priority level of the routine which was in progress at acceptance of an interrupt request is pulled into the IPL. Therefore, if the following relationship is satisfied when interrupt priority level detection is performed next, the held interrupt request is accepted. Held interrupt request’s priority level > Processor interrupt priority level (IPL) 7.8 Return from interrupt routine, 7.9 Multiple interrupts

7–17 Fig. 7.9.1 Processing for multiple interrupts Main routineReset I = 1 IPL = 0 I = 0 Interrupt 1 I = 1 IPL = 3 I = 0 I = 1 IPL = 5 RTI I = 0 IPL = 3 RTI I = 0 IPL = 0 I = 1 IPL = 2 RTI I = 0 IPL = 0 Interrupt 1 Interrupt priority level=3 This request cannot be accepted because its priority level is lower than the interrupt 1’s one. Interrupt request generated Nesting Time : They are automatically set. : They must be set by software. I : Interrupt disable flag IPL : Processor interrupt priority level Multiple interruptsInterrupt 2 Interrupt priority level=5 Interrupt 3 Interrupt priority level=2 Interrupt 2 Interrupt 3 Interrupt 3 The instruction in the main routine is not executed.

7–18 ____ ____ An external interrupt request occurs by an input signal to the INTi (i = 0 to 2) pin. The occurrence factor of the interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit When using P10 0/INT0 to P102/INT2 pins as input pins of external interrupts, set the corresponding bits at address 1816 (port P10 direction register) to “0.” (Refer to “Figure 7.10.2.”)____ The signals input to the INTi pin require “H”- or “L”- level width of 250 ns or more, independent of f(XIN).____ ____ Additionally, even when using the pins P100/INT0 to P102/INT2 as the input pins of external interrupts, the user can obtain the pin’s state by reading bits 0 to 2 at address 1616 (port P10 register). Note: When selecting an input signal’s falling or “L” level as the occurrence factor of an interrupt request, make sure that the input signal is held “L” for 250 ns or more. When selecting an input signal’s rising or “H” level as that, make sure that the input signal is held “H” for 250 ns or more. ___ ___ Table 7.10.1 Occurrence factor of INTi interrupt request ___ INTi interrupt request occurrence factor The INTi interrupt request occurs by detecting the state of pin INTi all the time. Therefore, when the user___ ___ does not use the INTi interrupt, set the INTi interrupt’s priority level to level 0. ___ Interrupt request occurs at the falling edge of a signal input to pin INTi (Edge sense). ___ Interrupt request occurs at the rising edge of a signal input to pin INTi (Edge sense). ___ Interrupt request occurs when pin INTi is at “H” level (Level sense). ___ Interrupt request occurs when pin INTi is at “L” level (Level sense).

7–19 ___ Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected. 0 : Interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1 : Interrupt request bit is set to “1” at “L” at level when level sense is selected; this bit is set to “1” at rising edge when edge sense is selected. 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit Interrupt request bit (Note) Bit name At reset RWFunctions b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW RW0 Polarity select bit 0 : Edge sense 1 : Level sense 7, 6 5 RW Undefined Level sense/Edge sense select bit Nothing is assigned. ___ Fig. 7.10.1 Structure of INTi (i=0 to 2) interrupt control register Bit Corresponding pin Functions INT0 pin MA 8 pin Port P10 direction register (Address 1816) b1 b0b2b3b4b5b6b7 At reset RW RW RW RW RW RW RW RW RW 0 : Input mode 1 : Output mode When using a pin as an input pin for an external interrupt,clear the corresponding bit to “0.” : Bits 3 to 7 are not used for external interrupts. INT1 pin INT2 pin TC pin CAS pin RAS pin MA 9 pin Fig. 7.10.2 Relationship between port P10 direction register and input pins of external interrupt

7–20 ___ ____

7.10.1 Functions of INTi interrupt request bit

(1) Functions when edge sense is selected The interrupt request bit has the same functions as that of an internal interrupt. That is, when an interrupt request occurs, the interrupt request bit is set to “1” and retains this state until the interrupt request is accepted. When this bit is cleared to “0” by software, the interrupt request is cancelled; when this bit is set to “1” by software, the interrupt request can be generated. (2) Functions when level sense is selected ___ The INTi interrupt request bit is ignored. ___ ___ Interrupt requests continuously occur while the level of the INTi pin is the valid level] 1; when the INTi___ pin’s level changes from the valid level to the invalid level] 2 before the INTi interrupt request is accepted, this interrupt request is not retained. (Refer to “Figure 7.10.4.”) Valid level] 1: This means the level selected by the polarity select bit (bit 4 at addresses 7D16 to 7F16) Invalid level] 2: This means the reversed level of “valid level” INTi pin Edge detection circuit Interrupt request Level sense/Edge sense select bit Data busInterrupt request bit “0” “1” ___ Fig. 7.10.3 INTi Interrupt request First interrupt routine INTi pin level Valid Invalid Main routine Interrupt request is accepted. Return to main routine. Second interrupt routine Third interrupt routine Main routine When the INTi pin’s level changes to the invalid level before an interrupt request is accepted, the interrupt request is not retained. ____ Fig. 7.10.4 Occurrence of INTi interrupt request when level sense is selected

7–21 ___ ___

7.10.2 Switching of INTi interrupt request occurrence factor___

When the INTi interrupt request occurrence factor is switched in one of the following ways, the interrupt request bit may be set to “1”:

Switching the level sense to the edge sense
Switching polarity Therefore, after this switching, make sure to clear the interrupt request bit to “0.” Figure 7.10.5 shows an ____ example of the switching procedure for the INTi interrupt request occurrence factor. Clear the level sense/edge sense select bit to “0.” ( Edge sense is selected. ) Clear the interrupt request bit to “0.” Set the polarity select bit. Clear the interrupt request bit to “0.” (2) Switching polarity(1) Switching level sense to edge sense Set the interrupt priority level to one of levels 1–7 or clear the interrupt disable flag (I) to “0.” (INTi interrupt request is acceptable.) Set the interrupt priority level to level 0 or set the interrupt disable flag (I) to “1.” (INTi interrupt is disabled. ) Note: The above settings must be done separately. Multiple settings must not be done at the same time, in other words, they must not be done only by 1 instruction. Set the interrupt priority level to level 0 or set the interrupt disable flag (I) to “1.” (INTi interrupt is disabled. ) Set the interrupt priority level to one of levels 1–7 or clear the interrupt disable flag (I) to “0.” (INTi interrupt request is acceptable.) ___ Fig. 7.10.5 Example of switching procedure for INTi interrupt request occurrence factor

7–22 Fig. 7.11.1 Program example to reserve time required for change of interrupt priority level Table 7.11.1 Correspondence between number of instructions to be inserted in Figure 7.11.1 and interrupt priority detection time select bits When changing the interrupt priority level select bits (bits 0 to 2 at addresses 6C16 to 7F16), 2 to 7 cycles of φ are required until the interrupt priority level is changed. Therefore, when the interrupt priority level of a certain interrupt source is repeatedly changed in a very short time, which consists of a few instructions, it is necessary to reserve the time required for the change by software. Figure 7.11.1 shows a program example to reserve the time required for the change. Note that the time required for the change depends on the contents of the interrupt priority detection time select bits (bits 4 and 5 at address 5E16). Table 7.11.1 lists the correspondence between the number of instructions inserted in Figure 7.11.1 and the interrupt priority detection time select bits. Interrupt priority detection time select bits (Note) Interrupt priority level detection time 7 cycles of φ 4 cycles of φ 2 cycles of φ Do not select. Number of inserted NOP instructions 4 or more 2 or more 1 or more Note: We recommend [b5 = “1”, b4 = “0”]. ; Write instruction for the interrupt priority level select bits ; Inserted NOP instruction (Note) ; Write instruction for the interrupt priority level select bits Note: Except the write instruction for address XX , any instruction which has the same cycles as the NOP instruction can also be inserted. For the number of inserted NOP instructions, refer to “Table 7.11.1.” XX: any of 6C to 7F LDM.B #0XH, 00XXH NOP NOP NOP LDM.B #0XH, 00XXH

8.1 Overview

8.2 Block description

8.3 Timer mode

[Precautions for timer mode]

8.4 Event counter mode

[Precautions for event counter mode]

8.5 One-shot pulse mode

[Precautions for one-shot pulse mode] 8.6 Pulse width modulation (PWM) mode [Precautions for pulse width modulation (PWM) mode]

8–2 Timer A consists of five counters, Timers A0 to A4, each equipped with a 16-bit reload function. Timers A0 to A4 operate independently of one another. Timer A has four operating modes listed below. Timers A0 and A1 operate in the timer mode only. Timers A2 to A4 have selective four operating modes listed below. (1) Timer mode (Timers A0 to A4) The timer counts an internally generated count source. For Timers A2 to A4, the following functions can be used in this mode:

Gate function
Pulse output function (2) Event counter mode (Timers A2 to A4) The timer counts an external signal. The following functions can be used in this mode:
Pulse output function
Two-phase pulse signal processing function (3) One-shot pulse mode (Timers A2 to A4) The timer outputs a pulse which has an arbitrary width once. (4) Pulse width modulation (PWM) mode (Timers A2 to A4) Timer outputs pulses which have an arbitrary width in succession. The counter functions as one of the following pulse width modulators:
16-bit pulse width modulator
8-bit pulse width modulator In this chapter, Timer Ai (i = 0 to 4) indicates Timers A0 to A4. Timer Aj (j = 2 to 4) indicates Timers A2 to A4; this is applies when the timer A’s input/output pins are used etc. (Hereafter, input/output pins are called I/O pins.)

7721 Group User’s Manual 8–3

Figure 8.2.1 shows the block diagram of Timer A. Explanation of registers relevant to Timer A is described below. Data bus (odd) Data bus (even) f 2 f 16 f 64 f 512 Count source select bits Timer mode One-shot pulse mode PWM mode Polarity switching Timer mode (Gate function) Event counter mode Trigger Count start bit Countdown Up-down bit (Low-order 8 bits) (High-order 8 bits) Timer Ai reload register (16) Timer Ai counter (16) Timer Ai interrupt request bit Countup/Countdown switching (Always “count down” except for event counter mode) Toggle F.F. Pulse output function select bit TAj IN TAj OUT i = 0–4, j = 2–4 Fig. 8.2.1 Block diagram of Timer A

7721 Group User’s Manual8–4

8.2.1 Counter and reload register (timer Ai register)

Each of timer Ai counter and reload register consists of 16 bits. Countdown in the counter is performed each time the count source is input. In the event counter mode, it can also function as an up-counter. The reload register is used to store the initial value of the counter. When a counter underflow or overflow occurs, the reload register’s contents are reloaded into the counter. A value is set to the counter and reload register by writing the value to the timer Ai register. Table 8.2.1 lists the memory assignment of the timer Ai register. The value written into the timer Ai register while counting is not in progress is set to the counter and reload register. The value written into the timer Ai register while counting is in progress is set only to the reload register. In this case, the reload register’s updated contents are transferred to the counter at the next reload time. The value obtained when reading out the timer Ai register varies according to the operating mode. Table 8.2.2 lists reading from and writing to the timer Ai register. Table 8.2.2 Reading from and writing to timer Ai register Write <While counting> Written only to reload register. <While not counting> Written to both of the counter and reload register. Operating mode Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode Note: At reset, the contents of the timer Ai register are undefined. Notes 1:Also refer to “[Precautions for timer mode]” and “[Precautions for event counter mode].” 2:When reading from and writing to the timer Ai register, perform it in a unit of 16 bits. Read Counter value is read out. (Note 1) Undefined value is read out. Table 8.2.1 Memory assignment of timer Ai register Timer Ai register High-order byte Low-order byte Timer A0 register Address 4716 Address 4616 Timer A1 register Address 4916 Address 4816 Timer A2 register Address 4B16 Address 4A16 Timer A3 register Address 4D16 Address 4C16 Timer A4 register Address 4F16 Address 4E16

7721 Group User’s Manual 8–5

8.2.2 Count start register

This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure 8.2.2 shows the structure of the count start register. Fig. 8.2.2 Structure of count start register Bit Timer B2 count start bit Timer B1 count start bit Timer B0 count start bit Timer A4 count start bit Timer A3 count start bit Timer A2 count start bit Timer A1 count start bit Timer A0 count start bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) 0 : Stop counting 1 : Start counting RW RW RW RW RW RW RW RW : Bits 5 to 7 are not used for Timer A.

7721 Group User’s Manual8–6

8.2.3 Timer Ai mode register

Figure 8.2.3 shows the structure of the timer Ai mode register. The operating mode select bits are used to select the operating mode of Timer Ai. Bits 2 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. Fig. 8.2.3 Structure of timer Ai mode register Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot pulse mode 1 1 : Pulse width modulation (PWM) mode b1 b0 These bits have different functions according to the operating mode. Operating mode select bits 0 RW RW RW RW RW RW RW RW

7721 Group User’s Manual 8–7

8.2.4 Timer Ai interrupt control register

Figure 8.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to “CHAPTER 7. INTERRUPTS.” Fig. 8.2.4 Structure of timer Ai interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select a timer Ai interrupt’s priority level. When using timer Ai interrupts, select one of the priority levels (1 to 7). When a timer Ai interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable timer Ai interrupts, set these bits to “000 2” (level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when a timer Ai interrupt request occurs. This bit is automatically cleared to “0” when the timer Ai interrupt request is accepted. This bit can be set to “1” or cleared to “0” by software. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned. Low level High level

7721 Group User’s Manual8–8

8.2.5 Port P5 direction register

The I/O pins of Timers A2 to A4 are multiplexed with port P5. When using these pins as Timer Aj’s input pins, set the corresponding bits of the port P5 direction register to “0” to set these port pins for the input mode. When used as Timer Aj’s output pins, these pins are forcibly set to the output pins of Timer Aj regardless of the direction registers’s contents. Figure 8.2.5 shows the relationship between the port P5 direction register and the Timer Aj’s I/O pins. Bit Bit name Functions TA2 OUT pin TA3 OUT pin TA3 IN pin 0 : Input mode 1 : Output mode When using these pins as Timer Aj’ s input pins, set the corresponding bits to “0.” Port P5 direction register (Address D16) b1 b0b2b3b4b5b6b7 TA2 IN pin At reset RW RW RW RW RW RW RW RW RW : Bits 6 and 7 are not used for Timer A. TA4 OUT pin TB0 IN pin TB1 IN pin TA4 IN pin Fig. 8.2.5 Relationship between port P5 direction register and Timer Aj’s I/O pins

7721 Group User’s Manual 8–9

shows the structures of the timer Ai mode register and timer Ai register in the timer mode. Table 8.3.1 Specifications of timer mode (n + 1) Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing TAj IN pin’s function TAjOUT pin’s function Read from timer Ai register Write to timer Ai register Specifications f2, f16, f64, or f512

Countdown
When a counter underflow occurs, reload register’s contents are reloaded, and counting continues. When the count start bit is set to “1.” When the count start bit is cleared to “0.” When a counter underflow occurs. Programmable I/O port or gate input Programmable I/O port or pulse output Counter value can be read out. l While counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. l While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) n : Timer Ai register’s set value

7721 Group User’s Manual8–10

(b15) (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 These bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Undefined RW Note: Read from or write to this register in a unit of 16 bits. Gate function select bits Pulse output function select bit Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) 0 0 : Timer mode 0 : No pulse output (TAjOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAjOUT pin functions as a pulse output pin.) 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b4 b3 0 0 : No gate function 0 1 : (TAjIN pin functions as a prog- rammable I/O port.) 1 0 : Counter counts only while TAjIN pin’s input signal is at “L” level. 1 1 : Counter counts only while TAjIN pin’s input signal is at “H” level. Bit At reset RW 0 RW 0 RW 0 RW 3 0 RW 0 RW 5 0 RW 0 RW 0 RW Fix this bit to “0” in timer mode. Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Timer A0 mode register (Address 5616) Timer A1 mode register (Address 5716) Fix these bits to “0.” 0 RW RW RW RW RW RW 00 0000 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits6 0 RW 0 RW Fig. 8.3.1 Structures of timer Ai mode register and timer Ai register in timer mode

7721 Group User’s Manual 8–11

8.3.1 Setting for timer mode

Note that when using interrupts, set up to enable the interrupts. For details, refer to section “CHAPTER 7. INTERRUPTS.” Fig. 8.3.2 Initial setting example for registers relevant to timer mode (1) Note: The counter divides the count source frequency by (n + 1). Setting division ratio b7 b0 Can be set to “000016” to “FFFF16” (n). (b15) (b8) b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Continue to Figure 8.3.3 on next page. b7 b0 Pulse output function select bit 0: No pulse output. 1: Pulses output. Selecting timer mode and each function Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Count source select bits 0 0: f2 0 1: f16 1 0: f64 1 1: f512 b7 b6 Gate function select bits 0 0: 0 1: 1 0: Gate function (Counter counts only while TAjIN pin’s input signal is at “L” level.) 1 1: Gate function (Counter counts only while TAjIN pin’s input signal is at “H” level.) b4 b3 Selection of timer mode No gate function Note: For Timers A0 and A1, set bits 0 to 5 to “0.”

7721 Group User’s Manual8–12

/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Count starts Setting count start bit to “1.” b7 b0 Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. From preceding Figure 8.3.2. Setting port P5 direction register b7 b0 Port P5 direction register (Address D16) TA2 IN pin TA3 IN pin TA4 IN pin When gate function is selected, set the bit corresponding to the TAjIN pin to “0.” Fig. 8.3.3 Initial setting example for registers relevant to timer mode (2)

7721 Group User’s Manual 8–13

8.3.2 Count source

In the timer mode, the count source select bits (bits 6 and 7 at addresses 5616 to 5A16) select the count source. Table 8.3.2 lists the count source frequency. Table 8.3.2 Count source frequency Count source select bits Count source f16 f64 f512 f(XIN) = 8 MHz

4 MHz

f(X IN) = 25 MHz

12.5 MHz

1.5625 MHz

390.625 kHz 48.8281 kHz f(XIN) = 16 MHz

8 MHz

1 MHz

7721 Group User’s Manual8–14

8.3.3 Operation in timer mode

À When the count start bit is set to “1,” the counter starts counting of the count source. \ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues. ´ The timer Ai interrupt request bit is set to “1” at the underflow in \ . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 8.3.4 shows an example of operation in the timer mode. Stops counting. Restarts counting. FFFF 16 n 000016 Time Count start bit Timer Ai interrupt request bit Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. 1 / fi 5 (n+1) fi = frequency of count source 2, f16, f64, f512) Cleared to “0” by software.Set to “1” by software. Fig. 8.3.4 Example of operation in timer mode (without pulse output and gate functions)

7721 Group User’s Manual 8–15

8.3.4 Selectable functions

The following describes the selectable gate function for Timers A2 to A4 and pulse output function. (1) Gate function The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 5816 to 5A16 ) to “102” or “112.” The gate function makes it possible to start or stop counting depending on of operation with the gate function selected. When selecting the gate function, set the port P5 direction registers’ bits which correspond to the TAj IN pin for the input mode. Additionally, make sure that the TAjIN pin’s input signal has a pulse width equal to or more than two cycles of the count source. Table 8.3.3 Count valid levels Gate function select bits Count valid level (Duration while counter counts) While TAjIN pin’s input signal is at “L” level While TAjIN pin’s input signal is at “H” level Note:The counter does not count while the TAjIN pin’s input signal is not at the count valid level. Fig. 8.3.5 Example of operation selecting gate function FFFF 16 n 000016 Time À Starts counting. n = Reload register’s contents Counter contents (Hex.) \ Stops counting. Set to “1” by software. Count start bit TAjIN pin’s input signal Count valid level Timer Aj interrupt request bit Cleared to “0” when interrupt request is accepted or cleared by software. À The counter counts when the count start bit = “1” and the TAj IN pin’s input signal is at the count valid level. \ The counter stops counting while the TAjIN pin’s input signal is not at the count valid level, and the counter value is retained. Invalid level

7721 Group User’s Manual8–16

(2) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 5816 to 5A16) to “1.” When this function is selected, the TAjOUT pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 direction register. The TAjOUT pin outputs pulses of which polarity is inverted each time a counter underflow occurs. When the count start bit (address 4016) is “0” (count stopped), the TAjOUT pin outputs “L” level. Figure 8.3.6 shows an example of operation with the pulse output function selected. Fig. 8.3.6 Example of operation selecting pulse output function FFFF 16 n 000016 Time Count start bit Timer Aj interrupt request bit Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Pulse output from TAjOUT pin Set to “1” by software.Cleared to “0” by software. Starts counting. Restarts counting.

7721 Group User’s Manual 8–17

[Precautions for timer mode] By reading the timer Ai register, the counter value can be read out at any timing. However, if the timer Ai register is read at the reload timing shown in Figure 8.3.7, the value “FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. Fig. 8.3.7 Reading timer Ai register 210 n n – 1Counter value (Hex.) 21 0 FFFF n – 1Read value (Hex.) Reload Timen = Reload register’s contents

7721 Group User’s Manual8–18

be used in this mode. Figure 8.4.1 shows the structures of the timer Aj mode register and timer Aj register in the event counter mode. Table 8.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing function) Specifications l External signal input to the TAjIN pin l The count source’s valid edge can be selected from the falling edge and the rising edge by software. l Countup or countdown can be switched by external signal or software. l When a counter overflow or underflow occurs, reload register’s contents are reloaded, and counting continues. l For countdown l For countup When the count start bit is set to “1.” When the count start bit is cleared to “0.” When a counter overflow or underflow occurs. Count source input Programmable I/O port, pulse output, or countup/countdown switch signal input Counter value can be read out. l While counting is stopped When a value is written to the timer Aj register, it is written to both of the reload register and counter. l While counting is in progress When a value is written to the timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing TAj IN pin’s function TAjOUT pin’s function Read from timer Aj register Write to timer Aj register (n + 1) (FFFF 16 – n + 1) n : Timer Aj register’s set value

7721 Group User’s Manual 8–19

Table 8.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function) Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing TAj IN, TAjOUT pin function Read from timer Aj register Write to timer Aj register (n + 1) Specifications External signal (two-phase pulse) input to the TAjIN or TAjOUT pin l Countup or countdown can be switched by external signal (two- phase pulse). l When a counter overflow or underflow occurs, reload register’s contents are reloaded, and counting continues. l For countdown l For countup When the count start bit is set to “1.” When the count start bit is cleared to “0.” When a counter overflow or underflow occurs. Two-phase pulse input Counter value can be read out. l While counting is stopped When a value is written to the timer Aj register, it is written to both of the reload register and counter. l While counting is in progress When a value is written to the timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) (FFFF 16 – n + 1) n : Timer Aj register’s set value

7721 Group User’s Manual8–20

Fig. 8.4.1 Structures of timer Aj mode register and timer Aj register in event counter mode b7 b6 b5 b4 b3 b2 b1 b0 00 1 Bit Up-down switching factor select bit Count polarity select bit Bit name These bits are invalid in event counter mode. Fix this bit to “0” in event counter mode. Functions 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 : Contents of up-down register 1 : Input signal to TAj OUT pin At reset RW Pulse output function select bit Operating mode select bits 0 : No pulse output (TAjOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAjOUT pin functions as a pulse output pin.) 0 1 : Event counter mode b1 b0 RW RW RW RW RW RW RW RW Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) b7 b0 b7 b0 (b15) (b8) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) RW 15 to 0 Bit Functions At reset RWThese bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (FFFF 16 – n + 1) during countup. When reading, the register indicates the counter value. Undefined Note: Read from or write to this register in a unit of 16 bits.

7721 Group User’s Manual 8–21

8.4.1 Setting for event counter mode

Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Fig. 8.4.2 Initial setting example for registers relevant to event counter mode (1) [ The counter divides the count source frequency by (n + 1) when counting down, or by (FFFF16 – n + 1) when counting up. Continue to Figure 8.4.3 on next page. b7 b0 010 Selecting event counter mode and each function Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) Pulse output function select bit 0: No pulse output 1: Pulse output Count polarity select bit 0: Counts at falling edge of external signal. 1: Counts at rising edge of external signal. Up-down switching factor select bit 0: Contents of up-down register 1: Input signal to TAj OUT pin 5 : It may be either “0” or “1.” Selection of event counter mode Setting division ratio b7 b0 Can be set to “000016” to “FFFF 16” (n). (b15) (b8) b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) b7 b0 Setting up-down register Up-down register (Address 4416) Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Set the corresponding up-down bit when the contents of the up-down register are selected as the up-down switching factor. Set the corresponding bit to “1” when the two-phase pulse signal processing function is selected for timers A2 to A4. 0: Countdown 1: Countup 0: Two-phase pulse signal processing function disabled 1: Two-phase pulse signal processing function enabled

7721 Group User’s Manual8–22

Fig. 8.4.3 Initial setting example for registers relevant to event counter mode (2) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting the count start bit to “1” b7 b0 Count start register (Address 4016) Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Count starts From preceding Figure 8.4.2. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting port P5 direction register b7 b0 Port P5 direction register (Address D16) TA2 IN pin TA3 OUT pin TA3 IN pin TA4 OUT pin TA4 IN pin Clear the bit corresponding to the TAjIN pin to “0.” When selecting the TAjOUT pin’s input signal as the up-down switching factor, set the bit corresponding to the TAjOUT pin to “0.” When selecting the two-phase pulse signal processing function, set the bit corresponding to the TAjOUT pin to “0.” TA2 OUT pin /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting interrupt priority level b7 b0 Timer Aj interrupt control register (j = 2 to 4) (Addresses 77 16 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0.

7721 Group User’s Manual 8–23

8.4.2 Operation in event counter mode

À When the count start bit is set to “1,” the counter starts counting of the count source’s valid edges. \ When a counter underflow or overflow occurs, the reload register’s contents are reloaded, and counting continues. ´ The timer Aj interrupt request bit is set to “1” at the underflow or overflow in \ . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 8.4.4 shows an example of operation in the event counter mode. Fig. 8.4.4 Example of operation in event counter mode (without pulse output and two-phase pulse signal processing functions) Timer Aj interrupt request bit FFFF 16 n 000016 Time Count start bit Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Up-down bit Note: The above applies when the up-down bit’s contents are selected as the up-down switching factor (i.e., up-down switching factor select bit = “0” ). Set to “1” by software.

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8.4.3 Switching between countup and countdown

The up-down register (address 4416) or the input signal from the TAjOUT pin is used to switch countup from and to countdown. This switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 5816 to 5A16) is “0,” and by the input signal from the TAjOUT pin when the up-down switching factor select bit is “1.” When the switching between countup and countdown is set while counting is in progress, this switching is actually performed when the count source’s next valid edge is input. (1) Switching by up-down bit Countdown is performed when the up-down bit is “0,” and countup is performed when the up-down bit is “1.” Figure 8.4.5 shows the structure of the up-down register. (2) Switching by TAjOUT pin’s input signal Countdown is performed when the TAjOUT pin’s input signal is at “L” level, and countup is performed when the TAjOUT pin’s input signal is at “H” level. When using the TAjOUT pin’s input signal to switch countup from and to countdown, set the port P5 direction register’s bit which corresponds to the TAjOUT pin for the input mode. Fig. 8.4.5 Structure of up-down register Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Up-down register (Address 4416) Timer A4 up-down bit Timer A3 up-down bit Timer A2 up-down bit Fix these bits to “0.” Timer A2 two-phase pulse signal processing select bit (Note) Timer A3 two-phase pulse signal processing select bit (Note) Timer A4 two-phase pulse signal processing select bit (Note) 0 : Countdown 1 : Countup This function is valid when the contents of the up-down register is selected as the up- down switching factor. 0 : Two-phase pulse signal processing function disabled 1 : Two-phase pulse signal processing function enabled When not using the two-phase pulse signal processing function, set the bit to “0.” The value is “0” at reading. Note: Use the LDM or STA instruction for writing to bits 5 to 7. RW RW RW RW RW WO WO WO

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8.4.4 Selectable functions

The following describes the selectable pulse output, and two-phase pulse signal processing functions. (1) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 16 to 5A16) to “1.” When this function is selected, the TAjOUT pin is forcibly set for the pulse output pin regardless of the corresponding bit of the port P5 direction register. The TAjOUT pin outputs pulses of which polarity is inverted each time a counter underflow or overflow occurs. (Refer to “Figure 8.3.6.”) When the count start bit (address 4016) is “0” (count stopped), the TAjOUT pin outputs “L” level.

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(2) Two-phase pulse signal processing function The two-phase pulse signal processing function is selected by setting the two-phase pulse signal shows the timer Aj mode registers when the two-phase pulse signal processing function is selected. For timers with the two-phase pulse signal processing function selected, the timer counts two kinds of pulses of which phases differ by 90 degrees. There are two types of the two-phase pulse signal processing: normal processing and quadruple processing. In Timers A2 and A3, normal processing is performed; in timer A4, quadruple processing is performed. For some bits of the port P5 direction register correspond to pins used for two-phase pulse input, set these bits for the input mode. Fig. 8.4.6 Timer Aj mode registers when two-phase pulse signal processing function is selected l Normal processing Countup is performed at the rising edges input to the TAkIN pin when the phase has the relationship that the TAkIN pin’s input signal level goes from “L” to “H” while the TAkOUT (k = 2 and 3) pin’s input signal is at “H” level. Countdown is performed at the falling edges input to the TAkIN pin when the phase has the relationship that the TAkIN pin’s input signal level goes from “H” to “L” while the TAkOUT pin’s input signal is at “H” level. (Refer to “Figure 8.4.7.”) Fig. 8.4.7 Normal processing 100 0 0 1 Timer A2 mode register (Address 5816) Timer A3 mode register (Address 5916) Timer A4 mode register (Address 5A16) b7 b6 b5 b4 b3 b2 b1 b0 5 : It may be either “0” or “1.” TAkOUT TAkIN (k=2, 3) Up count +1 +1 +1 –1 –1 –1 Counted up Counted up Counted up Counted down Counted down Counted down

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Countup is performed at all rising and falling edges input to the TA4OUT and TA4IN pins when the phase has the relationship that the TA4IN pin’s input signal level goes from “L” to “H” while the TA4 OUT pin’s input signal is at “H” level. Countdown is performed at all rising and falling edges input to the TA4OUT and TA4IN pins when the phase has the relationship that the TA4IN pin’s input signal level goes from “H” to “L” while the TA4 OUT pin’s input signal is at “H” level. (Refer to “Figure 8.4.8.”) Table 8.4.3 lists the relationship between the input signals to the TA4OUT and TA4IN pins and count operation when the quadruple processing is selected. Table 8.4.3 Relationship between input signals to TA4OUT and TA4 IN pins and count operation when quadruple processing is selected Fig. 8.4.8 Quadruple processing TA4 OUT TA4 IN Counted up at all edges Counted up at all edges Counted down at all edges Counted down at all edges Input signal to TA4OUT pin Input signal to TA4IN pin “H” level “L” level Rising edge Falling edge “H” level “L” level Rising edge Falling edge Rising edge Falling edge “L” level “H” level Falling edge Rising edge “H” level “L” level Up-count Down-count

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[Precautions for event counter mode] 1. While counting is in progress, by reading the timer Aj register, the counter value can be read out at any timing. However, if the timer Aj register is read at the reload timing shown in Figure 8.4.9, the value “FFFF 16” (at an underflow) or “000016” (at an overflow) is read out. If reading is performed in the period from when a value is set into the timer Aj register with the counter stopped until the counter starts counting, the set value is correctly read out. Fig. 8.4.9 Reading timer Aj register 2. The TAjOUT pin is used for all functions listed below. Accordingly, only one of these functions can be selected for each timer.

Switching between countup and countdown by TAjOUT pin’s input signal
Pulse output function
Two-phase pulse signal processing function 210 n n – 1 Counter value (Hex.)

210 FFFF n – 1

(Hex.) Reload Time n = Reload register’s contents (1) For countdown FFFD FFFE FFFF n n + 1 FFFD FFFE FFFF 0000 n + 1 (2) For countup Counter value (Hex.) Read value (Hex.) Reload Time n = Reload register’s contents

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In this mode, the timer outputs a pulse which has an arbitrary width once. (Refer to “Table 8.5.1.”) Timers A2 to A4 can be used in this mode. When a trigger occurs, the timer outputs “H” level from the TAjOUT pin for an arbitrary time. Figure 8.5.1 shows the structures of the timer Aj mode register and timer Aj register in the one-shot pulse mode. Table 8.5.1 Specifications of one-shot pulse mode Specifications f2, f16, f64, or f512 l Countdown l When the counter value becomes “000016,” reload register’s con- tents are reloaded, and counting stops. l If a trigger occurs during counting, reload register’s contents are reloaded, and counting continues. l When a trigger occurs. (Note) l Internal or external trigger can be selected by software. l When the counter value becomes “000016 l When the count start bit is cleared to “0” When counting stops. Programmable I/O port or trigger input One-shot pulse output An undefined value is read out. l While counting is stopped When a value is written to the timer Aj register, it is written to both of the reload register and counter. l While counting is in progress When a value is written to the timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Item Count source Count operation Output pulse width (“H”) Count start condition Count stop condition Interrupt request occurrence timing TAj IN pin’s function TAjOUT pin’s function Read from timer Aj register Write to timer Aj register n fi [S] n : Timer Aj register’s set value Note:The trigger is generated with the count start bit = “1.”

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Fig. 8.5.1 Structures of timer Aj mode register and timer Aj register in one-shot pulse mode Trigger select bits Fix this bit to “1” in one-shot pulse mode. 1 @ Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) 1 0 : One-shot pulse mode 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6 Count source select bits b1 b0 b4 b3 Fix this bit to “0” in one-shot pulse mode. 10 1 0 0 : Writing “1” to one-shot start register 0 1 : (TAjIN pin functions as a prog- rammable I/O port.) 1 0 : Falling edge of TAjIN pin’s input signal 1 1 : Rising edge of TAjIN pin’s input signal Bit At reset RW RW RW RW RW RW RW RW RW Operating mode select bits b7 b0 b7 b0 (b15) (b8) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) RW 15 to 0 These bits can be set to “000116” to “FFFF16.” Assuming that the set value = n, the “H” level width of the one-shot pulse output from the TAj OUT pin is expressed as follows : Undefined fi: Frequency of count source (f2, f16, f64, or f512) WO n fi. Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. FunctionsBit At reset

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8.5.1 Setting for one-shot pulse mode

Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Fig. 8.5.2 Initial setting example for registers relevant to one-shot pulse mode (1) Continue to Figure 8.5.3. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting interrupt priority level b7 b0 Timer Aj interrupt control register (j = 2 to 4) (Addresses 7716 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 100 Selecting one-shot pulse mode and each function Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)1 Trigger select bits 0 0 : 0 1 : 1 0 : Falling edge of TAj IN pin’s input signal: External trigger 1 1 : Rising edge of TAjIN pin’s input signal: External trigger b4 b3 Count source select bits 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6 Selection of one-shot pulse mode /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting “H” level width of one-shot pulse b7 b0 Can be set to “000116” to “FFFF16” (n). (b15) (b8) b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) “H” level width = Writing “1” to one-shot start bit: Internal trigger fi Note. n fi: Frequency of count source

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/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Count starts Trigger generated /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Trigger input to TAjIN pin When internal trigger is selected When external trigger is selected From preceding Figure 8.5.2. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 One-shot start register (Address 4216) Setting one-shot start bit to “1” Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting count start bit to “1” b7 b0 Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count start register (Address 4016) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 Port P5 direction register (Address D16) Setting port P5 direction register TA2 IN pin TA3 IN pin TA4 IN pin Set the corresponding bit to “0.” /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting count start bit to “1” b7 b0 Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count start register (Address 4016) 00 Fig. 8.5.3 Initial setting example for registers relevant to one-shot pulse mode (2)

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8.5.2 Count source

In the one-shot pulse mode, the count source select bits (bits 6 and 7 at addresses 5816 to 5A16) select the count source. Table 8.5.2 lists the count source frequency. Table 8.5.2 Count source frequency Count source select bits Count source f16 f64 f512 f(XIN) = 8 MHz f(X IN) = 25 MHz 390.625 kHz 48.8281 kHz f(XIN) = 16 MHz

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8.5.3 Trigger

The counter is enabled for counting when the count start bit (address 4016) is set to “1.” The counter starts counting when a trigger is generated after counting has been enabled. An internal or external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 5816 to 5A16) are “002” or “012”; an external trigger is selected when the bits are “102” or “112.” If a trigger is generated during counting, the reload register’s contents are reloaded and the counter continues counting. If generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timer’s count source or more has passed between the previously generated trigger and a new trigger. (1) When selecting internal trigger A trigger is generated when writing “1” to the one-shot start bit (bits 2 to 4 at address 4216). Figure 8.5.4 shows the structure of the one-shot start register. (2) When selecting external trigger A trigger is generated at the falling edge of the TAjIN pin’s input signal when bit 3 at addresses 5816 to 5A16 is “0,” or at its rising edge when bit 3 is “1.” When using an external trigger, set the port P5 direction registers’ bits which correspond to the TAjIN pins for the input mode. Fig. 8.5.4 Structure of one-shot start register . Bit 7 to 5Nothing is assigned. Timer A4 one-shot start bit Timer A3 one-shot start bit Timer A2 one-shot start bit Bit name At reset Undefined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register (Address 4216) 1 : Start outputting one-shot pulse (valid when internal trigger is selected.) The value is “0” at reading. WO WO WO WO WO Fix these bits to “0.” The value is “0” at reading.

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8.5.4 Operation in one-shot pulse mode

À When the one-shot pulse mode is selected with the operating mode select bits, the TAjOUT pin outputs “L” level. \ When the count start bit is set to “1,” the counter is enabled for counting. After that, counting starts when a trigger is generated. ´ When the counter starts counting, the TAjOUT pin outputs “H” level. ˆ When the counter value becomes “000016,” the output from the TAjOUT pin becomes “L” level. Additionally, the reload register’s contents are reloaded and the counter stops counting there. ˜ Simultaneously with ˆ , the timer Aj interrupt request bit is set to “1.” This interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 8.5.5 shows an example of operation in the one-shot pulse mode. When a trigger is generated after ˆ above, the counter and TAjOUT pin perform the same operations beginning from \ again. Furthermore, if a trigger is generated during counting, the counter performs countdown once after this new trigger is generated, and it continues counting with the reload register’s contents reloaded. If generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timer’s count source or more has passed between the previously generated trigger and a new trigger. The one-shot pulse output from the TAj OUT pin can be disabled by clearing the timer Aj mode register’s bit 2 to “0.” Accordingly, Timer Aj can be also used as an internal one-shot timer that does not perform the pulse output. In this case, the TAjOUT pin functions as a programmable I/O port.

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counting. Starts counting. FFFF 16 n 000116 Time À Count start bit Timer Aj interrupt request bit Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. TAjIN pin input signal One-shot pulse output from TAjOUT pin \ Trigger during counting 1 / fi 5 (n) Note: The above applies when an external trigger (rising of TAjIN pin’s input signal) is selected. 1 / fi 5 (n+1) À When the count start bit = “0” (counting stopped), the TAjOUT pin outputs “L” level. \ When a trigger is generated during counting, the counter counts the count source (n + 1) times after a new trigger is generated. fi = Frequency of count source (f2, f16, f64, or f512) Stops counting. Reloaded Reloaded Fig. 8.5.5 Example of operation in one-shot pulse mode (selecting external trigger)

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[Precautions for one-shot pulse mode] 1. If the count start bit is cleared to “0” during counting, the counter becomes as follows:

The counter stops counting, and the reload register’s contents are reloaded into the counter.
The TAjOUT pin’s output level becomes “L.”
The timer Aj interrupt request bit is set to “1.” 2. A one-shot pulse is output synchronously with an internally generated count source. Accordingly, when selecting an external trigger, there will be a delay equivalent to one cycle of the count source at maximum from when a trigger is input to the TAjIN pin until a one-shot pulse is output. Note: The above applies when an external trigger (falling edge of TAjIN pin’s input signal) is selected. TAjIN pin’s input signal Count source Trigger input Starts outputting of one-shot pulse One-shot pulse output from TAjOUT pin Fig. 8.5.6 Output delay in one-shot pulse output 3. When the timer’s operating mode is set by one of the following procedures, the timer Aj interrupt request bit is set to “1.” l When the one-shot pulse mode is selected after reset l When the operating mode is switched from the timer mode to the one-shot pulse mode l When the operating mode is switched from the event counter mode to the one-shot pulse mode Accordingly, when using the timer Aj interrupt (interrupt request bit), be sure to clear the timer Aj interrupt request bit to “0” after the above setting. 4. Don not set “000016” to the timer Aj register.

7721 Group User’s Manual8–38

8.6 Pulse width modulation (PWM) mode

In this mode, the timer continuously outputs pulses which have an arbitrary width. (Refer to “Table 8.6.1.”) Timers A2 to A4 can be used in this mode. Figure 8.6.1 shows the structures of the timer Aj mode registers and timer Aj registers in the PWM mode. Table 8.6.1 Specifications of PWM mode Item Count source Count operation PWM period/“H” level width Count start condition Count stop condition Interrupt request occurrence timing TAj IN pin’s function TAjOUT pin’s function Read from timer Aj register Write to timer Aj register Specifications f2, f16, f64, or f512 l Countdown (operating as an 8-bit or 16-bit pulse width modulator) l Reload register’s contents are reloaded at rising edge of PWM pulse, and counting continues. l A trigger generated during counting does not affect the counting. <16-bit pulse width modulator> <8-bit pulse width modulator> l When a trigger is generated. (Note) l Internal or external trigger can be selected by software. When the count start bit is cleared to “0.” At falling edge of PWM pulse Programmable I/O port or trigger input PWM pulse output An undefined value is read out. l While counting is stopped When a value is written to the timer Aj register, it is written to both of the reload register and counter. l While counting is in progress When a value is written to the timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Period = (216–1) fi [s] n fi“H” level width = [s] Period = (m + 1)(28–1) fi “H” level width = [s] n(m + 1) fi n : Timer Aj register’s set value [s] m : Timer Aj register low-order 8 bits’ set value n : Timer Aj register high-order 8 bits’ set value Note: The trigger is generated with the count start bit = “1.”

7721 Group User’s Manual 8–39

Fig. 8.6.1 Structures of timer Aj mode registers and timer Aj registers in PWM mode b7 b6 b5 b4 b3 b2 b1 b0 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits 11 1 At reset RW Trigger select bits Fix this bit to “1” in PWM mode. Operating mode select bits Functions 1 1 : PWM mode b1 b0 b4 b3 16/8-bit PWM mode select bit 0 0 : Writing “1” to count start register 0 1 : IN pin functions as a pro- grammable I/O port.) 1 0 : Falling edge of TAjIN pin’s input signal 1 1 : Rising edge of TAjIN pin’s input signal 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator RW RW RW RW RW RW RW RW <When operating as an 8-bit pulse width modulator> (b15) b7 b0 b7 b0 (b8) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 7 to 0 15 to 8 Undefined Undefined These bits can be set to “0016” to “FF16.” Assuming that the set value = m, PWM pulse’s period output from the TAjOUT pin is expressed as follows:(m + 1)(28 – 1) fi WO These bits can be set to “0016” to “FE16.” Assuming that the set value = n, the “H” level width of the PWM pulse output from the TAj OUT pin is expressed as follows: n(m + 1) fi WO fi: Frequency of count source (f2, f16, f64, or f512) Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. b7 b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0These bits can be set to “000016” to “FFFE16.” Assuming that the set value = n, the “H” level width of the PWM pulse output from the TAj OUT pin is expressed as follows: (PWM pulse period = ) Undefined <When operating as a 16-bit pulse width modulator> (b15) (b8) WO n fi fi: Frequency of count source (f2, f16, f64, or f512) Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. n16 – 1 fi Bit Bit name (TAj

7721 Group User’s Manual8–40

8.6.1 Setting for PWM mode

Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Fig. 8.6.2 Initial setting example for registers relevant to PWM mode (1) Note: When operating as 8-bit pulse width modulator fi : Frequency of count source However, if n = “0016”, the pulse width modulator does not operate and the TAjOUT pin outputs “L” level. At this time, no timer Aj interrupt request occurs. b7 b0 Count source select bits 0 0 : f 0 1 : f16 1 0 : f64 1 1 : f512 Selecting PWM mode and each function Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) b7 b6 16/8-bit PWM mode select bit 0 : Operates as 16-bit pulse width modulator 1 : Operates as 8-bit pulse width modulator Continue to Figure 8.6.3. Trigger select bits 0 0 : 0 1 : 1 0 : Falling edge of TAj IN pin’s input signal 1 1 : Rising edge of TAjIN pin’s input signal b3b4 Selection of PWM mode Setting PWM pulse’s period and “H” level width b7 b0 Can be set to “000016” to “FFFE16” (n) (b15) (b8) b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Note: When operating as 16-bit pulse width modulator fi : Frequency of count source However, if n = “000016”, the pulse width modulator does not operate and the TAjOUT pin outputs “L” level. At this time, no timer Aj interrupt request occurs. l When operating as 16-bit pulse width modulator b7 b0 Can be set to “0016” to “FF16” (m) (b15) (b8) b7 b0 l When operating as 8-bit pulse width modulator Can be set to “0016” to “FE16” (n) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Writing “1” to count start bit: Internal trigger : External trigger : External trigger “H” level width = Period = “H” level width = Period = 216 – 1 fi n fi (m+1) (2 8 –1 ) fi n(m+1) fi

7721 Group User’s Manual 8–41

Fig. 8.6.3 Initial setting example for registers relevant to PWM mode (2) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Count tt /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Trigger input to TAjIN pin When external trigger is selected When internal trigger is selected From preceding Figure 8.6.2. Trigger generated /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 Port P5 direction register (Address D16) Setting port P5 direction register TA2 IN pin TA3 IN pin TA4 IN pin Clear the corresponding bit to “0.” /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting interrupt priority level b7 b0 Timer Aj interrupt control register (j = 2 to 4) (Addresses 7716 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

7721 Group User’s Manual8–42

8.6.2 Count source

In the PWM mode, the count source select bits (bits 6 and 7 at addresses 5816 to 5A16) select the count source. Table 8.6.2 lists the count source frequency. Table 8.6.2 Count source frequency Count source select bits Count source f16 f64 f512 f(XIN) = 8 MHz f(XIN) = 25 MHz 390.625 kHz 48.8281 kHz f(XIN) = 16 MHz

8.6.3 Trigger

When a trigger is generated, the TAjOUT pin starts outputting PWM pulses. An internal or an external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 5816 to 5A16) are “002” or “012”; an external trigger is selected when the bits are “102” or “112.” A trigger generated during outputting of PWM pulses is invalid and it does not affect the pulse output operation. (1) When selecting internal trigger A trigger is generated when “1” is written to the count start bit (address 4016). (2) When selecting external trigger A trigger is generated at the falling edge of the TAjIN pin’s input signal when bit 3 at addresses 5816 to 5A16 is “0,” or at its rising edge when bit 3 is “1.” However, the trigger input is accepted only when the count start bit is “1.” When using an external trigger, set the port P5 direction registers’ bits which correspond to the TAjIN pins for the input mode.

7721 Group User’s Manual 8–43

8.6.4 Operation in PWM mode

À When the PWM mode is selected with the operating mode select bits, the TAjOUT pin outputs “L” level. \` When a trigger is generated, the counter (pulse width modulator) starts counting and the TAjOUT pin outputs a PWM pulse (Notes 1 and 2). ´ The timer Aj interrupt request bit is set to “1” each time the PWM pulse level goes from “H” to “L.” The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. ˆ Each time a PWM pulse has been output for one period, the reload register’s contents are reloaded and the counter continues counting. The following explains operations of the pulse width modulator. (1) 16-bit pulse width modulator When the 16/8-bit PWM mode select bit is set to “0,” the counter operates as a 16-bit pulse width (2) 8-bit pulse width modulator When the 16/8-bit PWM mode select bit is set to “1,” the counter is divided into 8-bit halves. Then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as Notes 1: If a value “000016” is set into the timer Aj register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output from the TAj OUT pin remains “L” level. The timer Aj interrupt request does not occur. Similarly, if a value “0016” is set into the high-order 8 bits of the timer Aj register when the counter operates as an 8-bit pulse width modulator, the same is performed. 2: When the counter operates as an 8-bit pulse width modulator, after a trigger is generated, the TAjOUT pin outputs “L” level which has the same width as “H” level width of the PWM pulse, which was set. After that, the PWM pulse output starts from the TAjOUT pin.

7721 Group User’s Manual8–44

Fig. 8.6.4 Operation example of 16-bit pulse width modulator Fig. 8.6.5 Operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 1 / fi 5 (216 – 1) 1 / fi 5 (n) Count source TAjIN pin’s input signal PWM pulse output from TAjOUT pin Note: The above applies when reload register (n) = “000316” and an external trigger (rising edge of TAjIN pin’s input signal) is selected. Trigger is not generated by this signal. Timer Aj interrupt request bit Cleared to “0” when interrupt request is accepted or cleared by software. fi: Frequency of count source (f2, f16, f64, or f512) À When an arbitrary value is set to the timer Aj register after setting “000016” to it, the timing at which the PWM pulse goes “H” depends on the timing at which the new value is set. Note: The above applies when an external trigger (rising edge of TAjIN pin’s input signal) is selected. FFFE 16 n 000116 TAjIN pin’s input signal Counter contents (Hex.) (216 –1) – n PWM pulse output from TAjOUT pin “000016” is set to timer Aj register. “200016” is set to timer Aj register. 200016 “FFFE16” is set to timer Aj register. n = Reload register’s contents fi: Frequency of count source (f2, f16, f64, or f512) Restarts counting.Stops counting. Time À

7721 Group User’s Manual 8–45

Fig. 8.6.6 Operation example of 8-bit pulse width modulator À Count source TAjIN pin’s input signal PWM pulse output from TAjOUT pin Note: The above applies when the reload register’s high-order 8 bits (n) = “0216” and low-order 8 bits (m) = “0216” and an external trigger (falling edge of TAjIN pin input signal) is selected. Timer Aj interrupt request bit Cleared to “0” when interrupt request is accepted or cleared by software.fi: Frequency of count source (f2, f16, f64, or f512) À The 8-bit prescaler counts the count source. \ The 8-bit pulse width modulator counts the 8-bit prescaler’s underflow signal. \ 8-bit prescaler’s underflow signal 1 / fi 5 (m+1)

7721 Group User’s Manual8–46

Fig. 8.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) PWM pulse output from TAjOUT pin À Count source TAjIN pin’s input signal 0016 Prescaler's contents (Hex.) 0216 Time Stops counting. 0116 Counter’s contents (Hex.) 0416 0A16 Time À When an arbitrary value is set to the timer Aj register after setting “0016” to it, the timing at which the PWM pulse level goes “H” depends on the timing at which the new value is set. “000216” is set to timer Aj register. “0A0216” is set to timer Aj register. “040216” is set to timer Aj register. Restarts counting. Note: The above applies when an external trigger (falling edge of TAjIN pin’s input signal) is selected. fi: Frequency of count source (f2, f16, f64, or f512) m: Contents of reload register’s low-order 8 bits

7721 Group User’s Manual 8–47

[Precautions for PWM mode] 1. If the count start bit is cleared to “0” while outputting PWM pulses, the counter stops counting. When the TAjOUT pin was outputting “H” level at that time, the output level becomes “L” and the timer Aj interrupt request bit is set to “1.” When the TAjOUT pin was outputting “L” level, the output level does not change and a timer Aj interrupt request does not occur. 2. When the timer’s operating mode is set by one of the following procedures, the timer Aj interrupt request bit is set to “1.” l When the PWM mode is selected after reset l When the operating mode is switched from the timer mode to the PWM mode l When the operating mode is switched from the event counter mode to the PWM mode Accordingly, when using the timer Aj interrupt (interrupt request bit), be sure to clear the timer Aj interrupt request bit to “0” after the above setting.

7721 Group User’s Manual8–48

9.1 Overview

9.2 Block description

9.3 Timer mode

[Precautions for timer mode]

9.4 Event counter mode

[Precautions for event counter mode] 9.5 Pulse period/Pulse width measurement mode [Precautions for pulse period/pulse width measurement (PWM) mode]

7721 Group User’s Manual9–2

Timer B consists of three counters, Timers B0 to B2, each equipped with a 16-bit reload function. Timers B0 to B2 operate independently of one another. Timer B has three operating modes listed below. Timers B0 and B1 have selective three operating modes listed below. Timer B2 operates only in the timer mode. (1) Timer mode (Timers B0 to B2) The timer counts an internally generated count source. (2) Event counter mode (Timers B0 and B1) The timer counts an external signal. (3) Pulse period/Pulse width measurement mode (Timers B0 and B1) The timer measures an external signal’s pulse period or pulse width. In this chapter, Timer Bi (i = 0 to 2) indicates Timers B0 to B2. Timer Bj (j = 0, 1) indicates Timers B0 and B1; this is used when the timer B’s input/output pins are used etc. (Hereafter, input/output pins are called I/O pins.) Figure 9.2.1 shows the block diagram of Timer B. Explanation of registers relevant to Timer B is described below. 9.1 Overview 9.2 Block description f 2 f 16 f 64 f 512 Count source select bits Timer mode Pulse period/Pulse width measurement mode Polarity switching and edge pulse generating circuit Event counter mode Count start bit Counter reset circuit Data bus (odd) Data bus (even) (Low-order 8 bits) (High-order 8 bits) Timer Bi reload register (16) Timer Bi counter (16) Timer Bi interrupt request bit TBj IN Timer Bj overflow flag (Valid in pulse period/pulse width measurement mode) i = 0–2, j = 0, 1 Fig. 9.2.1 Block diagram of Timer B

9–3

9.2.1 Counter and reload register (timer Bi register)

Each of timer Bi counter and reload register consists of 16 bits and has the following functions. (1) Functions in timer mode and event counter mode Countdown in the counter is performed each time the count source is input. The reload register is used to store the initial value of the counter. When a counter underflow occurs, the reload register’s contents are reloaded into the counter. A value is set to the counter and reload register by writing the value to the timer Bi register. Table 9.2.1 lists the memory assignment of the timer Bi register. The value written into the timer Bi register when the counting is not in progress is set to the counter and reload register. The value written into the timer Bi register when the counting is in progress is set only to the reload register. In this case, the reload register’s updated contents are transferred to the counter when the next underflow occurs. The counter value is read out by reading out the timer Bi register. Note: When reading from or writing to the timer Bi register, perform it in a unit of 16 bits. For more information about the value obtained by reading the timer Bi register, refer to “[Precautions for timer mode]” and “[Precautions for event counter mode].” (2) Functions in pulse period/pulse width measurement mode Countup in the counter is performed each time the count source is input. The reload register is used to retain the pulse period or pulse width measurement result. When a valid edge is input to the TBj IN pin, the counter value is transferred to the reload register. In this mode, the value obtained by reading the timer Bj register is the reload register’s contents, so that the measurement result is obtained. Note: When reading from the timer Bj register, perform it in a unit of 16 bits. Timer Bi register Timer B0 register Timer B1 register Timer B2 register Low-order byte Address 50 Address 5216 Address 5416 High-order byte Address 51 Address 5316 Address 5516 Note : At reset, the contents of the timer Bi register are undefined. Table 9.2.1 Memory assignment of timer Bi registers

7721 Group User’s Manual9–4

9.2.2 Count start register

This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure 9.2.2 shows the structure of the count start register. Fig. 9.2.2 Structure of count start register Bit Timer B2 count start bit Timer B1 count start bit Timer B0 count start bit Timer A4 count start bit Timer A3 count start bit Timer A2 count start bit Timer A1 count start bit Timer A0 count start bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) 0 : Stop counting 1 : Start counting RW RW RW RW RW RW RW RW : Bits 0 to 4 are not used for Timer B.

9–5

9.2.3 Timer Bi mode register

Figure 9.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used to select the operating mode of Timer Bi. Bits 2, 3, and bits 5 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. Fig. 9.2.3 Structure of timer Bi mode register Nothing is assigned. These bits have different functions according to the operating mode. Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Do not select. b1 b0 Bit At reset RW 0 RW RW RW Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. RW0 –Undefined4 RO (Note) Undefined RW0 RW0 These bits have different functions according to the operating mode.

7721 Group User’s Manual9–6

9.2.4 Timer Bi interrupt control register

Figure 9.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer to “CHAPTER 7. INTERRUPTS.” Fig. 9.2.4 Structure of timer Bi interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select a timer Bi interrupt’s priority level. When using timer Bi interrupts, select one of the priority levels (1 to 7). When a timer Bi interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable bit (I) = “0.”) To disable timer Bi interrupts, set these bits to “000 2” (level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when a timer Bi interrupt request occurs. This bit is automatically cleared to “0” when the timer Bi interrupt request is accepted. This bit can be set to “1” or cleared to “0” by software. b7 b6 b5 b4 b3 b2 b1 b0 Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned. Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16)

9–7

9.2.5 Port P5 direction register

Input pins of Timer Bj are multiplexed with port P5. When using these pins as Timer Bj’s input pins, set the corresponding bits of the port P5 direction register to “0” to set these port pins for the input mode. Figure 9.2.5 shows the relationship between port P5 direction register and the Timer Bj’s input pins. Fig. 9.2.5 Relationship between port P5 direction register and Timer Bj’s input pins TA2 OUT pin pinTA3 OUT pinTA4 OUT TB0 Port P5 direction register (Address D16) b1 b0b2b3b4b5b6b7 TA2 I I N RW : Bits 0 to 5 are not used for Timer B. Corresponding pin name FunctionsBit At reset 0 : Input mode 1 : Output mode When using these pins as Timer Bj's input pins, set the corresponding bits to "0 . " RW RW RW RW RW RW RW RW pin TA3 N pin ITA4 N pin IN pin TB1 IN pin

9–8 shows the structures of the timer Bi mode register and timer Bi register in the timer mode. Table 9.3.1 Specifications of timer mode Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing TBj IN pin’s function Read from timer Bi register Write to timer Bi register Specifications f 2, f16, f64, or f512

Countdown
When a counter underflow occurs, reload register’s contents are reloaded, and counting continues. When the count start bit is set to “1.” When the count start bit is cleared to “0.” When a counter underflow occurs. Programmable I/O port Counter value can be read out. l While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. l While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload time.) (n + 1) n : Timer Bi register’s set value

7721 Group User’s Manual 9–9

Fig. 9.3.1 Structures of timer Bi mode register and timer Bi register in timer mode b7 b6 b5 b4 b3 b2 b1 b0 Bit This bit is invalid in timer mode; its value is undefined at reading. Nothing is assigned. Bit name Count source select bits Functions At reset RW These bits are invalid in timer mode. Operating mode select bits 0 0 : Timer mode b1 b0 RW RW RW RW Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)5 –Undefined4 Undefined5 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6 RW0 RW0 RO b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) RW 15 to 0 Bit Functions At reset These bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Undefined RW Note: Read from or write to this register in a unit of 16 bits.

9–10

9.3.1 Setting for timer mode

Figure 9.3.2 shows an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Fig. 9.3.2 Initial setting example for registers relevant to timer mode Count Starts b7 b0 Count source select bits 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Selecting timer mode and count source Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit b7 b6 Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. 5 : It may be either “0” or “1.” Selection of timer mode Note: The counter divides the count source by (n + 1). Setting division ratio b7 b0 Can be set to “000016” to “FFFF16” (n). (b15) (b8) b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) 00555

7721 Group User’s Manual 9–11

9.3.2 Count source

In the timer mode, the count source select bits (bits 6 and 7 at addresses 5B16 to 5D16) select the count source. Table 9.3.2 lists the count source frequency. Table 9.3.2 Count source frequency Count source select bits Count source f16 f64 f512 f(XIN) = 8 MHz f(XIN) = 25 MHz 390.625 kHz 48.8281 kHz f(XIN) = 16 MHz

9–12

9.3.3 Operation in timer mode

À When the count start bit is set to “1,” the counter starts counting of the count source. \ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues. ´ The timer Bi interrupt request bit is set to “1” at the underflow in \ . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 9.3.3 shows an example of operation in the timer mode. Stops counting. Restarts counting. FFFF 16 n 000016 Time Count start bit Timer Bi interrupt request bit Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Set to “1” by software. 1 / fi 5 (n+1) fi = frequency of count source (f2, f16, f64, f512) Cleared to “0” by software. Fig. 9.3.3 Example of operation in timer mode

7721 Group User’s Manual 9–13

[Precautions for timer mode] While counting is in progress, by reading the timer Bi register, the counter value can be read out at any timing. However, if the timer Bi register is read at the reload timing shown in Figure 9.3.4, the value “FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting, the set value is correctly read out. Fig. 9.3.4 Reading timer Bi register 210 n n – 1Counter value (Hex.)

210 FFFF n – 1Read value

(Hex.) Reload Timen = Reload register’s contents

9–14 of the timer Bj mode register and the timer Bj register in the event counter mode. Table 9.4.1 Specifications of event counter mode Specifications

External signal input to the TBjIN pin
The count source’s valid edge can be selected from the falling edge, the rising edge, and both of the falling and rising edges by software.
Countdown
When a counter underflow occurs, reload register’s contents are reloaded, and counting continues. When the count start bit is set to “1.” When the count start bit is cleared to “0.” When a counter underflow occurs. Count source input Counter value can be read out. l While counting is stopped When a value is written to the timer Bj register, it is written to both of the reload register and counter. l While counting is in progress When a value is written to the timer Bj register, it is written only to the reload register. (Transferred to the counter at the next reload time.) (n + 1) n : Timer Bj register’s set value Item Count source Count operation Division ratio Count start condition Count stop condition Interrupt request occurrence timing TBj IN pin’s function Read from timer Bj register Write to timer Bj register

7721 Group User’s Manual 9–15

Fig. 9.4.1 Structures of timer Bj mode register and timer Bj register in event counter mode b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) RW 15 to 0 Bit Functions At reset RWThese bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Undefined Note: Read from or write to this register in a unit of 16 bits. 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Counts at both falling and rising edges of external signal 1 1 : Do not select. b7 b6 b5 b4 b3 b2 b1 b0 Bit Count polarity select bits Bit name These bits are invalid in event counter mode. This bit is invalid in event counter mode; its value is undefined at reading. Functions At reset RW Operating mode select bits 0 1 : Event counter mode b1 b0 RW RW RW RW RW RW Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) b3 b2 Nothing is assigned. Undefined Undefined RO

9–16

9.4.1 Setting for event counter mode

Figure 9.4.2 shows an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Note: The counter divides the count source by (n + 1). Setting division ratio b7 b0 Can be set to “000016” to “FFFF16” (n). (b15) (b8) b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Count starts b7 b0 0 0 : Counts at falling edge of external signal. 0 1 : Counts at rising edge of external signal. 1 0 : Counts at both of falling and rising edges of external signal. 1 1 : Do not select. Selecting event counter mode and count polarity Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit b3 b2 Setting interrupt priority level b7 b0 Timer Bj interrupt control register (j = 0, 1) (Addresses 7A16, 7B16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0.Setting port P5 direction register b7 b0 Port P5 direction register (Address D16) Clear the corresponding bit to “0.”TB0 IN pin TB1 IN pin 5 : It may be “0” or “1.” Selection of event counter mode Count polarity select bits Fig. 9.4.2 Initial setting example for registers relevant to event counter mode

7721 Group User’s Manual 9–17

9.4.2 Operation in event counter mode

À When the count start bit is set to “1,” the counter starts counting of the count source’s valid edges. \ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues. ´ The timer Bj interrupt request bit is set to “1” at the underflow in \ . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 9.4.3 shows an example of operation in the event counter mode. Stops counting. Restarts counting . FFFF 16 n 000016 Time Count start bit Timer Bj interrupt request bit Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Cleared to “0” by software. Set to “1” by software. Fig. 9.4.3 Example of operation in event counter mode

9–18 [Precautions for event counter mode] While counting is in progress, by reading the timer Bj register, the counter value can be read out at any timing. However, if the timer Bj register is read at the reload timing shown in Figure 9.4.4, the value “FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Bj register with the counter stopped until the counter starts counting, the set value is correctly read out. Fig. 9.4.4 Reading timer Bj register 21 0 n n – 1Counter value (Hex.) 21 0 FFFF n – 1Read value (Hex.) Reload Timen = Reload register’s contents

7721 Group User’s Manual 9–19

9.5 Pulse period/Pulse width measurement mode

In this mode, the timer measures an external signal’s pulse period or pulse width. (Refer to “Table 9.5.1.”) Timers B0 and B1 can be used in this mode. Figure 9.5.1 shows the structures of the timer Bj mode register and timer Bj register in the pulse period/pulse width measurement mode. l Pulse period measurement The timer measures the pulse period of the external signal that is input to the TBjIN pin. l Pulse width measurement The timer measures the pulse width (“L” level and “H” level widths) of the external signal that is input to the TBjIN pin. Table 9.5.1 Specifications of pulse period/pulse width measurement mode Item Count source Count operation Count start condition Count stop condition Interrupt request occurrence timing TBj IN pin’s function Read from timer Bj register Write to timer Bj register Timer Bj overflow flag] : The bit used to identify the source of an interrupt request occurrence. Notes 1: No interrupt request occurs when the first valid edge is input after the counter starts counting. 2: The value read out from the timer Bj register is undefined after the counter starts counting until the second valid edge is input. Specifications f2, f16, f64, or f512 l Countup l Counter value is transferred to the reload register at valid edge of measurement pulse, and counting continues after clearing the counter value to “0000 16.” When the count start bit is set to “1.” When the count start bit is cleared to “0.” l When valid edge of measurement pulse is input (Note 1). l When a counter overflow occurs (Timer Bj overflow flag ] is set to “1” simultaneously.) Measurement pulse input The value obtained by reading timer Bj register is the reload register’s contents (Measurement result) (Note 2). Invalid

9–20 Fig. 9.5.1 Structures of timer Bj mode register and timer Bj register in pulse period/pulse width measurement mode Measurement mode select bits Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) 1 0 : Pulse period/Pulse width measurement mode 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b3 b2 Nothing is assigned. 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : Do not select. Bit At reset Undefined RW RW RW RW RW RW RW Timer Bj overflow flag (Note) 0 : No overflow 1 : Overflowed Undefined RO Note: The timer Bj overflow flag is cleared to “0” at the next count timing of the count source when a value is written to the timer Bj mode register with the count start bit = “1.” b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) RW 15 to 0 The measurement result of pulse period or pulse width is read out. Undefined RO Note: Read from this register in a unit of 16 bits. FunctionsBit At reset

7721 Group User’s Manual 9–21

9.5.1 Setting for pulse period/pulse width measurement mode

Figure 9.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Fig. 9.5.2 Initial setting example for registers relevant to pulse period/pulse width measurement mode /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Count starts b7 b0 Measurement mode select bits Selecting pulse period/pulse width measurement mode and each function Timer Bj mode register (i = 0, 1) (Addresses 5B16, 5C16) Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit b3 b2 Count source select bits b7 b6 Timer Bj overflow flag (Note) 0: No overflow 1: Overflowed Setting port P5 direction register b7 b0 Port P5 direction register (Address D16) Clear the corresponding bit to “0.” TB0 IN pin TB1 IN pin 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement 1 1 : Do not select. 0 0 : f 0 1 : f16 1 0 : f64 1 1 : f512 Note: The timer Bj overflow flag is a read-only bit. This bit is undefined after reset. When a value is written to the timer Bj mode register with the count start bit = “1,” this bit is cleared to “0” at the next count timing of the count source. Setting interrupt priority level b7 b0 Timer Bj interrupt control register (j = 0, 1) (Addresses 7A16, 7B16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Selection of pulse period/pulse width measurement mode

9–22

9.5.2 Count source

In the pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses 5B 16 and 5C16) select the count source. Table 9.5.2 lists the count source frequency. Table 9.5.2 Count source frequency Count source select bits Count source f16 f64 f512 f(XIN) = 8 MHz f(X IN) = 25 MHz 390.625 kHz 48.8281 kHz f(XIN) = 16 MHz

7721 Group User’s Manual 9–23

9.5.3 Operation in pulse period/pulse width measurement mode

À When the count start bit is set to “1,” the counter starts counting of the count source. \ The counter value is transferred to the reload register when an valid edge of the measurement pulse is detected. (Refer to section “(1) Pulse period/Pulse width measurement.”) ´ The counter value is cleared to “000016” after the transfer in \ , and the counter continues counting. ˆ The timer Bj interrupt request bit is set to “1” when the counter value is cleared to “000016” in ´ (Note). The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. ˜ The timer repeats operations \` to ˆ above. Note:No timer Bj interrupt request occurs when the first valid edge is input after the counter starts counting. (1) Pulse period/Pulse width measurement The measurement mode select bits (bits 2 and 3 at addresses 5B16 and 5C16) specify whether the pulse period of an external signal is measured or its pulse width is done. Table 9.5.3 lists the relationship between the measurement mode select bits and the pulse period/pulse width measurements. Make sure that the measurement pulse interval from the falling edge to the rising edge, and vice versa are two cycles of the count source or more. Additionally, use software to identify whether the measurement result indicates the “H” level or the “L” level width. Table 9.5.3 Relationship between measurement mode select bits and pulse period/pulse width measurements Pulse period/Pulse width measurement Pulse period measurement Pulse width measurement Measurement interval (Valid edges) From falling edge to falling edge (Falling edges) From rising edge to rising edge (Rising edges) From falling edge to rising edge, and vice versa (Falling and rising edges) (2) Timer Bj overflow flag A timer Bj interrupt request occurs when a measurement pulse’s valid edge is input or a counter overflow occurs. The timer Bj overflow flag is used to identify the cause of the interrupt request, that is, whether it is an overflow occurrence or a valid edge input. The timer Bj overflow flag is set to “1” by an overflow. Accordingly, the cause of the interrupt request occurrence is identified by checking the timer Bj overflow flag in the interrupt routine. When a value is written to the timer Bj mode register with the count start bit = “1,” the timer Bj overflow flag is cleared to “0” at the next count timing of the count source The timer Bj overflow flag is a read-only bit. Use the timer Bi interrupt request bit to detect the overflow timing. Do not use the timer Bi overflow flag for this detection. during pulse width measurement.

9–24 Fig. 9.5.3 Operation during pulse period measurement Fig. 9.5.4 Operation during pulse width measurement Count source Measurement pulse Timing at which counter is cleared to “000016” Note: The above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse. Reload register Counter Transfer timing Count start bit À Counter is initialized by completion of measurement. \ Counter overflow. À \À Cleared to “0” when interrupt request is accepted or cleared by software. Timer Bj interrupt request bit Timer Bj overflow flag Transferred (undefined value) Transferred (measured value) Measurement pulse Count source Timing at which counter is cleared to “000016” Count start bit Timer Bj interrupt request bit Timer Bj overflow flag Reload register Counter Transfer timing À Counter is initialized by completion of measurement. \ Counter overflow. Transferred (measured value) Transferred (measured value) Transferred (measured value) Transferred (undefined value) À \ÀÀÀ Cleared to “0” when interrupt request is accepted or cleared by software.

7721 Group User’s Manual 9–25

[Precautions for pulse period/pulse width measurement mode] 1. A timer Bj interrupt request is generated by the following sources: l Input of measured pulse’s valid edge l Counter overflow When the overflow generates the interrupt request, the timer Bj overflow flag is set to “1.” 2. After reset, the timer Bj overflow flag is undefined. When a value is written to the timer Bj mode register with the count start bit = “1,” this flag is cleared to “0” at the next count timing of the count source. 3. An undefined value is transferred to the reload register when the first valid edge is input after the counter starts counting. In this case, no timer Bj interrupt request occurs. 4. The counter value at start of counting is undefined. Accordingly, a timer Bj interrupt request may be generated by an overflow immediately after the counter starts counting. 5. If the contents of the measurement mode select bits are changed after the counter starts counting, the timer Bj interrupt request bit is set to “1.” When the same value which has been set in these bits are written again, the timer Bj interrupt request bit is not changed, that is, the bit retains the state. 6. If the input signal to the TBjIN pin is affected by noise, etc., the counter may not perform the exact measurement. We recommend to verify, by software, that the measurement values are within a constant range.

9–26

10.1 Overview

10.2 Block description

10.3 Setting of real-time output

10.4 Real-time output operation

7721 Group User’s Manual10–2

The real-time output has the function of changing the output level of several pins simultaneously at every period of the timer. Figure 10.1.1 shows the block diagram of real-time output per bit. Real-time output has two operating modes described below. (1) Pulse mode 0 The 8-bit pulse output pins serve for two independent 4-bit outputs. Figure 10.1.2 shows the configuration of real-time output in the pulse mode 0. (2) Pulse mode 1 The 8-bit pulse output pins serve for a 2-bit and a 6-bit outputs. Figure 10.1.3 shows the configuration of real-time output in the pulse mode 1. Fig. 10.1.1 Block diagram of real-time output per bit Data bus Pulse output data register j Waveform output select bit j Bit i of port P6 direction register T D Q Timer Aj underflow signal P6i/RTP0k, P6i/RTP1k

i = 0–7
j = 0, 1
k = 0–3 Flip-flop Port P6i latch

7721 Group User’s Manual 10–3

Fig. 10.1.2 Configuration of real-time output in pulse mode 0 Fig. 10.1.3 Configuration of real-time output in pulse mode 1 a Port P6i direction register Port P6i latch (i = 0–7) Data bus (even) a a a a P64/RTP10 P65/RTP11 P66/RTP12 P67/RTP13 Timer A1 T D Q T D Q T D Q T D Q b7 b0 Pulse output data register 0 Bit 0 of waveform output select bits P60/RTP00 P61/RTP01 P62/RTP02 P63/RTP03 a a a a T D Q T D Q T D Q T D Q b7 b0 Timer A0 Pulse output data register 1 Bit 1 of waveform output select bits a Port P6i direction register Port P6i latch (i = 0–7) Data bus (even) Pulse output data register 0 Bit 0 of waveform output select bits P60/RTP00 P61/RTP01 a a T D Q T D Q b7 b0 Timer A0 a P62/RTP02 P63/RTP03 P64/RTP10 P65/RTP11 P66/RTP12 P67/RTP13 Bit 1 of waveform output select bits T D Q T D Q T D Q T D Q a a a a a T D Q T D Q b7 b0 Timer A1 Pulse output data register 1

7721 Group User’s Manual10–4

Relevant registers to real-time output are described below.

10.2.1 Real-time output control register

Figure 10.2.1 shows the structure of the real-time output control register. Fig. 10.2.1 Structure of real-time output control register b7 b6 b5 b4 b3 b2 b1 b0 Bit Nothing is assigned. The value is “0” at reading. Bit name Functions At reset RW Pulse output mode select bit Waveform output select bits See the following Table. 00 RW RW 7 to 3 RW Real-time output control register (Address 6216) –Undefined 0 : Pulse mode 0 1 : Pulse mode 1 Note: When using the P60–P67 pins as the pulse output pins for real-time output, set the corresponding bits of the port P6 direction register (address 1016) to “1.” b1 b0 When pulse mode 0 is selected 7/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port Port RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port RTP RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port Port When pulse mode 1 is selected 7/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 RTP RTP Port : This functions as a programmable I/O port. RTP : This functions as a pulse output pin.

7721 Group User’s Manual 10–5

10.2.2 Pulse output data registers 0 and 1

Figure 10.2.2 shows the structure of the pulse output data registers 0 and 1. The bit position of the RTP02 and RTP0 3 pulse output data bits differs according to the pulse mode. Before setting the pulse output data registers 0 and 1, set of the pulse output mode select bit (bit 2 at address 6216). The data written into the pulse output data registers 0 and 1 is output from the corresponding pulse output pins every underflow of Timers A0 and A1. Bit Bit name Functions 7 to 4 RTP0 0 pulse output data bit Pulse output data register 0 (Address 1A16) b1 b0b2b3b4b5b6b7 At reset RW Undefined Undefined Undefined Undefined Undefined 0 : “L” level output 1 : “H” level output WO Note: Use the LDM or STA instruction for writing to this register RTP0 1 pulse output data bit WO WO WO RTP0 2 pulse output data bit (Valid in pulse mode 0) RTP0 3 pulse output data bit (Valid in pulse mode 0) Nothing is assigned. Bit Bit name Functions 0, 1 Nothing is assigned. Pulse output data register 1 (Address 1C16) b1 b0b2b3b4b5b6b7 At reset RW Undefined Undefined Undefined Undefined Undefined 0 : “L” level output 1 : “H” level output WO Note: Use the LDM or STA instruction for writing to this register. WO WO WO RTP0 3 pulse output data bit (Valid in pulse mode 1) RTP0 2 pulse output data bit (Valid in pulse mode 1) RTP1 0 pulse output data bit RTP1 1 pulse output data bit RTP1 2 pulse output data bit RTP1 3 pulse output data bit Undefined Undefined WO WO Fig. 10.2.2 Structure of pulse output data registers 0 and 1

7721 Group User’s Manual10–6

10.2.3 Port P6 direction register

The pulse output pins are shared with port P6. When using these pins as pulse output pins of real-time output, set the corresponding bits of the port P6 direction register to “1” to set these ports for the output mode. Figure 10.2.3 shows the relationship between the port P6 direction register and the pulse output pins. After reset, the state of the port P6 pins are floated since these pins are in the input mode. The output levels of the pulse output pins are undefined until Timer A0 or A1 underflows first after the data for the timer is written. Because the pulse output data registers 0 and 1 are undefined after reset. When these conditions should be avoided, follow the procedure “Processing of avoiding undefined output When reading the port P6 register (address E 16), the output values of the real time output pins can be read out.

10.2.4 Timers A0 and A1

The data written into the pulse output registers 0 and 1 is output from the pulse output pins every underflow of Timer A0 or A1. Refer to section “8.3 Timer mode” for the setting of Timers A0 and A1. Fig. 10.2.3 Relationship between port P6 direction register and pulse output pins Bit Bit name Functions RTP0 0 pin 0 : Input mode 1 : Output mode When using these pins as pulse output pins, set the corresponding bits to “0.” Port P6 direction register (Address 1016) b1 b0b2b3b4b5b6b7 At reset RW RW RW RW RW RW RW RW RW Note: When setting these bits to “0,” the corresponding pins serve as input port (floated) regardless of the state of the waveform output select bits (bits 0 and 1 at address 6216). RTP0 1 pin RTP0 2 pin RTP0 3 pin RTP1 0 pin RTP1 1 pin RTP1 2 pin RTP1 3 pin

7721 Group User’s Manual 10–7

that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Fig. 10.3.1 Initial setting example for registers relevant to real-time output (1) P60–P67 pins functions as the programmable I/O port. Continue to “Figure 10.3.2” Processing of avoiding undefined output before starting pulse output (Note) b7 b0 Set to initial output level of real-time output 0 : “L” level 1 : “H” level RTP0 0 RTP0 1 RTP0 2 RTP0 3 RTP1 0 RTP1 1 RTP1 2 RTP1 3 Port P6 register (Address E16) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting port P6 direction register b7 b0 Set the bits corresponding to the selected pulse output pins to “1.” Note: This processing can be neglected if the system is not affected by undefined output. Setting pulse output mode b7 b0 Real-time output control register (Address 6216)00 Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1 When pulse mode 0 is selected /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting output data 0 : “L” level 1 : “H” level RTP0 0 RTP0 1 RTP0 2 RTP0 3 Pulse output data register 0 (Address 1A16) RTP1 0 RTP1 1 RTP1 2 RTP1 3 5 : It may be either “0” or “1.” /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b0b7 b0b7 RTP0 0 RTP0 1 RTP0 2 RTP0 3 RTP1 0 RTP1 1 RTP1 2 RTP1 3 Port P6 direction register (Address 1016) When pulse mode 1 is selected Setting output data Pulse output data register 1 (Address 1C16)5 0 : “L” level 1 : “H” level 5 : It may be either “0” or “1.” RTP0 0 RTP0 1 0 : “L” level 1 : “H” level Pulse output data register 0 (Address 1A16) Pulse output data register 1 (Address 1C16) 0 : “L” level 1 : “H” level RTP0 2 RTP0 3 RTP1 0 RTP1 1 RTP1 2 RTP1 3

7721 Group User’s Manual10–8

Fig. 10.3.2 Initial setting example for registers relevant to real-time output (2) From preceding “Figure 10.3.1” Processing of avoiding undefined output before starting pulse output (Note) Timer A0 mode register (Address 5616) Timer A1 mode register (Address 5716) Select of count source f2 0 0000 0 0 Set to “000016” b0 b7 b0 (b15) (b8) 0016 0016 b0b7 Interrupt disabled 00 0 No interrupt request Count start register (Address 4016) Timer A0 count start bit 1 : Start counting ] When Timer A0 or A1 underflows, the contents of the pulse output data register 0 or 1 are output from the flip-flop. b0b7 Setting Timers A0, A1 b0b7 Count source select bits 000 0 0 Can be set to “000016”–“FFFF16” (n) b0 b7 b0 (b15) (b8) 0016 0016 b0b7 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6 Continue to “Figure 10.3.3” Note: This processing can be neglected if the system is not affected by undefined output. Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A0 interrupt control register (Address 7516) Timer A1 interrupt control register (Address 7616) Timer A1 count start bit Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit 0 : Stop counting Timer A0 mode register (Address 5616) Timer A1 mode register (Address 5716) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A0 interrupt control register (Address 7516) Timer A1 interrupt control register (Address 7616)

7721 Group User’s Manual 10–9

Fig. 10.3.3 Initial setting example for registers relevant to real-time output (3) When pulse mode 0 is selected Continue to “Figure 10.3.2” /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting real-time output port 0 1 : RTP00–RTP0 3 1 0 : RTP10–RTP1 3 1 1 : RTP00–RTP0 3 and RTP1 0–RTP1 3 Real-time output control register (Address 6216) b1 b0 Pulse mode 0 Waveform output select bits /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b0b7 Pulse mode 1 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting count start bit to “1” Count start register (Address 4016) Timer A0 count start bit Pulse output starts after overflow of Timer A0 or A1/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines When pulse mode 1 is selected Setting real-time output port Real-time output control register (Address 6216) 0 1 : RTP00, RTP01 1 0 : RTP02, RTP03 and RTP1 0–RTP1 3 1 1 : RTP00–RTP0 3 and RTP1 0–RTP1 3 b1 b0 Waveform output select bits Timer A1 count start bit

7721 Group User’s Manual10–10

À When the timer Ai (i = 0, 1) count start bit is set to “1,” the counter starts counting of the count source. \ The contents of pulse output data register i are output from the pulse output pins at every underflow of Timer Ai. The timer is reloaded with the contents of the reload register and continues counting. ´ The timer Ai interrupt request bit is set to “1” when the counter underflows in \ . The interrupt request bit retains “1” until the interrupt request is accepted or it is cleared by software. ˆ Write the next output data into the pulse output data register i during the timer Ai interrupt routine or after the recognition of the timer Ai interrupt request occurrence. Figure 10.4.1 shows an example of real-time output operation. Contents of bits 3–0 of pulse output data register 0 RTP0 3 output RTP0 2 output RTP0 1 output RTP0 0 output Timer A0 interrupt request bit 000316 000016 Undefined ]2 00112 01102 11002 10012 00112Undefined Starts counting Counter contents (Hex.) ]1 : Written by software ]2 : To avoid undefined output for these terms, follow the procedure “Processing of ]3 : Cleared to “0” when interrupt request is accepted or cleared by software. The above figure shows an example of he following conditions:

Pulse mode 0 selected
RTP0 0–RTP0 3 selected
Timer A0 register set value n = 000316 Starts pulse outputting ]1 ]1 ]1 ]1 ]1 Undefined ]2 Undefined ]2 Undefined ]2 ]3 ]3 ]3 ]3 Fig. 10.4.1 Example of real-time output operation

11.1 Overview

11.2 Block description

11.3 Clock synchronous serial I/O mode

[Precautions for clock synchronous serial I/O mode]

11.4 Clock asynchronous serial I/O

(UART) mode CHAPTER 11 SERIAL I/O

7721 Group User’s Manual11–2

Serial I/O consists of 2 channels: UART0 and UART1. They each have a transfer clock generating timer for the exclusive use of them and can operate independently. UART0 and UART1 have the same functions. UARTi (i = 0 and 1) has the following 2 operating modes: (1) Clock synchronous serial I/O mode Transmitter and receiver use the same clock as the transfer clock. Transfer data has a length of 8 bits. (2) Clock asynchronous serial I/O (UART) mode Transfer rate and transfer data format can arbitrarily be set. The user can select a transfer data length of 7 bits, 8 bits, or 9 bits. Figure 11.1.1 shows the transfer data formats in each operating mode. l Clock synchronous serial I/O mode Transfer data length of 8 bits l UART mode Transfer data length of 7 bits Transfer data length of 8 bits Transfer data length of 9 bits Fig. 11.1.1 Transfer data formats in each operating mode

7721 Group User’s Manual 11–3

Figure 11.2.1 shows the block diagram of Serial I/O. Registers relevant to Serial I/O are described below. Data bus (odd) Data bus (even) 0000000 UARTi receive register UARTi receive buffer register UARTi transmit buffer register Receive control circuit Transmit control circuit 1 / (n+1) BRGi Clock synchronous (internal clock selected) UART Clock synchronous UART Clock synchronous (internal clock selected) Clock synchronous (external clock selected) Data bus (odd) Data bus (even) TxD i Transfer clock Transfer clock CLK i BRG count source select bits CTS i / RTSi UARTi transmit register n: Values set in UARTi baud rate register (BRGi) Clock synchronous D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 f16 f64 f512 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Fig. 11.2.1 Block diagram of Serial I/O

7721 Group User’s Manual11–4

11.2.1 UARTi transmit/receive mode register

Figure 11.2.2 shows the structure of UARTi transmit/receive mode register. The serial I/O mode select bits are used to select a UARTi’s operating mode. Bits 4 to 6 are described in section “11.4.2 Transfer data format,” and bit 7 is done in section “11.4.8 Sleep mode.” Serial I/O mode select bits 0 0 0 : Serial I/O disabled (P8 functions as a programmable I/O port.) 0 0 1 : Clock synchronous serial I/O mode 0 1 0 : Do not select. 0 1 1 : Do not select. 1 0 0 : UART mode (Transfer data length = 7 bits) 1 0 1 : UART mode (Transfer data length = 8 bits) 1 1 0 : UART mode (Transfer data length = 9 bits) 1 1 1 : Do not select. Sleep select bit (Valid in UART mode) (Note) Parity enable bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit is “1”) (Note) Stop bit length select bit (Valid in UART mode) (Note) Internal/External clock select bit UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode terminated (Invalid) 1 : Sleep mode selected 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits Fig. 11.2.2 Structure of UARTi transmit/receive mode register

7721 Group User’s Manual 11–5

(1) Internal/External clock select bit (bit 3) n Clock synchronous serial I/O mode By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the count source of the BRGi (described later). The BRGi’s output divided by 2 becomes the transfer clock. Additionally, the transfer clock is output from the CLKi pin. By setting this bit to “1” in order to select an external clock, the clock input to the CLKi pin becomes the transfer clock. n UART mode By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the count source of the BRGi (described later). Then, the CLKi pin functions as a programmable I/O port. By setting this bit to “1” in order to select an external clock, the clock input to the CLKi pin becomes the count source of BRGi. Always in the UART mode, the BRGi’s output divided by 16 becomes the transfer clock.

7721 Group User’s Manual11–6

11.2.2 UARTi transmit/receive control register 0

Figure 11.2.3 shows the structure of UARTi transmit/receive control register 0. For bits 0 and 1, refer to section “11.2.1 (1) Internal/External clock select bit (bit 3).” Fig. 11.2.3 Structure of UARTi transmit/receive control register 0 (1) By clearing this bit to “0” in order to select the CTS function, pins P80 and P84 function as CTS input pins, and the input signal of “L” level to these pins becomes one of the transmission conditions.____ ____ By setting this bit to “1” in order to select the RTS function, pins P80 and P84 become RTS output____ pins. When the receive enable bit (bit 2 at addresses 3516, 3D16) is “0” (reception disabled), the RTS output pin outputs “H” level. ____ In the clock synchronous serial I/O mode, the output level of the RTS pin becomes “L” when reception conditions are satisfied, and it becomes “H” when reception starts. Note that, when an internal clock____ is selected (bit 3 at addresses 3016, 3816 = “0”), the RTS output is undefined. Accordingly, do not____ select the RTS function. ____ In the clock asynchronous serial I/O mode, the output level of the RTS pin becomes “L” when the receive enable bit is set to “1.” It becomes “H” when reception starts and it becomes “L” when reception is completed. (2) Transmit register empty flag (bit 3) This flag is cleared to “0” when the UARTi transmit buffer register’s contents are transferred to the UARTi transmit register. When transmission is completed and the UARTi transmit register becomes empty, this flag is set to “1.” CTS/RTS select bit Bit BRG count source select bits Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b1 b0 0 : CTS function selected 1 : RTS function selected Transmit register empty flag0 : Data present in transmit register (During transmission) 1 : No data present in transmit register (Transmission completed) RW RW RO3 RW 7 to 4 Nothing is assigned. Undefined –

7721 Group User’s Manual 11–7

11.2.3 UARTi transmit/receive control register 1

Figure 11.2.4 shows the structure of UARTi transmit/receive control register 1. For bits 4 to 7, refer to Bit Bit name At reset

5 Framing error flag

(Valid in UART mode) 00 : No framing error 1 : Framing error detected RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Notes 1: Bit 4 is cleared to “0” when the receive enable bit is cleared to “0” or when the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) are cleared to “0002.” Bits 5 and 6 are cleared to “0” when one of the following is performed:

Clearing the receive enable bit to “0”
Reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16) out
Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to “0002” Bit 7 is cleared to “0” when all of bits 4 to 6 become “0.” 2: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.

0 Transmit enable bit 00 : Transmission disabled

1 : Transmission enabled

1 Transmit buffer empty flag 1

0 : Data present in transmit buffer register 1 : No data present in transmit buffer register

2 Receive enable bit 0

0 : Reception disabled 1 : Reception enabled

3 Receive complete flag 0

0 : No data present in receive buffer register 1 : Data present in receive buffer register

4 Overrun error flag 0

0 : No overrun error 1 : Overrun error detected

6 Parity error flag

(Valid in UART mode) 00 : No parity error 1 : Parity error detected

7 Error sum flag

(Valid in UART mode) 0 : No error 1 : Error detected (Notes 1, 2) (Notes 1, 2) (Notes 1, 2) (Note 1) RW RO RW RO RO RO RO RO Fig. 11.2.4 Structure of UARTi transmit/receive control register 1

7721 Group User’s Manual11–8

(1) Transmit enable bit (bit 0) By setting this bit to “1,” UARTi enters the transmission enable state. By clearing this bit to “0” during transmission, UARTi enters the transmission disable state after the transmission which is in progress at that time is completed. (2) Transmit buffer empty flag (bit 1) This flag is set to “1” when data set in the UARTi transmit buffer register is transferred from the UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to “0” when data is set in the UARTi transmit buffer register. (3) Receive enable bit (bit 2) By setting this bit to “1,” UARTi enters the reception enable state. By clearing this bit to “0” during reception, UARTi quits the reception immediately and enters the reception disable state. (4) Receive complete flag (bit 3) This flag is set to “1” when data is ready in the UARTi receive register and that is transferred to the UARTi receive buffer register (i.e., when reception is completed). This flag is cleared to “0” when one of the following is performed:

Reading the low-order byte of the UARTi receive buffer register out
Clearing the receive enable bit (bit 2) to “0”
Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 30 16, 3816) to “0002.”

7721 Group User’s Manual 11–9

11.2.4 UARTi transmit register and UARTi transmit buffer register

Figure 11.2.5 shows the block diagram for the transmitter; Figure 11.2.6 shows the structure of UARTi transmit buffer register. Fig. 11.2.5 Block diagram for transmitter SP SP PAR “0” 2SP 1SP UART 7-bit UART 8-bit UART 7-bit UART 9-bit UART Clock sync. Clock sync. Clock sync. Data bus (even) Data bus (odd) TxD i UARTi transmit register Parity enabled Parity disabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP : Stop bit PAR : Parity bit UARTi transmit buffer register 8-bit UART 9-bit UART Fig. 11.2.6 Structure of UARTi transmit buffer register b7 b0 Bit 8 to 0 At reset Undefined RWFunctions WO b7 b0 (b15) (b8) 15 to 9 –Undefined UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) Nothing is assigned. Transmit data is set. Note: Use the LDM or STA instruction for writing to this register.

7721 Group User’s Manual11–10

Transmit data is set into the UARTi transmit buffer register. Set the transmit data into the low-order byte of this register when the microcomputer operates in the clock synchronous serial I/O mode or when a 7- bit or 8-bit length of transfer data is selected in the UART mode. When a 9-bit length of transfer data is selected in the UART mode, set the transmit data into the UARTi transmit buffer register as follows:

Bit 8 of the transmit data into bit 0 of high-order byte of this register.
Bits 7 to 0 of the transmit data into the low-order byte of this register. The transmit data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit register when the transmission conditions are satisfied, and then it is output from the TxD i pin synchronously with the transfer clock. The UARTi transmit buffer register becomes empty when the data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit register. Accordingly, the user can set the next transmit data. When quitting the transmission which is in progress and setting the UARTi transmit buffer register again, follow the procedure described bellow: À Clear the serial I/O mode select bits (bits 2 to 0 at addresses 30 16, 3816) to “0002” (Serial I/O disabled). \` Set the serial I/O mode select bits again. ´ Set the transmit enable bit (bit 0 at addresses 3516, 3D16) to “1” (transmission enabled) and set transmit data in the UARTi transmit buffer register.

7721 Group User’s Manual 11–11

11.2.5 UARTi receive register and UARTi receive buffer register

Figure 11.2.7 shows the block diagram for the receiver; Figure 11.2.8 shows the structure of UARTi receive buffer register. Fig. 11.2.7 Block diagram for receiver Clock sync. SPSP PAR 2SP 1SP UART 0000000 RxD i D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP : Stop bit PAR : Parity bit 8-bit UART 9-bit UART 7-bit UART 9-bit UART Clock sync. Clock sync. 7-bit UART 8-bit UART Data bus (even) Data bus (odd) UARTi receive register Parity enabled Parity disabled UARTi receive buffer register b7 b0 Bit 8 to 0 At reset Undefined RWFunctions RO b7 b0 (b15) (b8) 15 to 9 – UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) Nothing is assigned. The value is “0” at reading. Receive data is read out from here. Fig. 11.2.8 Structure of UARTi receive buffer register

7721 Group User’s Manual11–12

The UARTi receive register is used to convert serial data which is input to the RxDi pin into parallel data. This register takes in the signal input to the RxDi pin in a unit of 1 bit synchronously with the transfer clock. The UARTi receive buffer register is used to read out receive data. When reception is completed, the receive data which is taken in the UARTi receive register is automatically transferred to the UARTi receive buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data is ready in the UARTi receive register before the data which has been transferred to the UARTi receive buffer register is read out. (i.e., an overrun error occurs.) The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 35 16, 3D 16) to “1” after clearing it to “0.” Figure 11.2.9 shows the contents of the UARTi receive buffer register when reception is completed. Receive data (9 bits) Receive data (8 bits) Receive data (7 bits) In UART mode (Transfer data length : 9 bits) In clock synchronous serial I/O mode In UART mode (Transfer data length : 8 bits) In UART mode (Transfer data length : 7 bits) Same value as bit 7 in low-order byte Same value as bit 6 in low-order byte High-order byte (addresses 3716, 3F16) Low-order byte (addresses 36 16, 3E16) Fig. 11.2.9 Contents of UARTi receive buffer register when reception is completed

7721 Group User’s Manual 11–13

11.2.6 UARTi baud rate register (BRGi)

The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer clock. It has a reload register. Assuming that the value set in the BRGi is “n” (n = “0016” to “FF16”), the BRGi divides the count source frequency by (n + 1). In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and the BRGi’s output divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and the BRGi’s output divided by 16 becomes the transfer clock. The data which is written to the UARTi baud rate register (BRGi) is written to both the timer and the reload register whether transmission/reception is in progress or not. Accordingly, writing to these register must be performed while transmission/reception is stopped. Figure 11.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 11.2.11 shows the block diagram of transfer clock generating section. UART0 baud rate register (Address 3116) UART1 baud rate register (Address 3916) FunctionsBit At reset RW 7 to 0 Can be set to “0016” to “FF16.” Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Undefined WO Note: Writing to this register must be performed while the transmission/reception halts. Use the LDM or STA instruction for writing to this register. Fig. 11.2.10 Structure of UARTi baud rate register (BRGi) BRGi 1/2 Transmit control circuit Receive control circuit Transfer clock for transmit operation Transfer clock for receive operation Transmit control circuit Receive control circuit Transfer clock for transmit operation Transfer clock for receive operation BRGi <Clock synchronous serial I/O mode> <UART mode> fi : Clock selected by BRG count source select bits (f2, f16, f64, or f512) fEXT : Clock input to CLKi pin (external clock) fi fEXT fEXT fi Fig. 11.2.11 Block diagram of transfer clock generating section

7721 Group User’s Manual11–14

11.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers

When using UARTi, 2 types of interrupts, which are UARTi transmit and UARTi receive interrupts, can be used. Each interrupt has its corresponding interrupt control register. Figure 11.2.12 shows the structure of UARTi transmit interrupt control and UARTi receive interrupt control registers. For details about interrupts, refer to “CHAPTER 7. INTERRUPTS.” Fig. 11.2.12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers (1) Interrupt priority level select bits (bits 0 to 2) These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt. When using UARTi transmit/receive interrupts, select one of the priority levels (1 to 7). When a UARTi transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable UARTi transmit/receive interrupts, set these bits to “000 2” (level 0). (2) Interrupt request bit (bit 3) The UARTi transmit interrupt request bit is set to “1” when data is transferred from the UARTi transmit buffer register to the UARTi transmit register. The UARTi receive interrupt request bit is set to “1” when data is transferred from the UARTi receive register to the UARTi receive buffer register. (However, when an overrun error occurs, it does not change.) Each interrupt request bit is automatically cleared to “0” when its corresponding interrupt request is accepted. This bit can be set to “1” or “0” by software. b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit interrupt control register (Address 7116) UART0 receive interrupt control register (Address 7216) UART1 transmit interrupt control register (Address 7316) UART1 receive interrupt control register (Address 7416) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned.

7721 Group User’s Manual 11–15

11.2.8 Port P8 direction register

I/O pins of UARTi are multiplexed with port P8. When using pins P82 and P86 as serial data input pins (RxD i), set the corresponding bits of the port P8 direction register to “0” to set these pins for the input____ ____ mode. When using pins P80, P81, P83 to P85 and P87 as I/O pins (CTSi/RTS i, CLKi, TxDi) of UARTi, these pins are forcibly set as I/O pins of UARTi regardless of the port P8 direction register’s contents. Figure 11.2.13 shows the relationship between the port P8 direction register and UARTi’s I/O pins. For details, refer to the description of each operating mode. Fig. 11.2.13 Relationship between port P8 direction register and UARTi’s I/O pins Bit Corresponding pin Functions CTS 0/RTS 0 pin RxD 0 pin TxD 0 pin CTS 1/RTS 1 pin RxD 1 pin 0 : Input mode 1 : Output mode When using pins P82 and P86 as serial data input pins (RxD0, RxD1), set the corresponding bits to “0.” CLK 1 pin Port P8 direction register (Address 1416) b1 b0b2b3b4b5b6b7 CLK 0 pin TxD 1 pin At reset RW RW RW RW RW RW RW RW RW

7721 Group User’s Manual11–16

Table 11.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 11.3.2 lists the functions of I/O pins in this mode. Table 11.3.1 Performance overview in clock synchronous serial I/O mode Item Transfer data format Transfer rate Transmit/Receive control When selecting internal clock When selecting external clock Functions Transfer data has a length of 8 bits. LSB first BRGi’s output divided by 2 Maximum 5 Mbps CTS function or RTS function can be selected by software. Table 11.3.2 Functions of I/O pins in clock synchronous serial I/O mode Functions Serial data output Serial data input Transfer clock output Transfer clock input ____ CTS input ____ RTS output Pin name TxD i (P83, P87) (Note) RxD i (P82, P86) CLK i (P81, P85) CTS i/RTS i (P80, P84) Method of selection (Dummy data is output when performing only reception.) Port P8 direction register \\ 1’s corresponding bit = “0” (Can be used as an I/O port when performing only transmission.) Internal/External clock select bit \\ 2 = “0” Internal/External clock select bit = “1” CTS/RTS select bit\\ 3 = “0” CTS/RTS select bit = “1” Port P8 direction register\\ 1: address 1416 Internal/External clock select bit\\ 2: bit 3 at addresses 3016, 3816____ ____ CTS/RTS select bit\\ 3: bit 2 at addresses 3416, 3C16 Note: The TxDi pin outputs “H” level until transmission starts after UARTi’s operating mode is selected.

7721 Group User’s Manual 11–17

11.3.1 Transfer clock (Synchronizing clock)

Data transfer is performed synchronously with the transfer clock. For the transfer clock, the user can select whether to generate the transfer clock internally or to input it from the external. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, set the transmit enable bit to “1,” and set dummy data in the UARTi transmit buffer register in order to make the transmit control circuit active. (1) Internal generation of transfer clock The count source selected with the BRG count source select bits is divided by the BRGi, and the BRGi output is further divided by 2. This is the transfer clock. The transfer clock is output from the CLK i pin. [Setting for relevant registers]

Select an internal clock (bit 3 at addresses 3016, 3816 = “0”).
Select the BRGi’s count source (bits 0 and 1 at addresses 3416, 3C16)
Set “division value – 1” (= n; 0016 to FF16) to the BRGi (addresses 3116, 3916). Transfer clock’s frequency =
Enable transmission (bit 0 at addresses 3516, 3D16 = “1”).
Set data to the UARTi transmit buffer register (addresses 3216, 3A16) [Pin’s state]
A transfer clock is output from the CLKi pin.
Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.) (2) Input of transfer clock from the external A clock input from the CLKi pin is the transfer clock. [Setting for relevant registers]
Select an external clock (bit 3 at addresses 30 16, 3816 = “1”).
Enable transmission (bit 0 at addresses 3516, 3D16 = “1”).
Set data to the UARTi transmit buffer register (addresses 3216, 3A16). [Pin’s state]
A transfer clock is input from the CLK i pin.
Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.) fi: Frequency of BRGi’s count source (f2, f16, f64 , f512) fi 2 (n+1)

7721 Group User’s Manual11–18

11.3.2 Method of transmission

Figure 11.3.1 shows an initial setting example for relevant registers when transmitting. Transmission is started when all of the following conditions (À to ´ ) are satisfied. When an external clock is selected, satisfy conditions À to ´ with the following precondition satisfied. <Precondition> The CLK i pin’s input is at “H” level Note: When an internal clock is selected, the above precondition is ignored. À Transmission is enabled (transmit enable bit = “1”). \` Transmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”)_____ ____ ´ The CTS i pin’s input is at “L” level (when the CTS function selected).____ Note: When the CTS function is not selected, condition ´ is ignored. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section “11.3.5 Receive operation.” When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Figure 11.3.2 shows writing data after start of transmission, and Figure 11.3.3 shows detection of transmit completion.

7721 Group User’s Manual 11–19

Fig. 11.3.1 Initial setting example for relevant registers when transmitting UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Transmit data is set. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Transmit enable bit 1: Transmission enabled (In the case of selecting the CTS function, transmission starts when the CTS i pin’s input level is “L.”) UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 BRG count source select bits 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b1 b0 1000 UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 Internal/External clock select bit 0: Internal clock 1: External clock 5 : It may be “0” or “1.” Clock synchronous serial I/O mode 555 UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Can be set to “0016” to “FF16.” ] Necessary only when internal clock is selected. Transmission starts. CTS / RTS select bit 0: CTS function selected 1: RTS function selected (CTS function disabled)

7721 Group User’s Manual11–20

Fig. 11.3.3 Detection of transmit completion [When not using interrupts] [When using interrupts] /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi transmit interrupt UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 Interrupt request bit Checking start of transmission UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Checking completion of transmission Transmit register empty flag 0: During transmitting 1: Transmitting completed Processing at completion of transmission 0: No interrupt requested 1: Interrupt requested (Transmission has started.) A UARTi transmit interrupt request occurs when the transmission starts. Note :This figure shows the bits and registers required for processing. Refer to “Figures 11.3.5 and 11.3.6” for the change of flag state and the occurrence timing of an interrupt request. [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when the UARTi transmit buffer register becomes empty. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi transmit interrupt Note : UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Writing of next transmit data Set transmit data here. UART0 transmit/receive control register 1 (Address 35 ) UART1 transmit/receive control register 1 (Address 3D ) Transmit buffer empty flag 0: Data present in transmit buffer register 1: No data present in transmit buffer register (Writing of next transmit data is possible.) Checking state of UARTi transmit buffer register This figure shows the bits and registers required for processing. Refer to “Figures 11.3.5 and 11.3.6” for the change of flag state and the occurrence timing of an interrupt request. Fig. 11.3.2 Writing data after start of transmission

7721 Group User’s Manual 11–21

11.3.3 Transmit operation

When the transmit conditions described in section “11.3.2 Method of transmission” are satisfied in the case of selecting an internal clock, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed. When the transmit conditions are satisfied and the external clock is input to the CLKi pin in the case of selecting an external clock, the following operations are automatically performed.

The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
The transmit buffer empty flag is set to “1.”
The transmit register empty flag is cleared to “0.”
8 transfer clocks are generated (when an internal clock is selected).
A UARTi transmit interrupt request occurs, and the interrupt request bit is set to “1.” The transmit operations are described below: À Data in the UARTi transmit register is transmitted from the TxD i pin synchronously with the falling edge of the transfer clock. \` This data is transmitted bit by bit sequentially beginning with the least significant bit. ´ When 1-byte data has been transmitted, the transmit register empty flag is set to “1.” This indicates the completion of transmission. Figure 11.3.4 shows the transmit operation. When an internal clock is selected, when the transmit conditions for the next data are satisfied at completion of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the transmit register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the transfer clock stops at “H” level. Fig. 11.3.4 Transmit operation Transfer clock UARTi transmit buffer register
• • D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 7 D 6 D 5 D 4 D 3 D 2 D 7 D 6 D 5 D 4 D 3 Transmit data
• • MSB b7 b0 D 0 D 1 D 2 D 7 LSB UARTi transmit register

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D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc TCLK CLK i TEND i TxD i Transfer clock Transmit enable bit Transmit buffer empty flag Transmit register empty flag UARTi transmit interrupt request bit Data is set in UARTi transmit buffer register. UARTi transmit register UARTi transmit buffer register. Stopped because transmit enable bit = “0.” TENDi: Next transmit conditions are examined when this signal level is “H.” ENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1) /fi 2, f16, f64, f512) Cleared to “0” when interrupt request is accepted or cleared by software. The above timing diagram applies when the following conditions are satisfied: l Internal clock selected l CTS function not selected D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc CTS i CLK i TEND i TxD i Transfer clock Transmit enable bit Transmit buffer empty flag Transmit register empty flag UARTi transmit interrupt request bit TCLK Data is set in UARTi transmit buffer register. UARTi transmit register UARTi transmit buffer register. Stopped because CTSi = “H.” Stopped because transmit enable bit = “0.” TENDi: Next transmit conditions are examined when this signal level is “H.” ENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1) /fi 2, f16, f64, f512) Cleared to “0” when interrupt request is accepted or cleared by software. The above timing diagram applies when the following conditions are satisfied: l Internal clock selected l CTS function selected ____ Fig. 11.3.5 Example of transmit timing (when selecting internal clock, selecting CTS function) ____ Fig. 11.3.6 Example of transmit timing (when selecting internal clock, not selecting CTS function) fi: BRGi count source frequency (f n: Value set in BRGi fi: BRGi count source frequency (f n: Value set in BRGi

7721 Group User’s Manual 11–23

11.3.4 Method of reception

started when all of the following conditions (À to ´ ) are satisfied. When an external clock is selected, satisfy conditions À to ´ with the following precondition satisfied. <Precondition> The CLK i pin’s input is at “H” level. Note: When an internal clock is selected, the above precondition is ignored. À Reception is enabled (receive enable bit = “1”). \` Transmission is enabled (transmit enable bit = “1”). ´ Dummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”) By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section “11.3.5 Receive operation.” When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Figure 11.3.9 shows processing after receive completion.

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Fig. 11.3.7 Initial setting example for relevant registers when receiving (1) ] Necessary only when an internal clock is selected. UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Can be set to 0016 to FF16 . 1000 UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 Internal/External clock select bit 0: Internal clock 1: External clock 5 : It may be “0” or “1.” Clock synchronous serial I/O mode Continued to Figure 11.3.8 on next page. UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 CTS / RTS select bit 0: CTS function selected 1: RTS function selected 55 5 BRG count source select bits b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512

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Fig. 11.3.8 Initial setting example for relevant registers when receiving (2) Port P8 direction register (Address 1416) b7 b0 R XD 0 pin R XD 1 pin From preceding Figure 11.3.7 UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Set dummy data here. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Transmit enable bit 1 : Transmission enabled Receive enable bit 1 : Reception enabled /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Reception starts. Note: Set the receive enable bit and the transmit enable bit to “1” simultaneously.

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Fig. 11.3.9 Processing after receive completion [When not using interrupts] [When using interrupts] A UARTi receive interrupt request occurs when reception is completed. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi receive interrupt Processing after reading out receive data UART0 receive buffer register (Address 3616) UART1 receive buffer register (Address 3E16) b7 b0 Reading of receive data Receive data is read out from here. b7 b0 Checking completion of reception Note :This figure shows the bits and registers required for processing. Refer to “Figure 11.3.12” for the change of flag state and the occurrence timing of an interrupt request. b7 b0 Checking error Overrun error flag 0: No overrun error 1: Overrun error detected UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Receive complete flag 0: Reception not completed 1: Reception completed

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11.3.5 Receive operation

In the case of selecting an internal clock, when the receive conditions described in section “11.3.4 Method of reception” are satisfied, a transfer clock is generated and the reception is started after 1 cycle of the transfer clock has passed. In the case of selecting an external clock, when the receive conditions are satisfied, the UARTi enters the receive enable state and reception is started by input of an external clock to the CLKi pin.____ In the case of selecting an external clock and the RTS function, when the UARTi enters the receive enable____ state, the RTSi pin’s output level becomes “L” to inform the transmitter side that reception is enabled. When____ ____ reception is started, the RTSi pin’s output level becomes “H.” Accordingly, by connecting the RTSi pin to____ the CTSi pin of the transmitter side, the timing of transmission and that of reception can be matched. When____ ____ an internal clock is selected, do not use the RTS function. It is because the RTS output becomes undefined. Figure 11.3.10 shows a connection example. The receive operations are described below: À The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register synchronously with the rising edge of the transfer clock. \ The contents of the UARTi receive register are shifted by 1 bit to the right. ´ Steps À and \ are repeated at each rising edge of the transfer clock. ˆ When 1-byte data is prepared in the UARTi receive register, the contents of this register are transferred to the UARTi receive buffer register. ˜ Simultaneously with step ˆ , the receive complete flag is set to “1,” and a UARTi receive interrupt request occurs and its interrupt request bit is set to “1.” The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register____ is read out. The RTSi pin outputs “H” level until the receive conditions are next satisfied (when selecting____ receive timing (when selecting an external clock). Fig. 11.3.10 Connection example TxD i RxD i CLK i TxD i RxD i CLK i Transmitter side Receiver side CTS i RTS i

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Fig. 11.3.11 Receive operation Fig. 11.3.12 Example of receive timing (when selecting external clock) UARTi receive register D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 0 D 1 D 0 Receive data MSB b7 b0 LSB D 2 D 1 D 0 Transfer clock UARTi receive buffer register

••
•• D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 1/fEXT RTS i CLK i RxD i : When the CLKi pin’s input level is “H,” satisfy the following conditions: l Transmit enable bit → “1” l Receive enable bit → “1” l Writing of dummy data to UARTi transmit buffer register Receive enable bit Transmit enable bit Transmit buffer empty flag Dummy data is set to UARTi transmit buffer register. UARTi transmit register¨← UARTi transmit buffer register Received data taken in UARTi receive register → UARTi receive buffer registerUARTi receive buffer register is read out. Receive complete flag UARTi receive interrupt request bit The above timing diagram applies when the following setting conditions are satisfied: Cleared to “0” when interrupt request is accepted or cleared by software. l External clock selected l RTS function selected fEXT : Frequency of external clock

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11.3.6 Processing on detecting overrun error

In the clock synchronous serial I/O mode, an overrun error can be detected. An overrun error occurs when the next data is prepared in the UARTi receive register with the receive complete flag = “1” (data is present in the UARTi receive buffer register) and next data is transferred to the UARTi receive buffer register, in other words, when the next data is prepared before reading out the contents of the UARTi receive buffer register. When an overrun error occurs, the next receive data is written into the UARTi receive buffer register, and the UARTi receive interrupt request bit is not changed. An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register and the overrun error flag is set to “1.” The overrun error flag is cleared to “0” by clearing the serial I/O mode select bits to “0002” or clearing the receive enable bit to “0.” When an overrun error occurs during reception, initialize the overrun error flag and the UARTi receive buffer register before performing reception again. When it is necessary to perform retransmission owing to an overrun error which occurs in the receiver side, set the UARTi transmit buffer register again before starting transmission again. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below. (1) Method of initializing UARTi receive buffer register À Clear the receive enable bit to “0” (Reception disabled). \ Set the receive enable bit to “1” again (Reception enabled). (2) Method of setting UARTi transmit buffer register again À Clear the serial I/O mode select bits to “000 2” (Serial I/O invalid). \ Set the serial I/O mode select bits to “0012” again. ´ Set the transmit enable bit to “1” (Transmission enabled), and set the transmit data to the UARTi transmit buffer register.

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[Precautions for clock synchronous serial I/O mode] 1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, transmit operation (setting for transmission) must be performed. In this case, dummy data is output from the TxDi pin. 2. When receiving, simultaneously set the receive enable bit and the transmit enable bit to “1.” 3. When receiving data, write dummy data to the low-order byte of the UARTi transmit buffer register for each reception of 1-byte data. 4. When selecting an external clock, satisfy the following 3 conditions with the input to the CLKi pin = “H” level. <When transmitting> À Set the transmit enable bit to “1.” \ Write transmit data to the UARTi transmit buffer register. ´ Input “L” level to the CTS i pin (when selecting the CTS function). <When receiving> À Set the receive enable bit to “1.” \ Set the transmit enable bit to “1.” ´ Write dummy data to the UARTi transmit buffer register.

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11.4 Clock asynchronous serial I/O (UART) mode

Table 11.4.1 lists the performance overview in the UART mode, and Table 11.4.2 lists the functions of I/O pins in this mode. Table 11.4.1 Performance overview in UART mode Item Transfer data format Transfer rate Error detection Start bit Character bit (Transfer data) Parity bit Stop bit When selecting internal clock When selecting external clock Functions 1 bit 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (Odd or even can be selected.) 1 bit or 2 bits BRGi’s output divided by 16 Maximum 312.5 kbps 4 types (Overrun, Framing, Parity, and Summing) Presence of error can be detected only by checking error sum flag. Table 11.4.2 Functions of I/O pins in UART mode Method of selection (Cannot be used as a programmable I/O port even when performing only reception.) Port P8 direction register \\ 1’s corresponding bit = “0” (Can be used as a programmable I/O port when performing only transmission.) Internal/External clock select bit\\ 2 = “0” Internal/External clock select bit = “1” CTS/RTS function select bit\\ 3 = “0” CTS/RTS function select bit = “1” Pin name TxD i (P83, P87) (Note 1) RxD i (P82, P86) CLK i (P81, P85) CTS i/RTS i (P80, P84) (Note 2) Functions Serial data output Serial data input Programmable I/O port BRGi’s count source input ____ CTS input ____ RTS output Port P8 direction register\\ 1: address 1416 Internal/External clock select bit\\ 2: bit 3 at addresses 3016, 3816____ ____ CTS/RTS select bit\\ 3: bit 2 at addresses 3416, 3C16 Notes 1: The TxDi pin outputs “H” level while transmission is not performed after selecting UARTi’s operating 2: The CTS i/RTS i pin can be used as an input port when performing only reception and not using___ ___ the RTS function (when selecting CTS function).

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11.4.1 Transfer rate (Frequency of transfer clock)

The transfer rate is determined by the BRGi (addresses 3116, 3916). When setting “n” into BRGi, BRGi divides the count source frequency by (n + 1). The BRGi’s output is further divided by 16, and the resultant clock becomes the transfer clock. Accordingly, “n” is expressed by the following formula. n = — 1F 16 5 B n: Value set in BRGi (0016 to FF16) F: BRGi’s count source frequency (Hz) B: Transfer rate (bps) An internal clock or an external clock can be selected as the BRGi’s count source with the internal/external clock select bit (bit 3 at addresses 3016, 3816). When an internal clock is selected, the clock selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the BRGi’s count source. When an external clock is selected, the clock input to the CLKi pin becomes the BRGi’s count source. examples of transfer rate. Table 11.4.3 Setting examples of transfer rate (1) BRGi’s set value : n 79 (4F16) 159 (9F16) 79 (4F16) 39 (2716) 159 (9F16) 79 (4F16) 52 (3416) 39 (2716) 19 (1316) Actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14490.57 19200.00 38400.00 BRGi’s count source f64 f16 f16 f16 BRGi’s set value : n 80 (5016) 162 (A216) 80 (5016) 40 (2816) 162 (A216) 80 (5016) 53 (3516) 40 (2816) 24 (1816) Actual time (bps) 301.41 599.12 1205.63 2381.86 4792.94 9645.06 14467.59 19054.58 31250.00 BRGi’s count source f64 f16 f16 f16 f(XIN) = 25 MHzf(XIN) = 24.576 MHzTransfer rate (bps) 300 600 1200 2400 4800 9600 14400 19200 31250 38400 BRGi’s set value : n 71 (4716) 143 (8F16) 71 (4716) 35 (2316) 143 (8F16) 71 (4716) 47 (2F16) 35 (2316) 23 (1716) 21 (1516) 17 (1116) 11 (0B16) 5 (0516) 2 (0216) Actual time (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14400.00 19200.00 28800.00 31418.18 38400.00 57600.00 115200.00 230400.00 BRGi’s count source f64 f16 f16 f16 f(XIN) = 22.1184 MHzTransfer rate (bps) 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 57600 115200 230400 Table 11.4.4 Setting examples of transfer rate (2)

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11.4.2 Transfer data format

The transfer data format can be selected from formats shown in Figure 11.4.1. Bits 4 to 6 at addresses 3016 and 3816 select the transfer data format. (Refer to “Figure 11.2.2.”) Set the same transfer data format for both transmitter and receiver sides. Transfer data length of 7 bits 1ST—7DATA 1SP 1ST—7DATA 2SP 1ST—7DATA—1PAR—1SP 1ST—7DATA—1PAR—2SP Transfer data length of 8 bits 1ST—8DATA 1SP 1ST—8DATA 2SP 1ST—8DATA—1PAR—1SP 1ST—8DATA—1PAR—2SP Transfer data length of 9 bits 1ST—9DATA 1SP 1ST—9DATA 2SP 1ST—9DATA—1PAR—1SP 1ST—9DATA—1PAR—2SP ST : Start bit DATA : Character bit (Transfer data) PAR : Parity bit SP : Stop bit Fig. 11.4.1 Transfer data format Name ST Start bit DATA Character bit PAR Parity bit SP Stop bit Functions “L” signal equivalent to 1 character bit which is added immediately before the character bits. It indicates start of data transmission. Transmit data which is set in the UARTi transmit buffer register. A signal that is added immediately after the character bits in order to improve data reliability. The level of this signal changes according to selection of odd/even parity in such a way that the sum of “1”s in this bit and character bits is always an odd or even number. “H” level signal equivalent to 1 or 2 character bits which is added immediately after the character bits (or parity bit when parity is enabled). It indicates finish of data transmission. Fig. 11.4.2 Example of transfer data format Table 11.4.5 Each bit in transmit data Time

For the case where 1ST–8DATA–1PAR–1SP ST LSB MSB PAR SP ST Transmit/Receive data DATA (8 bits) Next transmit/receive data (When continuously transferring)

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11.4.3 Method of transmission

Figure 11.4.3 shows an initial setting example for relevant registers when transmitting. The difference due to selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data length. When selecting a 7- or 8-bit data length, set the transmit data into the low-order byte of the UARTi transmit buffer register. When selecting a 9-bit data length, set the transmit data into the low-order byte and bit 0 of the high-order byte. Transmission is started when all of the following conditions (À to ´ ) are satisfied: À Transmit is enabled (transmit enable bit = “1”). \` Transmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”). ´ The CTS i pin’s input is at “L” level (when the CTS function selected).____ Note: When the CTS function is not selected, condition ´ is ignored. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section “11.4.6 Receive operation.” When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Figure 11.4.4 shows writing data after start of transmission, and Figure 11.4.5 shows detection of transmit completion.

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Fig. 11.4.3 Initial setting example for relevant registers when transmitting UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916 b7 b0 Can be set to 0016 to FF16. Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Transmit enable bit 1: Transmission enabled Transmission starts. UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) b7 b0 Set transmit data here. UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 Internal/External clock select bit 0: Internal clock 1: External clock 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity disabled 1: Parity enabled Sleep select bit 0: Sleep mode terminated (Invalid) 1: Sleep mode selected b2 b1 b0 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 BRG count source select bits CTS /RTS select bit 0: CTS function selected 1: RTS function selected (CTS function disabled) 0 0: f2 0 1: f16 1 0: f64 1 1: f512 b1 b0 (In the case of selecting the CTS function, transmission starts when the CTS i pin’s input level is “L.”) b8b15

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Fig. 11.4.4 Writing data after start of transmission [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when the UARTi transmit buffer register becomes empty./LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi transmit interrupt Note : UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) b7 b0 Writing of next transmit data Set transmit data here. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Transmit buffer empty flag 0: Data present in transmit buffer register 1: No data present in transmit buffer register (Writing of next transmit data is possible.) Checking state of UARTi transmit buffer register This figure shows the bits and registers required for processing. Refer to “Figures 11.4.6 to 11.4.8” for the change of flag state and the occurrence timing of an interrupt request. b8b15

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Fig. 11.4.5 Detection of transmit completion [When not using interrupts] [When using interrupts] /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi transmit interrupt UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 Interrupt request bit Checking start of transmission UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 Checking completion of transmission. Transmit register empty flag 0: During transmission 1: Transmission completed Processing at completion of transmission No interrupt requested Interrupt requested (Transmission has started.) A UARTi transmit interrupt request occurs when transmission starts. Note :This figure shows the bits and registers required for processing. Refer to “Figures 11.4.6 to 11.4.8” for the change of flag state and the occurrence timing of an interrupt request.

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11.4.4 Transmit operation

When the receive conditions described in section “11.4.3 Method of transmission” are satisfied, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock has passed.

The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
The transmit buffer empty flag is set to “1.”
The transmit register empty flag is cleared to “0.”
A UARTi transmit interrupt request occurs and the interrupt request bit is set to “1.” The transmit operations are described below: À Data in the UARTi transmit register is transmitted from the TxD i pin. \` This data is transmitted bit by bit sequentially in order of ST→ DATA (LSB) → •••→ DATA (MSB) → PAR → SP according to the transfer data format. ´ The transmit register empty flag is set to “1” at the center of the stop bit (or the second stop bit when selecting 2-stop bits), indicating completion of transmission. Additionally, whether the transmit conditions for the next data are satisfied or not is examined. When the transmit conditions for the next data are satisfied in step ´ , the start bit is generated following the stop bit, and the next data is transmitted. When performing transmission continuously, set the next transmit data in the UARTi transmit buffer register during transmission (when the transmit register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the TxD i pin outputs “H” level and the transfer clock stops. Figures 11.4.6 and 11.4.7 show examples of transmit timing when the transfer data length = 8 bits, and Figure 11.4.8 shows an example of transmit timing when the transfer data length = 9 bits.

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Fig. 11.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled,____ selecting 1 stop bit, selecting CTS function) Fig. 11.4.6 Example of transmit timing when transfer data length = 8 bits (when parity enabled,____ selecting 1 stop bit, not selecting CTS function) Tc D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP D 0 D 1D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P STSP TENDi TxD i TENDi: Next transmit conditions are examined when this signal level is “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc: 16(n + 1)/fi or 16(n + 1)/fEXT fi: BRGi’s count source frequency (f2, f16, f64, f512) fEXT : BRGi’s count source frequency (external clock) n: Value set in BRGi Transfer clock Transmit enable bit Transmit buffer empty flag Transmit register empty flag UARTi transmit interrupt request bit Data is set in UARTi transmit buffer register. Start bit Parity bit Cleared to “0” when interrupt request is accepted or cleared by software. The above timing diagram applies when the following conditions are satisfied: l Parity enabled l 1 stop bit l CTS function not selected UARTi transmit register UARTi transmit buffer register Stopped because transmit enable bit = “0” Stop bit The above timing diagram applies when the following conditions are satisfied: l Parity enabled l 1 stop bit l CTS function selected Tc D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP D 0 D 1D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP ST TENDi TxD i TENDi: Next transmit conditions are examined when this signal level is “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = 16(n + 1)/fi or 16(n + 1)/fEXT fi: BRGi’s count source frequency (f2, f16, f64, f512) fEXT : BRGi’s count source frequency (external clock) n: Value set in BRGi Transfer clock Transmit buffer empty flag Transmit register empty flag UARTi transmit interrupt request bit Data is set in UARTi transmit buffer register. Start bit Parity bit Cleared to “0” when interrupt request is accepted or cleared by software. UARTi transmit register Stopped because transmit enable bit = “0” Stop bit UARTi transmit buffer register Transmit enable bit CTSi Stopped because CTS = “H”

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The above timing diagram applies when the following conditions are satisfied: l Parity disabled l 2 stop bits l CTS function disabled D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SP D 0 D 1STD 8 SP SP SP Tc TENDi TxD i TENDi: Next transmit conditions are examined when this signal level is “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = 16(n + 1)/fi or 16(n + 1)/fEXT fi: BRGi count source frequency (f2, f16, f64, f512) fEXT : BRGi count source frequency (external clock) n: Value set in BRGi Transfer clock Transmit enable bit Transmit buffer empty flag Transmit register empty flag UARTi transmit interrupt request bit Data is set in UARTi transmit buffer register. Start bit Cleared to “0” when interrupt request is accepted or cleared by software. UARTi transmit register UARTi transmit buffer register Stopped because transmit enable bit = “0”Stop bitStop bit Fig. 11.4.8 Example of transmit timing when transfer data length = 9 bits (when parity disabled,____ selecting 2 stop bits, not selecting CTS function)

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11.4.5 Method of reception

Figure 11.4.9 shows an initial setting example for relevant registers when receiving. Reception is started when all of the following conditions (À and \ ) are satisfied: À Reception is enabled (receive enable bit = “1”). \ The start bit is detected. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section “11.4.6 Receive operation.” When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.” Figure 11.4.10 shows processing after receive completion.

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Fig. 11.4.9 Initial setting example for relevant registers when receiving Reception starts when the start bit is detected. UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Can be set to 0016 to FF16. UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Note: Set the transfer data format in the same way as set on the transmitter side. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Receive enable bit 1: Reception enabled UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 Internal/External clock select bit 0: Internal clock 1: External clock 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity disabled 1: Parity enabled Sleep select bit 0: Sleep mode terminated (Invalid) 1: Sleep mode selected b2b1b0 UART0 transmit/receive control register 0 (Address 34 ) UART1 transmit/receive control register 0 (Address 3C ) b7 b0 BRG count source select bits CTS /RTS select bit 0 : CTS function selected 1 : RTS function selected 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b1b0 Port P8 direction register (Address 1416) b7 b0 RxD 0 pin RxD 1 pin

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Fig. 11.4.10 Processing after receive completion [When not using interrupts] [When using interrupts] A UARTi receive interrupt request occurs when reception is completed. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi receive interrupt Processing after reading out receive data UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) b15 b8 Reading of receive data Read out receive data. b7 b0 0000000 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Receive complete flag 0 : Reception not completed 1 : Reception completed Checking completion of reception UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Checking error Framing error flag Parity error flag Error sum flag 0 : No error 1 : Error detected Note :This figure shows the bits and registers required for processing. Refer to “Figure 11.4.12” for the change of flag state and the occurrence timing of an interrupt request. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Checking error Overrun error flag 0 : No overrun error 1 : Overrun error detected

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11.4.6 Receive operation

When the receive enable bit is set to “1,” the UARTi enters the receive enable state. After this, reception starts when ST is detected and a transfer clock is generated.____ ____ In the case of selecting the RTS function, when the reception is enabled, the RTSi pin’s output level____ becomes “L” to inform the transmitter side that reception is enabled. When reception is started, the RTSi____ ____ pin’s output level becomes “H.” Accordingly, by connecting the RTSi pin to the CTSi pin of the transmitter side, the timing of transmission and that of reception can be matched. Figure 11.4.11 shows an connection example. The receive operation is described below. À The input signal of the RxD i pin is taken into the most significant bit of the UARTi receive register synchronously with the transfer clock’s rising edge. \ The contents of the UARTi receive register are shifted by 1 bit to the right. ´ Steps À and \ are repeated at each rising edge of the transfer clock. ˆ When one set of data has been prepared, in other words, when the shift has been performed several times according to the selected data format, the UARTi receive register’s contents are transferred to the UARTi receive buffer register. ˜ Simultaneously with step ˆ , the receive complete flag is set to “1.” Additionally, a UARTi receive interrupt request occurs and its interrupt request bit is set to “1.” The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register____ ____ is read out. The RTSi pin’s output level becomes “L” simultaneously with step ˜ (when selecting the RTS function). Figure 11.4.12 shows an example of receive timing when the transfer data length = 8 bits. TxD i RxD i TxD i RxD i Transmitter side Receiver side CTS i RTS i Fig. 11.4.11 Connection example

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Fig. 11.4.12 Example of receive timing when transfer data length = 8 bits (when parity disabled,____ selecting 1 stop bit, selecting RTS function) D 0 D 1 D 7RxD i RTS i The above timing diagram applies when the following conditions are satisfied: l Parity disabled l 1 stop bit l RTS function selected BRGi count source Receive enable bit Transfer clock Receive complete flag UARTi receive interrupt request bit Start bit Sampled “L” Received data taken in Stop bit At falling edge of start bit, transfer clock is generated and reception started. UARTi receive register UARTi receive buffer register Cleared to “0” when interrupt request is accepted or cleared by software.

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11.4.7 Processing on detecting error

In the UART mode, 3 types of errors can be detected. Each error can be detected when the data in the UARTi receive register is transferred to the UARTi receive buffer register, and the corresponding error flag is set to “1.” When any error occurs, the error sum flag is set to “1.” Accordingly, presence of errors can be judged by using the error sum flag. Table 11.4.6 lists conditions for setting each error flag to “1” and method for clearing it to “0.” Table 11.4.6 Conditions set to “1” and method cleared to “0” for each error flag Method for being cleared to “0”

Clear the serial I/O mode select bits to “000 2.”
Clear the receive enable bit to “0.”
Clear the serial I/O mode select bits to “0002.”
Clear the receive enable bit to “0.”
Read out the low-order byte of the UARTi receive buffer register.
Clear the serial I/O mode select bits to “0002.”
Clear the receive enable bit to “0.”
Read out the low-order byte of the UARTi receive buffer register.
Clear the all error flags, which are overrun, framing and parity error flags. Error flag Overrun error flag Framing error flag Parity error flag Error sum flag Conditions for being set to “1” When the next data is prepared in the UARTi receive register with the receive complete flag = “1” (i.e., data is present in the UARTi receive buffer register). In other words, when the next data is prepared before the contents of the UARTi receive buffer register are read out. (Note) [UARTi receive interrupt request bit is not changed.] When the number of detected stop bits does not match the set number of stop bits. [UARTi receive interrupt request bit is set to “1.”] When the sum of “1”s in the parity bit and character bits does not match the set number of “1”s. [UARTi receive interrupt request bit is set to “1.”] When 1 or more errors listed above occur. Note: The next data is written into the UARTi receive buffer register. When an error occurs during reception, initialize the error flag and the UARTi receive buffer register, and then perform reception again. When it is necessary to perform retransmission owing to an error which occurs in the receiver side during transmission, set the UARTi transmit buffer register again, and then restarts transmission. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below. (1) Method of initializing UARTi receive buffer register À Clear the receive enable bit to “0” (reception disabled). \ Set the receive enable bit to “1” again (reception enabled). (2) Method of setting UARTi transmit buffer register again À Clear the serial I/O mode select bits to “0002” (serial I/O invalid). \ Set the serial I/O mode select bits again. ´ Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi transmit buffer register.

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11.4.8 Sleep mode

This mode is used to transfer data between the specified microcomputers, which are connected by using UARTi. The sleep mode is selected by setting the sleep select bit (bit 7 at addresses 3016, 3816) to “1” when receiving. In the sleep mode, receive operation is performed when the MSB (D8 when the transfer data is 9 bits length, D7 when it is 8 bits length, D6 when it is 7 bits length) of the receive data is “1.” Receive operation is not performed when the MSB is “0.” (The UARTi receive register’s contents are not transferred to the UARTi receive buffer register. Additionally, the receive complete flag and error flags do not change and a UARTi receive interrupt request does not occur.) The following shows an usage example of the sleep mode when the transfer data is 8 bits length. À Set the same transfer data format for the master and slave microcomputers. Select the sleep mode for the slave microcomputers. \ Transmit data, which has “1” in bit 7 and the address of the slave microcomputer to be communicated in bits 0 to 6, from the master microcomputer to all slave microcomputers. ´ All slave microcomputers receive data of step \ . (At this time, a UARTi receive interrupt request occurs.) ˆ For all slave microcomputers, check in the interrupt routine whether bits 0 to 6 in the receive data match their own addresses. ˜ For the slave microcomputer of which address matches bits 0 to 6 in the receive data, terminate the sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.) By performing steps \ to ˜ , “ the microcomputer which performs transfer” is specified. ¯ Transmit data, which has “0” in bit 7, from the master microcomputer. (Only the microcomputer specified in steps \ to ˜ can receive this data. The other microcomputers do not receive this data.) ˘ By repeating step ¯ , transfer can be performed between two specific microcomputers continuously. When communicating with another microcomputer, perform steps \` to ˜ in order to specify the new slave microcomputer. Fig. 11.4.13 Sleep mode Master Slave BSlave A Slave DSlave C Data is transferred between the master microcomputer and one specific slave microcomputer selected from multiple slave microcomputers.

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12.1 Overview

12.2 Block description

12.3 A-D conversion method

12.4 Absolute accuracy and differential

12.5 One-shot mode

12.6 Repeat mode

12.7 Single sweep mode

12.8 Repeat sweep mode

12.9 Precautions for A-D converter

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Table 12.1.1 lists the performance specifications of the A-D converter. Table 12.1.1 Performance specifications of A-D converter Conversion rate per analog input pin Performance specifications Successive approximation conversion method 8 bits ±3 LSB 8 pins (AN 0 to AN7) (Note ) 57 φAD ] cycles φAD ] : A-D converter’s operation clock The A-D converter has the 4 operation modes listed below.

One-shot mode This mode is used to perform the operation once for a voltage input from one selected analog input pin.
Repeat mode This mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin.
Single sweep mode This mode is used to perform the operation for voltages input from multiple selected analog input pins, one at a time.
Repeat sweep mode This mode is used to perform the operation repeatedly for voltages input from multiple selected analog input pins.

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Figure 12.2.1 shows the block diagram of the A-D converter. Registers relevant to the A-D converter are described below. Fig. 12.2.1 Block diagram of A-D converter AV SS VREF Vref AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7/ADTRG VIN 1/2f2 1/2 AD Decoder Resistor ladder network Successive approximation register A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 A-D register 0 A-D register 1 A-D control register Comparator Selector Data bus (even) A-D sweep pin select register

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12.2.1 A-D control register

Figure 12.2.2 shows the structure of the A-D control register. The A-D operation mode select bit selects the operation mode of the A-D converter. The other bits are described below. Fig. 12.2.2 Structure of A-D control register (1) Analog input select bits (bits 2 to 0) These bits are used to select an analog input pin in the one-shot mode and repeat mode. Pins which are not selected as analog input pins function as programmable I/O ports. These bits must be set again when the user switches the A-D operation mode to the one-shot mode or repeat mode after A-D conversion is performed in the single sweep mode or repeat sweep mode. b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (Address 1E16) Bit A-D conversion frequency ( AD ) select bit A-D conversion start bit Trigger select bit A-D operation mode select bits Bit name At reset Undefined RWFunctions 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected (Note 2) b2 b1 b0 0 : Internal trigger 1 : External trigger 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 : Stop A-D conversion 1 : Start A-D conversion b4 b3 Notes 1: These bits are ignored in the single sweep and repeat sweep mode. (They may be either “0” or “1.”) 2: When an external trigger is selected, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts. Analog input select bits (Valid in one-shot and repeat modes) (Note 1) Undefined Undefined RW RW RW RW RW RW RW RW 0 : f2 divided by 4 1 : f2 divided by 2

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(2) Trigger select bit (bit 5) This bit is used to select the source of trigger occurrence. (Refer to section “(3) A-D conversion start bit.”) (3) A-D conversion start bit (bit 6) l When internal trigger is selected Setting this bit to “1” generates a trigger, causing the A-D converter to start operating. Clearing this bit to “0” causes the A-D converter to stop operating. In the one-shot mode or single sweep mode, this bit is cleared to “0” after the operation is completed. In the repeat mode or repeat sweep mode, the A-D converter continues operating until this bit is cleared to “0” by software. l When external trigger is selected When the AD TRG pin level goes from “H” to “L” with this bit = “1,” a trigger occurs, causing the A-D converter to start operating. The A-D converter stops when this bit is cleared to “0.” In the one-shot mode or single sweep mode, this bit remains set to “1” even after the operation is completed. In the repeat mode or repeat sweep mode, the A-D converter continues operating until this bit is cleared to “0” by software. (4) A-D conversion frequency (φAD ) select bit (bit 7) As listed in Table 12.2.1, the conversion time of the A-D converter varies depending on the operating clock (φAD ) selected by this bit. Since the A-D converter’s comparator consists of capacity coupling amplifiers, keep that φAD ≥ 250 kHz during A-D conversion. Table 12.2.1 Conversion time per one analog input pin (unit: µs) f2/2 28.5 14.25 9.12 f2/4 57.0 28.5 18.24 A-D conversion frequency (φAD ) select bit φAD Conversion time f(XIN) = 8 MHz f(XIN) = 16 MHz f(XIN) = 25 MHz

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12.2.2 A-D sweep pin select register

Figure 12.2.3 shows the structure of the A-D sweep pin select register. Fig. 12.2.3 Structure of A-D control register 1 (1) A-D sweep pin select bits (bits 1 and 0) These bits are used to select analog input pins in the single sweep mode or repeat sweep mode. In the single sweep mode and repeat sweep mode, pins which are not selected as analog input pins function as programmable I/O ports. b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select register (Address 1F16) Bit Bit name At reset Undefined RWFunctions Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”) 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit of the A-D sweep pin select register must be performed while the A-D converter halts. 7 to 2 RW0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) (Note 2) A-D sweep pin select bits (Valid in single sweep and repeat sweep mode ) (Note 1) b1 b0 1 RW Nothing is assigned. –

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12.2.3 A-D register i (i = 0 to 7)

Figure 12.2.4 shows the structure of the A-D register i. When the A-D conversion is completed, the conversion result (contents of the successive approximation register) is stored into this register. Each A- D register i corresponds to an analog input pin (AN i). Fig. 12.2.4 Structure of A-D register i A-D register 0 (Addresses 2016) A-D register 1 (Addresses 2216) A-D register 2 (Addresses 2416) A-D register 3 (Addresses 2616) A-D register 4 (Addresses 2816) A-D register 5 (Addresses 2A16) A-D register 6 (Addresses 2C16) A-D register 7 (Addresses 2E16) Bit 7 to 0 At reset Undefined RWFunctions ROReads an A-D conversion result. b7 b6 b5 b4 b3 b2 b1 b0

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12.2.4 A-D conversion interrupt control register

Figure 12.2.5 shows the structure of the A-D conversion interrupt control register. For details about interrupts, refer to “CHAPTER 7. INTERRUPTS.” Fig. 12.2.5 Structure of A-D conversion interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select an A-D conversion interrupt’s priority level. When using A-D conversion interrupts, select one of the priority levels (1 to 7). When an A-D conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable A-D conversion interrupts, set these bits to “000 2” (level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when an A-D conversion interrupt request occurs. This bit is automatically cleared to “0” when the A-D conversion interrupt request is accepted. This bit can be set to “1” or cleared to “0” by software. b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion interrupt control register (Address 7016) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned.

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12.2.5 Port P7 direction register

Input pins of the A-D converter are multiplexed with port P7. When using these pins as A-D converter’s input pins, set the corresponding bits of the port P7 direction register to “0” to set these port pins for the input mode. Figure 12.2.6 shows the relationship between the port P7 direction register and A-D converter’s input pins. Fig. 12.2.6 Relationship between port P7 direction register and A-D converter’s input pins Bit Corresponding pin Functions AN 0 pin 0 : Input mode 1 : Output mode When using these pins as A-D converter’s input pins, set the corresponding bits to “0.” Port P7 direction register (Address 1116) b1 b0b2b3b4b5b6b7 At reset RW RW RW RW RW RW RW RW RW AN 1 pin AN 2 pin AN 3 pin AN 4 pin AN 5 pin AN 6 pin AN 7/ADTRG pin

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The A-D converter compares the comparison voltage (Vref), which is internally generated according to the contents of the successive approximation register, with the analog input voltage (VIN), which is input from the analog input pin (ANi). By reflecting the comparison result on the successive approximation register, VIN is converted into a digital value. When a trigger is generated, the A-D converter performs the following processing: À Determining bit 7 of the successive approximation register The A-D converter compares Vref with VIN. At this time, the contents of the successive approximation register is “100000002” (initial value). Bit 7 of the successive approximation register changes according to the comparison result as follows: When V ref < VIN, bit 7 = “1” When V ref > VIN, bit 7 = “0” \ Determining bit 6 of the successive approximation register After setting bit 6 of the successive approximation register to “1,” the A-D converter compares Vref with VIN. Bit 6 changes according to the comparison result as follows: When V ref < VIN, bit 6 = “1” When V ref > VIN, bit 6 = “0” ´ Determining bits 5 to 0 of the successive approximation register Operations in \ are performed for bits 5 to 0. When bit 0 is determined, the contents (conversion result) of the successive approximation register is transferred to the A-D register i. The comparison voltage (Vref) is generated according to the latest contents of the successive approximation register. Table 12.3.1 lists the relationship between the successive approximation register’s contents and Vref. Table 12.3.2 lists changes of the successive approximation register and Vref during the A-D conversion. Figure 12.3.1 shows the ideal A-D conversion characteristics. Table 12.3.1 Relationship between successive approximation register’s contents and Vref V REF ] 256 Successive approximation register’s contents: n 1 to 255 5 (n – 0.5) V ref (V) V REF ] : Reference voltage

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Table 12.3.2 Change in successive approximation register and Vref during A-D conversion Successive approximation register Change of Vref A-D converter halt 1st comparison 2nd comparison 3rd comparison 8th comparison Conversion complete VREF 512 VREF VREF VREF VREF – 512 VREF VREF VREF VREF – 512 VREF ± ±2 VREF VREF 256 – 512 VREF [V] [V] [V] [V] [V] VREF•n7=1 VREF

n7=0 VREF VREF
n6=1
n6=0 : : Fig. 12.3.1 Ideal A-D conversion characteristics 0016 0116 0216 0316 FE 16 FF16 Analog input voltage VREF 256 5 1 VREF 256 5 2 VREF 256 5 3 5 253VREF 256 VREF 256 5 254 VREF 256 5 255 VREF VREF 256 5 0.5 ldeal A-D conversion characteristics A-D conversion result FD 16

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12.4 Absolute accuracy and differential non-linearity error

The A-D converter’s accuracy is described below. Refer to section “Appendix 12.3 A-D converter standard characteristics,” also.

12.4.1 Absolute accuracy

The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result and the output code of an A-D converter with ideal characteristics. The analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an A-D converter with ideal characteristics. For example, when V REF = 5.12 V, 1 LSB width is 20 mV, and 0 mV, 20 mV, 40 mV, 60 mV, 80 mV, ... are selected as the analog input voltages. The absolute accuracy = ±3 LSB indicates that when the analog input voltage is 100 mV, the output code expected from an ideal A-D conversion characteristics is “005 16,” however the actual A-D conversion result is between “00216” to “00816.” The absolute accuracy includes the zero error and the full-scale error. The absolute accuracy is degraded when VREF is lowered. Any of the output codes for analog input voltages from VREF to AVCC is “FF16.” 0016 0116 0216 0316 0416 0516 0616 0 20 40 60 80 100 120 140 160 180 200 220 0716 0816 0916 0A16 0B16 +3 LSB –3 LSB Ideal A-D conversion characteristics Analog input voltage (mV) Output code (A-D conversion result) Fig. 12.4.1 Absolute accuracy of A-D converter

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12.4.2 Differential non-linearity error

The differential non-linearity error indicates the difference between the 1 LSB step width (the ideal analog input voltage width while the same output code is expected to output) of an A-D converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). For example, when VREF = 5.12 V, the 1 LSB width of an A-D converter with ideal characteristics is 20 mV, however when the differential non-linearity error is ±1 LSB, the actual measured 1 LSB width is 0 to 40 mV. Fig. 12.4.2 Differential non-linearity error 0016 0116 0216 0316 0416 0516 0616 0 20 40 60 80 100 120 140 160 180 0716 0816 0916 Output code (A-D conversion result) Differential non-linearity error Analog input voltage (mV)

1 LSB width with ideal

A-D conversion characteristics

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In the one-shot mode, the operation for the input voltage from the one selected analog input pin is performed once, and the A-D conversion interrupt request occurs when the operation is completed.

12.5.1 Settings for one-shot mode

Figure 12.5.1 shows an initial setting example for registers relevant to the one-shot mode. When using an interrupt, it is necessary to set the relevant registers to enable the interrupt. Refer to “CHAPTER 7. INTERRUPTS” for more descriptions.

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Fig. 12.5.1 Initial setting example for registers relevant to one-shot mode b7 b0 A-D control register (address 1E16)000 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected b1 b0b2 Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0: Stop A-D conversion Analog input select bits A-D conversion frequency (AD ) select bit 0 : f2 divided by 4 1 : f2 divided by 2 l A-D control register One-shot mode Note : Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts (before a trigger occurs). l Interrupt priority level b7 b0 A-D conversion interrupt control register (address 7016) Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt. Set to a level 0 when disabling this interrupt. l Set A-D conversion start bit to “1” b7 b0 A-D control register (address 1E16)1 A-D conversion start bit When external trigger is selected When internal trigger is selected Input falling edge to AD TRG pin Trigger occur Operation start b7 b0 Port P7 direction register (address 1116) l Port P7 direction register Set the bits corresponding to analog input pins to “0.” Set bit 7 to “0” when selecting external trigger. AN AN 2 AN 3 AN 5 AN 6 AN 7 AN 4 AN 0

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12.5.2 One-shot mode operation description

(1) When an internal trigger is selected À The A-D converter starts operation when the A-D conversion start bit is set to “1.” \ The A-D conversion is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. ´ At the same time as step \ , the A-D conversion interrupt request bit is set to “1.” ˆ The A-D conversion start bit is cleared to “0” and the A-D converter stops operation. (2) When an external trigger is selected _____ À The A-D converter starts operation when the input level to the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.” \ The A-D conversion is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. ´ At the same time as step \ , the A-D conversion interrupt request bit is set to “1.” ˆ The A-D conversion stops. The A-D conversion start bit remains set to “1” after the operation is completed. Accordingly, the_____ operation of the A-D converter can be performed again from step À when the level of the ADTRG pin When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point is cancelled and is restarted from step À . Figure 12.5.2 shows the conversion operation in the one-shot mode. Fig. 12.5.2 Conversion operation in one-shot mode Trigger occur Convert input voltage from AN i pin Conversion result A-D register i A-D conversion interrupt request occurs. A-D converter halt

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In the repeat mode, the operation for the input voltage from the one selected analog input pin is performed repeatedly. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E 16) remains set to “1” until it is cleared to “0” by software, and the operation is performed repeatedly while the A-D conversion start bit is “1.”

12.6.1 Settings for repeat mode

Figure 12.6.1 shows an initial setting example for registers relevant to the repeat mode.

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Fig. 12.6.1 Initial setting example for registers relevant to repeat mode b7 b0 Port P7 direction register (address 1116) l Port P7 direction register Set the bits corresponding to analog input pins to “0.” Set bit 7 to “0” when selecting external trigger. l Set A-D conversion start bit to “1” b7 b0 A-D control register (address 1E16)1 A-D conversion start bit When external trigger is selected When internal trigger is selected Trigger occur Operation start Note : Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts (before a trigger occurs). Input falling edge to AD TRG pin AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 b7 b0 A-D control register (address 1E16)010 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected A-D conversion start bit 0: Stop A-D conversion Analog input select bits A-D conversion frequency (AD ) select bit l A-D control register Repeat mode Trigger select bit 0 : Internal trigger 1 : External triggeer 0 : f 2 divided by 4 1 : f2 divided by 2 b1 b0

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12.6.2 Repeat mode operation description

(1) When an internal trigger is selected À The A-D converter starts operation when the A-D conversion start bit is set to “1.” \ The first A-D conversion is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. ´ The A-D converter repeats operation until the A-D conversion start bit is cleared to “0” by software. The conversion result is transferred to the A-D register i each time the conversion is completed. (2) When an external trigger is selected ____ À The A-D converter starts operation when the input level to the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.” \ The first A-D conversion is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. ´ The A-D converter repeats operation until the A-D conversion start bit is cleared to “0” by software. The conversion result is transferred to the A-D register i each time the conversion is completed. When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point is cancelled and is restarted from step À . Figure 12.6.2 shows the conversion operation in the repeat mode. Trigger occur Convert input voltage from AN i pin Conversion result A-D register i Fig. 12.6.2 Conversion operation in repeat mode

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In the single sweep mode, the operation for the input voltage from multiple selected analog input pins is performed, one at a time. The A-D converter is operated in ascending sequence from the AN0 pin. The A-D conversion interrupt request occurs when the operation for all selected input pins are completed.

12.7.1 Settings for single sweep mode

Figure 12.7.1 shows an initial setting example for registers relevant to the single sweep mode. When using an interrupt, it is necessary to set the relevant registers to enable the interrupt. Refer to “CHAPTER 7. INTERRUPTS” for more information.

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Fig. 12.7.1 Initial setting example for registers relevant to single sweep mode b7 b0 Port P7 direction register (address 1116) l Port P7 direction register Set the bits corresponding to analog input pins to “0.” Set bit 7 to “0” when selecting external trigger. l Set A-D conversion start bit to “1” b7 b0 A-D control register (address 1E16)1 A-D conversion start bit l Interrupt priority level b7 b0 A-D conversion interrupt control register (address 7016) Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt. Set to a level 0 when disabling this interrupt. When external trigger is selected When internal trigger is selected Trigger occur Operation start Note : Writing to each bit (except bit 6) of the A-D control register and each bit of the A-D sweep pin select register must be performed while the A-D converter halts (before a trigger occurs). Input falling edge to AD TRG pin AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 A-D control register (address 1E16) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0–AN 3 (4 pins) 1 0 : AN0–AN 5 (6 pins) 1 1 : AN0–AN 7 (8 pins) b1 b0 Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0: Stop A-D conversion A-D conversion frequency (AD ) select bit 0 : f 2 divided by 4 1 : f2 divided by 2 b7 b0 l A-D control register and A-D sweep pin select register A-D sweep pin select register (address 1F16) b7 b0 100 555 A-D sweep pin select bits 5 : “0” or “1” Single sweep mode

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12.7.2 Single sweep mode operation description

(1) When an internal trigger is selected À The operation for the input voltage from the AN0 pin starts when the A-D conversion start bit is set to “1.” \ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. ´ For all of the selected analog input pins, the A-D conversion is performed. The conversion result is transferred to the A-D register i each time each pin is converted. ˆ When step ´ is completed, the A-D conversion interrupt request bit is set to “1.” ˜ The A-D conversion start bit is cleared to “0” and the A-D converter stops operation. (2) When an external trigger is selected À The A-D converter starts operation for the input voltage from the AN0 pin when the input level to_____ the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.” \ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. ´ For all of the selected analog input pins, the A-D conversion is performed. The conversion result is transferred to the A-D register i each time each pin is converted. ˆ When step ´ is completed, the A-D conversion interrupt request bit is set to “1.” ˜ The A-D conversion stops. The A-D conversion start bit remains set to “1” after the operation is completed. Accordingly, the operation of the A-D converter can be performed again from step À when the level of the ADTRG pin When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point is cancelled and is restarted from step À . Figure 12.7.2 shows the conversion operation in the single sweep mode.

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Convert input voltage from AN 0 pin Conversion result A-D register 0 A-D register i A-D register 1 Conversion result Conversion result A-D converter halt A-D converter interrupt request occur Convert input voltage from AN 1 pin Convert input voltage from AN i pin Fig. 12.7.2 Conversion operation in single sweep mode

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In the repeat sweep mode, the operation for the input voltages from the multiple selected analog input pins is performed repeatedly. The A-D converter is operated in ascending sequence from the AN0 pin. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E16) remains set to “1” until it is cleared to “0” by software, and the operation is performed repeatedly while the A-D conversion start bit is “1.”

12.8.1 Settings for repeat sweep mode

Figure 12.8.1 shows an initial setting example for registers relevant to the repeat sweep mode.

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Fig. 12.8.1 Initial setting example for registers relevant to repeat sweep mode b7 b0 Port P7 direction register (address 1116) l Port P7 direction register Set the bits corresponding to analog input pins to “0.” Set bit 7 to “0” when selecting external trigger. l Set A-D conversion start bit to “1” b7 b0 A-D control register (address 1E16)1 A-D conversion start bit When external trigger is selected When internal trigger is selected Trigger occur Operation start Note : Writing to each bit (except bit 6) of the A-D control register and each bit of the A-D sweep pin select register must be performed while the A-D converter halts (before a trigger occurs). Input falling edge to AD TRG pin AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 A-D control register (address 1E16) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0–AN 3 (4 pins) 1 0 : AN0–AN 5 (6 pins) 1 1 : AN0–AN 7 (8 pins) b1 b0 Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0: Stop A-D conversion A-D conversion frequency (AD ) select bit 0 : f 2 divided by 4 1 : f2 divided by 2 b7 b0 l A-D control register and A-D sweep pin select register A-D sweep pin select register (address 1F16) b7 b0 110 555 A-D sweep pin select bits 5 : “0” or “1” Repeat sweep mode

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12.8.2 Repeat sweep mode operation description

(1) When an internal trigger is selected À The operation for the input voltage from the AN0 pin starts when the A-D conversion start bit is set to “1.” \ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. ´ For all of the selected analog input pins, the A-D conversion is performed. The conversion result is transferred to the A-D register i each time each pin is converted. ˆ For all of the selected analog input pins, the A-D conversion is performed again. ˜ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by software. (2) When an external trigger is selected À The A-D converter starts operation for the input voltage from the AN0 pin when the input level to______ the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.” \ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. ´ For all of the selected analog input pins, the A-D conversion is performed. The conversion result is transferred to the A-D register i each time each pin is converted. ˆ For all of the selected analog input pins, the A-D conversion is performed again. ˜ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by software. When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point is cancelled and is restarted from step À . Figure 12.8.2 shows the conversion operation in the repeat sweep mode.

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Convert input voltage from AN0 pin Conversion result A-D register 0 A-D register i A-D register 1Conversion result Conversion result Convert input voltage from AN1 pin Convert input voltage from ANi pin Fig. 12.8.2 Conversion operation in repeat sweep mode

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Writing to the following must be performed before a trigger occurs (while the A-D converter halts).

Each bit (except bit 6) of the A-D control register
Each bit of the A-D sweep pin select register 2. When an external trigger is selected, the AN7/ADTRG pin is disconnected from the comparator. Therefore, this pin cannot be used as an analog input pin. When the AN 7 pin is selected as an analog input pin while an external trigger is selected, the A-D converter operates, however, an undefined value is stored into the A-D register 7. 3. Refer to “Appendix. 8 Countermeasure against noise” when using the A-D converter.

13.1 Overview

13.2 Block description

[Precautions for DMAC]

13.3 Control

13.4 Operation

[Precautions for 2-bus cycle transfer] [Precautions for 1-bus cycle transfer] [Precautions for burst transfer mode] [Precautions for cycle-steal transfer mode]

13.5 Single transfer mode

13.6 Repeat transfer mode

13.7 Array chain transfer mode

[Precautions for array chain transfer mode]

13.8 Link array chain transfer mode

[Precautions for link array chain transfer mode]

13.9 DMA transfer time

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The DMA controller (hereafter called DMAC) transfers data using the bus and bypassing the CPU. DMAC of the M37721 provides four independent channels of DMA0–DMA3, which have the same function each. In this chapter, the source and destination of each DMA transfer are represented as follows. l Memory A device which needs its own address to be specified Examples: Internal RAM and SFRs, external memory, and memory-mapped I/Os l I/O A device which does not need its own address to be specified Example: External I/O devices

13.1.1 Performance overview

Table 13.1.1 lists the performance overview. Table 13.1.1 DMAC performance overview Item Performance specifications Number of channels Transfer space Number of transfer bytes DMA request source Channel priority Transfer rate Data transfer method Transfer unit Address direction of transfer Transfer mode Continuous transfer mode 4 channels

16 Mbytes (between arbitrary spaces)

Internal 14 sources and External 1 source Fixed or Rotating Maximum of 12.5 Mbytes/sec (at f(X IN) = 25 MHz, 1-bus cycle transfer) Maximum of 6.25 Mbytes/sec (at f(XIN) = 25 MHz, 2-bus cycle transfer) 1-bus cycle or 2-bus cycle transfer 8 or 16 bits Fixed, Forward, or Backward (Directions of source and destination are independently selectable.) Burst transfer or Cycle-steal transfer mode Single transfer, Repeat transfer, Array chain transfer, or Link array chain transfer mode

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13.1.2 Bus use priority levels

The bus use priority levels are fixed by hardware as follows: DRAMC > Hold function > DMAC > CPU (DRAM refresh) Because DMAC has the third priority, it actually operates as follows:

When DRAM refresh request or Hold request is generated during DMA transfer After the transfer of one transfer unit (8-bit or 16-bit data), which is being performed at that time, is complete, DMAC relinquishes the bus to a DRAM refresh or a Hold function. When DMAC regains the right to use bus after the DRAM refresh ends or the Hold state is removed, DMA transfer is restarted at the following address.
When DMA request is generated during DRAM refresh or in Hold state DMAC gains the right to use bus after the DRAM refresh ends or the Hold state is removed.
When DMA request is generated while CPU uses bus Upon end of the bus cycle, DMAC gains the right to use bus if any DRAM refresh request or Hold request is not generated at that time. If a DRAM refresh request or a Hold request is generated when the bus cycle ends, DMAC gains the right to use bus after the DRAM refresh ends or the Hold state is removed. For details, refer to section “13.2.1 Bus access control circuit” and bus request sampling signals in timing diagrams.

13.1.3 Modes

DMAC has the following transfer methods and modes. Because these methods and modes are independent each other, any combination between them is selectable. (1) Data transfer method n 2-bus cycle transfer This is a method used to transfer data between memories. A DMA transfer consumes 2 cycles: a read and a write cycle of data. For details, refer to section “13.4.1 2-bus cycle transfer.” n 1-bus cycle transfer This is a method used to transfer data between a memory and an I/O. A read and write of data is carried out at the same time (in 1-bus cycle), so that high-speed transfer can be accomplished. For details, refer to section “13.4.2 1-bus cycle transfer.” (2) Transfer unit n 8-bit transfer A minimum unit of DMA transfer is 8 bits; that is, an 8-bit data is transferred for one DMA request in the cycle-steal transfer mode. In the burst transfer mode, if a DRAM refresh request or a Hold request is generated during DMA ___ transfer, or if TC input is driven from “H” to “L” to force DMA transfer into termination, DMAC relinquishes the bus after completion of 8-bit data transfer which is being performed at that time. n 16-bit transfer A minimum unit of DMA transfer is 16 bits; that is, a 16-bit data is transferred for one DMA request in the cycle-steal transfer mode. In the burst transfer mode, if a DRAM refresh request or a Hold request is generated during DMA ___ transfer, or if TC input is driven from “H” to “L” to force DMA transfer into termination, DMAC relinquishes the bus after completion of 16-bit data transfer which is being performed at that time.

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(3) Transfer modes n Burst transfer mode When once a DMA request is accepted in this mode, an entire batch of data is transferred. Neither is the right to use bus returned to the CPU, nor the DMA request of the channel with the higher priority is accepted until the transfer is complete. However, if an external source (DMAREQi ) is selected as a DMA request source with the level sense selected, DMA transfer is performed when the DMAREQi pin’s input level is “L,” and the right to use bus is returned to the CPU when the DMAREQi pin’s input level is “H.” Even in this case, any DMA request of the other channels is not accepted until the entire batch of data has been transferred. For details, refer to section “13.4.3 Burst transfer mode.” n Cycle-steal transfer mode For each DMA request, 1 transfer unit of data is transferred. (Hereafter, transferring 1-transfer-unit data, which is 8-bit or 16-bit data in the M37721, is called “1-unit transfer.”) When 1-unit transfer is complete and another DMA request (including that of other channels) is not generated, the DMAC relinquishes the right to use bus to the CPU. In the cycle-steal transfer mode, all of the DMA request sources are available. For details, refer to section “13.4.4 Cycle-steal transfer mode.” Figure 13.1.1 shows the outline of the DMA transfer modes. n Burst transfer mode (External source (DMAREQi), level sense) n Burst transfer mode (Edge sense) Right to use bus (Transfer of entire batch of data) CPU DMAi CPU DMAi DMAREQi input CPU DMAi CPU CPU CPU DMA1DMA0 DMA0 CPU Right to use bus Right to use bus n Cycle-steal transfer mode DMA0 request is accepted. DMA0 request is accepted. DMA1 request is accepted. DMAi request is accepted. (One transfer unit)(One transfer unit) (One transfer unit) Fig. 13.1.1 Outline of DMA transfer modes

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(4) Continuous transfer mode n Single transfer mode 1 block of data is transferred once. For details, refer to section “13.5 Single transfer mode.” n Repeat transfer mode 1 block of data is transferred repeatedly. For details, refer to section “13.6 Repeat transfer mode.” n Array chain transfer mode Several blocks of data are transferred. The transfer parameters (transfer source and destination addresses, the number of transfer bytes) of each block must be located on the memory in series. For details, refer to section “13.7 Array chain transfer mode.” n Link array chain transfer mode Several blocks of data are transferred. Transfer parameters for each block can be located on the memory in separate, in a unit of 1- block’s parameters. For details, refer to section “13.8 Link array chain transfer mode.”

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Source address register 0 (SAR0) Destination address register 0 (DAR0) DMA latch high-order Address bus Decrementer Transfer counter register 0 (TCR0) : Microcomputer’s internal bus Data bus (Odd) Data bus (Even) Transfer counter register 1 (TCR1) Transfer counter register 2 (TCR2) Transfer counter register 3 (TCR3) Source address register 1 (SAR1) Destination address register 1 (DAR1) Source address register 2 (SAR2) Destination address register 2 (DAR2) Source address register 3 (SAR3) Destination address register 3 (DAR3) DMA latch low-order: DMAC’s internal bus Fig. 13.2.1 DMAC block diagram (1) Request source selection Request Enable Channel 0 DMAREQ0 Software Timer A0 TImer A1 Refresh timer DRAM refresh request DRAMC Hold request Hold function Channel priority level determination Array state DMAC Acknowledge signal generation DMAACK0 DMAACK1 DMAACK2 DMAACK3 Bus access control circuit CPU wait request BUS REQUEST (DMAC) ST0 ST1 BIUBUS REQUEST (DRAMC) HOLD f16 Channel 1 Channel 2 Channel 3 BUS REQUEST (Hold) Fig. 13.2.2 DMAC block diagram (2)

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13.2.1 Bus access control circuit

In the M37721, the bus is used by DRAMC, Hold function, DMAC, and CPU. When each request of DRAM refresh, Hold, and DMA is generated, each of DRAMC, Hold function, and DMAC issues its bus request to the bus access control circuit in DMAC. (Refer to “Figure 13.2.2.”) Table 13.2.1 lists the bus request generating sources. Table 13.2.1 Bus request generating sources Bus request BUS REQUEST (DRAMC) BUS REQUEST (Hold) BUS REQUEST (DMAC) Bus request generating source DRAM refresh request (Generated by an underflow of the refresh timer.) Hold request (Generated by “L”-level input to the HOLD pin.) DMA request (Generated by a DMA request source.) The bus access control circuit relinquishes the right to use bus to the function with the highest priority among functions, which issue bus requests when the BUS REQUEST signal is sampled. This is the bus request acceptance. If any bus request is not generated at bus request sampling, the CPU gains the right to use bus. The bus use priority levels are fixed by hardware, and the bus status is reported by status signal outputs ST0 and ST1. Table 13.2.2 lists the relationship between the bus use priority level, bus status, and status signals. Table 13.2.2 Relationship between bus use priority level, bus status, and status signals Bus use priority level 1 (Highest) 4 (Lowest) Bus status DRAM refresh Hold DMAC CPU (Including the term while the CPU does not use the bus; for example, the term when the CPU is calculating and does not use the bus) Status signals ST1 ST0

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Bus request sampling timing After completion of a DRAM refresh cycle Every 1 cycle of φ All except the following At the end of each block All except the following At the end of each block (except the last block) At the end of the last block At an array state When an instruction is fetched into queue buffer At a read from or a write into memory While CPU does not use bus timings of bus request sampling. Also, bus request sampling signals are shown in them. Table 13.2.3 Bus request sampling timing After completion of 1-unit transfer After 1-unit transfer and terminate-processing (3 cycles of φ) etc. are performed sequentially After completion of 1-unit transfer n During transfer in burst transfer mode After the last 1-unit transfer of 1 block, the subsequent 3 cycles of φ, and a read of the first 2 bytes in the array state of the next block are performed sequentially n During transfer in cycle-steal transfer mode After the last 1-unit transfer of 1 block and the subsequent 3 cycles of φ are performed sequentially After 1-unit transfer and terminate-processing (3 cycles of φ) are performed sequentially After a read of 2 bytes of a transfer parameter After completion of 1 bus cycle After completion of 1 bus cycle, or after completion of the second bus cycle if a 16-bit data is accessed in a unit of 8 bits (Note 2). Every 1 cycle of φ Bus user DRAM refresh Hold DMAC CPU S/R (Note 1) Array/ Link (Note 1) Notes 1: S = Single transfer mode, R = Repeat transfer mode, Array = Array chain transfer mode, Link = Link array chain transfer mode 2: This applies when the data bus width is 8 bits or when memory is accessed starting at an odd address. If a DRAM refresh request or a Hold request is generated during a data transfer in the burst transfer mode, the request is accepted at the above-mentioned bus request sampling. Another DMA request (including that of other channels) cannot be accepted until the DMA transfer which is in progress normally terminates or is forced into termination. If a DRAM refresh request, a Hold request or another DMA request (including that of other channels) is generated during a data transfer in the cycle-steal transfer mode, the bus request with the highest priority is accepted at the above-mentioned bus request sampling. (If only several DMA requests are generated, the request of the channel whose priority is highest is accepted.) If any bus request is not generated at the above-mentioned bus sampling, the right to use bus is relinquished to the CPU. Note that no DMA request is accepted in array states.

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Fig. 13.2.3 Timing of bus request sampling The above applies on the following conditions:

Cycle-steal transfer mode
DMA request source = external request (DMAREQi)
1-bus cycle transfer
No Wait E HOLD BUS REQUEST (Hold) Bus request sampling ST1, ST0 When access is complete in 1 bus cycle When 16-bit data is accessed in a unit of 8 bits Transition of right to use bus Refresh E Refresh request BUS REQUEST(DRAMC) Bus request sampling ST1, ST0 (0, 0) Bus used by CPU n DRAM refresh This is the term in which the bus is not used so that samp ing is performed every 1 cycle of . Sampling is performed after completion of Sampling is performed after completion of a refresh cycle. 1 bus cycle. H Hold state H DMA transfer H n Hold n DMA transfer Refresh (1, 1) Hold state E DMAREQi DMAi request bit BUS REQUEST (DMAC) Bus request sampling ST1, ST0 DMA transfer This is the term in which the bus is not used so that sampling is performed every 1 cycle of . This is at Holo l state so that sampling is performed every 1 cycle of . Sampling is performed after completion of 1 bus cycle. This is the term in which the bus is not used so that sampling is performed every 1 cycle of Sampling is performed after completion of Sampling is performed after complet on of 1-unit transfer. 1 bus cycle. n CPU E Bus request sampling ST1, ST0 (1, 1) Bus used by CPU by CPU Bus used by CPU Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus Transition of right to use bus This is the term in which the bus is not used so that sampling is performed every 1 cycle of Sampling is performed after completion of 1 bus cycle. 16-bit data is accessed in a unit of 8 bits, so that sampling is performed after completion of the second bus cycle. Bus used i

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Fig. 13.2.4 Structure of DMAC control register L

13.2.2 DMAC control register L

priority levels,” and bits 4–7 are also in section “13.3.2 DMA requests.” (1) ___ TC pin validity bit (Bit 1) When this bit is set to “1,” port P103 functions as the TC pin. The TC pin is of an N-channel open- drain type and provides the following functions: l Terminal count signal output When the transfer of an entire batch of data is normally terminated, the pin outputs “L” for 1 cycle of φ. (Refer to section “13.3.5 (1) Normal termination.”) l Forced termination signal input ___ When the TC pin’s input level goes from “H” to “L” during DMA transfer, this DMA transfer is forced into termination. (Refer to section “13.3.5 (2) Forced termination.”) Notes 1: The state of bits 4 to 7 is not changed when writing “1” to these bits. 2: • When writing to this register while any of DMAi enable bits (bits 4 to 7 at address 6916) is “1,” use the LDM or STA instruction in m flag = “1.” When DMAi request bit (bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to “1.”

When writing to this register while all of DMAi enable bits (bits 4 to 7 at address 6916) are “0,” m flag may be “0” or “1.” Use the LDM or STA instruction for writing to this register. When DMAi request bit (bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to “1.” 0 : Fixed 1 : Rotating Bit Bit name Functions At reset RW Priority select bit Undefined 0 : No request 1 : Requested (Note 1) DMAC control register L (Address 6816) b1 b0b2b3b4b5b6b7 RW RW 3, 2 0 RW 0 RW TC pin validity bit 0 : Invalid (P103 pin functions as a programmable I/O port (CMOS).) 1 : Valid (P103 pin functions as TC pin (N- channel open-drain).) Nothing is assigned. – DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit 0R W 0 RW

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13.2.3 DMAC control register H

Figure 13.2.5 shows the structure of DMAC control register H. Each of bits 0–3 is a software DMAi (i = 0 to 3) request bit, which corresponds to each channel. When a software DMA source is selected as a DMA request source, each of these bits is valid. (Refer to “13.3.2 DMA requests.”) Bits 4–7 are described in section “13.3.1 DMA enabling.” Fig. 13.2.5 Structure of DMAC control register H 1 : DMA request (Valid when software DMA source is selected.) The value is “0” at reading. Bit Bit name Functions At reset RW Software DMA0 request bit 0 : Disabled 1 : Enabled DMAC control register H (Address 6916) b1 b0b2b3b4b5b6b7 WO RW 0W O

0 RW4

Note: When any of bits 4 to 7 is set to “1,” use the CLB or SEB instruction for writing to this register.

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13.2.4 Source address register i (SARi)

Source address register i (hereafter called SARi) is a 24-bit register with a latch. SARi indicates the transfer source address of the data to be transferred next. The SARi latch has the following functions:

Maintains the value written to the address of SARi (in the single transfer and repeat transfer modes).
Indicates the start address of the transfer parameter memory of the next block (in the array chain transfer and link array chain transfer modes). When a value is written into the address of SARi, the same value is written into SARi and the SARi latch. When writing a value to the address of SARi, all 24 bits must be written. The contents of SARi can be read by reading the address of SARi; however, the value of the SARi latch

13.2.5 Destination address register i (DARi)

Destination address register i (hereafter called DARi) is a 24-bit register with a latch. DARi indicates the transfer destination address of the data to be transferred next. The DARi latch maintains the value written to the address of DARi. When a value is written into the address of DARi, the same value is written into DARi and the DARi latch. When writing a value to the address of DARi, all 24 bits must be written. The contents of DARi can be read by reading the address of DARi; however, the value of the DARi latch

13.2.6 Transfer counter register i (TCRi)

Transfer counter register i (hereafter called TCRi) is a 24-bit register with a latch. TCRi indicates the number of remaining bytes of the block under transfer. The TCRi latch has the following functions:

Maintains the value written to the address of TCRi (in the single transfer and repeat transfer modes).
Indicates the number of remaining blocks (in the array chain transfer mode). When a value is written into the address of TCRi, the same value is written into TCRi and the TCRi latch. When writing a value to the address of TCRi, all 24 bits must be written. The contents of TCRi can be read by reading the address of TCRi; however, the value of the TCRi latch Table 13.2.4 Addresses of SARi, DARi, and TCRi Channel Source address register i (SARi) 1FC2 16–1FC0 16 1FD2 16–1FD0 16 1FE2 16–1FE0 16 1FF2 16–1FF0 16 Destination address register i (DARi) 1FC6 16–1FC4 16 1FD6 16–1FD4 16 1FE6 16–1FE4 16 1FF6 16–1FF4 16 1FCA 16–1FC8 16 1FDA 16–1FD8 16 1FEA 16–1FE8 16 1FFA 16–1FF8 16 Transfer counter register i (TCRi)

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Maintains the transfer start address of the source. Single transfer modeRepeat transfer modeArray chain transfer mode SARi DARi Indicates the transfer source address of the data to be transferred next.SARi SARi latch DARi Indicates the transfer destination address of the data next to be transferred DARi latch Indicates the start address of the transfer parameter memory of the next block. Maintains the transfer start address of the destination. (Not used) TCRi Indicates the number of remaining bytes of the block under transfer.TCRi TCRi latch Table 13.2.5 Functions of SARi, DARi, and TCRi Maintains the byte number of the transfer data. Indicates the number of remaining blocks. (Not used) Link array chain transfer mode (Not used) (Note) Note: Any value other than 0 (00000116–FFFFFF 16) must be written before DAM transfer.

13.2.7 Incrementer/Decrementer

The incrementer/decrementer is a 24-bit register. After every 1-unit transfer, that increments (adds) or decrements (subtract) the contents of SARi and DARi. Table 13.2.6 lists the increment/decrement values. Table 13.2.6 Increment/Decrement values Transfer unit 8 bits 16 bits Address directions Forward Backward + 1 – 1 + 2 – 2

13.2.8 Decrementer

The decrementer is a 24-bit register. After every 1-unit transfer, that decrements the contents of TCRi by 1 when the transfer unit is 8 bits, and by 2 when 16 bits. In the array chain transfer mode, every time a transfer parameter is read, the contents of the TCRi latch are also decremented by 1.

13.2.9 DMA latch

The DMA latch is a 16-bit latch. In 2-bus cycle transfer mode, the DMA latch maintains the value read from the transfer source memory with a read cycle until this value is written into the transfer destination memory. In 1-bus cycle transfer mode, the DMA latch is used to copy data. For copy, refer to section “13.4.2 1-bus cycle transfer.”

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13.2.10 DMAi mode register L

(1) Transfer source address direction select bits (bits 4 and 5) and Transfer destination address direction select bits (bits 6 and 7) Address direction means an order of accessing memory in DMA transfer and is defined as follows:

Fixed direction: an address does not move.
Forward direction: an address moves upward from the specified start address.
Backward direction: an address moves downward from the specified start address. For details, refer to section “13.4.1 (3) Address directions in 2-bus cycle transfer” and section “13.4.2 (3) Address directions in 1-bus cycle transfer.” Fig. 13.2.6 Structure of DMAi mode register L Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Note: When the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set bit 0 to “1.” 0 00 : 16 bits 1 : 8 bits 1 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer 0 : Burst transfer mode 1 : Cycle-steal transfer mode 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. RW RW Number-of-unit-transfer-bits select bit (Note) Transfer method select bit Transfer mode select bit Fix this bit to “0.” Transfer source address direction select bits Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. b5b4 b7b6 RW RW RW RW RW RW

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13.2.11 DMAi mode register H

Figure 13.2.7 shows the structure of DMAi mode register H. Bits 0 and 1 are used in 1-bus cycle transfer. For details, refer to section “13.4.2 1-bus cycle transfer.” Bits 6 and 7 are the bits for selecting the continuous transfer mode. For details, refer to section “13.5 Single transfer mode” through section “13.8 Link array chain transfer mode.” (1) Transfer source wait bit and Transfer destination wait bit (bits 4 and 5) When each of these bits is set to “1,” 1-bus cycle in a DMA transfer consumes 3 cycles of φ, and when cleared to “0,” 2 cycles of φ. These bits are valid for the internal and external areas. In the DRAM area, however, 1-bus cycle consumes 3 cycles of φ regardless of the states of these bits. (Refer to “CHAPTER 14. DRAM CONTROLLER.” ) The wait bit (bit 2 at address 5E16) is invalid in DMA transfer. However, Ready function is still valid in DMA transfer. Fig. 13.2.7 Structure of DMAi mode register H Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Notes 1: Set bit 0 to “0” in 2-bus cycle transfer. 2: Bits 4 and 5 are valid to the external and internal areas. However, DRAM area is always handled with “Wait” regardless of the contents of these bits. The wait bit (bit 2 at address 5E16) is invalid in DMA transfer. 0 00 : From memory to I/O 1 : From I/O to memory 1 Refer to below. RW RW Transfer direction select bit (Used in 1-bus cycle transfer)(Note 1) I/O connection select bit (Valid in 1-bus cycle transfer) Fix these bits to “0.” Transfer source wait bit (Note 2) Continuous transfer mode select bits 0 0 : Single transfer 0 1 : Repeat transfer 1 0 : Array chain transfer 1 1 : Link array chain transfer b7b6 RW RW RW RW RW RW Transfer destination wait bit (Note 2) 0 : Wait 1 : No Wait Setting for I/O connection select bit Transfer method 1-bus cycle transfer 2-bus cycle transfer External data bus width 8 bits 16 bits I/O connection D 0–D 7 D 0–D 15 (16-bit I/0 5 1 or 8-bit I/O 5 2) D 0–D 7 (8-bit I/O) D 8–D 15 (8-bit I/O) Setting for I/O connection select bit It may be either “0” or “1.”

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13.2.12 DMAi control register

(1) DMA request sources.” (1) DMAACKi validity bit (bit 5) When this bit is set to “1,” the corresponding pin of port P9 serves as the DMAACKi pin and outputs “L” during a DMA transfer. For details, refer to each timing diagram of section “13.5 Single transfer mode” through section “13.8 Link array chain transfer mode.” Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) Note: When a certain source other than an external source is selected by bits 0 to 3 or when the cycle-steal transfer mode is selected, set bit 4 to “0.” Level sense can be selected only when both of the external source and the burst transfer mode are selected. 0 0 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion 7, 6 RW RW DMA request source select bits (Note) Edge sense/Level sense select bit (Used when external source and burst transfer mode are selected) (Note) DMAACKi validity bit 0 : Invalid (The pin functions as a programmable I/O port.) 1 : Valid (The pin functions as DMAACKi.) RW RW RW RW Undefined – 0 : Edge sense (Falling edge) 1 : Level sense (“L” level) Nothing is assigned. b3b2b1b0 Fig. 13.2.8 Structure of DMAi control register

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13.2.13 DMAi interrupt control register

Figure 13.2.9 shows the structure of the DMAi interrupt control register. For details about interrupts, refer to “CHAPTER 7. INTERRUPTS.” b7 b6 b5 b4 b3 b2 b1 b0 DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned. Low level High level Fig. 13.2.9 Structure of DMAi interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select a DMAi interrupt’s priority level. When using DMAi interrupts, select one of the priority levels (1 to 7). When a DMAi interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable DMAi interrupts, set these bits to “0002” (level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when a DMAi interrupt request occurs after the DMA transfer is complete. This bit is automatically cleared to “0” when the DMAi interrupt request is accepted. This bit can be set to “1” or cleared to “0” by software.

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13.2.14 Port P9 direction register

I/O pins of DMAi are multiplexed with port P9. When using these pins as the DMAREQi input pins, set the corresponding bits of the port P9 direction register to “0” to set these port pins for the input mode. When using these pins as the DMAACKi output pins, these pins are forcibly set to the DMAACKi output pins regardless of the direction register’s contents. Figure 13.2.10 shows the relationship between the port P9 direction register and DMAi’s I/O pins. Bit Corresponding pin Functions DMAACK0 pin 0 : Input mode 1 : Output mode When using pins P91, P93, P95 and P97 as DMAREQi input pins,set the corresponding bits to “0.” Port P9 direction register (Address 1516) b1 b0b2b3b4b5b6b7 At reset RW RW RW RW RW RW RW RW RW DMAREQ0 pin DMAACK1 pin DMAREQ1 pin DMAACK2 pin DMAREQ2 pin DMAACK3 pin DMAREQ3 pin Fig. 13.2.10 Relationship between port P9 direction register and DMAi’s I/O pins [Precautions for DMAC] Do not access the registers relevant to DMAC by using DMA transfers; the address of the accessing register collides with that of the accessed one on the DMAC internal bus.

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The conditions for performing DMA transfer of DMAi (i = 0–3) are as follows:

Neither a DRAM refresh request nor a Hold request is generated.
A request of the channel with a higher priority than that of DMAi is not generated; or the request is disabled though it has been generated.
DMAi is enabled (DMAi enable bit = “1”).
A DMAi request is generated (DMAi request bit = “1”). The control method for each channel is described below.

13.3.1 DMA enabling

Each of DMA channels 0–3 has a DMAi enable bit (bits 4–7 at address 69 16). Table 13.3.1 lists the conditions for changing each DMAi enable bit. Table 13.3.1 Conditions for changing DMAi enable bit DMAi enable bit Conditions for bit change Is set to “1.” Is cleared to “0.” A write of “1” to the DMAi enable bit

A write of “0” to the DMAi enable bit
Transfer of an entire batch of data is complete (normal termination). ___
A change of TC input level from “H” to “L” during a DMA transfer of DMAi (Note) ___ (Forced termination, when TC pin is valid.) Note: In the burst transfer mode (level sense), however, the term from the DMA transfer start until the transfer completion of an entire batch of data is applied. (It is also valid while the CPU has the right to use bus.)

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13.3.2 DMA requests

(1) DMA request sources DMA request sources are specified by the DMA request source select bits and the edge sense/level sense select bit. (Refer to “Figure 13.2.8.”) Table 13.3.2 lists the conditions for generating a DMA request. Table 13.3.2 Conditions for generating DMA request DMA request sources Condition for generating DMA request Level sense Edge sense External source DMAREQi Software DMAi request Timers A0–A4, Timers B0–B2, UART0, UART1, A-D converter “L”-level input to the DMAREQi pin (only in the burst transfer mode) Change of the DMAREQi input pin’s level from “H” to “L” A write of “1” to the software DMAi request bit (each of bits 0–3 at address 6916; refer to “Figure 13.2.5.”) When the interrupt request bit of each peripheral is set to “1” by the activity of peripherals (If “1” is written to any of these interrupt request bits by software, the DMAi request bit does not change. Also, whatever value within 0–7 an interrupt priority level takes, this does not affect DMA requests.) (2) Change of DMAi request bit A read of the DMAi request bits (each of bits 4–7 at address 68 16) indicates whether the corresponding channel (0–3) is generating its DMA request or not. The DMAi request bit changes synchronized with the falling edge of φ1. Table 13.3.3 lists the conditions for changing the DMAi request bit. Table 13.3.3 Conditions for changing DMAi request bit DMAi request bit Mode Is set to “1.” (Note) Is cleared to “0.” Generation of DMAi request (Refer to “Table 13.3.2.”) Generation of DMAi request (“L”-level input to the DMAREQi pin) Generation of DMAi request (Refer to “Table 13.3.2.”)

Normal termination ___
Change of the TC pin’s input level from “H ”to “L” during ___ DMA transfer (when the TC pin is valid)
“H”-level input to the DMAREQi pin ___
Change of the TC pin’s input level from “H” to “L” (when ___ the TC pin is valid)
A write of “0” to the DMAi request bit
A write of “0” to the DMAi enable bit
Start of 1-unit transfer ___
Change of the TC pin’s input level from “H” to “L” during ___ DMA transfer (when the TC pin is valid)
A write of “0” to the DMAi request bit
A write of “0” to the DMAi enable bit Cycle-steal transfer modeBurst transfer mode Edge sense Level sense Note: While the DMAi enable bit is “0,” the DMAi request bit is not set to “1” even if a DMA request is generated. When the DMAi enable bit is cleared to “0,” also the DMAi request bit is cleared to “0.” However, the DMA request generated while the DMAi enable bit = “0” is maintained; and when the DMAi enable bit is set to “1,” the DMAi request bit is also set to “1,” except for the burst transfer mode (level sense).

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13.3.3 Channel priority levels

When the DMA enable bits of several channels are “1” and their DMA request bits are set to “1,” the request of the channel with the highest priority is accepted first. The fixed or rotating channel priority can be selected by the priority select bit (bit 0 at address 6816). The priority levels themselves cannot be specified arbitrary. The channel priority levels are determined after the DMA requests are determined. (1) Fixed priority The fixed priority is selected when the priority select bit (bit 0 at address 6816) = “0.” In the fixed priority, the channel priority levels are as follows: channel 0 > channel 1 > channel 2 > channel 3. (2) Rotating priority The rotating priority is selected when the priority select bit = “1.” After reset, the priority levels are the same descending order as in the fixed priority: channel 0 > channel 1 > channel 2 > channel 3. Then, after every normal termination of a DMA transfer, the priority levels rotate in such a way that the lowest priority is given to the channel having been performed. When DMA transfer is forced into termination, the channel priority levels does not rotate. Figure 13.3.1 shows an example of determining the channel priority levels.

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l Priority level: Fixed priority Bus request sampling DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Channel priority level : 0 > 1 > 2 > 3 DMA transfer execution channel 120 13 (Nothing) 021 1 03 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 123 13 023 1 33 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines l Priority level: Rotating priority Bus request sampling DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Channel priority level DMA transfer execution channel (Nothing) The above timing diagram applies on the following conditions:

No DRAM refresh request, no Hold request
All of DMAi enable bits are “1.” Fig. 13.3.1 Example of determining channel priority levels

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13.3.4 Processing from DMA request until DMA transfer execution

DMA requests are sampled at every falling edge of φ1; when requested, the DMAi request bit is set to “1.” Then, the channel priority levels and bus use priority levels are determined, and BUS REQUEST (DMAC) goes “1” if any DRAM refresh request or Hold request is not generated (Note). BUS REQUEST (DMAC) signal is sampled while the bus request sampling signal is “1” and is accepted (DMA request acceptance). Figure 13.3.2 shows an example of timing from the determination of a DMA request until the DMA transfer execution. Refer to section “13.9 DMA transfer time” for the time from DMA request generation until the CPU’s regaining the right to use bus via DMA transfer. Note: In the following cases, BUS REQUEST (DMAC) does not go “1.” However, the DMAi request bit remains set to “1.” Accordingly, after completion of each state, the channel priority levels and bus use priority levels are determined, and BUS REQUEST (DMAC) goes “1” if any DRAM refresh request or Hold request is not generated. l When a DMA request is generated during a burst transfer or in an array state (However, if a DRAM refresh request or Hold request is generated during this term, its BUS REQUEST goes “1.”) l When a DMA request is not accepted with a DRAM refresh request or Hold request generated

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Fig. 13.3.2 Example of timing from determination of DMA request until DMA transfer execution The above timing diagram applies on the following conditions:

Single transfer mode, or Repeat transfer mode
2-bus cycle transfer
No Wait
DMAACKi valid, TC valid
External source (DMAREQi)
After DMAi request occurs (“L” is input to the DMAREQi pin.), the right to use bus is relinquished to DMAC at the shortest time. ALE E R/W Address Address/Data DMAi enable bit DMAREQi DMAi request bit BUS REQUEST(DMAC) Bus request sampling DMAACKi TC ST1 ST0 DMAi interrupt request bit PC SAR DAR PC,PG SAR DARData H Transition of right to use bus 1-unit transfer Read cycle Write cycle When DMAi request is sampled at this point Data When Burst transfer mode (edge sense) selected When Burst transfer mode (level sense) selected When Cycle-steal transfer mode selected ]: Channel priority level determination and bus use priority level determination (1.5 cycles of φ)

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13.3.5 Termination of DMA transfer

As the methods of terminating DMA transfer, normal and forced termination are used. (1) Normal termination All of the DMAi transfers terminate and DMAC stops. This method is used in the single transfer, array chain transfer, and link array chain transfer modes. In the repeat transfer mode, however, normal termination cannot be applied to terminating transfer; then, forced termination must be used. (Refer to “(2) Forced termination” of this section.) Table 13.3.4 lists the states of DMAC at normal termination. Table 13.3.4 States of DMAC at normal termination Item State DMAi interrupt request bit DMAi request bit DMAi enable bit ___ TC output Channel priority levels In the burst transfer mode (edge sense): 0 In the burst transfer mode (level sense): not changed In the cycle-steal transfer mode: not changed (Note) ___ Outputs “L” (when the TC pin is valid) Rotating (when the rotating priority is selected) Note: In the cycle-steal transfer mode, the DMAi request bit is cleared to “0” when a DMA request is accepted. This bit is does not change at normal termination. At normal termination, the CPU regains the right to use bus after the terminate processing (3 cycles of φ) via the transition of the right to use bus (1 cycle of φ). Figure 13.3.3 shows a timing example at normal termination.

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The above timing diagram applies on the following conditions:

DMAACKi valid, TC valid
External source (DMAREQi) ALE E R/W Address Address/Data DMAi enable bit DMAi request bit BUS REQUEST (DMAC) Bus request sampling DMAACKi TC ST1 ST0 DMAi interrupt request bit Transition of right to use bus SAR ± 1 SAR ± 1 L When Burst transfer mode (edge sense) selected When Burst transfer mode (level sense) selected When Cycle-steal transfer mode selected Terminate processing Fig. 13.3.3 Timing example at normal termination

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(2) Forced termination The methods of terminating DMAC other than normal termination are as follows:

Drives the TC pin’s input level from “H” to “L” during a DMA transfer (when the TC pin is valid).
Writes “0” to the DMAi enable bit. Table 13.3.5 lists the states of DMAC at forced termination. Table 13.3.5 States of DMAC at forced termination Item State DMAi interrupt request bit DMAi request bit DMAi enable bit ___ TC output Channel priority levels Not changed. Not changed. Not changed. When the TC pin is used for forced termination, select “TC pin valid” (bit 1 at address 6816 = “1”). ___ Forced termination by the TC input is valid in the following cases:
During a DMA transfer in the burst transfer mode (edge sense)
During the term from the DMA transfer start until the transfer completion of an entire batch of data in the burst transfer mode with the level sense selected. (It is also valid while the CPU has the right to use bus). ___
During a DMA transfer in the cycle-steal transfer mode (Forced termination by the TC input is invalid while the CPU has the right to use bus.) ___ The TC pin’s input is determined at the falling edge of φ1, and DMAC will relinquish the right to use bus to the CPU upon completion of the 1-unit transfer under execution at that time. At the forced termination by the DMAi enable bit, “0” is written to this bit at the rising edge of E of a write cycle to the DMAi enable bit. Accordingly, DMAi is disabled after this write.

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13.3.6 DMA transfer restart after termination

(1) Restarting the same DMA transfer as the previous one from the beginning At normal and forced termination, the latches of SARi, DARi, and TCRi maintain their values written before the transfer start. (Refer to “Figure 13.3.4-a.”) Therefore, DMA transfer must be restarted according to the following procedures: l In single or repeat transfer mode Set the DMAi enable bit to “1.” It is not necessary to re-set the values of SARi, DARi, and TCRi by software. (Refer to “Figure 13.3.4-b.”) l In array chain or link array chain transfer mode Re-set the values of SARi and TCRi. Set the DMAi enable bit to “1.” (2) Restarting transfer of data subsequent to one which has been transferred just before forced termination When reading values at the addresses of SARi, DARi, and TCRi after forced termination, the values of these registers (counters) can be read. These read values are the transfer source address, the transfer destination address which were to be transferred subsequently, and the number of remaining bytes. When writing these read values to the addresses of SARi, DARi, and TCRi respectively, the same values are also written to their latches. When setting the DMAi enable bit to “1” under this condition, transfer of data subsequent to one which has been transferred just before forced termination is restarted. (Refer to “Figure 13.3.4-c.”) l In single transfer mode The remaining data can be transferred by the following procedure: Read the values at addresses of SARi, DARi and TCRi. Then, rewrite these values into these addresses. Set the DMAi enable bit to “1.” l In repeat transfer, array chain transfer, and link array chain transfer modes The remaining data of the block that was interrupted by forced termination can be transferred by the following procedure: Switch over the current mode to the single transfer mode. Read the values at addresses of SARi, DARi and TCRi. Then, rewrite these values into these addresses. Set the DMAi enable bit to “1.” (Refer to “Figure 13.3.4-c.”) In order to transfer the next block, switch over the current mode to the previous mode after the above-mentioned transfer is normally terminated. Then, re-set the values of SARi, DARi, and TCRi. In the array chain or the link array chain transfer mode, information such as the next transfer parameters etc. cannot be read from each latch.

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Fig.13.3.4 States of SARi, DARi, TCRi after forced termination Previously written values Latch Register Transfer source/destination address is specified. Contents are updated by incrementer/decrementer and decrementer. a. State at forced termination b. When setting DMAi enable bit to “1” without rewriting values at addresses of SARi, DARi, and TCRi A value read from each latch is used by hardware only at the first 1-unit transfer. The contents updated by the incrementer/decrementer and the decrementer are loaded in each register. Values are used by reading them from registers at the second and the following 1-unit transfers. Latch Register Previously written values Updated contents are written. c. When reading values at addresses of SARi, DARi, and TCRi after forced termination and rewriting them Latch Register Previously written values Written by software Read by software Addresses which were to be transferred subsequently or the number of remaining bytes Addresses which were to be transferred subsequently or the number of remaining bytes Addresses which were to be transferred subsequently or the number of remaining bytes Addresses which were to be transferred subsequently or the number of remaining bytes

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Operation of 1-unit transfer varies according to the data transfer method (2-bus cycle or 1-bus cycle transfer). In addition, how many units of transfer data are transferred for a DMA request varies according to the transfer mode (burst transfer or cycle-steal transfer mode). These data transfer methods and modes are described below. 13.4.1 2-bus cycle transfer When the transfer method select bit (Refer to “Figure 13.2.6.”) = “0,” 2-bus cycle transfer is selected. 2- bus cycle transfer is the method used to transfer data between memories. Since this method has a read and a write cycle, it consumes a minimum of 2 bus cycles for 1-unit transfer. Figure 13.4.1 shows an example of connecting external memories in 2-bus cycle transfer. Fig. 13.4.1 Example of connecting external memories in 2-bus cycle transfer M37721 Address bus E BHE BLE R/W Data bus D8–D 15 Data bus D0–D 7 Transfer source memory (Even address) Transfer source memory (Odd address) Transfer destination memory (Even address) Transfer destination memory (Odd address) Note. The external circuit such as an address latch is disregarded.

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(1) Read cycle SARi SARi latch DARi DARi latch TCRi TCRi latch DMA latch Decrementer DMAC Memory (Transfer source) Transfer source address is specified by SARi (Note). Contents of TCRi are updated by decrementer (Note); when value read from TCRi is “0,” transfer of 1 data block is terminated. Contents of SARi are updated by incrementer/ decrementer. Data is read from memory and maintained in DMA latch. DMAC ] When the transfer unit is 16 bits

When an even address is accessed with 16-bit external data bus width, data can be read or written at 1-bus cycle. Accordingly, the incrementer/decrementer and the decrementer increment or decrement by 2, and sequences through are performed once.
When an odd address is accessed with 16-bit external data bus width or when 8 bits is used as external data bus width, data is read or written at 2-bus cycles, and sequences through or through are repeated twice. The incrementer/decrementer and the decrementer increment or decrement by 1 every time sequences through or through are performed once. Note: In the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read from SARi latch, DARi latch, and TCRi latch are used. (The results obtained by increment or decrement are written to SARi, DARi, and TCRi. Except for the first transfer of the block, the values read from SARi, DARi, and TCRi are used.) (Transfer destination) (2) Write cycle Memory SARi SARi latch DARi DARi latch TCRi TCRi latch DMA latch Incrementer/ Decrementer Decrementer (Transfer source) (Transfer destination) Transfer destination address is specified by DARi (Note). Contents of DARi are updated by incrementer/ decrementer. Contents of DMA latch are written to memory. (1) Register operation in 2-bus cycle transfer Figure 13.4.2 shows a basic operation of registers for 1-unit transfer in 2-bus cycle transfer. For register values to be specified, refer to section “13.5 Single transfer mode” through section “13.8 Link array chain transfer mode.” It is because that these values vary according to continuous transfer modes. In 2-bus cycle transfer, the data read at a read cycle is maintained temporarily in the DMA latch, and the contents of this latch are written to a memory at a write cycle. Fig. 13.4.2 Basic operation of registers for 1-unit transfer in 2-bus cycle transfer

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Read/Write cycle (Unit: φ cycle)Transfer unit 16 bits 8 bits 16 bits 8 bits External bus width 16 bits (including internal bus) 8 bits Address directions Fixed/Forward Backward Fixed/Forward/ Backward Fixed/Forward/ Backward Fixed/Forward/ Backward Even Odd Even Odd Even/Odd Even/Odd Even/Odd Data’s start address DRAM areaFormula 1 + i 2 + 2i 2 + 2i 2 + i 1 + i 2 + 2i 1 + i No Wait 2 (a) 4 (c) 4 (c) 3 (b) 2 (a) 4 (c) 2 (a) With Wait 3 (d) 6 (f) 6 (f) 3 (d) 6 (f) 3 (d) Address directions: Refer to section “13.4.1 (3) Address directions in 2-bus cycle transfer.” i: A term of E = “L” in 1-bus cycle; i = 1 at “No Wait”, and i = 2 at “With Wait” or “DRAM area”. When Ready function is used (Refer to section “3.3 Ready function.”), the number of cycles extended by Ready must be added. ( ): Indicates the corresponding waveform in Figure 13.4.3. Note: When a transfer destination applies to this condition, 2-bus cycle transfer cannot be performed. When a transfer source applies to this condition and a transfer destination is in the DRAM area, 2-bus cycle transfer cannot also be performed. (2) Bus operation in 2-bus cycle transfer The time required for 1-unit transfer in 2-bus cycle transfer is given by the following formula: Transfer time per 1-unit transfer = (Read cycle) + (Write cycle) Since any area can be specified as a transfer source or a transfer destination, a read cycle varies with the conditions of a transfer source, and a write cycle with that of a transfer destination. Table 13.4.1 lists the time required for a read or write cycle per 1-unit transfer in 2-bus cycle transfer, and Figure 13.4.3 shows the bus-cycle operation waveforms in 2-bus cycle transfer. Table 13.4.1 Time required for a read or write cycle per 1-unit transfer in 2-bus cycle transfer 4 (e) 4 (e) (Note)

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E ALE A/D E ALE A/D E ALE A/D E ALE Internal clock (a) A/D E ALE (b) (c) A/D E ALE (d) (e) (f) : Read or write term per 1-unit transfer A D A DA–1 A A ± 1D D A DA–1 A A ± 1DD A D A: Address, D : Data Fig. 13.4.3 Bus-cycle operation waveforms in 2-bus cycle transfer

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(3) Address directions in 2-bus cycle transfer In 2-bus cycle transfer, the address direction of a transfer source and that of a transfer destination each can be selected independently. (Refer to “Figure 13.2.6.”) Addresses move in the specified transfer and examples of transfer result. Tables 13.4.2 Address directions in 2-bus cycle transfer and examples of transfer result (1) High order High order Transfer unit : 8 bits Address direction Transfer source Fixed Forward Backward Transfer unit : 16 bits Transfer sequence Data External data bus width : 16 bits or 8 bits Transfer destination Fixed Fixed Fixed Data arrangement on transfer source memory Data arrangement on transfer source memory Data arrangement on transfer destination memory (transfer result) Transfer sequence Data arrangement on transfer destination memory (transfer result) Data Low order ] Data Low order High order High order ]] Data ] Data Low order Data Low order High order Data Low order High order Data Low order High order ] Data Data Data Data Data Data Data Data Low order Data Low order High order Data Low order High order Data Low order High order ] Data Data Data Data Data Data Data ] ] : Transfer start address

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Tables 13.4.3 Address directions in 2-bus cycle transfer and examples of transfer result (2) Note: The position relationship between low- order byte and high-order byte is not reversed. Transfer unit : 8 bits Address direction Transfer source Transfer unit : 16 bits Transfer sequence External data bus width : 16 bits or 8 bits Transfer destination Data arrangement on transfer source memory Data arrangement on transfer source memory Data arrangement on transfer destination memory (transfer result) Transfer sequence Data arrangement on transfer destination memory (transfer result) Forward Fixed Forward Forward Forward Backward Data 1 Low order High order Data 2 Low order High order Data 3 Low order High order Data 1–3 Low order High order ] ] Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1–6 ] Data 1 Low order High order Data 2 Low order High order Data 3 Low order High order Data 1 Low order High order Data 2 Low order High order Data 3 Low order High order ]] ]] Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 ] Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 ] Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 1 Data 2 Data 3 ] Low order High order Low order High order Low order High order Data 3 Data 2 Data 1 Low order High order Low order High order Low order High order ] : Transfer start address

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Tables 13.4.4 Address directions in 2-bus cycle transfer and examples of transfer result (3) Address direction Transfer source Transfer unit : 16 bits Transfer sequence External data bus width : 16 bits or 8 bits Transfer destination Data arrangement on transfer source memory Data arrangement on transfer source memory Data arrangement on transfer destination memory (transfer result) Transfer sequence Data arrangement on transfer destination memory (transfer result) Transfer unit : 8 bits Backward Fixed ForwardBackward Data 1 Low order High order Data 2 Low order High order Data 3 Low order High order ]Data 1–3 Low order High order Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 1–6 ] Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 Data 2 Data 3 Low order High order Low order High order Low order High order Data 1 Low order High order Data 2 Low order High order Data 3 Low order High order Data 1 Low order High order Data 2 Low order High order Data 3 Low order High order] ] Data 1 Low order High order Data 2 Low order High order Data 3 Low order High order Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1] ] Backward ] : Transfer start address Backward

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[Precautions for 2-bus cycle transfer] When the 16-bit external data bus width = 16 bits and the transfer unit = 16 bits under the following conditions, 2-bus cycle transfer cannot be performed. (Refer to “Table 13.4.1.”)

Conditions for transfer destination Transfer destination = DRAM area, Address direction = Backward, Data’s start address = Odd address
Conditions for transfer source and destination Transfer source = DRAM area, Address direction = Backward, Data’s start address = Odd address Transfer destination = DRAM area

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13.4.2 1-bus cycle transfer When the transfer method select bit (Refer to “Figure 13.2.6.”) = “1,” 1-bus cycle transfer is selected. 1-bus cycle transfer is the method used to transfer data between a memory and an I/O. In this method, a read and write of 1-tansfer-unit data are simultaneously performed during 1-bus cycle. The address bus, BHE , BLE , and R/W indicate the states of memory. Figure 13.4.4 shows an example of connecting external memories and I/Os in 1-bus cycle transfer. I/O M37721 Address bus Data bus (D8–D 15) E BHE BLE R/W DMAACKi DMAREQi I/O Data bus (D0–D 7) Memory(Odd address) Memory (Even address) Note. The external circuit such as an address latch is disregarded. Fig. 13.4.4 Example of connecting external memories and I/Os in 1-bus cycle transfer

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In 1-bus cycle transfer, the following considerations must be taken in designing the system:

Achieve the condition that 1-transfer-unit data can be accessed in 1-bus cycle. (Refer to “Table 13.4.5.”)
Specify the transfer address direction and I/O connections. (Refer to “Figure 13.2.7.”)
Compose the read and write signal generating circuit externally. (These signals are for I/Os.) The M37721 outputs signals to the memory. Accordingly, make sure to compose the circuit which generates write signals for I/Os when the M37721 outputs read signals; which generates read signals for I/Os when the M37721 outputs write signals. Figure 13.4.5 shows an example of the circuit generating a write signal and a read signal for I/Os. M37721 R/W DMAACKi DMAREQi E Read Write I/O Generating circuit for read and write signals to I/Os DMA acknowledge DMA request Fig. 13.4.5 Example of circuit generating write signal and read signal for I/Os

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(1) Register operation in 1-bus cycle transfer Figure 13.4.6 shows a basic operation of registers for 1-unit transfer in 1-bus cycle transfer. For register values to be specified, refer to section “13.5 Single transfer mode” through section “13.8 Link array chain transfer mode.” It is because these values vary depending on each continuous transfer mode. In 1-bus cycle transfer, a read and write of 1-transfer-unit data are simultaneously performed during 1-bus cycle. Fig. 13.4.6 Basic operation of registers for 1-unit transfer in 1-bus cycle transfer Transfer source address is specified by DARi (Note). Contents of TCRi are updated by decrementer (Note); when value read from TCRi is “0,” transfer of 1 data block is terminated. Contents of DARi are updated by incrementer/ decrementer. I/O is specified by DMAACKi. Data is output from I/O and is written to memory simultaneously (R/W = L level). Transfer source address is specified by SARi (Note). Contents of TCRi are updated by decrementer (Note); when value read from TCRi is “0,” transfer of 1 data block is terminated. Contents of SARi are updated by incrementer/ decrementer. I/O is specified by DMAACKi. Data is output from memory and is written to I/O simultaneously (R/W = H level). l When transferring from memory to I/O SARi SARi latch DMA latch DMAC Memory (Transfer source) DMAC I/O DMAACKi I/O DARi DARi latch TCRi TCRi latch (Transfer destination) Incrementer/ Decrementer Decrementer l When transferring from I/O to memory Memory SARi SARi latch DMA latch DMAACKi DARi DARi latch TCRi TCRi latch Incrementer/ Decrementer Decrementer (Transfer source) (Transfer destination) ] When the transfer unit is 16 bits, the incrementer/decrementer and the decrementer increment or decrement by 2. Note: In the single transfer mode and repeat transfer mode, only at the first transfer of the block, the values read from SARi latch, DARi latch, and TCRi latch are used. (The results obtained by increment or decrement are written to SARi, DARi, and TCRi. Except for the first transfer of the block, the values read from SARi, DARi, and TCRi are used.)

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(2) Bus operation in 1-bus cycle transfer The time required for 1-unit transfer in 1-bus cycle transfer is given by the following formulas:

Transfer from memory to I/O: Transfer time per 1-unit transfer = (Read cycle of memory)
Transfer from I/O to memory: Transfer time per 1-unit transfer = (Write cycle of memory) In 1-bus cycle transfer, 1-transfer-unit data is accessed in 1-bus cycle, so that limitations are imposed on the transfer conditions to be applied. Table 13.4.5 lists the conditions of 1-bus cycle transfer and the transfer time per 1-unit transfer, and Figure 13.4.7 shows the bus-cycle operation waveforms in 1-bus cycle transfer. Table 13.4.5 Conditions of 1-bus cycle transfer and Transfer time per 1-unit transfer Transfer unit 16 bits 8 bits 16 bits 8 bits External bus width 16 bits (including internal bus) 8 bits Address directions Fixed/Forward Backward Fixed/Forward/ Backward Fixed/Forward/ Backward Fixed/Forward/ Backward Even Odd Even Odd Even/Odd Even/Odd Even/Odd Data’s start address Read/Write cycle (Unit: φ cycle) Formula 1 + i 2 + i 1 + i 1 + i No Wait 2 (a) 3 (b) 2 (a) 2 (a) With Wait 3 (c) 3 (c) 3 (c) DRAM area 4 (d) Address directions: Refer to section “13.4.2 (3) Address directions in 1-bus cycle transfer.” There is no address direction on the I/O side. i: A term of E = ‘L” in 1-bus cycle; i = 1 at “No Wait”, and i = 2 at “With Wait” or “DRAM area”. When Ready function is used (Refer to section “3.3 Ready function.”), the number of cycles extended by Ready must be added. ( ): Indicates the corresponding waveform in Figure 13.4.7. /: 1-bus cycle transfer cannot be performed. When the external data bus width = 16 bits and the transfer unit = 8 bits are selected, the data bus which the memory uses and the data bus to which I/O is connected may be different. In such a case, data is copied from the data bus of a transfer source to that of a transfer destination by using the DMA latch. For the combination that data copy may occur, data copy delay time t d(data) must be taken into consideration. Table 13.4.6 lists the data flows on the data bus in 1-bus cycle transfer, and Table 13.4.7 lists the outputs of the address bus, the data bus, and the bus control signals in 1-bus cycle transfer.

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E ALE (a) : Transfer term per 1-unit transfer A D A DA–1 A DA–1 A D A : Address, D : Data A/D E ALE (b) A/D E ALE (c) A/D E ALE (d) Fig. 13.4.7 Bus-cycle operation waveforms in 1-bus cycle transfer

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D0–D 7 and D 8–D 15 Even address and Odd address Even address M37721 Memory I/O I/O Data bus D8–D 15 Data bus D0–D 7 M37721 I/O M37721 I/O M37721 M37721 (Note) Note: Data is copied from data bus D0–D 7 to D8–D 15 or from data bus D8–D 15 to D 0–D 7 in the M37721’s DMAC. Note the data copy delay time td(data). M37721 16 bits 16 bits 8 bits Memory Memory Memory Data bus D8–D 15 Data bus D0–D 7 Data bus D8–D 15 Data bus D0–D 7 Odd address I/OMemory Memory 16 bits 8 bits Data bus D 0–D 7 Data bus D 8–D 15 Even address Odd address (Note) Memory Memory I/O Data bus D8–D 15 Data bus D0–D 7 Note: Data is copied from data bus D0–D 7 to D8–D 15 or from data bus D8–D 15 to D 0–D 7 in the M37721’s DMAC. Note the data copy delay time td(data). Data bus D8–D 15 Data bus D0–D 7 Memory Memory 8 bits8 bits Data bus D 0–D 7 Data bus D0–D 7 I/OMemory Even address and Odd address Note: When the memory is the internal memory or SFR, the above case for external data bus width = 16 bits applies. Table 13.4.6 Data flows on data bus in 1-bus cycle transfer

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Output of address bus, data bus, and bus control signals 16 bits 16 bits Data bus D 0–D 7 and D 8–D 15 Data bus D 8–D 15 8 bits Even address and Odd address : When the memory is the internal memory or SFR, data is output. When the memory is the external memory, it enters a floating state. A8/D8–A15/D15 A16/D0–A23/D7 BLE BHE L L Transfer source address Odd address data A8/D8–A15/D15 A16/D0–A23/D7 BLE BHE H L Invalid data BLE BHE H L Odd address data Copy BLE BHE H L BLE BHE H L Data H E R/W Transferred from memory to I/O L L L H L Invalid data H L I/O data H L H L Transferred from I/O to memory 16 bits Transfer source address Even address data Transfer destination address Transfer destination address 16 bits 8 bitsData bus D 0–D 7 Even address Odd address Transfer source address Transfer source address Even address data Transfer destination address Transfer destination address A8/D8–A15/D15 A16/D0–A23/D7 Transfer source address Transfer source address Transfer destination address Transfer destination address Copy Transfer destination address Transfer destination address Copy I/O data A8/D8–A15/D15 A16/D0–A23/D7 Transfer source address Transfer source address Copy Even address data Even address Odd address A8/D8–A15/D15 A16/D0–A23/D7 Transfer source address Transfer source address Odd address data Invalid data Invalid data Transfer destination address Transfer destination address 8 bits8 bits Data bus D 0–D 7 Even address and Odd address A8–A15 A16/D0–A23/D7 Transfer source address Transfer source address Transfer destination address Transfer destination address Table 13.4.7 Outputs of address bus, data bus, and bus control signals in 1-bus cycle transfer

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(3) Address directions in 1-bus cycle transfer In 1-bus cycle transfer, the transfer source and destination address directions of memory are selectable. (Refer to “Figure 13.2.6.”) Addresses move in the specified direction by the transfer unit. Tables 13.4.8 and 13.4.9 list address directions in 1-bus cycle transfer and examples of transfer results. Table 13.4.8 Address directions in 1-bus cycle transfer and examples of transfer results (1) Fixed — Forward — Backward — Data Low order Data Data Data] Transfer unit : 8 bits Address direction Transfer source memory Transfer unit : 16 bits Transfer sequence External data bus width : 16 bits Transfer destination I/O Data arrangement on transfer source memory Data arrangement on transfer source memory Transfer destination I/O Transfer sequence External data bus width : 16 bits or 8 bits Transfer destination I/O High order Low order High order Data 1 Low order High order Data 2 Low order High order Data 3 Low order High order ] Data 1–3 Low order High order ] Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1–6 Data 3 Data 2 Data 1 Low order High order Low order High order Low order High order] Data 1–3 Low order High order ] Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1–6 ] : Transfer start dd

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Table 13.4.9 Address directions in 1-bus cycle transfer and examples of transfer results (2) — Fixed Forward Data ] Data Transfer unit : 8 bits Address direction Transfer unit : 16 bits Transfer sequence External data bus width : 16 bits Transfer source I/O Data arrangement on transfer destination memory (transfer result) Transfer source I/O External data bus width : 16 bits or 8 bits Transfer destination memory Transfer sequence Data arrangement on transfer destination memory (transfer result) Transfer source I/O Data ] Data ] Data Data Low order High order Data Low order High order Data Low order High order Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Low order High order Low order High order Low order High order Low order High order Low order High order Low order High order ] : Transfer start dd Backward— Low order High order

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[Precautions for 1-bus cycle transfer] 1. The area that overlaps with internal RAM and SFRs must not be assigned to an external memory. When the contents in the overlapped area are read, the data of internal RAM or SFRs and that of external memory are simultaneously placed on the data bus; and they collide with each other. 2. For the system that transfers data with 16-bit external data bus width from an external memory to an 8-bit I/O, the external memory must be composed to be read in a unit of 8 bits. If the external memory cannot be read in a unit of 8 bits, the data read from the external memory at data copy collides with the copied data on the data bus. l External data bus width = 16 bits, Transfer unit = 16 bits, Address direction of memory = Fixed or Forward, Data’s start address of memory = Odd l External data bus width = 16 bits, Transfer unit = 16 bits, Address direction of memory = Backward, Data’s start address of memory = Even l External data bus width = 16 bits, Transfer unit = 16 bits, Target memory of DMA transfer = DRAM area, Address direction of memory = Backward, Data’s start address of memory = Odd l External data bus width = 8 bits, Transfer unit = 16 bits

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13.4.3 Burst transfer mode

The burst transfer mode can operate in either edge sense or level sense mode. (1) Burst transfer mode (edge sense) When the transfer mode select bit = “0” and the edge sense/level sense select bit = “0,” this mode In this mode, all of the DMA request sources are available. Figure 13.4.8 shows a transfer example in the burst transfer mode (edge sense). When once a DMA request is accepted in this mode, an entire batch of data is transferred: the right to use bus is not returned to the CPU until the transfer is complete. During a burst transfer, any DMA request (including that of other channels) cannot be accepted. However, the BUS REQUEST signal is sampled basically at every completion of 1-unit transfer. (Refer to “Table 13.2.3.”) When a DRAM refresh request or Hold request is generated at this time, the right to use bus is not returned to the CPU, and the request is accepted. When the transfer of an entire batch of data is complete, the DMAC relinquishes the right to use bus to the CPU. When the next DMA request is generated, the right is once returned to the CPU to sample the DMA request. (2) Burst transfer mode (level sense) When the transfer mode select bit = “0” and the edge sense/level sense select bit = “1 ,” this mode In this mode, only the external source is used as a DMA request source. Set the DMA request source select bits to “0001 2.” (Refer to “Figure 13.2.8.”) Figure 13.4.9 shows a transfer example in the burst transfer mode (level sense). When the DMAREQi pin’s input level = “L,” the DMAi request bit is cleared to “0”; when this pin’s input level = “L,” the DMAi request bit is set to “1.” Therefore, when the DMAREQi pin’s input level is “L” with the DMAi enable bit = “1,” a DMA transfer starts. When the DMAREQi pin’s input level goes from “L” to “H,” the right to use bus will be returned to the CPU at completion of 1-unit transfer under execution at that time. When the DMAREQi pin’s input level goes “L” again, the DMA transfer restarts at the next address. Once a DMAi transfer starts, any DMA request (including that of other channels) cannot be accepted, even if the DMAREQi pin’s input level is “H,” until the transfer is terminated normally or forcibly. However, the BUS REQUEST signal is sampled basically at every completion of 1-unit transfer. (Refer to “Table 13.2.3.”) When a DRAM refresh request or Hold request is generated at this time, the right to use bus is not returned to the CPU, and the request is accepted. When the transfer of an entire batch of data is complete, the DMAC relinquishes the right to the CPU. If the next DMA request is generated, the right is once returned to the CPU to sample the DMA request.

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CPU DMA1 DRAM refresh DMA1CPU DMA0 CPU This example applies on the following conditions:

Channel priority level: Fixed (Channel 0 > Channel 1) DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Right to use bus CPU DMA1 DRAM refresh DMA1 CPU DMA0 CPU Channel 1 This example applies on the following conditions:
Both of DMA0 and DMA1 request sources are external sources.
Channel priority level: Fixed (Channel 0 > Channel 1) Entire data transfer Entire data transferChannel 0 Fig. 13.4.8 Transfer example in the burst transfer mode (edge sense) Fig. 13.4.9 Transfer example in the burst transfer mode (level sense) Channel 1 Entire data transfer Entire data transferChannel 0

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[Precautions for burst transfer mode] 1. In the burst transfer mode (edge sense), the DMAi request bit is cleared to “0” when the transfer of an entire batch of data is complete or the transfer is forced into termination. Therefore, another DMA request of the same channel i is invalid if generated during DMAi transfer. Fig. 13.4.10 Timing when clearing DMAi request bit to “0” in burst transfer mode 2. Because interrupt priority levels are determined while the CPU fetches an operation code, interrupt requests are not accepted during a DMA transfer. In the burst transfer mode (edge sense), therefore, interrupt requests cannot be accepted until the transfer of an entire batch of data is complete or the transfer is forced into termination. E Transition of right to use bus (from DMAC to CPU)1-unit transfer Termination processing DMAi request bit is set to “0.”

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13.4.4 Cycle-steal transfer mode

When the transfer mode select bit = “1” and the edge sense/level sense select bit = “0,” this mode is In this mode, all of the DMA request sources are available. Figure 13.4.11 shows a transfer example in the cycle-steal transfer mode 1-transfer-unit data is transferred for each DMA request. The BUS REQUEST signal is sampled basically at every completion of 1-unit transfer. (Refer to “Table 13.2.3.”) When a DRAM refresh request or Hold request is generated at this time, the right to use bus is not returned to the CPU, and the request is accepted. When several DMA requests are generated, the request of the channel which has the highest priority among them is accepted, and DMA transfer is performed without returning the right to use bus to the CPU. When any request is not generated, the CPU gains the right. CPU DMA1 DRAM refreshCPU CPUDMA0 DMA1 DMA0DMA1 DMA1 DMAREQ0 DMA0 request bit DMA0 enable bit DMAREQ1 DMA1 request bit DMA1 enable bit DRAM refresh request Right to use bus This example applies on the following conditions:

Both of DMA0 and DMA1 request sources are external sources
Channel priority level: Fixed (Channel 0 > Channel 1) Fig. 13.4.11 Transfer example in cycle-steal transfer mode

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[Precautions for cycle-steal transfer mode] 1. When DMA transfers of the same channel are continuously performed In the cycle-steal transfer mode, the DMAi request bit is cleared to “0” in every 1-unit transfer. Also, it takes 1.5 cycles of φ from the generation of a DMA request until that of a BUS REQUEST (DMAC). Therefore, if another DMA request of the same channel i is generated during a DMAi transfer in the cycle- steal transfer mode, any one of the following three cases occurs depending on the timing of request generation:

The DMA request becomes invalid.
The DMA transfer continues without returning the right to use bus.
After returning the right to use bus to the CPU, the DMAC regains the right and restarts the DMA transfer. Fig. 13.4.12 Conditions for performing DMA transfers of the same channel continuously 1-unit transfer E DMA transfers are continuously performed if DMAi request bit becomes “1” during this term (on condition that DMAi request bit becomes “1” at the timing satisfying t su(DRQ – φ1)). After returning the right to use bus to CPU, DMAC regains the right and restarts DMA transfer if DMAi request bit becomes “1” during this term. When a DMAi request is generated at the following timings, it is not in time to the next bus request sampling (]). Therefore, DMAC returns the right to use bus to the CPU. Then, DMAC regains the right and restarts the DMA transfer.
Except for the last 1-unit transfer, 1-bus cycle transfer is selected without Wait.
Except for the last 1-unit transfer, 1-bus cycle transfer is selected with Wait. In addition, a time of 0.5 cycle of φ is less than tsu(DRQ – φ 1). DMAi request is invalid even when DMAi request bit becomes “1.” Bus request sampling (]) DMAi request bit is cleared to “0” during this term.

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When a DMA transfer of another channel is subsequently performed In the cycle-steal transfer mode, it takes 1.5 cycles of φ from the generation of a DMA request until that of a BUS REQUEST (DMAC). Therefore, if a DMA request of another channel is generated during a DMAi transfer in the cycle-steal mode, either one of the following two cases occurs depending on its timing of request generation:

The DMAC performs the DMA transfer subsequently without returning the right to use bus.
After returning the right to use bus to the CPU once, the DMAC regains the right and performs the DMA transfer. Fig. 13.4.13 Conditions for performing DMA transfers of another channel subsequently Bus request sampling 1-unit transfer φ E When a DMA request is generated at the following timing, it is not in time to the next bus request sampling (]). Therefore, DMAC returns the right to use bus to the CPU. Then, the DMAC regains the right and restarts DMA transfer.
Except for the last 1-unit transfer is selected without Wait. In addition, a time of 0.5 cycle of φ is less than tsu(DRQ – φ1). (]) DMA transfer is subsequently performed if DMAi request bit of another channel becomes “1” during this term (on condition that DMAi request bit of another channel becomes “1” at the timing satisfying t su(DRQ – φ1)). After returning the right to use bus to CPU once, DMAC regains the right and restarts DMA transfer if DMAi request bit of another channel becomes “1” during this term.

This mode is used to transfer a block of data once. Table 13.5.1 lists the specifications of the single transfer mode, and Figure 13.5.1 shows the register structures of SARi, DARi, and TCRi in this mode. Table 13.5.1 Specifications of single transfer mode Performance specifications Not required. TCRi = 0 ___ l Falling edge of the TC pin’s input from “H” to “L” ___ (when the TC pin validity bit =“1”) l Write “0” to the DMAi enable bit At normal termination SARi latch: Indicates the transfer start address of data block at the transfer source. SARi: Indicates the address of the next transfer source. DARi latch: Indicates the transfer start address of data block at the transfer destination. DARi: Indicates the address of the next transfer destination. TCRi latch: Indicates the number of transfer bytes. TCRi: Indicates the number of remaining transfer bytes. Item Transfer parameter memory Condition of normal termination Conditions of forced termination Interrupt request generation timing Functions of registers ___ TC pin validity bit: Bit 1 at address 6816

Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) FunctionsBit At reset RW 23 to 0 [Write] Set the transfer start address of the source. These bits can be set to “000000 16” to “FFFFFF16.” [Read] The read value indicates the source address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) FunctionsBit At reset RW 23 to 0 [Write] Set the transfer start address of the destination. These bits can be set to “000000 16” to “FFFFFF16.” [Read] The read value indicates the destination address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) FunctionsBit At reset RW 23 to 0 [Write] Set the byte number of the transfer data. These bits can be set to “000001 16” to “FFFFFF16.” [Read] The read value indicates remaining byte number of the transfer data. Undefined RW Note: When writing to this register, write to all 24 bits. Do not set this register to “00000016.” b23 b16 Fig. 13.5.1 Register structures of SARi, DARi, and TCRi in single transfer mode

13.5.1 Setting of single transfer mode

Figures 13.5.2 through 13.5.4 show an initial setting example for registers relevant to the single transfer mode. In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral function. When a DMAi interrupt is used, the setting for enabling the interrupt is also required. For details, refer to “CHAPTER 7. INTERRUPTS.” Fig. 13.5.2 Initial setting example for registers relevant to single transfer mode (1) When external DMA source is selected When internal DMA source is selected /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting interrupt priority level b7 b0 DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continue to “Figure 13.5.3” on next page. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 Port P9 direction register (Address 1516) Setting port P9 direction register DMAREQ0 pin DMAREQ1 pin DMAREQ2 pin Clear the corresponding bit to “0.” DMAREQ3 pin

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These bits can be set to “00000016” to “FFFFFF16.” b7 b0 b0b0 b7 b7 b7 b0 b0b0 b7 b7 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer Transfer mode select bit 0 : Burst transfer mode 1 : Cycle-steal transfer mode Transfer source address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Transfer direction select bit (Used in 1-bus cycle transfer) 0 : From memory to I/O 1 : From I/O to memory I/O connection select bit (Valid in 1-bus cycle transfer) 0 : Data bus D0–D 7 or D0–D 15 1 : Data bus D8–D 15 Transfer source wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Transfer destination wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Selection of single transfer mode Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) Set the transfer start address of destination. These bits can be set to “00000016” to “FFFFFF16.” Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Set the byte number of transfer data. These bits can be set to “000001 16” to “FFFFFF16.” Notes 1: When writing to these registers, write to all 24 bits. 2: Do not write “00000016” to TCRi. Note 3: When data is transferred from memory to I/O in 1-bus cycle transfer, it is unnecessary to set DARi. When data is transferred form I/O to memory in 1-bus cycle transfer, it is unnecessary to set SARi. DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion Edge sense/Level sense select bit (Note) 0 : Edge sense 1 : Level sense DMAACKi validity bit 0 : Invalid 1 : Valid Note: When an external source (DMAREQi) is selected or when the cycle-steal transfer mode is selected, set this bit to “0.” Continue to “Figure 13.5.4” on next page. DMA request source select bits Fig. 13.5.3 Initial setting example for registers relevant to single transfer mode (2)

Fig. 13.5.4 Initial setting example for registers relevant to single transfer mode (3) DMA transfer starts/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 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/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines When selecting external DMA source From preceding “Figure 13.5.3” Priority select bit 0 : Fixed 1 : Rotating DMAC control register L (Address 6816) TC pin validity bit 0 : Invalid (P103 pin functions as a programmable I/O port.) 1 : Valid (P103 pin functions as TC pin.) DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Selection of priority level and TC pin, and setting DMAi request bit to “0” Software DMAi request bit (Valid in software DMA source selected) Bit 0 : Channel 0 Bit 1 : Channel 1 Bit 2 : Channel 2 Bit 3 : Channel 3 0 : Disabled 1 : Enabled DMAC control register H (Address 6916) DMA0 enable bit DMA1 enable bit DMA2 enable bit DMA3 enable bit When selecting internal DMA source When selecting internal DMA source except software Inputting DMA request signal to DMAREQi pin Interrupt request of each peripheral function occursDMAC control register H (Address 6916) Software DMA0 request bit Software DMA1 request bit Software DMA2 request bit Software DMA3 request bit 0 : No request 1 : Requested When selecting software DMA request When writing “1,” DMA request is generated.

13.5.2 Operation in single transfer mode

Figure 13.5.5 shows the operation flowchart of the single transfer mode, and Figure 13.5.6 shows a timing diagram of the single transfer mode (burst transfer mode). For the cycle-steal transfer mode, refer to the following:

All transfers except for the last 1-unit transfer: Figure 13.8.12
Last 1-unit transfer: Figure 13.8.14 Also, refer to section “13.2.1 Bus access control circuit” for the bus request sampling during transfer. DMAi request bit ← 0 1-unit transfer Transfer completion of 1 block ? TC “L” output (Note) DMAi interrupt request bit ← 1 DMAi enable bit ← 0 (Only in cycle-steal transfer mode) (Refer to section “13.4 Operation.”) N Y Note: When TC pin validity bit is “1” Burst·Edge : In burst transfer mode (edge sense) Burst·Level·L : In burst transfer mode (level sense) with DMAREQi pin’s input level = L Burst·Level·H : In burst transfer mode (level sense) with DMAREQi pin’s input level = H Cycle-steal·Requested : In cycle-steal transfer mode with any request of DMA0–3 Cycle-steal·No request h no request of DMA0–3 DMAi request bit ← 0 (Only burst·edge) DMAi request bit ? Burst·Level·H Cycle-Steal·No request Burst·Edge Burst·Level·L Cycle-steal·Requested Fig. 13.5.5 Operation flowchart of single transfer mode : In cycle-steal transfer mode wit

Fig. 13.5.6 Timing diagram of single transfer mode (burst transfer mode) f ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 Read cycle 1-unit transfer Transition of right to use bus Terminate processing PC L sarL darL (sar+2)L (dar+2)L (sar+4)L (dar+4)L (sar+6)L PC L PC H sar M dar M (sar+2) M (sar+6)M PC H PG sar H dar H (sar+2) H (sar+6)L PG Memory Data 0 Data 1 Data 2 L H L H L H dar dar+5 Transfer sar sar+5 1, 0 (DMAC) 1, 1 (CPU) Write cycle l This example applies on the following conditions: External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer mode : Burst Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source Wait : No Transfer destination Wait : No sar : The value which is set to SARi (even) dar : The value which is set to DARi (even) TCR set value : 6 Right to use bus : CPU ﬁ DMAC ﬁ CPU l The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1,” and is accepted. Transition of right to use bus Data 0H Data 0L Data 0H Data 0L (dar+2) M (dar+2) H Data 1H Data 1L Data 1H Data 1L (sar+4) M (sar+4) H Data 2H Data 2L (dar+4) M (dar+4) H Data 2H Data 2L

This mode is used to transfer one block of data repeatedly. Table 13.6.1 lists the specifications of the repeat transfer mode, and Figure 13.6.1 shows the register structures of SARi, DARi, and TCRi in this mode. Table 13.6.1 Specifications of repeat transfer mode Item Transfer parameter memory Condition of normal termination Conditions of forced termination Interrupt request generation timing Functions of registers Performance specifications Not required — (No normal termination) ___ l Falling edge of the TC pin’s input from “H” to “L” ___ (when the TC pin validity bit = “1”) l Write “0” to the DMAi enable bit No request is generated. SARi latch: Indicates the transfer start address of data block at the transfer source. SARi: Indicates the address of the next transfer source. DARi latch: Indicates the transfer start address of data block at the transfer destination. DARi: Indicates the address of the next transfer destination. TCRi latch: Indicates the number of transfer bytes. TCRi: Indicates the number of remaining bytes being transferred. ___ TC pin validity bit: Bit 1 at address 6816

Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) FunctionsBit At reset RW 23 to 0 Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) FunctionsBit At reset RW 23 to 0 [Write] Set the transfer start address of the destination. These bits can be set to “000000 16” to “FFFFFF16.” [Read] The read value indicates the destination address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) FunctionsBit At reset RW 23 to 0 [Write] Set the byte number of transfer data. These bits can be set to “000001 16” to “FFFFFF16.” [Read] The read value indicates the remaining byte number of the block which is being transferred. Undefined RW Note: When writing to this register, write to all 24 bits. Do not write “00000016” to this register. b23 b16 [Write] Set the transfer start address of the source. These bits can be set to “000000 16” to “FFFFFF16.” [Read] The read value indicates the source address of data which is next transferred. Fig. 13.6.1 Register structures of SARi, DARi, and TCRi in repeat transfer mode

13.6.1 Setting of repeat transfer mode

Figures 13.6.2 through 13.6.4 show an initial setting example for registers relevant to the repeat transfer mode. In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral function. In this mode, only the forced termination can terminate the DMA transfer. (Refer to section “13.3.5 (2) Forced termination.” Therefore, in the burst transfer mode (edge sense selected), be sure to validate the ___ TC pin. When external DMA source is selected When internal DMA source is selected Continue to “Figure 13.6.3” on next page. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 Port P9 direction register (Address 1516) Setting port P9 direction register DMAREQ0 pin DMAREQ1 pin DMAREQ2 pin Clear the corresponding bit to “0.” DMAREQ3 pin Fig. 13.6.2 Initial setting example for registers relevant to repeat transfer mode (1)

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These bits can be set to “00000016” to “FFFFFF16.” b7 b0 b0b0 b7 b7 b7 b0 b0b0 b7 b7 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer Transfer mode select bit 0 : Burst transfer mode 1 : Cycle-steal transfer mode Transfer source address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Transfer direction select bit (Used in 1-bus cycle transfer) 0 : From memory to I/O 1 : From I/O to memory I/O connection select bit (Valid in 1-bus cycle transfer) 0 : Data bus D 0–D 7 or D0–D 15 1 : Data bus D8–D 15 Transfer source wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Transfer destination wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Selection of repeat transfer mode Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) Set the transfer start address of destination. These bits can be set to “00000016” to “FFFFFF16.” Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Set the byte number of transfer data. These bits can be set to “000001 16” to “FFFFFF16.” Notes 1: When writing to these registers, write to all 24 bits. 2: Do not write “00000016” to TCRi. Note 3: When data is transferred from memory to I/O in 1-bus cycle transfer, it is unnecessary to set DARi. When data is transferred form I/O to memory in 1-bus cycle transfer, it is unnecessary to set SARi. DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion Edge sense/Level sense select bit (Note) 0 : Edge sense 1 : Level sense DMAACKi validity bit 0 : Invalid 1 : Valid Note: When an external source (DMAREQi) is selected or when the cycle-steal transfer mode is selected, set this bit to “0.” Continue to “Figure 13.6.4” on next page. DMA request source select bits Fig. 13.6.3 Initial setting example for registers relevant to repeat transfer mode (2)

Fig. 13.6.4 Initial setting example for registers relevant to repeat transfer mode (3) DMA transfer starts/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 0000 0 : No request /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Inputting DMA request signal to DMAREQi pin /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines When selecting external DMA source From preceding “Figure 13.6.3” Priority select bit 0 : Fixed 1 : Rotating DMAC control register L (Address 6816) TC pin validity bit 0 : Invalid (P103 pin functions as a programmable I/O port.) 1 : Valid (P103 pin functions as TC pin.) DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Software DMAi request bit (Valid in software DMA source selected) Bit 0 : Channel 0 Bit 1 : Channel 1 Bit 2 : Channel 2 Bit 3 : Channel 3 0 : Disabled 1 : Enabled DMAC control register H (Address 6916) DMA0 enable bit DMA1 enable bit DMA2 enable bit DMA3 enable bit When selecting internal DMA source When selecting internal DMA source except software Interrupt request of each peripheral function occursDMAC control register H (Address 6916) Software DMA0 request bit Software DMA1 request bit Software DMA2 request bit Software DMA3 request bit 0 : No request 1 : Requested When selecting software DMA request When writing “1,” DMA request is generated. Note: When the burst transfer mode (edge sense) is selected, set bit 1 to “1.” Selection of priority level and TC pin, and setting DMAi request bit to “0”

13.6.2 Operation in repeat transfer mode

Figure 13.6.5 shows the operation flowchart of the repeat transfer mode, and Figure 13.6.6 shows a timing diagram of the repeat transfer mode (burst transfer mode). For the cycle-steal transfer mode, refer to the following:

All transfers except for the last 1-unit transfer: Figure 13.8.12
Last 1-unit transfer: Figure 13.8.13 Also, refer to section “13.2.1 Bus access control circuit” for the bus request sampling during transfer. DMAi request bit ← 0 1-unit transfer (Only in cycle-steal transfer mode) (Refer to section “13.4 Operation.”) Burst·Edge : In burst transfer mode (edge sense) Burst·Level·L : In burst transfer mode (level sense) with DMAREQi pin’s input level = L Burst·Level·H : In burst transfer mode (level sense) with DMAREQi pin’s input level = H Cycle-steal·Requested : In cycle-steal transfer mode with any request of DMA0–3 Cycle-steal·No request : In cycle-steal transfer mode with no request of DMA0–3 DMAi request bit ? Burst·Level·H Cycle-steal·No request Burst·Edge Burst·Level·L Cycle-steal·Requested 0Fig. 13.6.5 Operation flowchart of repeat transfer mode

Fig. 13.6.6 Timing diagram of repeat transfer mode (burst transfer mode) f ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 Transfer of entire batch of data (first) PC L sar dar (sar+4) (dar+4) (sar+6) sar dar PC H sar (sar+6) dar PG sar (sar+6) dar H 1, 0 (DMAC) 1-unit transfer Transition of right to use bus Transfer of entire batch of data (second) Memory Data 0 Data 1 Data 2 L H L H L H dar dar+5 Transfer sar sar+5 l This example applies on the following conditions: External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer mode : Burst Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source Wait : No Transfer destination Wait : No sar : The value which is set to SARi (even) dar : The value which is set to DARi (even) TCR set value : 6 Right to use bus : CPU ﬁ DMAC l The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1,” and is accepted. L M H L L L L M L L L M H Data0H Data0L darM darH Data0H Data0L (sar+4)M (sar+4)H Data2H Data2L (dar+4)M (dar+4)H Data2H Data2L sarM sarH Data0H Data0L

This mode is used to transfer several blocks of data. According to the information of each block stored in memory area (Note), several blocks of data are transferred. All of the transfer parameters must be located register structures of SARi, DARi, and TCRi in this mode. Note: Each of the following information is called “transfer parameter”: transfer start addresses of transfer source and destination, and transfer data’s byte number. Table 13.7.1 Specifications of array chain transfer mode Item Transfer parameter memory Condition of normal termination Conditions of forced termination Interrupt request generation timing Functions of registers Performance specifications Required. l In 2-bus cycle transfer: 12 bytes per one block (transfer source’s transfer start address, transfer destination’s transfer start address, transfer data’s byte number) l In 1-bus cycle transfer: 8 bytes per one block (from memory to I/O: transfer source’s transfer start address, transfer data’s byte number) (from I/O to memory: transfer destination’s transfer start address, transfer data’s byte number) TCRi latch = 0 and TCRi = 0 ___ l Falling edge of the TC pin’s input from “H” to “L” ___ (when the TC pin validity bit = “1”) l Write “0” to the DMAi enable bit At normal termination SARi latch: Indicates the transfer parameter memory’s start address of the next block. SARi: Indicates the address of the next transfer source. DARi latch: Not used. DARi: Indicates the address of the next transfer destination. TCRi latch: Indicates the number of remaining transfer blocks. TCRi: Indicates the number of remaining transfer bytes. ___ TC pin validity bit: Bit 1 at address 6816

After a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory).
After transfer starts, the read value indicates the source address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) FunctionsBit At reset RW 23 to 0 Need not to be set. [Read] After transfer starts, the read value indicates the destination address of data which is next transferred. Undefined RW b23 b16 b7 b0b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) FunctionsBit At reset RW 23 to 0 [Write] Set the number of transfer blocks. These bits can be set to “000001 16” to “FFFFFF16.” [Read]
After a value is written to this register and until transfer starts, the read value indicates the written value (the transfer block number) .
After transfer starts, the read value indicates the remaining byte number of the block which is being transferred. Undefined RW Note: When writing to this register, write to all 24 bits. Do not write “00000016” to this register. b23 b16 Fig. 13.7.1 Register structures of SARi, DARi, and TCRi in array chain transfer mode

13.7.1 Transfer parameter memory in array chain transfer mode

The transfer parameters required for each transfer method are described below. These parameters must be located in series starting at an even addresses. Figure 13.7.2 shows a transfer parameter memory map in the array chain transfer mode. (1) In 2-bus cycle transfer All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 12 bytes for each block.

Transfer source’s transfer start address (24 bits) + Dummy data (8 bits)
Transfer destination’s transfer start address (24 bits) + Dummy data (8 bits)
Transfer data’s byte number (24 bits) + Dummy data (8 bits) (2) In 1-bus cycle transfer from memory to I/O All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 8 bytes for each block.
Transfer source’s transfer start address (24 bits) + Dummy data (8 bits)
Transfer data’s byte number (24 bits) + Dummy data (8 bits) (3) In 1-bus cycle transfer from I/O to memory All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 8 bytes for each block.
Transfer destination’s transfer start address (24 bits) + Dummy data (8 bits)
Transfer data’s byte number (24 bits) + Dummy data (8 bits)

(1) 2-bus cycle transfer ] The above applies when 4-block transfer is performed. Transfer source’s transfer start address 1 Transfer destination’s transfer start address 1 Transfer data’s byte number 1 Transfer source’s transfer start address 2 Transfer destination’s transfer start address 2 Transfer data’s byte number 2 Transfer source’s transfer start address 3 Transfer destination’s transfer start address 3 Transfer data’s byte number 3 Transfer source’s transfer start address 4 Transfer destination’s transfer start address 4 Transfer data’s byte number 4 L M H L M H L M H Transfer data’s byte number Dummy data Even address4 bytes 4 bytes 4 bytes Transfer source’s transfer start address Transfer destination’s transfer start address Dummy data Dummy data Even address Even address Transfer parameters for 1 block (2) 1-bus cycle transfer 4 bytes 4 bytes Transfer source’s transfer start address 1 Transfer data’s byte number 1 Transfer source’s transfer start address 2 Transfer data’s byte number 2 Transfer source’s transfer start address 3 Transfer data’s byte number 3 Transfer source’s transfer start address 4 Transfer data’s byte number 4 Transfer data’s byte number Dummy data Transfer source’s transfer start address Dummy data L M H L M H Even address Even address Transfer parameters for 1 block ] The above applies on the following conditions:

When data is transferred from memory to I/O (When transferring from I/O to memory, replace all the above mentioned “Transfer source’s transfer start address” with “Transfer destination’s transfer start address.”)
4-block transfer Fig. 13.7.2 Transfer parameter memory map in array chain transfer mode

13.7.2 Setting of array chain transfer mode

Figures 13.7.3 through 13.7.5 show an initial setting example for registers relevant to the array chain transfer mode. In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral function. When a DMAi interrupt is used, the setting for enabling the interrupt is also required. For details, refer to “CHAPTER 7. INTERRUPTS.” Fig. 13.7.3 Initial setting example for registers relevant to array chain transfer mode (1) When external DMA source is selected When internal DMA source is selected /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting interrupt priority level b7 b0 DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continue to “Figure 13.7.4” on next page. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 Port P9 direction register (Address 1516) Setting port P9 direction register DMAREQ0 pin DMAREQ1 pin DMAREQ2 pin Clear the corresponding bit to “0.” DMAREQ3 pin

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These bits can be set to “00000016” to “FFFFFF16.” b7 b0 b0b0 b7 b7 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer Transfer mode select bit 0 : Burst transfer mode 1 : Cycle-steal transfer mode Transfer source address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Transfer direction select bit (Used in 1-bus cycle transfer) 0 : From memory to I/O 1 : From I/O to memory I/O connection select bit (Valid in 1-bus cycle transfer) 0 : Data bus D0–D 7 or D0–D 15 1 : Data bus D8–D 15 Transfer source wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Transfer destination wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Selection of array chain transfer mode Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Set the number of transfer blocks. These bits can be set to “00000116” to “FFFFFF16.” Notes 1: When writing to these registers, write to all 24 bits. 2: Do not write “00000016” to TCRi. DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion Edge sense/Level sense select bit (Note) 0 : Edge sense 1 : Level sense DMAACKi validity bit 0 : Invalid 1 : Valid Note: When an external source (DMAREQi) is selected or when the cycle-steal transfer mode is selected, set this bit to “0.” Continue to “Figure 13.7.5” on next page. DMA request source select bits Fig. 13.7.4 Initial setting example for registers relevant to array chain transfer mode (2)

13.7.3 Operation in array chain transfer mode

Figure 13.7.6 shows the operation flowchart of the array chain transfer mode, and Figures 13.7.7 and 13.7.8 show timing diagrams of the array chain transfer mode (burst transfer mode). For the cycle-steal transfer mode, refer to the following:

Transfer of transfer parameters in an array state: Figures 13.8.10 and 13.8.11
All transfers except in an array state and except the last 1-unit transfer of each block: Figure 13.8.12
Last 1-unit transfer of each block except the last block: Figure 13.8.13
Last 1-unit transfer of the last block: Figure 13.8.14 The processing performed in the array chain transfer mode consists of an array state and a transfer state. (1) Array state In an array state, transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers SARi, DARi, and TCRi and their latches. As shown in Figure 13.7.2, a transfer parameter consists of 4 bytes (24 bits of data + 8 bits of dummy data). One bus cycle always consumes 3 cycles of During an array state, the DMAACKi pin outputs “H” level. For the bus request sampling in an array state, refer to section “13.2.1 Bus access control circuit.” (2) Transfer state Data is transferred in a transfer state. For the bus request sampling in a transfer state, refer to section “13.2.1 Bus access control circuit.”

Fig. 13.7.6 Operation flowchart of array chain transfer mode Burst·Level·H Cycle-steal·No request Note: When TC pin validity bit is “1” First of 1 block ? SARi ← Transfer parameter (Note) (Transfer source’s transfer start address) DARi ← Transfer parameter (Note) (Transfer destination’s transfer start address) TCRi ← Transfer parameter (Byte number of transfer data) TCRi latch ← TCRi latch – 1 N Y 1 First On and after second Transfer completion of all blocks ? TCRi latch = 0 ? Y. Completion N DMAi request bit ← 0 1-unit transfer Transfer completion of 1 block ? (Only in cycle-steal transfer mode) (Refer to section “13.4 Operation.”) TC “L” output (Note) DMAi interrupt request bit ← 1 DMAi enable bit ← 0 DMAi request bit ← 0 (Only in burst transfer mode (edge sense)) DMAi request bit ? Burst·Level·H Cycle-steal·No request Burst·Edge : In burst transfer mode (edge sense) Burst·Level·L : In burst transfer mode (level sense) with DMAREQi pin = L Burst·Level·H : In burst transfer mode (level sense) with DMAREQi pin = H Cycle-steal·Requested : In cycle-steal transfer mode with any request of DMA0–3 Cycle-steal·No request : In cycle-steal transfer mode with no request of DMA0–3 SARi latch indicates the start address of the transfer parameter memory of the next block. TCRi latch indicates the number of remaining transfer blocks. Note: The above figure applies when 2-bus cycle transfer is performed. When data is transferred from memory to I/O in 1-bus cycle transfer, there is no “DARi ← Transfer parameter.” When data is transferred from I/O to memory in 1-bus cycle transfer, there is no “SARi ← Transfer parameter.” Burst•Edge Burst·Level·L Cycle-steal·Requested DMAi request bit ? Burst·Edge Burst·Level·L Cycle-steal·Requested

Fig. 13.7.7 Timing diagram of array chain transfer mode (burst transfer mode) (1) Transfer of transfer parameters 1-unit transfer 1, 0 (DMAC) H H Transfer of 1 transfer parameter Transfer of data Transfer stateArray state First block transfer Memory sa1 da1 m sa2 da2 n tp tp+4 tp+8 tp+12 tp+16 tp+20 First block’s transfer parameters sa1 sa1+m–1 sa1+m sa2+n–1 sa2+n sa2 PC L tpL (tp+2)L (tp+4)L (tp+6)L (tp+8)L (tp+10)L sa1L da1L PC H tpM sa1M Dummy data da1 PG tpH sa1L sa1H da1 Dummy data da1H m M m L m H sa1M DataH da1M DataH sa1H DataL da1H DataL H ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 Dummy data Transition of right to use bus l This example applies on the following conditions: External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer mode : Burst Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source Wait : No Transfer destination Wait : No sa1, sa2, da1, da2 : Transfer parameters (even) tp : Start address of first block’s transfer parameter memory TCR set value : 6 Right to use bus : CPU ﬁ DMAC ﬁ CPU l The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1,” and is accepted. Second block’s transfer parameters Memory Second block transfer Memory da1 da1+m–1 da1+m da2+n–1 da2+n da2 Continue to “Figure 13.7.8” on next page. L M(tp+2)M (tp+2)H (tp+4)M (tp+4)H (tp+6)M (tp+6)H (tp+8)M (tp+8)H (tp+10)M (tp+10)H (tp+12)M (tp+12)H (tp+12)L

Fig. 13.7.8 Timing diagram of array chain transfer mode (burst transfer mode) (2) Transfer of data Transfer state Transition of right to use bus Terminate processing Transfer stateArray state 1, 0 (DMAC) (da1+m–2)L (sa1+m)L (tp+12)L (tp+22)L (tp+24) (da2+n–2)L DataH Dummy data (sa2+n)L PC Lsa2 (sa1+m)M sa2M DataH DataH (sa2+n)M PC H DataL nH(sa1+m)H sa2L DataL DataL (sa2+n)H PG 1, 1 (CPU) From proceeding “Figure 13.7.7” ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 L L (tp+12)M (tp+12)H (tp+24)M (tp+24)H sa2M sa2H

[Precautions for array chain transfer mode] If the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed, the array chain transfer mode can be used:

The external data bus width = 16 bits or the internal memory is used.
The transfer start address on the address-direction-fixed side is an even address.

This mode is used to transfer several blocks of data. According to the information of each block stored in memory area (Note), several blocks of data are transferred. Transfer parameters can be located in separate memory locations, in a unit of one block’s parameters. Table 13.8.1 lists the specifications of the link array chain transfer mode, and Figure 13.8.1 shows the register structures of SARi, DARi, and TCRi in this mode. Note: Each of the following information is called “transfer parameter”: transfer start addresses of transfer source and destination, and transfer data’s byte number. Table 13.8.1 Specifications of link array chain transfer mode Item Transfer parameter memory Condition of normal termination Conditions of forced termination Interrupt request generation timing Functions of registers Performance specifications Required. l In 2-bus cycle transfer: 16 bytes per one block (transfer source’s transfer start address, transfer destination’s transfer start address, transfer data’s byte number, next transfer parameter memory’s start address) l In 1-bus cycle transfer: 12 bytes per one block (from memory to I/O: transfer source’s transfer start address, transfer data’s byte number, next transfer parameter memory’s start address) (from I/O to memory: transfer destination’s transfer start address, transfer data’s byte number, next transfer parameter memory’s start address) SARi latch = 0 and TCRi = 0 ___ l Falling edge of TC pin’s input from “H” to “L” ___ (when the TC pin validity bit = “1”) l Write “0” to the DMAi enable bit At normal termination SARi latch: Indicates the transfer parameter memory’s start address of the next block. SARi: Indicates the address of the next transfer source. DARi latch: Not used. DARi: Indicates the address of the next transfer destination. TCRi latch: Not used. TCRi: Indicates the number of remaining bytes being transferred. ___ TC pin validity bit: Bit 1 at address 6816

13-817721 Group User‘s Manual b7 b0b15 b8 Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) FunctionsBit At reset RW 23 to 0 [Write] Set the start address of transfer parameter memory of block which is first transferred. These bits can be set to “000000 16” to “FFFFFF16.” [Read]

After a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory of block which is first transferred).
After transfer starts, the read value indicates the source address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) (DAR0) Destination address register 1 (Addresses 1FD616 to 1FD416) (DAR1) Destination address register 2 (Addresses 1FE616 to 1FE416) (DAR2) Destination address register 3 (Addresses 1FF616 to 1FF416) (DAR3) FunctionsBit At reset RW 23 to 0 Need not to be set. [Read] After transfer starts, the read value indicates the destination address of data which is next transferred. Undefined RW b23 b16 b7 b0b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) FunctionsBit At reset RW 23 to 0 [Write] Set the dummy data. These bits can be set to “000001 16” to “FFFFFF16.” [Read]
After a value is written to this register and until transfer starts, the read value indicates the written value (dummy data).
After transfer starts, the read value indicates the remaining byte number of the block which is being transferred. Undefined RW Note: When writing to this register, write to all 24 bits. Do not write “00000016” to this register. b23 b16 Fig. 13.8.1 Register structures of SARi, DARi, and TCRi in link array chain transfer mode

13.8.1 Transfer parameter memory in link array chain transfer mode

The transfer parameters required for each transfer method are described below. These parameters can be located in separate memory locations, in a unit of one block’s parameters. However, these parameters must be located starting at an even address. Figure 13.8.2 shows a transfer parameter memory map in the link array chain transfer mode. (1) In 2-bus cycle transfer All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 16 bytes for each block.

Transfer source’s transfer start address (24 bits) + Dummy data (8 bits)
Transfer destination’s transfer start address (24 bits) + Dummy data (8 bits)
Transfer data’s byte number (24 bits) + Dummy data (8 bits)
Start address of next transfer parameter memory (24 bits) (Note) + Dummy data (8 bits) (2) In 1-bus cycle transfer from memory to I/O All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 12 bytes for each block.
Transfer source’s transfer start address (24 bits) + Dummy data (8 bits)
Transfer data’s byte number (24 bits) + Dummy data (8 bits)
Start address of next transfer parameter memory (24 bits) (Note) + Dummy data (8 bits) (3) In 1-bus cycle transfer from I/O to memory All of the following transfer parameters are required for each block of data; that is, a transfer parameter memory consumes 12 bytes for each block.
Transfer destination’s transfer start address (24 bits) + Dummy data (8 bits)
Transfer data’s byte number (24 bits) + Dummy data (8 bits)
Start address of next transfer parameter memory (24 bits) (Note) + Dummy data (8 bits) Note: For the last block of data, write “000000 16” as the start address of the next transfer parameter memory.

13-837721 Group User‘s Manual Fig. 13.8.2 Transfer parameter memory map in link array chain transfer mode ] The above applies on the following conditions:

When data is transferred from memory to I/O (When transferring from I/O to memory, replace all the above mentioned “Transfer source’s transfer start address” with “Transfer destination’s transfer start address.”
4-block transfer ] The above figure applies when 4-block transfer is performed. Dummy data Transfer parameter address 1 (1) 2-bus cycle transfer (2) 1-bus cycle transfer 4 bytes Transfer source’s transfer start address 1 Transfer destination’s transfer start address 1 Transfer data’s byte number 1 Next transfer parameter memory’s start address 2 Transfer source’s transfer start address 4 Transfer destination’s transfer start address 4 Transfer data’s byte number 4 “00000016” Transfer source’s transfer start address 3 Transfer destination’s transfer start address 3 Transfer data’s byte number 3 Next transfer parameter memory’s start address 4 Transfer source’s transfer start address 2 Transfer destination’s transfer start address 2 Transfer data’s byte number 2 Next transfer parameter memory’s start address 3 Transfer parameter address 4 (last block) Transfer parameter address 3 Transfer parameter address 2 Dummy data Transfer data’s byte number Transfer source’s transfer start address L M H L M H L M H L M H Even address Transfer parameters for 1 block Dummy data Dummy data Even address Even address Even address Transfer destination’s transfer start address Next transfer parameter memory’s start address 4 bytes Transfer source’s transfer start address 1 Transfer data’s byte number 1 Next transfer parameter memory’s start address 2 Transfer source’s transfer start address 3 Transfer data’s byte number 3 Next transfer parameter memory’s start address 4 Transfer source’s transfer start address 2 Transfer data’s byte number 2 Next transfer parameter memory’s start address 3 Transfer source’s transfer start address 4 Transfer data’s byte number 4 “000000 16” Transfer parameter address 1 Transfer parameter address 3 Transfer parameter address 2 Transfer parameter address 4 (last block) Dummy data Transfer data’s byte number Transfer source’s transfer start address L M H L M H L M H Even address Transfer parameters for 1 block Dummy data Dummy data Even address Even addressNext transfer parameter memory’s start address

13.8.2 Setting of link array chain transfer mode

Figures 13.8.3 through 13.8.5 show an initial setting example for registers relevant to the link array chain transfer mode. In addition, when timer A, timer B, UART, or the A-D converter is selected as a DMA request source, the setting for the peripheral is required. For details of the setting, refer to the chapter of each peripheral function. When a DMAi interrupt is used, the setting for enabling the interrupt is also required. For details, refer to “CHAPTER 7. INTERRUPTS.” Fig. 13.8.3 Initial setting example for registers relevant to link array chain transfer mode (1) When external DMA source is selected When internal DMA source is selected /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting interrupt priority level b7 b0 DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continue to “Figure 13.8.4” on next page. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 Port P9 direction register (Address 1516) Setting port P9 direction register DMAREQ0 pin DMAREQ1 pin DMAREQ2 pin Clear the corresponding bit to “0.” DMAREQ3 pin

13-857721 Group User‘s Manual b7 b0 Selection of transfer mode and each function b7 b0 b7 b0 0011 From preceding “Figure 13.8.3” b7 b0 b0b0 b7 b7 b7 b0 b0b0 b7 b7 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Number-of-unit-transfer-bits select bit 0 : 16 bits 1 : 8 bits Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer Transfer mode select bit 0 : Burst transfer mode 1 : Cycle-steal transfer mode Transfer source address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Transfer direction select bit (Used in 1-bus cycle transfer) 0 : From memory to I/O 1 : From I/O to memory I/O connection select bit (Valid in 1-bus cycle transfer) 0 : Data bus D0–D 7 or D0–D 15 1 : Data bus D8–D 15 Transfer source wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Transfer destination wait bit (Valid in DMA transfer) 0 : Wait 1 : No wait Selection of link array chain transfer mode Source address register 0 (Addresses 1FC216 to 1FC016) (SAR0) Source address register 1 (Addresses 1FD216 to 1FD016) (SAR1) Source address register 2 (Addresses 1FE216 to 1FE016) (SAR2) Source address register 3 (Addresses 1FF216 to 1FF016) (SAR3) Transfer counter register 0 (Addresses 1FCA16 to 1FC816) (TCR0) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) (TCR1) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) (TCR2) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) (TCR3) Notes 1: When writing to these registers, write to all 24 bits. 2: Do not write “00000016” to TCRi. DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion Edge sense/Level sense select bit (Note) 0 : Edge sense 1 : Level sense DMAACKi validity bit 0 : Invalid 1 : Valid Note: When an external source (DMAREQi) is selected or when the cycle steal transfer mode is selected, set this bit to “0.” Continue to “Figure 13.8.5” on next page. DMA request source select bits Set the start address of transfer parameter memory of block which is first transferred. These bits can be set to “000000 16” to “FFFFFF16.” Set the dummy data. These bits can be set to “000001 16” to “FFFFFF16.” Fig. 13.8.4 Initial setting example for registers relevant to link array chain transfer mode (2)

Fig. 13.8.5 Initial setting example for registers relevant to link array chain transfer mode (3) DMA transfer starts/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 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/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Selection of priority level and TC pin, and setting DMAi request bit to “0” TC pin validity bit 0 : Invalid (P103 pin functions as a programmable I/O port.) 1 : Valid (P103 pin functions as TC pin.) b7 b0 0000 0 : No request /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 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selecting internal DMA source except software Interrupt request of each peripheral function occursDMAC control register H (Address 6916) Software DMA0 request bit Software DMA1 request bit Software DMA2 request bit Software DMA3 request bit 0 : No request 1 : Requested When selecting software DMA request When writing “1,” DMA request is generated.

13-877721 Group User‘s Manual

13.8.3 Operation in link array chain transfer mode

Figure 13.8.6 shows the operation flowchart of the link array chain transfer mode, and Figures 13.8.7 and 13.8.8 show timing diagrams of the link array chain transfer mode (burst transfer mode). In addition, Figure 13.8.14. For the cycle-steal transfer mode, refer to the following:

Transfer of transfer parameters in an array state: Figures 13.8.10 and 13.8.11
All transfers except for that in an array state and except for the last 1-unit transfer of each block: Figure 13.8.12
Last 1-unit transfer of each block except for the last block: Figure 13.8.13
Last 1-unit transfer of the last block: Figure 13.8.14 The processing performed in the link array chain transfer mode consists of an array state and a transfer state. (1) Array state In an array state, transfer parameters are read from the transfer parameter memory in a unit of 2 bytes and transferred to registers SARi, DARi, and TCRi and their latches. As shown in Figure 13.8.2, a transfer parameter consists of 4 bytes (24 bits of data + 8 bits of dummy data). One bus cycle always consumes 3 cycles of During an array state, the DMAACKi pin outputs “H” level. For the bus request sampling in an array state, refer to section “13.2.1 Bus access control circuit.” (2) Transfer state Data is transferred in a transfer state. For the bus request sampling in a transfer state, refer to section “13.2.1 Bus access control circuit.”

Note: When TC pin validity bit is “1” First of each block ? SARi ← Transfer parameter (Note) (Transfer source’s transfer start address) DARi ← Transfer parameter (Note) (Transfer destination’s transfer start address) TCRi ← Transfer parameter (Byte number of transfer data) SARi latch ← Transfer parameter (Start address of next transfer parameter memory) N Y 1 First On and after second Transfer completion of all blocks ? SARi latch = 0 ? Y. Completion

1 TC “L” output (Note)

DMAi interrupt request bit ← 1 DMAi enable bit ← 0 N DMAi request bit ← 0 1-unit transfer Transfer completion of 1 block ? (Only in cycle-steal transfer mode) (Refer to section “13.4 Operation.”) DMAi request bit ← 0 (Only in burst transfer mode (edge sense)) DMAi request bit ? Burst·Level·H Cycle-steal·No request Burst·Edge : In burst transfer mode (edge sense) Burst·Level·L : In burst transfer mode (level sense) with DMAREQi pin’s input level = L Burst·Level·H : In burst transfer mode (level sense) with DMAREQi pin’s input level = H Cycle-steal·Requested : In cycle-steal transfer mode with any request of DMA0–3 Cycle-steal·No request : In cycle-steal transfer mode with no request of DMA0–3 SARi latch indicates the start address of the transfer parameter memory of the next block. Note: The above figure applies when 2-bus cycle transfer is performed. When data is transferred from memory to I/O in 1-bus cycle transfer, there is no “DARi← Transfer parameter.” When data is transferred from I/O to memory in 1-bus cycle transfer, there is no “SARi← Transfer parameter.” Burst·Edge Burst·Level·L Cycle-steal·Requested Burst·Level·H Cycle-steal·No request DMAi request bit ? Burst·Edge Burst·Level·L Cycle-steal·Requested Fig. 13.8.6 Operation flowchart of link array chain transfer mode

13-897721 Group User‘s Manual Fig. 13.8.7 Timing diagram of link array chain transfer mode (burst transfer mode) (1) ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 Array state Transfer of transfer parameters PC L tp1L (tp1+2)L (tp1+4)L (tp1+6)L (tp1+8)L PC H tp1M sa1M Dummy data da1 PG tp1H sa1L sa1H da1 H H H (tp1+10)L Dummy data m M m L m H tp2M tp2L (tp1+12)L 1, 0 (DMAC) Continue to “Figure 13.8.8.” (tp1+14)L Dummy data tp2H Transfer of 1 transfer parameter Transition of right to use bus l The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1,” and is accepted. Dummy data L M(tp1+2)M (tp1+2)H (tp1+4)M (tp1+4)H (tp1+6)M (tp1+6)H (tp1+8)M (tp1+8)H (tp1+10)M (tp1+10)H (tp1+12)M (tp1+12)H (tp1+14)M (tp1+14)Hda1H

Fig. 13.8.8 Timing diagram of link array chain transfer mode (burst transfer mode) (2) Transfer state Transfer of data tp2L sa1L (da1+m-2)L (sa1+m)L tp2L tp2M tp2H sa1H 1,0 (DMAC) (tp2+14)L sa2M 0016 Dummy data sa2H sa2M sa2H 1-unit transfer sa2L Array state Array state Transfer state Terminate processing Transition of right to use bus sa1M da1L (sa1+m)M (sa1+m)H 0016 0016 0016 (da2+n–2)L (sa2+n)L (sa2+n)M (sa2+n)H PC L PC H PG 1, 1 (CPU) ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 From preceding “Figure 13.8.7” DataH DataL DataH DataL DataH DataL DataH DataL DataH DataL da1M da1H tp2M tp2H

13-917721 Group User‘s Manual through 13.8.14. 13.8.14 Memory sa1 da1 m tp2 sa2 da2 n 00000016 tp1 tp1+4 tp1+8 tp1+12 tp2 tp2+4 tp2+8 tp2+12 External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer mode : Burst ( “Figure 13.8.7” and “Figure 13.8.8”) : Cycle-steal ( “Figure 13.8.10” through “Figure 13.8.14”) Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source Wait : No Transfer destination Wait : No sa1, sa2, da1, da2 : Transfer parameter (even) tp1 : Start address of first block’s transfer parameter memory Transfer block’s number : 2 Right to use bus : CPU → DMAC → CPU Memory First block transfer First block’s transfer parameter sa1 sa1+m–1 sa1+m sa2+n–1 sa2+n sa2 Second block’s transfer parameter Second block transfer Memory da1 da1+m–1 da1+m da2+n–1 da2+n da2

Transfer of transfer parameters Transition of right to use bus ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 PC L tp1L (tp1+2)L (tp1+4)L (tp1+6)L (tp1+8)L PC H tp1M sa1M (tp1+2)M Dummy data (tp1+4)M da1 M (tp1+6)M PG tp1 H sa1L (tp1+2)H sa1H (tp1+4)H da1L (tp1+6)H H H H Dummy data da1H (tp1+8)M (tp1+8)H m M m L Array state l The above figure is the example of initial term for processing the first block in “Figure 13.8.9.” l The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1,” and is accepted. l The Bus request caused by DMA is sampled while the bus request sampling signal (]1) is “1” in the transition of the right to use bus, and is accepted. The DMA requests of the other channels are not accepted in an array state. Continue to “Figure 13.8.11.” l Initial term for processing each block in array chain and link array chain transfer modes The operation from an array state to the first 1-unit transfer is continuously performed by one DMAi request. 1, 0 (DMAC) Fig. 13.8.10 Timing diagram of cycle-steal transfer mode (1)

13-937721 Group User‘s Manual Transfer of transfer parameters Array state (tp1+14)L tp2H sa1L (tp1+14)M Dummy data tp2M DataH da1 M (tp1+14)H tp2H tp2L Data Lsa1H da1H 1, 0 (DMAC) First 1-unit transfer ]2 Transition of right to use bus sa1M da1L Data H Data L PC L PC H PG 1, 1 (CPU) H (tp1+12)L(tp1+10)L (tp1+12)M tp2M(tp1+10)M Dummy data (tp1+12)H tp2L(tp1+10)H m H From preceding “Figure 13.8.10” ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 l The above figure is the example of initial term for processing the first block in “Figure 13.8.9.” When the array chain transfer mode is selected, there is not the term of ]2. l The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1,” and is accepted. l The Bus request caused by DMA is sampled while the bus request sampling signal (]1) is “1” in transition of the right to use bus, and is accepted. The DMA requests of the other channels are not accepted in an array state. Fig. 13.8.11 Timing diagram of cycle-steal transfer mode (2)

Fig. 13.8.12 Timing diagram of cycle-steal transfer mode (3) (sa1+2)L 1, 0 (DMAC) 1-unit transfer Transition of right to use bus Data H DataL PC L PC H PG H PC L PC H PG (da1+2)L Data H DataL (sa1+2)M (sa1+2)H (da1+2)M (da1+2)H 1, 1 (CPU) l 1-unit transfer 1-unit transfer is performed with a DMAi request on the following conditions:

Single transfer mode (except for the last 1-unit transfer)
Repeat transfer mode (except for the last 1-unit transfer of block)
Array chain transfer mode (except for the first and last 1-unit transfers of each block)
Link array chain transfer mode (except for the first and last 1-unit transfers of each block) ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 Transition of right to use bus l The above figure is the example of the second 1-unit transfer for processing the first block in “Figure 13.8.9.” l The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the Bus request sampling signal is “H,” and is accepted.

13-957721 Group User‘s Manual Fig. 13.8.13 Timing diagram of cycle-steal transfer mode (4) (sa1+m–2)L 1, 0 (DMAC) 1-unit transfer H Data L PC L PC H PG H PC L PC H PG (da1+m–2)L DataH L (sa1+m-2)M (sa1+m-2)H (da1+m-2)M (da1+m-2)H 1, 1 (CPU) Transition of right to use bus (sa1+m)L (sa1+m)M (sa1+m)H ALE E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 l The above figure is the example of the last term for processing the first block in “Figure 13.8.9.” l The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the bus request sampling signal is “H,” and is accepted. Transition of right to use bus l Last transfer of each block At the last term (except for the last block) for processing of each block in the repeat, array chain, and link array chain transfer modes, 1-unit transfer is performed with one DMAi request, and the right to use bus is relinquished after 3 cycles of . Data Data

E R/W A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 Bus request sampling DMAACKi TC ST1, ST0 (sa2+n-2)L 1, 0 (DMAC) 1-unit transfer H Data L PC L PC H PG H PC L PC H PG (da2+n-2)L Data H L (sa2+n-2)M (sa2+n-2)H (da2+n-2)M (da2+n-2)H 1, 1 (CPU) (sa2+n)L (sa2+n)M (sa2+n)H Terminate processing l Last transfer of last block At the last term for processing the last block in the single, array chain, and link array chain transfer modes, 1-unit transfer and terminate processing are subsequently performed with one DMAi request. Transition of right to use bus l The above figure is the example of the last term for processing the second block in “Figure 13.8.9.” l The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the bus request sampling signal is “H,” and is accepted. Transition of right to use bus Fig. 13.8.14 Timing diagram of cycle-steal transfer mode (5) Data Data

13-977721 Group User‘s Manual [Precautions for link array chain transfer mode] If the following two conditions are satisfied when the transfer unit is 16 bits and the address direction of transfer source or destination is fixed, the link array chain transfer mode can be used:

The external data bus width = 16 bits or the internal memory is used.
The transfer start address on the address-direction-fixed side is an even address.

Calculation of time from the CPU’s relinquishing the right to use bus until its regaining the right under the following conditions is described with reference to cycles of φ:

A DMAi request is generated while the CPU holds the right to use bus.
The above right is returned to the CPU after completion of DMA transfer for one DMA request. For the time per 1-unit transfer, refer to section “13.4.1 (2) Bus operation in 2-bus cycle transfer” and section “13.4.2 (2) Bus operation in 1-bus cycle transfer.” Also, for the time from DMA request generation until the start of the DMA transfer, refer to section “13.3.4 Processing from DMA request until DMA transfer execution”: and for that from issuing instructions for forced termination until returning the right to use bus to the CPU, refer to section “13.3.5 (2) Forced termination.”

13.9.1 Cycle-steal transfer mode

(1) 1-unit transfer In the following cases, 1-unit transfer is performed at one DMAi transfer. (Refer to “Figure 13.8.12.”)

Single transfer mode: except for the last 1-unit transfer
Repeat transfer mode: except for the last 1-unit transfer of a block
Array chain transfer mode: except for the first and last 1-unit transfers of each block
Link array chain transfer mode: except for the first and last 1-unit transfers of each block Right to use bus À Transfer CPU DMAC CPU TransitionTransition Fig. 13.9.1 1-unit transfer À Transition of the right to use bus from CPU to DMAC: 1 cycle \` DMA transfer per 1-transfer unit:
In 2-bus cycle transfer···Read cycle + Write cycle (Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”)
In 1-bus cycle transfer···Refer to “Table 13.4.5.” ´ Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] 2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following conditions:
Transfer source: address direction = forward, start address of data = even, with Wait
Transfer destination: address direction = backward, start address of data = even, without Wait

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(2) Last transfer of each block In the following cases, 1-unit transfer and the processing for 3 cycles are performed sequentially.

Single transfer mode: the last 1-unit transfer
Repeat transfer mode: the last 1-unit transfer of a block
Array chain transfer mode: the last 1-unit transfer of each block (including the last block)
Link array chain transfer mode: the last 1-unit transfer of each block (including the last block) Termination etc. Right to use bus CPU DMAC CPU Transfer Transition ´ ˆÀ Transition Fig. 13.9.2 Last transfer of each block À Transition of the right to use bus from CPU to DMAC: 1 cycle \` DMA transfer per 1-unit transfer:
In 2-bus cycle transfer···Read cycle + Write cycle (Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”)
In 1-bus cycle transfer···Refer to “Table 13.4.5.” ´ Terminate processing or the last processing of each block: 3 cycles ˆ Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] 2-bus cycle transfer, transfer unit =16 bits, external data bus width = 16 bits, and under the following conditions:
Transfer source: address direction = forward, start address of data = even, with Wait
Transfer destination: address direction = backward, start address of data = even, without Wait

(3) Transfer of array state In the following cases, the processing in an array state and the first 1-unit transfer are performed

Array chain transfer mode: the first transfer of each block
Link array chain transfer mode: the first transfer of each block Right to use bus Array state CPU DMAC CPU Transfer Transition ˆ Transition Fig. 13.9.3 Transfer of array state À Transition of the right to use bus from CPU to DMAC: 1 cycle \` Array state: The number of transfer parameters × the number of reads of a transfer parameter × the number of bus cycles for a read + 1 cycle (Refer to “Table 13.9.1.”) ´ DMA transfer per 1-unit transfer:
In 2-bus cycle transfer···Read cycle + Write cycle (Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”)
In 1-bus cycle transfer···Refer to “Table 13.4.5.” ˆ Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] Link array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, and under the following conditions:
Transfer source: address direction = forward, start address of data = even, with Wait
Transfer destination: address direction = backward, start address of data =odd, with Wait Table 13.9.1 Time required for processing in array state External data bus width Mode Transfer method Array chain transfer mode 16 bits (Including internal bus) 8 bits 8 bits 16 bits (Including internal bus) Link array chain transfer mode 2-bus cycle transfer 1-bus cycle transfer 2-bus cycle transfer 1-bus cycle transfer 2-bus cycle transfer 1-bus cycle transfer 2-bus cycle transfer 3 1-bus cycle transfer 3 × 2 × 3 + 1 = 19 2 × 2 × 3 + 1 = 13 3 × 4 × 3 + 1 = 37 2 × 4 × 3 + 1 = 25 4 × 2 × 3 + 1 = 25 3 × 2 × 3 + 1 = 19 4 × 4 × 3 + 1 = 49 3 × 4 × 3 + 1 = 37 Time required for processing in array state (Unit: φ cycle) Number of reads of a transfer parameter Number of transfer parameters

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13.9.2 Burst transfer mode

(1) Single transfer mode Right to use bus CPU DMAC CPU Transfer \ ˆ Transition À Transition Termination Fig. 13.9.4 Single transfer mode (burst transfer mode selected) À Transition of the right to use bus from CPU to DMAC: 1 cycle \ DMA transfer per an entire batch of data:

In 2-bus cycle transfer···(Read cycle + Write cycleh 1) × the number of transfersh 2 h1: Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.” h 2: When the transfer unit is 16 bits, the number of transfers = the number of transfer bytes/2 When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes
In 1-bus cycle transfer···Refer to “Table 13.4.5.” ´ Terminate processing: 3 cycles ˆ Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] External data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of the transfer bytes = 10 bytes, and under the following conditions:
Transfer source: address direction = forward, start address of data = even, with Wait
Transfer destination: address direction = backward, start address of data = even, without Wait

(2) Repeat transfer mode In the repeat transfer mode of burst transfer (edge sense), the method of terminating DMA transfer ___ is only the forced termination by the TC input. Therefore, the time from the CPU’s relinquishing the ___ right to use bus until regaining the right depends on the timing of the TC input. Transfer Right to use bus CPU DMAC CPU TC input 1 block Transfer Transfer ˆ ´À Transition \ ˜ Transition Fig. 13.9.5 Repeat transfer mode (burst transfer mode and edge sense selected) À Transition of the right to use bus from CPU to DMAC: 1 cycle \ DMA transfer per 1 block:

In 2-bus cycle transfer···(Read cycle + Write cycleh 1) × the number of transfersh 2 h1: Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.” h 2: When the transfer unit is 16 bits, the number of transfers = the number of transfer bytes/2 When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes
In 1-bus cycle transfer···Refer to “Table 13.4.5.” ´ Terminate processing: 3 cycles ___ ˆ DMA transfer of the block at the TC input: above \` The number of transfers is assumed to be up to the DMA transfer of 1-unit transfer which was in ___ progress at the TC input. ˜ Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] External data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of the transfer bytes = 10 bytes, and under the following conditions:
Transfer source: address direction = forward, start address of data = even, with Wait
Transfer destination: address direction = backward, start address of data = even, without Wait ___
TC is input when the “m”th byte (m = even) of the “n”th block is in transfer.

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ˆ Array state Transfer TransitionTermination ´´\À Transition (3) Array chain transfer mode and Link array chain transfer mode Fig 13.9.6 Array chain transfer mode and Link array chain transfer mode À Transition of the right to use bus from CPU to DMAC: 1 cycle \ Array state: The number of transfer parameters × the number of reads of a transfer parameter× the number of bus cycles for a read + 1 cycle (Refer to “Table 13.9.1.”) ´ DMA transfer per an entire batch of data:

In 2-bus cycle transfer···(Read cycle + Write cycleh 1) × the number of transfersh 2 h1: Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.” h 2: When the transfer unit is 16 bits, the number of transfers = the number of transfer bytes/2 When the transfer unit is 8 bits, the number of transfers = the number of transfer bytes
In 1-bus cycle transfer···Refer to “Table 13.4.5.” ˆ Last processing of each block: 3 cycles ˜ Terminate processing: 3 cycles ¯ Transition of the right to use bus from DMAC to CPU: 1 cycle [Example] Array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit =16 bits, the number of transfer blocks = 3, and under the following conditions:
Transfer source: address direction = forward, without Wait
Transfer destination: address direction = backward, without Wait
First block: transfer source’s data start address = even, transfer destination’s data start address = even, the number of transfer bytes =10 bytes
Second block: transfer source’s data start address = even, transfer destination’s data start address =odd, the number of transfer bytes =12 bytes
Third block: transfer source’s data start address =odd, transfer destination’s data start address =odd, the number of transfer bytes =14 bytes

14.1 Overview

14.2 Block description

14.3 Setting for DRAMC

14.4 DRAMC operation

14.5 Precautions for DRAMC

14-2 7721 Group User’s Manual DRAM CONTROLLER Table 14.1.1 lists the performance specifications of DRAM controller (hereafter called DRAMC). Table 14.1.1 Performance specifications of DRAMC 14.1 Overview, 14.2 Block description Item DRAM area Refreshing method Refresh timer Multiplexed address pins Performance specifications 0 to 15 Mbytes; programmable in a unit of 1 Mbyte CAS before RAS; dispersive refreshing 8 bits Figure 14.2.1 shows the block diagram of DRAMC. Registers relevant to DRAMC are described below. Bus Access controller RAS and CAS generating circuit Address comparator Address multiplexer Refresh timer 1/(n+1) DRAM control register Address Bits 0–3 A20–A23 A0–A20 f(XIN) f16 RAS CAS MA 0–MA 9 Refresh request Fig. 14.2.1 Block diagram of DRAMC

14-37721 Group User’s Manual DRAM CONTROLLER

14.2.1 DRAM control register

Figure 14.2.2 shows the structure of the DRAM control register. Fig. 14.2.2 Structure of DRAM control register 0 0 0 0 : No DRAM area 0 0 0 1 : F0000016–FFFFFF 16 (1 Mbyte) 0 0 1 0 : E0000016–FFFFFF 16 (2 Mbytes) 0 0 1 1 : D00000 16–FFFFFF 16 (3 Mbytes) 0 1 0 0 : C00000 16–FFFFFF 16 (4 Mbytes) 0 1 0 1 : B0000016–FFFFFF 16 (5 Mbytes) 0 1 1 0 : A0000016–FFFFFF 16 (6 Mbytes) 0 1 1 1 : 90000016–FFFFFF 16 (7 Mbytes) 1 0 0 0 : 80000016–FFFFFF 16 (8 Mbytes) 1 0 0 1 : 70000016–FFFFFF 16 (9 Mbytes) 1 0 1 0 : 60000016–FFFFFF 16 (10 Mbytes) 1 0 1 1 : 50000016–FFFFFF 16 (11 Mbytes) 1 1 0 0 : 40000016–FFFFFF 16 (12 Mbytes) 1 1 0 1 : 30000016–FFFFFF 16 (13 Mbytes) 1 1 1 0 : 20000016–FFFFFF 16 (14 Mbytes) 1 1 1 1 : 10000016–FFFFFF 16 (15 Mbytes) Bit Bit name Functions At reset RW 6 to 4 DRAM area select bits DRAM validity bit (Note) 00 : Invalid (P104–P107 pins function as programmable input ports. A0– A7 pins function as address output pins. Refresh timer stops counting.) 1 : Valid (P10 4–P107 pins function as CAS, RAS, MA8, and MA9. A0–A7 function as MA0–MA 7. Refresh timer starts counting.) DRAM control register (Address 6416) b1 b0b2b3b4b5b6b7 RW 0 – RW Nothing is assigned. The value is “0” at reading. RW b3 b2 b1 b0 RW 0 RW Note: Set the refresh timer (address 6616) before setting this bit to “1.”

14-4 7721 Group User’s Manual DRAM CONTROLLER ST0, ST1 ST0, ST1 ST0, ST1 ([0,0] is output.) ST0, ST1 ST0, ST1 P106/MA 8, P107/MA 9 MA 8, MA9 MA 8, MA9 MA 8, MA9 P10 6, P107 (1) DRAM area select bits (bits 0 to 3) These 4 bits specify a DRAM area of 15 Mbytes maximum in a unit of 1 Mbyte. Figure 14.2.3 shows setting examples of DRAM areas.

1 Mbyte

00000016 00000016 00000016 00000016 10000016 80000016 C00000 16 FFFFFF 16 F0000016 FFFFFF 16 FFFFFF 16 FFFFFF 16

4 Mbytes

DRAM area(00012)DRAM area select bits (Bits 3–0) Minimum Maximum

8 Mbytes 15 Mbytes

Fig. 14.2.3 Setting examples of DRAM areas (2) DRAM validity bit (bit 7) When this bit is set to “1,” pin functions for DRAM control become valid, and the refresh timer starts counting. Table 14.2.1 lists the pin functions for DRAM control. Table 14.2.1 Pin functions for DRAM control Pins A0/MA 0 –A7/MA 7 MA 0–MA 7 A 0–A 7 A 0–A 7 A 0–A 7 P104/CAS, P105/RAS CAS, RAS CAS, RAS CAS, RAS P10 4,P105 A 16/D0–A 23/D7, A8/D8–A 15/D15, R/W, E, BLE, BHE A 16/D0–A 23/D7, A 8/D8–A 15/D15, R/W, E, BLE, BHE A 16/D0–A 23/D7, A 8/D8–A 15/D15 R/W, E, BLE, BHE A 16/D0–A 23/D7, A 8/D8–A 15/D15, R/W, E, BLE, BHE A 16/D0–A 23/D7, A 8/D8–A 15/D15 R/W, E, BLE, BHE OperationDRAM validity bit Accessing DRAM area DRAM refresh Other than the above

14-57721 Group User’s Manual DRAM CONTROLLER

14.2.2 Refresh timer

The refresh timer is an 8-bit timer with a reload register and is used to generate refresh requests for DRAM data. Assuming that the set value of the refresh timer = “n,” the refresh timer counts f16 (n + 1) times. Figure 14.2.4 shows the structure of the refresh timer, and the following formula gives the value to be written to the refresh timer. n = {m [ µs] 5 } – 1 n: a set value of the refresh timer (n = 0116–FF 16) m:a refresh interval Examples of “m”: an average of 15.625 µs for 512 refresh cycles at 8-ms intervals an average of 125 µs for 512 refresh cycles at 64-ms intervals Fig. 14.2.4 Structure of refresh timer b7 b0 Refresh timer (Address 6616) FunctionsBit At reset RW 7 to 0 These bits can be set to “0116” to “FF16.” Assuming that the set value = n, this register divides f16 by (n + 1). Undefined WO Note: Use the LDM or STA instruction for writing to this register. Do not set this register to “0016.” f(XIN)

14-6 7721 Group User’s Manual DRAM CONTROLLER Row address Column address Row address Column address

14.2.3 Address comparator

The address comparator examines whether the address to be accessed is within the DRAM area. When____ ____ this address is within DRAM area, control signals are sent to the RAS and CAS generating circuit and the address multiplexer.

14.2.4 RAS and CAS generating circuit

The RAS signal (a timing signal to latch a row address) and the CAS signal (a timing signal to latch a column address) are generated by a control signal from the address comparator.

14.2.5 Address multiplexer

Address data is time-shared by the control signal from the address comparator and is output to the MA0– MA 9 pins. The time-sharing method depends on the external bus width. Table 14.2.2 lists the time-sharing method for the address at DRAM access. When the 8-bit external bus width is selected, A0–A 19 are time- shared and are output; when the 16-bit external bus width is selected, A1–A 20 are time-shared and are output. Table 14.2.2 Time-sharing method for address at DRAM access Pin name P107/MA9A 1/MA 1 A 2/MA 2 A3/MA 3 A4/MA 4 A 5/MA 5 A7/MA 7 P106/MA8A 0/MA 0 A 1 A 9 A 1 A 9 A10 A10 A 3 A 11 A 3 A 11 A 12 A 12 A 13 A 13 A 6 A 14 A 6 A 14 A 7 A 15 A 7 A 15 A16 A17 A18 A17 A18 A19 A20 A19 Output signal 8-bit external bus width 16-bit external bus width A 0 A 8 A 16 A 8 A6/MA 6

14-77721 Group User’s Manual DRAM CONTROLLER DRAM area setting and DRAM validity selection b7 b0 DRAM area select bits b3 b2 b1 b0

During DRAM area access, CAS, RAS, and MA0–MA 9 are output.
Each time an underflow of the refresh timer occurs, CAS and RAS for refresh are output.
During refresh, ST0 and ST1 output “L” level. Division ratio setting for refresh timer b7 b0 Can be set to “0016” to “FF16” (n). Refresh timer divides f16 by (n+1). Refresh timer (Address 6616) DRAM control register [Address 6416]1 0 0 0 0: No DRAM area 0 0 0 1: Addresses F0000016–FFFFFF 16 (1 Mbyte) 0 0 1 0: Addresses E0000016–FFFFFF 16 (2 Mbytes) 0 0 1 1: Addresses D0000016–FFFFFF 16 (3 Mbytes) 0 1 0 0: Addresses C0000016–FFFFFF 16 (4 Mbytes) 0 1 0 1: Addresses B0000016–FFFFFF 16 (5 Mbytes) 0 1 1 0: Addresses A0000016–FFFFFF 16 (6 Mbytes) 0 1 1 1: Addresses 90000016–FFFFFF 16 (7 Mbytes) 1 0 0 0: Addresses 80000016–FFFFFF 16 (8 Mbytes) 1 0 0 1: Addresses 70000016–FFFFFF 16 (9 Mbytes) 1 0 1 0: Addresses 60000016–FFFFFF 16 (10 Mbytes) 1 0 1 1: Addresses 50000016–FFFFFF 16 (11 Mbytes) 1 1 0 0: Addresses 40000016–FFFFFF 16 (12 Mbytes) 1 1 0 1: Addresses 30000016–FFFFFF 16 (13 Mbytes) 1 1 1 0: Addresses 20000016–FFFFFF 16 (14 Mbytes) 1 1 1 1: Addresses 10000016–FFFFFF 16 (15 Mbytes) DRAM is valid. (P10 4–P107 pins function as CAS,RAS, MA8, and MA9. A0–A7 function as MA0–MA 7 when accessing the DRAM area. Refresh timer starts counting.)

Figure 14.3.1 shows an initial setting example for registers relevant to DRAMC. Fig. 14.3.1 Initial setting example for registers relevant to DRAMC

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14.4.1 Waveform example of DRAM control signals

Figure 14.4.1 shows a waveform example of the DRAM control signals. When DRAM is accessed, the bus__ cycle is always with “wait” (the low-level width of E is equivalent to 2 cycles of φ). It is not affected by the wait bit, the wait bit of the transfer source, and the wait bit of the transfer destination. In the read cycle, the CAS signal falls with a delay of 0.5 cycle of φ after the RAS signal has changed from “H” to “L.” The address bus signal changes from “row address” to “column address” within a____ ____ period from a fall of RAS until a fall of CAS. Pins A 16/D0–A 23/D7 and A8/D8–A 15/D15 output addresses and input data in the same way as in reading external devices other than DRAM. In the write cycle, the CAS signal falls with a delay of 1 cycle of φ after the RAS signal has changed from “H” to “L.” The address bus signal changes “row address” to “column address” within a period____ ____ from a fall of RAS until a fall of CAS. Pins A 16/D0–A 23/D7 and A8/D8–A15/D15 output addresses and data in the same way as in writing external devices other than DRAM. In the refresh cycle, the RAS signal falls with a delay of 0.5 cycle of φ after the CAS signal has R/W is undefined. One refresh request requires 5 cycle of φ, including the time for passing the right to use buses.

14-97721 Group User’s Manual DRAM CONTROLLER Fig. 14.4.1 Waveform example of DRAM control signals Column address E RAS CAS R/W (a) At reading Row address Column address Address Data Read cycle (1 bus cycle) MA 0–MA 9 A16/D0–A23/D7 A8/D8–A15/D15 E RAS CAS R/W MA 0–MA 9 A16/D0–A23/D7 A8/D8–A15/D15 (c) At refresh Undefined Refresh cycle Undefined Undefined Floating Transition of right to use bus E RAS CAS R/W MA 0–MA 9 A16/D0–A23/D7 A8/D8–A15/D15 (b) At writing Row address Address Data Write cycle (1 bus cycle) Undefined Transition of right to use bus

14-10 7721 Group User’s Manual DRAM CONTROLLER DMAC CPU

14.4.2 Refresh request

À When the DRAM validity bit is set to “1,” the refresh timer starts counting down. The count source is f16. \` When the contents of the refresh timer reach “0016,” a refresh request occurs. The refresh timer reloads the contents of address 6616 and continues counting. ´ Refresh requests are sampled as bus requests (DRAMC) by using the bus access controller. As soon as a refresh request is acknowledged by sampling, the following ˆ is performed because DRAM refresh has the highest priority in using the bus. However, when the CPU or DMAC uses the bus, no bus request is sampled until the CPU or DMAC releases the bus. Therefore, in a period from when a refresh request occurs until DRAM refresh is performed, the delay listed in Table 14.4.1 occurs depending on the refresh request generating timing. Figures 14.4.2 and 14.4.3 show refresh delay time examples when CPU is operating and during DMA transfer. For a bus request, refer to “13.2.1 Bus access control circuit.” ˆ When the refresh request is accepted, the right to use the bus is passed to DRAM refresh (1 cycle of φ). Both of the output levels of ST1 and ST0 are “L.” (The bus status is indicated as [0, 0].)____ ____ ˜ The RAS and the CAS signals are output and the DRAM data is refreshed (refresh cycle: 3 cycles of φ). ¯ The right to use the bus is passed to the CPU, DRAM or Hold (1 cycle of φ). The outputs of ST1 and ST0 change. Note: In Stop or Wait mode, DRAM refresh is not performed because no refresh request occurs. Table 14.4.1 Delay time from when refresh request occurs until DRAM refresh is performed Maximum (with Wait)Maximum (no Wait)Minimum 1.5 1.5 1.5 4.5 8.5 11.5 6.5 1.5 6.5 12.5 15.5 6.5 1.5 Source of using bus Array state Transfer (a unit of 1 transfer) Transfer (a unit of 1 transfer) + Complete cycle Delay time (unit: φ cycle) Note: The above is applied when Ready is not used. The delay time includes the time for passing the right to use buses to DRAM refresh (1 cycle).

14-117721 Group User’s Manual DRAM CONTROLLER Fig. 14.4.2 Refresh delay time example when CPU is operating E R/W Refresh request Bus request (DRAMC) Bus request sampling ST1,ST0 11 (CPU) 00 (Refresh) Refresh cycleDelay time (Max.): 6.5 cycles of Refresh cycle Transition of right to use bus The following are internal signals:

Refresh request
Bus request (DRAMC)
Bus request sampling Refresh request becomes “0” at an underflow of the refresh timer. Delay time (Min.): 1.5 cycles of Transition of right to use bus Transition of right to use bus Transition of right to use bus 10 (DMAC) 00 (Refresh) Refresh cycleDelay time (Max.): 12.5 cycles of E R/W Refresh request Bus request (DRAMC) Bus request sampling ST1,ST0 The following are internal signals:
Refresh request
Bus request (DRAMC)
Bus request sampling Refresh request becomes “0” at an underflow of the refresh timer. Transition of right to use bus Fig. 14.4.3 Refresh delay time example during DMA transfer

14-12 7721 Group User’s Manual DRAM CONTROLLER

Set the refresh timer (address 6616) to any of 0116–FF 16. 2. When a DRAM refresh request occurs during Hold state, a refresh cycle is activated regardless of the bus state. It is because a bus request is always sampled during Hold state. Therefore, in order to use the DRAMC together with the Hold function, an external circuit which is controlled depending on the states of ST0 and ST1 is required. 3. DRAM refresh is not performed in Stop or Wait mode.

15.1 Block description

15.2 Operation description

15.3 Precautions for Watchdog timer

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Watchdog functions as follows: l Detects a program runaway. l Measures a certain time from when oscillation starts owing to terminating Stop mode. (Refer to section “5.3 Stop mode.”) Figure 15.1.1 shows the block diagram of Watchdog timer. Fig. 15.1.1 Block diagram of Watchdog timer 2Vcc detection circuit “FFF16” is set. Writing to watchdog timer register (address 6016) STP instruction Bus request (Hold) Watchdog timer interrupt request RESET S Q R f32 Watchdog timer CPU wait request f512 Bus request (DRAMC) Bus request (DMAC)

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15.1.1 Watchdog timer

Watchdog timer is a 12-bit counter where the count source which is selected with the watchdog timer frequency select bit (bit 0 at address 6116) is counted down. A value “FFF16” is automatically set in Watchdog timer in the cases listed below. An arbitrary value cannot be set to Watchdog timer. l When dummy data is written to the watchdog timer register (Refer to “Figure 15.1.2.”) l When the most significant bit of Watchdog timer becomes “0” l When the STP instruction is executed (Refer to section “5.3 Stop mode.”) l At reset Fig. 15.1.2 Structure of watchdog timer register

15.1.2 Watchdog timer frequency select register

This is used to select a Watchdog timer’s count source. Figure 15.1.3 shows the structure of the watchdog timer frequency select register. Fig. 15.1.3 Structure of watchdog timer frequency select register b7 b0 Watchdog timer register (Address 6016) Bit Initializes Watchdog timer. When dummy data is written to this register, Watchdog timer’s value is initialized to “FFF 16.” (Dummy data: 0016 to FF16) At reset Undefined RWFunctions 7 to 0 – 0 : f512 1 : f32 At reset Undefined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit Nothing is assigned. Watchdog timer frequency select bit Bit name 7 to 1 RW

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15.2.1 Basic operation

À Watchdog timer starts counting down from “FFF16.” \ When the Watchdog timer’s most significant bit becomes “0” (counted 2048 times), a watchdog timer interrupt request occurs. (Refer to “Table 15.2.1.”) ´ When the interrupt request occurs at above \ , a value “FFF16” is set to Watchdog timer. The watchdog timer interrupt is a non-maskable interrupt. When the watchdog timer interrupt request is accepted, the processor interrupt priority level (IPL) is set to “1112.” Table 15.2.1 Occurrence interval of watchdog timer interrupt request f(XIN) = 25 MHz Occurrence interval 41.94 ms 2.62 ms Count source f512 f32 Watchdog timer frequency select bit

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Write dummy data to the watchdog timer register (address 6016) before the most significant bit of Watchdog timer becomes “0.” When Watchdog timer is used to detect a program runaway, a watchdog timer interrupt request occurs if writing to address 6016 is not performed owing to a program runaway and the most significant bit of Watchdog timer becomes “0.” This means that a program runaway has occurred. In order to reset the microcomputer when a program runaway is detected, write “1” to the software reset bit (bit 3 at address 5E16) in the watchdog timer interrupt routine. Watchdog timer interrupt routine Watchdog timer register (Address 6016) 8-bit dummy data Watchdog timer interrupt request occur (program runaway detected) Watchdog timer initialized Value of watchdog timer : “FFF 16” (Note 1) Software reset bit (Address 5E 16, b3) “1” (Note 2) Reset microcomputer Notes 1: Initialize Watchdog timer before the most significant bit of Watchdog timer becomes “0.” (Write dummy data to address 6016 before a watchdog timer interrupt request occurs). 2: When a program runaway occurs, values of the data bank register (DT), direct page register (DPR), etc., may be changed. When “1” is written to the software reset bit by the addressing mode using DT, DPR, etc., set values to DT and DPR again. Fig. 15.2.1 Example of program runaway detection by Watchdog timer

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15.2.2 Stop period

Watchdog timer stops operation in the following period: À Hold state (Refer to section “3.4 Hold function.”) \` During DMAC operation (Refer to “CHAPTER 13. DMA CONTROLLER.” ) ´ During DRAM refresh (Refer to “CHAPTER 14. DRAM CONTROLLER.” ) ˆ Stop mode When states À to ´ are terminated, Watchdog timer restarts counting from the state before it stops operation. For Watchdog timer’s operation when state ˆ is terminated, refer to section “15.2.3 Operation in Stop mode.”

15.2.3 Operation in Stop mode

In Stop mode, Watchdog timer stops operation. Immediately after Stop mode is terminated, Watchdog timer operates as follows. (Refer to section “5.3 Stop mode.”) (1) When Stop mode is terminated by hardware reset Supply of φ and φCPU starts immediately after Stop mode is terminated, and the microcomputer performs “operation after reset.” (Refer to “CHAPTER 4. RESET.” ) The watchdog timer frequency select bit becomes “0,” and Watchdog timer starts counting of f512 from “FFF16.” (2) When Stop mode is terminated by interrupt request occurrence Immediately after Stop mode is terminated, Watchdog timer starts counting of f32 from “FFF16” regardless of the contents of watchdog timer frequency select bit (bit 0 at address 6116). Supply of φ and φCPU starts when Watchdog timer’s most significant bit becomes “0.” (At this time, a watchdog timer interrupt request does not occur.) When supply of φCPU starts, the microcomputer executes the routine of the interrupt which is used to terminate Stop mode. Watchdog timer restarts counting of the count source (f32 or f512), which was counted immediately before executing the STP instruction, from “FFF16.”

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When dummy data is written to address 6016 with the 16-bit data length, writing to address 6116 is simultaneously performed. Accordingly, when the user does not want to change a value of the watchdog timer frequency select bit (bit 0 at address 6116), write the previous value to the bit simultaneously with writing to address 6016. 2. When the STP instruction is executed, Watchdog timer stops. (Refer to section “5.3 Stop mode.”) 3. Watchdog timer stops during DRAM refresh, hold state, and DMAC operation. (For Watchdog timer’s structure, refer to “Figure 15.1.1.”) Accordingly, when a bus request is changed in the period which is shorter than 1 cycle of the count source (Note), Watchdog timer’s count may gain. (Refer to “Figure 15.3.1.”) Note: f32 or f512, which is selected by the watchdog timer frequency select bit Fig. 15.3.1 Count source for Watchdog timer f32 or f512 Bus request Count source which is actually counted by Watchdog timer In case the bus request is changed in a period which is shorter than 1 cycle of f32 or f512

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16.1 Memory connection

16.2 Examples of using DMA controller

16.3 Comparison of sample program

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This chapter describes application. Application shown here is just examples. The user shall modify them according to the actual application and test them. This section shows examples for memory and I/O connection. Refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES” for details about the functions and operations of used pins when connecting a memory or I/O. Refer to section “Appendix 11. Electrical characteristics” for timing requirements of the microcomputer.

16.1.1 Memory connection model

For the M37721, the level of the external data bus width select signal makes it possible to select the memory connection model from the four models listed in Table 16.1.1. (1) Minimum model This is a connection model of which external data bus width is 8 bits and access space is expanded up to 64 Kbytes. It is unnecessary to connect the address latch externally, so this model gives priority to cost and is most suitable when connecting the memory of which data bus width is 8 bits. (2) Medium model A This is a connection model of which external data bus width is 8 bits and access space is expanded up to 16 Mbytes. In this model, the high-order 8 bits of the external address bus (A16 to A23) are multiplexed with the external data bus. Therefore, an n-bit (n ≤ 8) address latch is required for latching n bits of the address in A16 to A23. (3) Medium model B This is a connection model of which external data bus width is 16 bits and access space is expanded up to 64 Kbytes. This model gives priority to rate performance. In this model, the middle-order 8 bits of the external address bus (A8 to A15) are multiplexed with the external data bus. Therefore, an 8- bit address latch is required for latching A8 to A15. (4) Maximum model This is a connection model of which external data bus width is 16 bits and access space is expanded up to 16 Mbytes. In this model, the high- and middle-order 16 bits of the external address bus (A8 to A23) are multiplexed with the external data bus. Therefore, an 8-bit address latch for latching A8 to A15 and an n-bit (n ≤ 8) address latch for latching n bits of A16 to A23 are required.

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Table 16.1.1 Memory connection model BYTE BYTE M37721 BYTE M37721 BYTE M37721 A0–A15 D 0–D 7 A0–A15 E D 0–D 15 DQ A0–A15+n D 0–D 7 16+n E n DQ Latch E A0–A15+n D 0–D 15 n 16+n DQ E DQ A0–A7 ALE BHE M37721 ALE ALE BHE 8-bit width; BYTE = “H” Notes 1: Refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES” for details about the functions and operations of used pins when connecting a memory. Refer to section “Appendix 11. Electrical characteristics” for timing requirements. 2: Because the address bus can be expanded up to 24 bits when connecting a memory, strengthen the M37721’s Vss and Vcc lines on the system. (Refer to section “Appendix 8. Countermeasure against noise.”) External data bus width 16-bit width; BYTE = “L” Access space Maximum 64 Kbytes Maximum 16 Mbytes Memory connection modelMinimum model Latch Memory connection modelMedium model B Memory connection modelMedium model A Latch Latch Memory connection modelMaximum model A8–A15 A16/D0–A23/D7 A0–A7 A8–A15 A16/D0–A23/D7 A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 BLE A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 BLE

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16.1.2 How to calculate timing

Timings at which data is read or written when connecting a memory and precautions when connecting a memory are described below. For timing requirements of the memory and detailed account except limits described below, also refer to the memory’s Data book etc. When using bus buffers, various logical circuits, etc., be sure to consider the propagation delay time etc. (1) Timing for reading data When reading data, the external data bus is placed in a floating state, and data is read from the external memory. This floating state is maintained after the falling edge of the E signal until an_ interval of tpzx(E–DLZ/DHZ) has passed after the rising edge of the E signal. Satisfy tsu(DL/DH-E) when inputting data read from the external memory. The following are described below:

Timing for reading data from the flash memory, SRAM, and DRAM
Calculation formulas for the external memory’s access time, which are for t su(DL/DH-E) to be satisfied___ __ The memory output enable signal (OE) is assumed to be generated from the E signal. l Timing for reading data from flash memory and SRAM Fig. 16.1.1 Timing for reading data from flash memory and SRAM External memory data output ]1: This applies when the external data bus has a width of 16 bits (BYTE = “L”). External memory output enable signal (Read signal) OE E External memory chip select signal CE, S ]2: If data is output from the external memory before the falling edge of E, there is a possi bility that the tail of address collides wit t h the head of data. of collides wi h the head of . → Refer to section “(3) Precautions on memory connection.” ]3: If one of the external memory’s specifications is greater than tpzx(E-DLZ/DHZ) , there is a possibility that the tail → Refer to section “(3) Precautions on memory connection.” Address output and Data input A8/D 8–A15/D15 A16/D0–A23/D7 ten(OE) Address tpzx(E-DLZ/DHZ) tsu(DL/DH-E) : Specifications of the M37721 (The others are specifications of external memory.) ta(OE) tDF , tdis(OE) tw(EL) Data ten(CE), ten(S) Address ta(CE), ta(S) ta(AD), tsu(A-DL/DH) Note: tsu(A-DL/DH) : tsu(A-DL) or tsu(A-DH) tpzx(E-DLZ/DHZ) : tpzx(E-DLZ) or tpzx(E-DHZ) tsu(DL/DH-E) : tsu(DL-E) or tsu(DH-E) data address

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Address access time : ta(AD) ≤ tsu(A-DL/DH) – address latch delay time] 1 ___ OE access time : ta(OE) ≤ tw(EL) – tsu(DL/DH-E) Chip select access time : ta(S) ≤ tsu(A-DL/DH) – (address decode time] 2 + address latch delay time] 1) Address latch delay time] 1 : Delay time required when latching address (Unnecessary in minimum model) Address decode time] 2 : Time required for validating chip select signal after decoding address 16.1.2 shows the relationship between tsu(A-DL/DH) and f(XIN). Table 16.1.2 Calculation formulas and Values for each parameter in Figure 16.1.1 (unit : ns) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 200 300 400 500 600 700 644 555 485 430 384 346 314 287 263 242 224 207 193 180 168 157 147 138 130 358 305 263 230 202 180 160 144 130 117 106 96 87 80 72 66 60 55 50 [ns] [MHz] External clock input frequency f(XIN) Data setup time with address stabilized tsu(A–DL/DH) Wait No Wait Calculation formulas and Values No Wait Wait tw(EL) tsu(A-DL) tsu(A-DH) tpzx(E-DLZ) tpzx(E-DHZ) tsu(DL-E) tsu(DH-E) 2 5 109 f(XIN) 3 5 109 f(XIN) –25 4 5 109 f(XIN) 5 5 109 f(XIN) –25 –70–70 1 5 109 f(XIN) –20 Fig. 16.1.2 Relationship between tsu(A-DL/DH) and f(XIN)

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l Timing for reading data from DRAM Fig. 16.1.3 Timing for reading data from DRAM ____ CAS access time : tCAC ≤ tw(EL) – td(E-CASL) – tsu(DL/DH-E)____ RAS access time : tRAC ≤ tw(EL) – td(E-RASL) – tsu(DL/DH-E) Column address access time : tAA ≤ tw(EL) – td(E-CA) – tsu(DL/DH-E)___ OE access time : tOEA ≤ tw(EL) – tsu(DL/DH-E) 16.1.4 shows the relationship between tCAC , tRAC , tAA and f(XIN). tw(EL) td(E-RASL) td(E-CA) Address tOEA tRAC tCLZ tCAC tOEZ ]2 td(E-CASL) Row address Column address E RAS CAS Address output (MA 0–MA 7) Address output and Data I/O tAA tsu(DL/DH-E) A8/D8–A15/D15 A16/D0–A23/D7 DRAM data output Data : Specifications of the M37721 (The others are specifications of DRAM.) ]1 This applies when the external data bus has a width of 16 bits (BYTE = “L”). ]2 If one of DRAM’s specifications is greater than tpzx(E–DLZ/DHZ) , there is a possibility that the tail of data collides with the head of address. → Refer to section “(3) Precautions on memory connection.” Note: tpzx(E-DLZ/DHZ) : tpzx(E-DLZ) or tpzx(E-DHZ) tsu(DL/DH-E) : tsu(DL-E) or tsu(DH-E) OE DRAM output enable signal (Read signal) tpzx(E–DLZ/DHZ)

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Table 16.1.3 Calculation formula and Value for each parameter in Figure 16.1.3 (unit : ns) Calculation formula and Value tw(EL) td(E-RASL) td(E-CASL) td(E-CA) tpzx(E-DLZ) tpzx(E-DHZ) tsu(DL-E) tsu(DH-E) 1 5 109 f(XIN) 4 5 109 f(XIN) – 25 + 37.5 1 5 109 f(XIN) + 25 1 5 109 f(XIN) – 20 Note: When accessing DRAM, Wait is always inserted regardless of the contents of the Wait bit, source’s Wait bit, and destination’s Wait bit. Fig. 16.1.4 Relationship between tCAC , tRAC , tAA and f(XIN) 7 8 9 10 11 12 137.5 13 14 15 16 17 18 19 20 21 22 23 24 25 100 150 200 250 300 350 400 450 500 451 380 324 280 243 213 187 165 146 130 115 102 90 80 70 61 53 46 40 486 415 359 315 278 248 222 181 165 150 137 125 115 105 96 88 81 75 335.5 282.5 240.5 207.5 179.5 157.5 Column address access time : tAA RAS access time : tRAC CAS access time : tCAC Access time [ns] External clock input frequency f(XIN) [MHz] 107.5 121.5 200

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(2) Timing for writing data When writing data, the output data is stabilized when an interval of td(E-DLQ/DHQ) has passed after the_ falling edge of the E signal. This data is continuously output until when an interval of th(E-DLQ/DHQ) has_ passed after the rising edge of the E signal. Data to be written to an external memory must satisfy the data set up time (tsu(D)) (for DRAM, the data hold time (tDH )) of the external memory. The following are described below:

Timing for writing data to flash memory, SRAM, and DRAM
Calculation formulas which are for t su(D) and tDH to be satisfied l Timing for writing data to flash memory and SRAM tsu(D) th(D) AddressData E W External memory chip select signalsCE, S tw(EL) th(E-DLQ/DHQ) (The others are specifications of external memory.) : Specifications of the M37721 ] This applies when the external data bus has a width of 16 bits (BYTE = “L”). td(E–DLQ/DHQ) A8/D8–A15/D15 A16/D0–A23/D7 Address output and Data input External memory write signal Address Fig. 16.1.5 Timing for writing data to flash memory and SRAM Data setup time : tsu(D) ≤ tw(EL) – td(E-DLQ/DHQ) Table 16.1.4 lists the calculation formulas and values for each parameter in Figure 16.1.5, Figure 16.1.6 shows the relationship between tsu(D) and f(XIN).

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Table 16.1.4 Calculation formulas and Values for each parameter in Figure 16.1.5 (unit : ns) Calculation formulas and Values No Wait Wait tw(EL) td(E-DLQ) td(E-DHQ) th(E-DLQ) th(E-DHQ) 2 5 109 f(XIN) –25 4 5 109 f(XIN) –25 1 5 109 f(XIN) –22 Fig. 16.1.6 Relationship between tsu(D) and f(XIN) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 200 300 400 500 600 506 435 379 335 298 268 242 220 201 185 170 157 145 135 125 116 108 101 95 220 185 157 135 116 101 88 77 68 60 52 46 40 35 30 25 21 18 15 No Wait Wait External clock input frequency f(XIN) Data setup time tsu(D) [MHz] [ns]

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l Timing for writing data to DRAM Fig. 16.1.7 Timing for writing data to DRAM Data hold time : tDH ≤ tw(EL) – td(E-CASL) + th(E-DLQ/DHQ) 16.1.8 shows the relationship between tDH and f(XIN). DRAM write signal W tw(EL) td(E-CASL) Row address Column address Address Data td(E-DLQ/DHQ) tDH th(E-DLQ/DHQ)] This applies when the external data bus has a width of 16 bits (BYTE = “L”). E RAS CAS Address output (MA0–MA 7) Address output and Data I/O A8/D8–A15/D15 A16/D0–A23/D7 : Specifications of the M37721 (The others are specifications of DRAM.)

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Table 16.1.5 Calculation formula and value for each parameter in Figure 16.1.7 (unit : ns) Calculation formula and Value tw(EL) td(E-CASL) td(E-DLQ) td(E-DHQ) th(E-DLQ) th(E-DHQ) 4 5 109 f(XIN) –25 80 to 115 1 5 109 f(XIN) –22 Note: When accessing DRAM, Wait is always inserted regardless of the contents of the Wait bit, source’s Wait bit, and destination’s Wait bit. Fig. 16.1.8 Relationship between tDH and f(XIN) 100 200 300 400 500 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 2 2 32 42 5 486.5 415.5 359.5 315.5 278.5 248.5 222.5 200.5 181.5 tDH [ns] External clock input frequency f(XIN) [MHz]

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(3) Precautions on memory connection As described in À to ´ below, if specifications of the external memory do not match those of the M37721, some considerations must be incorporated into circuit design: À When using an external memory that requires a long access time _ \` When data is output from an external memory before falling edge of the E signal ´ When using an external memory that outputs data for more than tpzx(E-DLZ/DHZ) after rising edge of_ the E signal À When using external memory that requires long access time If the M37721’s tsu(DL/DH-E) cannot be satisfied because the external memory requires a long access time, try to carry out the following: l Lower f(XIN). l Select “software Wait is inserted.” (Refer to section “3.2 Software Wait.”) l Use Ready function. (Refer to section “3.3 Ready function.”) an example of using Ready function (software Wait). Ready function is valid for the internal areas, so that the circuits in Figures 16.1.9 and 16.1.10 use___ ___ the chip select signal (CS2) to specify areas where Ready function is valid. In these cases, the CS2 signal is externally generated.

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A8–A23 (D0–D 15) A0–A7 RDY E Address decode circuit D CK Q AC74 AC32 AC32 Data bus CS 1 CS 2 Address bus AC04 Validate Ready function only for areas accessed by CS Circuit conditions : f(XIN) ≤ 15.7 MHz, no software Wait ]1 to ]3 : Make sure that the sum of propagation delay time is within 15 ns. ]3 to ]5 : Make sure that the sum of propagation delay time is within 72 ns. Ready request is accepted at A . Termination request for Ready state is accepted at B . A , B : Judgement timing of RDY pin’s input level tc td(E- 1) E CS 2 Q RDY tsu(RDY- 1) AC32(tPHL ) A B ]2]1 Address latch circuit : E (“L” level) stopped by Ready function ] The condition satisfy tsu(RDY– 1) ≥ 55 ns is tc ≥ 63.5 ns. (This applies when AC32’s propagation delay time is within 8.5 ns.) Accordingly, when f(XIN) ≤ 15.7 MHz, this circuit example satisfies tsu(RDY– 1) ≥ 55 ns. Fig. 16.1.9 Example of using Ready function (no software Wait)

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Fig. 16.1.10 Example of using Ready function (software Wait) M37721 1CK AC74 AC32 AC32 AC04 2CK CLR AC04 E CS 2 RDY tsu(RDY- 1) AC04 + AC74 + AC32’s propagation delay time th( 1-RDY) A B A8–A23 (D0–D 15) A0–A7 RDY E Address decode circuit Address latch circuit Data bus CS 1 CS 2 Address bus Validate Ready function only for areas accessed by CS ]1 to ]3 : Make sure that the sum of propagation delay time is within 25 ns. Circuit conditions : f(XIN) ≤ 25 MHz, software Wait Ready request is accepted at A . Termination request for Ready state is accepted at B . A , B : Judgement timing of RDY pin’s input level : E (“L” level) stopped by Ready function : E (“L” level) stopped by software Wait

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\` When data is output from external memory before falling edge of E signal_ Because the external memory outputs data before the falling edge of the E signal, there is a possibility that the tail of address collides with the head of data. In such a case, generate the__ _ external memory read signal (OE) by using E. (Refer to “Figure 16.1.11.”) Fig. 16.1.11 Example of making data output timing delayed ´ When using external memory that outputs data for more than tpzx(E-DLZ/DHZ) after rising edge of_ E signal Because the external memory outputs data for more than tpzx(E-DLZ/DHZ) after the rising edge of the_ E signal, there is a possibility that the tail of data collides with the head of address. In such a case, try to carry out the following: l Cut the tail of data output from the memory by using, for example, a bus buffer. l Use the Mitsubishi’s memory chips that can be connected without a bus buffer. lists the Mitsubishi’s memory chips that can be connected without a bus buffer. When using one of these memory chips, timing parameters t DF and tdis(OE) listed below are guaranteed. Accordingly,___ no bus buffer is necessary for the system where the external memory’s read signal (OE) goes high_ within tpzx(E-DLZ/DHZ) -tDF (or tdis(OE)) [ns] after the rising edge of the E signal. Table 16.1.6 Mitsubishi’s memory chips that can be connected without bus buffers Note: Make sure that d ≥ 0 is satisfied when generating the external memory read signal (OE). External memory output enable signal (Read signal) Address ta(OE) E OE Address output External memory data output Specifications of external memory d ten(OE) Address Data Memory Flash memory SRAM Type M5M28F101AP, FP, J, VP, RV-85, -10 M5M28F102AFP, J, VP-85, -10 M5M5256DP, FP, KP, VP, RV-45LL, -45XL, -55LL, -55XL, -70LL, -70XL M5M5278DP, J-12 M5M5278DP, FP, J-15, -15L M5M5278DP, FP, J-20, -20L tDF /tdis(OE) (Maximum) 15 ns (Guaranteed as kit.) (Note) 6 ns 7 ns 8 ns Note: tDF or tdis(OE) listed above is guaranteed when these memory chips are connected with the M37721. When the user wants specifications of these memory chips, add a comment “tDF /tdis(OE) = 15 ns, microcomputer and kit.”

7721 Group User’s Manual16–16

CNVss A0–A7 BYTE ALE A8/D8–A15/D15 E R/W BHE BLE XIN XOUT A16/D0–A23/D7 RD WO WE DQ LE OE DQ LE OE AB DIR OC AB DIR OC AC245 AC245 AC573 AC573 AC32 AC04 AC32

25 MHz

Data bus (odd) Address bus Data bus (even) Circuit condition: Software Wait ]1: Make sure that the propagation delay time is within 20 ns. ]2, ]3: Make sure that the sum of output disable time in ]2 and propagation delay time in ]3 is within 20 ns. ]4: Make sure that the propagation delay time is within 15 ns. Fig. 16.1.12 Example of using bus buffers (1)

7721 Group User’s Manual 16–17

D AC245(tPHZ /tPLZ )AC245 PZH /tPZL ) AC32(tPHL ) AC32(t PLH ) tw(EL) = 135 (min.) tpzx(E-DLZ/DHZ) = 20 (min.) E A8/D8–A15/D15 A16/D0–A23/D7 OC(AC245), RD E A8/D8–A15/D15 A16/D0–A23/D7 OC(AC245), WO, WE A A D AC245 (tPHZ /tPLZ ) AC245 PHL /tPLH ) AC32(tPHL ) AC32(tPLH ) td(E-DLQ/DHQ) = 35 (max.) tw(EL) = 135 (min.) D <When reading> <When writing> (Unit : ns) Data output A from external memory (AC245) Data output B from external memory (AC245) Fig. 16.1.13 Timing chart for circuit example using bus buffers (1)

7721 Group User’s Manual16–18

CNVss A0–A7 BYTE ALE A8/D8–A15/D15 E R/W BHE BLE XIN XOUT A16/D0–A23/D7 Address bus AB DIR OC AB DIR OC AC245 DQ LE OE AC573 DQ LE OE AC573 RD WO WE AC32 AC04 AC32 Data bus (even) Data bus (odd) These circuits make the occurrence of the write signal’s rising edge earlier by 1/21, so that the write hold time is extended. Circuit condition : Software Wait ]1: Make sure that the propagation delay time is within 20 ns. ]2: Make sure that the output disable time is within 20 ns. Fig. 16.1.14 Example for using bus buffers (2) (connecting with memory requiring long data hold time for writing)

7721 Group User’s Manual 16–19

D AC245(tPHZ /tPLZ )AC245 PZH /tPZL ) AC32(tPHL ) AC32(t PLH ) tw(EL) = 135 (min.) tpzx(E-DLZ/DHZ) = 20 (min.) E, OC (AC245) A8/D8–A15/D15 A16/D0–A23/D7 RD E, OC (AC245) A8/D8–A15/D15 A16/D0–A23/D7 A D AC245 (tPHL /tPLH ) 35 (max.) D AC245 (tPHZ /tPLZ ) AC32 5 2(tPLH ) AC04(tPLH ) + AC74(tPLH ) 1Q (AC74) 2Q (AC74) WO, WE <When reading> Data output A from external memory (AC245) <When writing> (Unit : ns) Write hold time tw(EL) = 135(min.) Data output B from external memory (AC245) Fig. 16.1.15 Timing chart for circuit example using bus buffers (2)

7721 Group User’s Manual16–20

16.1.3 Example of memory connection

Examples of the flash memory, SRAM, and DRAM connection and the timing charts are described as follows. (1) Example of flash memory connection (minimum model) M37721 A0–A15 BYTE AC04 D 0–D 7 BHE BLE E R/W Address bus A0–A15 Data bus D0–D 7 A0–A15 D 0–D 7 WE CEOE M5M28F101AFP-10 000016 008016 048016 1FC0 16 200016 FFFF 16 XIN XOUT ]: Make sure that the propagation delay time is within 25 ns. SFR area Internal RAM area External ROM area (M5M28F101AFP) Memory map SFR area External ROM area (M5M28F101AFP) Circuit condition : Software Wait Fig. 16.1.16 Example of flash memory connection (minimum model)

7721 Group User’s Manual 16–21

<When reading> E, OE A16/D0–A23/D7 RW External ROM data output CE tpzx(E-DLZ) = 20 (min.) AA D th(E-R/W) = 18 (max.) tw(EL) = 135 (min.) tsu(DL-E) ≥ 30 ta(OE)] ta(CE)] tDF ] = 15 (max.) (Guaranteed as kit.) AC04 (tPLH ) td(R/W-E) = 20 (min.) ta (AD)], tsu (A-DL) = 130 (max.) AC04 (tPHL ) td(AH-E) = 15 (min.) ] : Specifications of M5M28F101AFP-10 The others are specifications of M37721. Fig. 16.1.17 Timing chart for flash memory connection example (minimum model)

7721 Group User’s Manual16–22

(2) Example of flash memory and SRAM connection (maximum model) SFR area Internal RAM area External ROM area (M5M28F102AFP) 000016 008016 048016 1FC0 16 200016 1FFFF 16 Memory map External RAM area (M5M5256DP 5 2) 2000016 2FFFF 16 Circuit condition : Software Wait M37721 A1–A7 BYTE ALE A8/D8–A15/D15 E R/W BHE BLE XIN XOUT A16/D0–A18/D2 Address bus Data bus (odd) RD WE WO DQ E E DQ AC573 AC573 AC04 ]3 A B AC139 A0–A14 M5M5256DP-70LL DQ 1–DQ 8 S OE A0–A14 M5M5256DP-70LL DQ 1–DQ 8 S A0–A15 M5M28F102AFP -10 D 0–D 15 CE OE WE AC32 ]4 AC32 ]5 D 3–D 7 A8–A16 A1–A15 D 8–D 15 A1–A15 D 0–D 7 A1–A16 D 0–D 15 A18 A17 (M5M28F102AFP) ]1, ]2: Make sure that the sum of propagation delay time is within 30 ns. ]3, ]4: Make sure that the sum of propagation delay time is within 20 ns. ]5: Make sure that the propagation delay time is within 5 ns. Data bus (even) Fig. 16.1.18 Example of flash memory and SRAM connection (maximum model)

7721 Group User’s Manual 16–23

WE, WO th(E-DLQ/DHQ) = 18 (min.) (Unit : ns) <When writing> E A1–A7 S AA tw(EL) = 135 (min.) AC32(tPLH ) AC573(tPHL )+AC139(tPHL ) tsu (D)]] ≥ 30 td(AL-E) = 15 (min.) A8/D8–A15/D15 A16/D0–A18/D2 D 3–D 7 A A AC32(tPHL ) D td (E-DLQ/DHQ) = 35 (max.) ]: Specifications of M5M28F102AFP-10 ] ]: Specifications of M5M5256DP-70LL The others are specifications of M37721. E A1–A7 CE, S External memory data output OE A8/D8–A15/D15 A16/D0–A18/D2 D 3–D 7 <When reading> AA D tw(EL) = 135 (min.) tsu(DL/DH-E) ≥ 30 ta(OE)]] tsu(A-DL/DH) = 130 (max.) ta(AD)]] +AC573(tPHL /tPLH ) tDF ]/tdis(OE)]] = 15 (max.) (Guaranteed as kit.) AC32(tPLH ) AC573(tPHL /tPLH )+AC139(tPHL ) td(AL-E) = 15 (min.) tpzx(E-DLZ/DHZ) = 20 (min.) AA ta(CE)], ta(S)]] AC32(tPHL ) ] Fig. 16.1.19 Timing chart for example of flash memory and SRAM connection (maximum model)

7721 Group User’s Manual16–24

(3) Example of DRAM connection (external bus width = 8 bits) À DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 M5M44800CJ-7 MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 MA 8 MA 9 RAS CAS R/W E A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 BYTE RAS CAS W OE M37721 XIN XOUT AC32 ] 00000016 00008016 00047F16 001FC0 16 001FFF 16 F0000016 FFFFFF 16 F7FFFF 16 SFR area Internal RAM area DRAM area (M5M44800CJ) Memory map Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00012” ]: Make sure that the propagation delay time is within 80 ns. SFR area Not used Not used Not used Fig. 16.1.20 Example of M5M44800CJ (512K 5 8 bits) connection (external bus width = 8 bits)

7721 Group User’s Manual 16–25

tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 92.5 (min) td(RAS-CAS) = 28 (min) tw(RASH) = 60 (min) td(E-RASL) = 30 (max) td(RA-RAS) = 5 (min) td(E-CA) = 60 (max) Input dataAddress tOEA ] = 20 (max) tRAC ] = 70 (max) tCLZ ] = 5 (min) tCAC ] = 20 (max) tsu(DL-E) ≥ 30 tOEZ ] = 0–20 tpzx(E-DLZ) = 20 (min) td(CA-CAS) = 5 (min) td(E-CASL) = 77.5 (max) Row address Column address E (OE) RAS CAS MA 0–MA 9 A16/D0– A23/D7 <When reading> tAA ] = 35 (max) tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 55 (min) tw(RASH) = 60 (min) td(R/W-E) = 20 (min) td(E-CASL) = 80–115 E RAS CAS <When writing> MA 0–MA 9 A16/D0– A23/D7 ] : Specifications of M5M44800CJ-7 The others are specifications of M37721. Address Data AC32(tPHL ) tWCS ] = 0 (min) t WCH ] = 15 (min) td(RA-RAS) = 5 (min) th(RAS-RA) = 18 (min) AC32(tPHL ) th(CAS-CA) = 60 (min)td(CA-CAS) = 10 (min) tDH ] = 15 (min) th(E-DLQ) = 18 (min) R/W W Row address Column address (Unit : ns) Fig. 16.1.21 Timing chart for example of M5M44800CJ (512K 5 8 bits) connection (external bus width = 8 bits)

7721 Group User’s Manual16–26

(4) Example of DRAM connection (external bus width = 8 bits) \` Fig. 16.1.22 Example of M5M417800CJ (2M 5 8 bits) connection (external bus width = 8 bits) 00000016 00008016 00047F16 001FC0 16 001FFF 16 E0000016 FFFFFF 16 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 M5M417800CJ-7 MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 MA 8 MA 9 RAS CAS R/W E A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 ALE A10 RAS CAS OE M37721 XIN XOUT W SFR area Internal RAM area DRAM area (M5M417800CJ) Memory map Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00102” ]1 : Make sure that the propagation delay time is within 80 ns. ]2 : Make sure that the propagation delay time is within 15 ns. SFR area Not used Not used

7721 Group User’s Manual 16–27

tASR = 0 (min) AC573 (M5M417800AJ) tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 92.5 (min) td(RAS-CAS) = 28 (min) tw(RASH) = 60 (min) td(E-RASL) = 30 (max) td(RA-RAS) = 5 (min) td(E-CA) = 60 (max) Input dataAddress tOEA ] = 20 (max) tRAC ] = 70 (max) tCLZ ] = 5 (min) tCAC ] = 20 (max) tOEZ ] = 0–15 tpzx(E-DLZ) = 20 (min) td(CA-CAS) = 5 (min) td(E-CASL) = 77.5 (max) Row address Column address E (OE) RAS CAS MA 0–MA 9 A16/D0– A23/D7 <When reading> tAA ] = 35 (max) td(AH-E) = 15 (min) tsu(DL-E) ≥ 30 tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 55 (min) tw(RASH) = 60 (min) td(R/W-E) = 20 (min) td(E-CASL) = 80–115 E RAS CAS <When writing> MA 0–MA 9 A16/D0– A23/D7 ] : Specifications of M5M417800CJ-7 The others are specifications of M37721. Address Data AC32(tPHL ) tWCS ] = 0 (min) t WCH ] = 10 (min) td(RA-RAS) = 5 (min) th(RAS-RA) = 18 (min) AC32(tPHL ) th(CAS-CA) = 60 (min)td(CA-CAS) = 10 (min) tDH ] = 15 (min) th(E-DLQ) = 18 (min) R/W W Row address Column address (Unit : ns) Fig. 16.1.23 Timing chart for example of M5M417800CJ (2M 5 8 bits) connection (external bus width = 8 bits)

7721 Group User’s Manual16–28

(5) Example of DRAM connection (external bus width = 8 bits) ´ Fig. 16.1.24 Example of M5M44400CJ (1M 5 4 bits) connection (external bus width = 8 bits) 00000016 00008016 00047F16 001FC0 16 001FFF 16 F0000016 FFFFFF 16 M5M44400CJ-7 MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 MA 8 MA 9 RAS CAS R/W E A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 M37721 DQ 1 DQ 2 DQ 3 DQ 4 RAS CAS W OE XIN XOUT W RAS CAS W E DQ 1 DQ 2 DQ 3 DQ 4 BYTE M5M44400CJ-7 SFR area Internal RAM area DRAM area (M5M44400CJ 5 2) Memory map Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00012” ] : Make sure that the propagation delay time is within 80 ns. SFR area Not used Not used

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Fig. 16.1.25 Timing chart for example of M5M44400CJ (1M 5 4 bits) connection (external bus width = 8 bits) E (OE) RAS CAS MA 0–MA 9 A16/D0– A23/D7 <When reading> tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 92.5 (min) td(RAS-CAS) = 28 (min) tw(RASH) = 60 (min) td(E-RASL) = 30 (max) td(RA-RAS) = 5 (min) td(E-CA) = 60 (max) Input dataAddress tOEA ] = 20 (max) tRAC ] = 70 (max) tCLZ ] = 5 (min) tCAC ] = 20 (max) tpzx(E-DLZ) = 20 (min) td(CA-CAS) = 5 (min) td(E-CASL) = 77.5 (max) Row address Column address tAA ] = 35 (max) tsu(DL-E) ≥ 30 tOEZ ] = 0–20 tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 55 (min) tw(RASH) = 60 (min) td(R/W-E) = 20 (min) td(E-CASL) = 80–115 <When writing> MA 0–MA 9 A16/D0– A23/D7 ] : Specifications of M5M44400CJ-7 The others are specifications of M37721. Address Data AC32(tPHL ) tWCS ] = 0 (min) t WCH ] = 15 (min) td(RA-RAS) = 5 (min) th(RAS-RA) = 18 (min) AC32(tPHL ) th(CAS-CA) = 60 (min)td(CA-CAS) = 10 (min) tDH ] = 15 (min) th(E-DLQ) = 18 (min) Row address Column address (Unit : ns) E RAS CAS R/W W

7721 Group User’s Manual16–30

(6) Example of DRAM connection (external bus width = 16 bits) À 00000016 00008016 00047F16 001FC0 16 001FFF 16 E0000016 FFFFFF 16 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 16 M5M418160CJ-7 MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 MA 8 MA 9 RAS A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 RAS M37721 AC32 BYTE XIN XOUT E R/W AC157 SELECT ST LCAS UCAS OE W SFR area Internal RAM area DRAM area (M5M418160CJ) Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00102” ] 1 : Make sure that the propagation delay time is within 20 ns. ] 2 : Make sure that the propagation delay time is within 7.5 ns. SFR area Not used Not used Memory map Fig. 16.1.26 Example of M5M418160CJ (1M 5 16 bits) connection (external bus width = 16 bits)

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Fig. 16.1.27 Timing chart for example of M5M418160CJ (1M 5 16 bits) connection (external bus width = 16 bits) tDH ] = 15 (min) + AC157(tPHL ) tCLZ ] = 5 (min) + AC157 (tPHL ) tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 92.5 (min) td(RAS-CAS) = 28 (min) tw(RASH) = 60 (min) td(E-RASL) = 30 (max) td(RA-RAS) = 5 (min) td(E-CA) = 60 (max) Input dataAddress tOEA ] = 20 (max) tRAC ] = 70 (max) tsu(DL/DH-E) ≥ 30 tOEZ ] = 0–15 tpzx(E-DLZ/DHZ) = 20 (min) td(CA-CAS) = 5 (min) td(E-CASL) = 77.5 (max) Row address E (OE) RAS CAS MA 0–MA 9 A16/D0–A23/D7, A8/D8–A15/D15 <When reading> tAA ] = 35 (max) tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 55 (min) tw(RASH) = 60 (min) td(R/W-E) = 20 (min) td(E-CASL) = 80–115 E RAS CAS Row Column addressMA 0–MA 9 Address Data AC32(tPHL ) tWCS ] = 0 (min) t WCH ] = 10 (min) td(RA-RAS) = 5 (min) th(RAS-RA) = 18 (min) AC32(tPHL ) th(CAS-CA) = 60 (min)td(CA-CAS) = 10 (min) th(E-DLQ/DHQ) = 18 (min) R/W W A16/D0–A23/D7, A8/D8–A15/D15 BLE/BHE td(BLE/BHE-E) = 20 (min) BLE/BHE td(BLE/BHE-E) = 20 (min) Column address ] : Specifications of M5M418160CJ-7 The others are specifications of M37721. (Unit : ns) <When writing> tCAC ] = 20 (max) + AC157 (tPHL ) Address

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(7) Example of DRAM connection (external bus width = 16 bits) \` 00000016 00008016 00047F16 001FC0 16 001FFF 16 F0000016 FFFFFF 16 F7FFFF 16 M5M44170CJ-7 MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 RAS CAS OE M37721 XIN XOUT E A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 ALE A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 ]2AC573 LE AC32 WL WH BYTE DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 16 LW UWBLE BHE R/W OE SFR area Internal RAM area DRAM area (M5M44170CJ) SFR area Not used Not used Memory map Not used Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00012” ]1 : Make sure that the propagation delay time is within 40 ns. ]2 : Make sure that the propagation delay time is within 15 ns. Fig. 16.1.28 Example of M5M44170CJ (256K 5 16 bits) connection (external bus width = 16 bits)

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Fig. 16.1.29 Timing chart for example of M5M44170CJ (256K 5 16 bits) connection (external bus width = 16 bits) BLE/BHE tASR = 0 (min) AC573 (M5M44170AJ) A8, A9 E (OE) RAS CAS MA 0–MA 7 A16/D0–A23/D7, A8/D8–A15/D15 <When reading> tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 92.5 (min) td(RAS-CAS) = 28 (min) tw(RASH) = 60 (min) td(E-RASL) = 30 (max) td(RA-RAS) = 5 (min) td(E-CA) = 60 (max) Input dataAddress tOEA ] = 20 (max) tRAC ] = 70 (max) tCLZ ] = 5 (min) tCAC ] = 20 (max) tpzx(E-DLZ/DHZ) = 20 (min) td(CA-CAS) = 5 (min) td(E-CASL) = 77.5 (max) Row address Column address tAA ] = 35 (max) tsu(DL/DH-E) ≥ 30 tOEZ ] = 0–20td(AH-E) = 15 (min) tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 55 (min) tw(RASH) = 60 (min) td(R/W-E) = 20 (min) td(E-CASL) = 80–115 <When writing> MA 0–MA 9 A16/D0–A23/D7, A8/D8–A15/D15 ] : Specification of M5M44170CJ-7 The others are specifications of M37721. Address Data AC32(tPHL ) 5 2 tWCS ] = 0 (min) t WCH ] = 15 (min) td(RA-RAS) = 5 (min) th(RAS-RA) = 18 (min) AC32(tPHL ) 5 2 th(CAS-CA) = 60 (min)td(CA-CAS) = 10 (min) tDH ] = 15 (min) th(E-DLQ/DHQ) = 18 (min) Row address Column address E RAS CAS R/W WL/WH td(BLE/BHE–E) = 20 (min) (Unit : ns)

7721 Group User’s Manual16–34

(8) Example of DRAM connection (external bus width = 16 bits) ´ 00000016 00008016 00047F16 001FC0 16 001FFF 16 E0000016 FFFFFF 16 MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 MA 8 MA 9 RAS CAS E M37721 M5M417800CJ-7 A10 RAS CAS OE W RAS CAS OE W A10 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15 XIN XOUT (M5M417800CJ 5 2) ] 1 : Make sure that the propagation delay time is within 40 ns. ] 2 : Make sure that the propagation delay time is within 15 ns. SFR area Not used Not used Memory map Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00102” Fig. 16.1.30 Example of M5M417800CJ (2M 5 8 bits) connection (external bus width = 16 bits)

7721 Group User’s Manual 16–35

Fig. 16.1.31 Timing chart for example of M5M417800CJ (2M 5 8 bits) connection (external bus width = 16 bits) W tASR = 0 (min) AC573 (M5M417800AJ) A10 E (OE) RAS CAS MA 0–MA 9 A16/D0–A23/D7, A8/D8–A15/D15 <When reading> tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 92.5 (min) td(RAS-CAS) = 28 (min) tw(RASH) = 60 (min) td(E-RASL) = 30 (max) td(RA-RAS) = 5 (min) td(E-CA) = 60 (max) Input dataAddress tOEA ] = 20 (max) tRAC ] = 70 (max) tCLZ ] = 5 (min) tCAC ] = 20 (max) tpzx(E-DLZ/DHZ) = 20 (min) td(CA-CAS) = 5 (min) td(E-CASL) = 77.5 (max) Row address Column address tAA ] = 35 (max) tsu(DL/DH-E) ≥ 30td(AH-E) = 15 (min) tOEZ ] = 0–15 tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 55 (min) tw(RASH) = 60 (min) td(R/W-E) = 20 (min) td(E-CASL) = 80–115 <When writing> MA 0–MA 9 A16/D0–A23/D7, A8/D8–A15/D15 ] : Specifications of M5M417800CJ-7 The others are specifications of M37721. Address Data AC32(tPHL ) tWCS ] = 0 (min) t WCH ] = 10 (min) td(RA-RAS) = 5 (min) th(RAS-RA) = 18 (min) AC32(tPHL ) th(CAS-CA) = 60 (min)td(CA-CAS) = 10 (min) tDH ] = 15 (min) th(E-DLQ/DHQ) = 18 (min) Row address Column address E RAS CAS R/W (Unit : ns)

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(9) Example of DRAM connection (external bus width = 16 bits) ˆ 00000016 00008016 00047F16 001FC0 16 001FFF 16 E0000016 FFFFFF 16 M5M44400CJ-7 MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 MA 8 MA 9 RAS CAS E R/W BLE A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 M37721 AC32 WL WH BHE XIN XOUT A A A A A A A A A 8/D A 9/D A A A A A A W DQ DQ DQ DQ W DQ DQ DQ DQ W DQ DQ DQ DQ SFR area Internal RAM area DRAM area (M5M4400CJ 5 4) ] : Make sure that the propagation delay time is within 40 ns. SFR area Not used Not used Memory map Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00102” Fig. 16.1.32 Example of M5M44400CJ (1M 5 4 bits) connection (external bus width = 16 bits)

7721 Group User’s Manual 16–37

Fig. 16.1.33 Timing chart for example of M5M44400CJ (1M 5 4 bits) connection (external bus width = 16 bits) E (OE) RAS CAS MA 0–MA 9 A16/D0–A23/D7, A8/D8–A15/D15 tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 92.5 (min) td(RAS-CAS) = 28 (min) tw(RASH) = 60 (min) td(E-RASL) = 30 (max) td(RA-RAS) = 5 (min) td(E-CA) = 60 (max) Input dataAddress tOEA ] = 20 (max) tRAC ] = 70 (max) tCLZ ] = 5 (min) tCAC ] = 20 (max) tpzx(E-DLZ/DHZ) = 20 (min) td(CA-CAS) = 5 (min) td(E-CASL) = 77.5 (max) Row address Column address tAA ] = 35 (max) tsu(DL/DH-E) ≥ 30 tOEZ ] = 0–20 <When reading> tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 55 (min) tw(RASH) = 60 (min) td(R/W-E) = 20 (min) td(E-CASL) = 80–115 <When writing> MA 0–MA 9 A16/D0–A23/D7, A8/D8–A15/D15 ] : Specifications of M5M44400CJ-7 The others are specifications of M37721. Address Data AC32(tPHL ) 5 2 tWCS ] = 0 (min) tWCH ] = 10 (min) td(RA-RAS) = 5 (min) th(RAS-RA) = 18 (min) AC32(tPHL ) 5 2 th(CAS-CA) = 60 (min)td(CA-CAS) = 10 (min) tDH ] = 15 (min) th(E-DLQ/DHQ) = 18 (min) Row address Column address E RAS CAS R/W WL/WH BLE/BHE td(BLE/BHE–E) = 20 (min) (Unit : ns)

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(10) Example of DRAM connection (external bus width = 16 bits) ˜ AC157 00000016 00008016 00047F16 001FC0 16 001FFF 16 F0000016 FFFFFF 16 F7FFFF 16 M5M44260CJ-7 MA 0 MA 1 MA 2 MA 3 MA 4 MA 5 MA 6 MA 7 MA 8 RAS CAS M37721 RAS AC32 SELECT ST LCAS UCAS OE W BLE BHE ST0 ST1 E R/W BYTE (M5M44260CJ) ] 1 : Make sure that the propagation delay time is within 20 ns. ] 2 : Make sure that the propagation delay time is within 7.5 ns. SFR area Not used Not used Memory map Circuit condition : DRAM area select bits (bits 3 to 0 at address 6416) = “00012” Not used A16/D0 A17/D1 A18/D2 A19/D3 A20/D4 A21/D5 A22/D6 A23/D7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 16 XIN XOUT Fig. 16.1.34 Example of M5M44260CJ (256K 5 16 bits) connection (external bus width = 16 bits)

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Fig. 16.1.35 Timing chart for example of M5M44260CJ (256K 5 16 bits) connection (external bus width = 16 bits) tDH ] = 15 (min) + AC157(tPHL ) tCLZ ] = 5 (min) + AC157 (tPHL ) tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 92.5 (min) td(RAS-CAS) = 28 (min) tw(RASH) = 60 (min) td(E-RASL) = 30 (max) td(RA-RAS) = 5 (min) td(E-CA) = 60 (max) Input dataAddress tOEA ] = 20 (max) tRAC ] = 70 (max) tsu(DL/DH-E) ≥ 30 tOEZ ] = 0–20 tpzx(E-DLZ/DHZ) = 20 (min) td(CA-CAS) = 5 (min) td(E-CASL) = 77.5 (max) Row address E (OE) RAS MA 0–MA 8 A16/D0–A23/D7, A8/D8–A15/D15 <When reading> tAA ] = 35 (max) tw(EL) = 135 (min) tw(RASL) = 120 (min) tw(CASL) = 55 (min) tw(RASH) = 60 (min) td(R/W-E) = 20 (min) td(E-CASL) = 80–115 E RAS CAS Row Column addressMA 0–MA 8 Address Data AC32(tPHL ) tWCS ] = 0 (min) t WCH ] = 15 (min) td(RA-RAS) = 5 (min) th(RAS-RA) = 18 (min) AC32(tPHL ) th(CAS-CA) = 60 (min)td(CA-CAS) = 10 (min) th(E-DLQ/DHQ) = 18 (min) R/W W A16/D0–A23/D7, A8/D8–A15/D15 BLE/BHE td(BLE/BHE-E) = 20 (min) BLE/BHE td(BLE/BHE-E) = 20 (min) Column address ] : Specifications of M5M44260CJ-7 The others are specification of M37721. (Unit : ns) <When writing> tCAC ] = 20 (max) + AC157 (tPHL ) CAS Address

7721 Group User’s Manual16–40

16.1.4 Example of I/O expansion

(1) Example of port expansion circuit using M66010FP Figure 16.1.36 shows an example of a port expansion circuit using the M66010FP. Make sure that the frequency of Serial I/O transfer clock must be 1.923 MHz or less. About Serial I/O control in this expansion example is described below. In this example, 8-bit data transmission/reception is performed 3 times by using UART0, so that 24- bit port expansion is realized. Setting of UART0 is described below: l Clock synchronous serial I/O mode: Transmission/Reception enable state l Internal clock is selected. Transfer clock frequency is 1.66 MHz. l LSB first The control procedure is described below: À Output “L” level from port P4 5. (Expanded I/O ports of the M66010FP enter a floating state by this signal. ) \` Output “H” level from port P45. ´ Output “L” level from port P44. ˆ Transmit/Receive 24-bit data by using UART0. ˜ Output “H” level from port P44. Figure 16.1.37 shows the serial transfer timing between the M37721 and the M66010FP.

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A0–A7 A8/D8–A15/D15 A16/D0–A23/D7 ALE E R/W BHE BLE M37721 DI DO CLK CS S Vcc GND BYTE Circuit conditions: •UART0 used in clock synchronous serial I/O mode

Internal clock selected
Frequency of transfer clock =f2 2 (3 + 1)= 1.5625 MHz Fig. 16.1.36 Example of port expansion circuit using M66010FP

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Fig. 16.1.37 Serial transfer timing between M37721 and M66010FP DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO20 DO21 DO22 DO23 DO24 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI20 DI21 DI22 DI23 DI24 DI1 DI2 DI24 S CS CLK DI DO Expanded I/O port DO24 DO2 DO1D1 D24 P45 P44 CLK 0 TXD 0 R XD 0 Expanded I/O port Expanded I/O port Expanded I/O ports are released from floating state. Data of expanded I/O ports is output to shift register 1. Serial data is input to shift register 2. Data of shift register 1 is output in serial. ] Output structure of expanded I/O ports is N-channel open-drain output. : M37721’s pin name The others are M66010FP’s pin’s names or operations. Data of shift register 2 is output to expanded I/O ports. to

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16.2.1 Example of Centronics interface configuration

The following is an example of Centronics interface configurated by using DMA0, Timers A2 and A3. (1) Specifications

Octal latch’s contents are transferred to the data buffer (RAM) by using DMA0. The trigger is the____ STB signal. (Refer to “Figure 16.2.1.”)____
“L” level width of the ACK signal is generated by using Timer A2; one-shot pulse mode; the trigger_________ is the rising edge of the DMAACK0 signal. (Refer to “Figure 16.2.2.”)____
Timer A3 generates the time from when the ACK signal rises until the BUSY signal falls; one-shot_________ pulse mode; the trigger is the rising edge of the DMAACK0 signal. (Refer to “Figure 16.2.2.”)
P43 is used for BUSY signal generation. When outputting “H” level, the next transfer can wait. In that case, the contents of the preceding transfer are hold in the octal latch.
When the data buffer is filled (in other words, DMA transfer is completed), a DMA interrupt occurs.

7721 Group User’s Manual16–44

Fig. 16.2.1 Example of Centronics interface configuration Data bus DMAREQ0 TA3 OUT (one-shot output) TA3 IN DMAACK0 TA2 IN P43 TA2 OUT (one-shot output) M37721 Octal latch AC574 OC T Q D S T Data D-F/F CS RD STB BUSY ACK XIN XOUT T2 : Timer A2’s set time T3 : Timer A3’s set time ____ Fig. 16.2.2 Relationship between ACK and BUSY

7721 Group User’s Manual 16–45

(2) Initial setting example for relevant register b7 b0 Port P4 register (Address A16) P43 output : H level TA3 OUT output : H level (D-F/F initialized) b7 b0 b7 b0 P43 : Output mode b7 b0 b7 b0 DMAREQ0 pin : Input mode b7 b0 Transfer source Wait Transfer destination Wait Single transfer mode 5 0000000 5 : It may be “0” or “1.” b7 b0 DMA0 mode register L (Address 1FCC16) Transfer unit : 8 bits 2-bus cycle transfer Cycle-steal transfer mode Transfer source address direction : Fixed Transfer destination address direction : Forward 0 1010001 TA2 IN pin : Input mode 100 Port P5 register (Address B16) Port P4 direction register (Address C16) Port P5 direction register (Address D16) TA3 IN pin : Input mode TA3 OUT pin : Output mode (D–F/F initialized) Port P9 direction register (Address 1516) DMA0 mode register H (Address 1FCD16) Fig. 16.2.3 Initial setting example for relevant register (1)

7721 Group User’s Manual16–46

Fig. 16.2.4 Initial setting example for relevant register (2) Period from falling edge of ACK signal until falling edge of BUSY signal (T3 in Figure 16.2.2) Octal latch’s address b23 b0b16 b15 b8 b7 Data buffer’s start address b23 b0b16 b15 b8 b7 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Data buffer size (unit : byte) b23 b0b16 b15 b8 b7 b7 b0 Timer A2 mode register (Address 5816) One-shot pulse mode Trigger : Rising edge of TA2IN pin’s input signal Count source 11001 1 b7 b0 11001 1 ACK signal’s “L” level time (T2 in Figure 16.2.2) b15 b0 b8 b7 b15 b0 b8 b7 Source address register 0 (Addresses 1FC216 to 1FC016) Destination address register 0 (Addresses 1FC616 to 1FC416) Timer A3 mode register (Address 5916) One-shot pulse mode Trigger : Rising edge of TA3 IN pin’s input signal Count source Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16)

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P43 output : L level b7 b0 DMA0 enabled b7 b0 Timer A2 count start Timer A3 count start b7 b0 DMA0 request flag is set to “0.” b7 b0 DMA0 control register (Address 1FCE16) DMA request source : External source (DMAREQ0) Edge sense selected DMAACK0 pin : Valid 0 11000 b7 b0 DMA0 interrupt control register (Address 6C16) Interrupt priority level : any of “0012” to “1112” Count start register (Address 4016) DMAC control register L (Address 6816) DMAC control register H (Address 6916) Port P4 register (Address A16) Fig. 16.2.5 Initial setting example for relevant register (3)

7721 Group User’s Manual16–48

16.2.2 Example of stepping motor control

The following is an example where the slow-up or slow-down control for the stepping motor is performed by using DMA1, DMA2, and RTP0. (1) Specifications

DMA1 transfers the stepping motor’s phase output data from the phase output data table to the
DMA2 transfers the step time for slow up or slow down from the timer A0 set value data table to the timer A0 register. (Refer to “Figure 16.2.6.”) After slow up or slow down is completed, a DMA2 interrupt occurs.
After slow up or slow down is completed, the motor operates with the definite rate. M37721 ROM RTP0 Timer Stepping motor Phase output data table DMAC1 DMAC2 Bus /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLinesM /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer A0 set value data table Motor driver Fig. 16.2.6 Example of stepping motor control

7721 Group User’s Manual 16–49

Table 16.2.1 Example of phase output data table 2-2 phase 0011 1001 1100 0110 0011 1001 1100 0110 1-2 phase 0011 0001 1001 1000 1100 0100 0110 0010 Fig. 16.2.7 Example of phase output 0 12 3 4 5 6 7Step Phase 2-2 phase RTP0 3 RTP0 2 RTP0 1 RTP0 0 RTP0 3 RTP0 2 RTP0 1 RTP0 0 1-2 phase

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(2) Initial setting example for relevant register b7 b0 DMA1 mode register L (Address 1FDC16) Transfer unit : 8 bits 2-bus cycle transfer Cycle-steal transfer mode Transfer source address direction : At regular turning ; “01 2” (Forward) At reverse turning ; “102” (Backward) Transfer destination address direction : Fixed 0 100 01 b7 b0 DMA1 mode register H (Address 1FDD16) Transfer source Wait No transfer destination Wait Repeat transfer mode 0011000 Source address register 1 (Addresses 1FD216 to 1FD016) Phase output data table’s start address b23 b0b16 b15 b8 b7 Phase output data table’s data number b23 b0b16 b15 b8 b7 Pulse output data register 0’s address b23 b0b16 b15 b8 b7 0016 0016 1A16 b7 b0 DMA1 control register (Address 1FDE16) DMA request source : Timer A0 DMAACK1 pin : Invalid 1 10000 b7 b0 DMA1 interrupt control register (Address 6D16) Interrupt disabled 000 Destination address register 1 (Addresses 1FD616 to 1FD416) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) 5 : It may be “0” or “1.” Fig. 16.2.8 Initial setting example for relevant register (1)

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DMA2 mode register L (Address 1FEC16) Transfer unit : 16 bits 2-bus cycle transfer Cycle-steal transfer mode Transfer source address direction : At slow up; “01 2” (Forward) At slow down; “102” (Backward) Transfer destination address direction : Fixed 0 000 01 b7 b0 DMA2 mode register H (Address 1FED16) Transfer source Wait No transfer destination Wait Single transfer mode 5 0001000 Source address register 2 (Addresses 1FE216 to 1FE016) Timer A0 set value data table’s start address b23 b0b16 b15 b8 b7 Timer A0 register’s address b23 b0b16 b15 b8 b7 0016 0016 4616 b23 b0b16 b15 b8 b7 b7 b0 DMA2 control register (Address 1FEE16) DMA request source : Timer A0 DMAACK2 pin : Invalid 1 10000 b7 b0 DMA2 interrupt control register (Address 6E16) Interrupt priority level : any of “0012” to “1112” Destination address register 2 (Addresses 1FE616 to 1FE416) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Data number of Timer A0 set value data table 5 : It may be “0” or “1.” Fig. 16.2.9 Initial setting example for relevant register (2)

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Fig. 16.2.10 Initial setting example for relevant register (3) DMA1 request bit DMA2 request bit b7 b0 Port P6 register (Address E16) RTP0 0/P60–RTP0 3/P63 initial output : H level 1111 b7 b0 1111 b7 b0 Count source 00000 b7 b0 RTP0 Pulse mode 0 001 Timer A0 register (Addresses 4716, 4616) First step time b15 b0 b8 b7 b7 b0 First phase output data b7 b0 Timer A0 count start DMA1 enabled DMA2 enabled b7 b0 b7 b0 are set to “0.” Port P6 direction register (Address 1016) RTP0 0/P60–RTP0 3/P63 pin : Output mode Pulse output data register 0 (Address 1A16)

5 TImer A0 mode register (Address 5616)

Real-time output control register (Address 6216) Count start register (Address 4016) DMAC control register L (Address 6816) DMAC control register H (Address 6916) 5 : It may be “0” or “1.”

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16.2.3 Example of dynamic lighting for LED

The following is an example of dynamic lighting for LED by using DMA3 and Timer B0. (1) Specifications

The eight 7-segment LEDs are lighted up; port P6 outputs the segment data; port P7 outputs the digit data. (Refer to “Figure 16.2.11.”)
The display data and the segment data are transferred from the data buffer to the port P6 and P7 registers by DMA3.
Digit switch interval is generated by Timer B0.
16 bytes of RAM are used as the data buffer. 1-digit display data consists of 2 bytes; the digit data is placed in the high-order byte; the segment data is placed in the low-order byte. (Refer to “Table 16.2.2.”) When the digit data and segment data are “0,” the LED is lighted up (ON): when they are “1,” the light goes out (OFF). Assuming that the segment pattern is generated by another processing. M37721 LED driver Data buffer P67 P60 P77 P70 7-segment LED 5 8 LED driver Data buffer Digit data 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 Segment pattern of the contents to be displayed in each digit Segment pattern Fig. 16.2.11 Example of dynamic lighting for LED Table 16.2.2 Data buffer Notes 1: This applies in the following:
when the digit data is “0,” the light goes out.
when the digit data is “1,” the LED is lighted up. 2: Assuming that the segment pattern is generated by another processing.

7721 Group User’s Manual16–54

DMA3 mode register L (Address 1FFC16) Transfer unit : 16 bits 2-bus cycle transfer Cycle-steal transfer mode Transfer source address direction : Forward Transfer destination address direction : Fixed DMA3 mode register H (Address 1FFD 16) No transfer source Wait No transfer destination Wait Repeat transfer mode Source address register 3 (Addresses 1FF2 16 to 1FF016) Data buffer’s start address Port P6, P7 register’s address Destination address register 3 (Addresses 1FF616 to 1FF416) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) Data number (unit : byte) DMA3 control register (Address 1FFE16) DMA request source : Timer B0 DMAACK3 pin : Invalid DMA3 interrupt control register (Address 6F16) Interrupt disabled 5 : It may be “0” or “1.” Fig. 16.2.12 Initial setting example for relevant register (1)

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DMA3 request bit : “0” Digit switch interval b15 b0 b8 b7 b7 b0 Port P6 register (Address E16) Output : L level (Lights go out.) 00000000 b7 b0 00000000 b7 b0 Output mode 11111111 b7 b0 11111111 b7 b0 Timer mode Count source b7 b0 Interrupt disabled 000 Port P7 register (Address F16) Output : L level (All digits OFF) Port P6 direction register (Address 1016) Port P7 direction register (Address 1116) Output mode Timer B0 register (Addresses 5116, 5016) 55 5 Timer B0 mode register (Address 5B16) Timer B0 interrupt control register (Address 7A16) Count start register (Address 4016) Timer B0 count started DMAC control register L (Address 6816) DMAC control register H (Address 6916) 5 : It may be “0” or “1.” Fig. 16.2.13 Initial setting example for relevant register (2)

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16.3 Comparison of sample program execution rate

Sample program execution rates are compared in this paragraph. The execution time ratio depends on the program or the usage conditions.

16.3.1 Differences depending on data bus width and software Wait

Internal areas are always accessed with data bus of which width is 16 bits and no software Wait. In the external areas, the external data bus width and software Wait are selectable. Table 16.3.1 lists the sample program (Refer to “Figure 16.3.1.”) execution time ratio depending on these selection and usable memory areas. Table 16.3.1 Sample program execution time ratio (external data bus width and software Wait) Sample program execution time ratio Sample A 1.00 1.17 1.19 1.67 1.00 1.25 1.19 1.78 0.92 Sample B 1.00 1.10 1.08 1.46 1.00 1.17 1.13 1.65 0.90 External data bus width (unit : bit) Memory area ROM External Internal RAM Internal External Software Wait None Inserted None Inserted None Inserted None Inserted Calculated value ] Calculated value ] : The value is calculated from the shortest execution cycle number of each instruction described in “7700 Family Software Manual.”

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SEP M,X LDA.B A,#0 STA A,DEST+64 STA A,DEST+65 STA A,DEST+66 LDX.B #63 LDA A,SOUR,X TAY AND.B A,#00000011B STA A,DEST,X TYA AND.B A,#00001100B ORA A,DEST+1,X STA A,DEST+1,X TYA AND.B A,#00110000B ORA A,DEST+2,X STA A,DEST+2,X TYA AND.B A,#11000000B ORA A,DEST+3,X STA A,DEST+3,X DEX BPL ITALIC ITALIC: SEP X CLM .DATA 16 .INDEX 8 LDY #69 LDX #69 ASL SOUR,X SEM .DATA 8 ROL SOUR+2,X ROL B CLM .DATA 16 ROR A DEX DEX DEX BNE LOOP1 STA A,DEST,Y SEM .DATA 8 STA B,DEST+2,Y CLM .DATA 16 DEY DEY DEY BNE LOOP0 LOOP0: LOOP1: Sample A Sample B ] SOUR, DEST : Work area (Direct page area : Access this area by using the following modes.)

Direct addressing mode
Direct Indexed X addressing mode
Absolute Indexed Y addressing mode Fig. 16.3.1 Sample program list

7721 Group User’s Manual16–58

16.3.2 Comparison between software Wait (f(XIN) = 20 MHz) and software Wait + Ready (f(XIN) = 25 MHz)

Figure 16.3.3 shows the execution time ratio when sample programs in Figure 16.3.1 are executed on the The execution time ratio depends on the program or the usage conditions. Table 16.3.2 Comparison conditions Fig. 16.3.2 Memory assignment at execution rate comparison External SRAM SFR area Condition \ Ready valid area Insert Wait which is equivalent to 2 cycles of at access (Software Wait included) M37721 memory map Internal SRAM Program area External EPROM Area where software Wait is valid Specify either area as work area Item Processor mode f(XIN) External data bus width Software Wait Ready Program area Work area Condition \ Microprocessor mode Valid only for external EPROM area External EPROM Internal or External SRAM Condition À Microprocessor mode

20 MHz

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Figure 16.3.3 shows that there is almost no difference between conditions À and \ about the execution Considering this, the case where software Wait is inserted with f(XIN) = 20 MHz (condition À ) is superior in the cost performance. 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 Work area = Internal RAM 1.00 1.04 1.00 1.01 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 Sample B excution time ratio 1.00 1.05 1.00 1.03 : Condition \ : Condition À Work area = External RAM Work area = Internal RAM Work area = External RAM Sample A excution time ratio Fig. 16.3.3 Execution time ratio

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Appendix 1.Memory assignment of

7721 Group

Appendix 2.Memory assignment in SFR area Appendix 3. Control registers Appendix 4. Package outline Appendix 5.Examples of handling unused pins Appendix 6. Machine instructions Appendix 7.Hexadecimal instruction code table Appendix 8. Countermeasure against noise Appendix 9. 7721 Group Q & A Appendix 10. Differences between 7721 Group and 7720 Group Appendix 11. Electrical characteristics Appendix 12. Standard characteristics

Appendix 1. Memory assignment of 7721 Group

7721 Group User’s Manual17–2

Appendix 1. Memory assignment of 7721 Group Microprocessor mode Fig. 1 Memory assignment (microprocessor mode) SFR area External area Internal RAM area (512 bytes) (Note 2) External area (Note 1) 00000216 SFR area External area 00000916 00000016 00008016 001FC0 16 00FFFF 16 00047F16 SFR area External area Bank 116 Bank FF16 Bank 016 01000016 01FFFF 16 FF000016 FFFFFF 16 M37721S2BFP 00007F16 00027F16 Internal RAM area (512 bytes) (512 bytes) 001FFF 16 SFR area M37721S1BFP SFR area Case of internal RAM area select bit = “0” Case of internal RAM area select bit = “1” Notes 1: Interrupt vector table is assigned to addresses FFCE 16 to FFFF16. Make sure to set a ROM to this area. 2: For the M37721S1BFP, fix the internal RAM area select bit to “0.” (Note 1) External area

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Appendix 2. Memory assignment in SFR area Appendix 2. Memory assignment in SFR area 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. : Always “0” at reading. 0 : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” 1016 1116 1216 1316 Port P8 direction register1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 016 116 216 316 416 516 616 716 816 916 B16 C 16 D 16 E16 F16 A16 Address Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register A-D sweep pin select register Register name Access characteristics State immediately after reset RW RW RW RW RW RW RW RW RW RW 0016 0016 0 0 000 ? b7 b0 b7 b0 : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. RW RO WO RW ? 0016 ??? ? : Always “1” at reading. 1 RW RW RW RW RW WO WO Port P9 register Port P9 direction register Port P10 register Port P10 direction register Pulse output data register 0 Pulse output data register 1 000 00000000 Access characteristics State immediately after reset 0016 0016

Appendix 2. Memory assignment in SFR area

7721 Group User’s Manual17–4

0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. : Always “0” at reading. 0 : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. RW RO WO : Always “1” at reading. 1 Access characteristics State immediately after a reset UART0 transmit/receive control register 0 UART0 transmit/receive mode register UART0 baud rate register UART0 transmit buffer register UART1 receive buffer register Register name UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 2816 2916 2B16 2C 16 2D 16 2E16 2F16 2A16 2016 2116 2216 2316 2416 2516 2616 2716 3F16 Address Access characteristics RW WO WO RO RO b7 b0 WO RWRO RO RORW RW RO RO RW WO WO WO RW RORW RW State immediately after reset 1 000 0016 0 000 00 0 ? b7 b0 0016 00000010 0000 0 0 0 1 000 0000 0 0 1 0 A-D register 5 A-D register 1 A-D register 3 A-D register 2 A-D register 4 A-D register 0 A-D register 6 A-D register 7 RO RO RO RO RO RO RO RO RO RO ??? ? ???

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Appendix 2. Memory assignment in SFR area RW RW RW Timer B2 register 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 4B16 4C 16 4D 16 4E16 4F16 4A16 Address Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Processor mode register 0 One-shot start register Timer A0 register Up-down register Timer A1 register Register name Count start register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Access characteristics WO (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) b7 b0 RW (Note 2) RW RW RW RW RW RW WO State immediately after reset 0016 0016 0016 0016 b7 b0 WO RW (Note 1) (Note 1) (Note 1) RW Timer A0 mode register Timer A4 mode register (Note 0 00 0 0 0 0 0 0 0 0 0 0 00 0 000 0 0 0 0 0 0 0RWRW Notes 1: The access characteristics at addresses 4A 16 to 4F16 vary according to Timer A’s operating mode. (Refer to “CHAPTER 8. TIMER A.”) 2: The access characteristics at addresses 5016 to 5316 vary according to Timer B’s operating mode. (Refer to “CHAPTER 9. TIMER B.”) 3: The access characteristics for bit 5 at addresses 5B16 and 5C16 vary according to Timer B’s operating mode. Bit 5 at address 5D16 is invalid. (Refer to “CHAPTER 9. TIMER B.”) 4: Bit 1 at address 5F16 becomes “0” immediately after reset. For the M37721S1BFP, fix this bit to “0.” RW (Note RW(Note 00 0 0 00?? 0 0 0 000?? ?Processor mode register 1 RW RW RW RW RW RW RW 00 0 000 0 0 00 0 0000 0 ?(Note 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. : Always “0” at reading. 0 : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. RW RO WO : Always “1” at reading. 1 Access characteristics State immediately after reset

Appendix 2. Memory assignment in SFR area

7721 Group User’s Manual17–6

UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address A-D conversion interrupt control register UART0 transmit interrupt control register UART1 transmit interrupt control register INT2 interrupt control register Watchdog timer frequency select register Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW b7 b0 RW State immediately after reset ?(Note 6) b7 b0 UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register 0 00 0 By writing dummy data to address 6016, the value “FFF16” is set to the watchdog timer. The dummy data is not retained anywhere. The value “FFF16” is set to the watchdog timer. (Refer to “CHAPTER 15. WATCHDOG TIMER .”) It is possible to read the bit state at reading. When writing “0” to this bit, this bit becomes “0.” But when writing “1” to this bit, this bit does not change. RW Notes 5: (Note 5) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 000 Real-time output control register Refresh timer DMAC control register L DMAC control register H DMA0 interrupt control register DMA1 interrupt control register DMA2 interrupt control register DMA3 interrupt control register RW 00000000 RWRWDRAM control register WO RW(Note 7) RW WO RW RW RW RW 00000000 000000 00000000 0 00 0 0 00 0? 0 00 0? 000 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. : Always “0” at reading. 0 : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. RW RO WO : Always “1” at reading. 1 Access characteristics State immediately after reset

7721 Group User’s Manual 17–7

Appendix 2. Memory assignment in SFR area 1FC0 16 1FC1 16 1FC2 16 1FC3 16 1FC4 16 1FC5 16 1FC6 16 1FC7 16 1FC8 16 1FC9 16 1FD0 16 1FD1 16 1FD2 16 1FD3 16 1FD4 16 1FD5 16 1FD6 16 1FD7 16 1FD8 16 1FD9 16 1FDA 16 1FDB 16 1FDC 16 1FDD 16 1FDE 16 1FDF 16 1FCB 16 1FCC 16 1FCD 16 1FCE 16 1FCF 16 1FCA 16 Address Register name Source address register 0 Access characteristics b7 b0 State immediately after reset b7 b0 RW 0 00 0 0 00 0 0 00 0 RW RW 0 00 0 0 00 0 000 Destination address register 0 Transfer counter register 0 DMA0 mode register L DMA0 mode register H DMA0 control register Source address register 1 Destination address register 1 Transfer counter register 1 DMA1 mode register L DMA1 mode register H DMA1 control register RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 00 0 0 0 000 0 00 0 0 00 0 0 0?? 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. : Always “0” at reading. 0 : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. RW RO WO : Always “1” at reading. 1 Access characteristics State immediately after reset

Appendix 2. Memory assignment in SFR area

7721 Group User’s Manual17–8

State immediately after reset b7 b0 RW 0 00 0 0 00 0 0 00 0 RW RW 0 00 0 0 00 0 000 Destination address register 2 Transfer counter register 2 DMA2 mode register L DMA2 mode register H DMA2 control register Source address register 3 Destination address register 3 Transfer counter register 3 DMA3 mode register L DMA3 mode register H DMA3 control register RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 00 0 0 0 000 0 00 0 0 00 0 0 0?? 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. : Always “0” at reading. 0 : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. RW RO WO : Always “1” at reading. 1 Access characteristics State immediately after reset

Appendix 3. Control registers

7721 Group User’s Manual 17–9

Appendix 3. Control registers The control registers allocated in the SFR area are shown on the following pages. Below is the structure diagram for all registers. XXX register (Address XX16) b1 b0b2b3b4b5b6b7 ]2 ]3 1 : ... 1 : ... The value is “0” at reading. 0 : ... 1 : ... Fix this bit to “0.” 7 to 5Nothing is assigned. RW WO RO RW RW Bit Bit name This bit is invalid in ... mode. Functions At reset RW ... flag Undefined Undefined Blank : Set to “0” or “1” according to the usage. 0 : Set to “0” at writing. 1 : Set to “1” at writing. 5 : Invalid depending on the mode or state. It may be “0” or “1.” : Nothing is assigned. 0 : “0” immediately after reset. 1 : “1” immediately after reset. Undefined : Undefined immediately after reset. RW : It is possible to read the bit state at reading. The written value becomes valid. RO Accordingly, the written value may be “0” or “1.” WO : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when [“0” is at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at reading. (See ]4 above.) : It is impossible to read the bit state. The value is undefined at reading. However, when [“0” is at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at reading. (See ]4 above.) The written value becomes invalid. Accordingly, the written value may be “0” or “1.” : It is possible to read the bit state at reading. The written value becomes invalid.

Appendix 3. Control registers

7721 Group User’s Manual17–10

Port Pi0’s pin Port Pi2’s pin Port Pi3’s pin Port Pi4’s pin Port Pi6’s pin Data is input from or output to a pin by reading from or writing to the corresponding bit. Port Pi 5’s pin Port Pi register (i = 4 to 10) (Addresses A16, B16, E16, F16, 1216, 1316, 1616) b1 b0b2b3b4b5b6b7 Port Pi1’s pin Port Pi7’s pin At reset RW Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 : “L” level 1 : “H” level RW RW RW RW RW RW RW RW Note: For bits 0 to 2 of the port P4 register, nothing is assigned and these bits are fixed to “0” at reading. Port Pi direction register Bit Bit name Functions Port Pi 0 direction bit Port Pi2 direction bit Port Pi3 direction bit Port Pi4 direction bit Port Pi6 direction bit 0 : Input mode (The port functions as an input port) 1 : Output mode (The port functions as an output port) Port Pi5 direction bit Port Pi direction register (i = 4 to 10) (Addresses C16, D16, 1016, 1116, 1416, 1516, 1816) b1 b0b2b3b4b5b6b7 Port Pi1 direction bit Port Pi7 direction bit At reset RW RW RW RW RW RW RW RW RW Note: For bits 0 to 2 of the port P4 direction register, nothing is assigned and these bits are fixed to “0” at reading.

Appendix 3. Control registers

7721 Group User’s Manual 17–11

Pulse output data register 0 Bit Bit name Functions 7 to 4 RTP0 0 pulse output data bit Pulse output data register 0 (Address 1A16) b1 b0b2b3b4b5b6b7 At reset RW Undefined Undefined Undefined Undefined Undefined 0 : “L” level output 1 : “H” level output WO Note: Use the LDM or STA instruction for writing to this register RTP0 1 pulse output data bit WO WO WO RTP0 2 pulse output data bit (Valid in pulse mode 0) RTP0 3 pulse output data bit (Valid in pulse mode 0) Nothing is assigned. Pulse output data register 1 Bit Bit name Functions 0, 1 Nothing is assigned. Pulse output data register 1 (Address 1C16) b1 b0b2b3b4b5b6b7 At reset RW Undefined Undefined Undefined Undefined Undefined 0 : “L” level output 1 : “H” level output WO Note: Use the LDM or STA instruction for writing to this register. WO WO WO RTP0 3 pulse output data bit (Valid in pulse mode 1) RTP0 2 pulse output data bit (Valid in pulse mode 1) RTP1 0 pulse output data bit RTP1 1 pulse output data bit RTP1 2 pulse output data bit RTP1 3 pulse output data bit Undefined Undefined WO WO

Appendix 3. Control registers

7721 Group User’s Manual17–12

A-D control register (Address 1E16) Bit A-D conversion frequency ( AD ) select bit A-D conversion start bit Trigger select bit A-D operation mode select bit Bit name At reset Undefined RWFunctions 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected (Note 2) b2 b1 b0 0 : Internal trigger 1 : External trigger 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 : Stop A-D conversion 1 : Start A-D conversion b4 b3 Notes 1: These bits are invalid in the single sweep and repeat sweep mode. (They may be either “0” or “1.”) 2: When selecting an external trigger, the AN 7 pin cannot be used as an analog input pin. 3: Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts. Analog input select bits (Valid in one-shot and repeat modes) (Note 1) Undefined Undefined RW RW RW RW RW RW RW RW 00 : f2 divided by 4 1 : f2 divided by 2 A-D sweep pin select register b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select register (Address 1F16) Bit Bit name At reset Undefined RWFunctions Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”) 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit of the A-D sweep pin select register must be performed while the A-D converter halts. 7 to 2 RW RW 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) (Note 2) A-D sweep pin select bits (Valid in single sweep and repeat sweep modes) (Note 1) b1 b0 Nothing is assigned. – A-D register i b7 b0 A-D register i (i = 0 to 7) (Addresses 2016, 2216, 2416, 2616, 2816, 2A16, 2C16, 2E16) Bit 7 to 0 At reset Undefined RWFunctions ROReads an A-D conversion result.

Appendix 3. Control registers

7721 Group User’s Manual 17–13

UARTi transmit/receive mode register UARTi baud rate register b7 b6 b5 b4 b3 b2 b1 b0 Bit Bit name At reset RWFunctions b2 b1 b0 RW RW RW RW RW RW RW RW Serial I/O mode select bits 0 0 0 : Serial I/O disabled (P8 functions as a programmable I/O port.) 0 0 1 : Clock synchronous serial I/O mode 0 1 0 : Do not select. 0 1 1 : Do not select. 1 0 0 : UART mode (Transfer data length = 7 bits) 1 0 1 : UART mode (Transfer data length = 8 bits) 1 1 0 : UART mode (Transfer data length = 9 bits) 1 1 1 : Do not select. Sleep select bit (Valid in UART mode) (Note) Parity enable bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit is “1”) (Note) Stop bit length select bit (Valid in UART mode) (Note) Internal/External clock select bit UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode terminated (Invalid) 1 : Sleep mode selected 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits b7 b0 UART0 baud rate register (Address 3116) UART1 baud rate register (Address 3916) FunctionsBit At reset RW 7 to 0 Can be set to “0016” to “FF16.” Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Undefined WO Note: Writing to this register must be performed while the transmission/reception halts. Use the LDM or STA instruction for writing to this register.

Appendix 3. Control registers

7721 Group User’s Manual17–14

UARTi transmit buffer register UARTi transmit/receive control register 0 b7 b0 Bit 8 to 0 At reset Undefined RWFunctions WO b7 b0 (b15) (b8) 15 to 9 –Undefined UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) Nothing is assigned. Transmit data is set. Note: Use the LDM or STA instruction for writing to this register. CTS/RTS select bit Bit BRG count source select bits Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b1 b0 0 : CTS function selected 1 : RTS function selected Transmit register empty flag0 : Data present in transmit register (During transmission) 1 : No data present in transmit register (Transmission completed) RW RW RO3 RW 7 to 4 Nothing is assigned. Undefined –

Appendix 3. Control registers

7721 Group User’s Manual 17–15

UARTi transmit/receive control register 1 Bit Bit name At reset (Valid in UART mode) 00 : No framing error 1 : Framing error detected RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Notes 1: Bit 4 is cleared to “0” when the receive enable bit is cleared to “0” or when the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) are cleared to “0002.” Bits 5 and 6 are cleared to “0” when one of the following is performed:

Clearing the receive enable bit to “0”
Reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16) out
Clearing the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to “0002” Bit 7 is cleared to “0” when all of bits 4 to 6 become “0.” 2: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.

1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No overrun error 1 : Overrun error detected (Valid in UART mode) 00 : No parity error 1 : Parity error detected (Valid in UART mode) 0 : No error 1 : Error detected (Notes 1, 2) (Notes 1, 2) (Notes 1, 2) (Note 1) RW RO RW RO RO RO RO RO UARTi receive buffer register b7 b0 Bit 8 to 0 At reset Undefined RWFunctions RO b7 b0 (b15) (b8) 15 to 9 – UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) Nothing is assigned. The value is “0” at reading. Receive data is read out from here.

Appendix 3. Control registers

7721 Group User’s Manual17–16

Count start register (Address 4016) 0 : Stop counting 1 : Start counting RW RW RW RW RW RW RW RW One-shot start register Bit 7 to 5Nothing is assigned. Timer A4 one-shot start bit Timer A3 one-shot start bit Timer A2 one-shot start bit Bit name At reset Undefined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register (Address 4216) 1 : Start outputting one-shot pulse (valid when internal trigger is selected.) The value is “0” at reading. WO WO WO WO WO Fix these bits to “0.” The value is “0” at reading.

Appendix 3. Control registers

7721 Group User’s Manual 17–17

Up-down register (Address 4416) Timer A4 up-down bit Timer A3 up-down bit Timer A2 up-down bit Fix these bits to “0.” Timer A2 two-phase pulse signal processing select bit (Note) Timer A3 two-phase pulse signal processing select bit (Note) Timer A4 two-phase pulse signal processing select bit (Note) 0 : Countdown 1 : Countup This function is valid when the contents of the up-down register is selected as the up- down switching factor. 0 : Two-phase pulse signal processing function disabled 1 : Two-phase pulse signal processing function enabled When not using the two-phase pulse signal processing function, set the bit to “0.” The value is “0” at reading. Note: Use the LDM or STA instruction for writing to bits 5 to 7. RW RW RW RW RW WO WO WO

Appendix 3. Control registers

7721 Group User’s Manual17–18

Appendix 3. Control registers

7721 Group User’s Manual 17–19

(b15) (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 These bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Undefined RW Gate function select bits Pulse output function select bit Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) 0 0 : Timer mode 0 : No pulse output (TAjOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAjOUT pin functions as a pulse output pin.) 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b4 b3 0 0 : No gate function 0 1 : (TAjIN pin functions as a prog- rammable I/O port.) 1 0 : Counter counts only while TAjIN pin’s input signal is at “L” level. 1 1 : Counter counts only while TAjIN pin’s input signal is at “H” level. Bit At reset RW 0 RW 0 RW 0 RW 3 0 RW 0 RW 5 0 RW 0 RW 0 RW Fix this bit to “0” in timer mode. Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Timer A0 mode register (Address 5616) Timer A1 mode register (Address 5716) Fix these bits to “0.” 0 RW RW RW RW RW RW Note: Read from or write to this register in a unit of 16 bits. 00 0000 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits6 0 RW 0 RW

Appendix 3. Control registers

7721 Group User’s Manual17–20

Up-down switching factor select bit Count polarity select bit Bit name These bits are invalid in event counter mode. Fix this bit to “0” in event counter mode. Functions 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 : Contents of up-down register 1 : Input signal to TAj OUT pin At reset RW Pulse output function select bit Operating mode select bits 0 : No pulse output (TAjOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAjOUT pin functions as a pulse output pin.) 0 1 : Event counter mode b1 b0 RW RW RW RW RW RW RW RW Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) b7 b0 b7 b0 (b15) (b8) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) RW 15 to 0 Bit Functions At reset RWThese bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (FFFF 16 – n + 1) during countup. When reading, the register indicates the counter value. Undefined Note: Read from or write to this register in a unit of 16 bits.

Appendix 3. Control registers

7721 Group User’s Manual 17–21

(b15) (b8) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) RW 15 to 0 These bits can be set to “000116” to “FFFF16.” Assuming that the set value = n, the “H” level width of the one-shot pulse output from the TAj OUT pin is expressed as follows : Undefined fi: Frequency of count source (f2 , f16, f64, or f512) WO Trigger select bits Fix this bit to “1” in one-shot pulse mode. Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) 1 0 : One-shot pulse mode 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b4 b3 Fix this bit to “0” in one-shot pulse mode. 10 1 0 0 : Writing “1” to one-shot start register 0 1 : (TAjIN pin functions as a prog- rammable I/O port.) 1 0 : Falling edge of TAjIN pin’s input signal 1 1 : Rising edge of TAjIN pin’s input signal Bit At reset RW RW RW RW RW RW RW RW RW Operating mode select bits n fi. Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. Bit Functions At reset

Appendix 3. Control registers

7721 Group User’s Manual17–22

Pulse width modulation (PWM) mode b7 b0 b7 b0 Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0These bits can be set to “000016” to “FFFE16.” Assuming that the set value = n, the “H” level width of the PWM pulse output from the TAjOUT pin is expressed as follows: (PWM pulse period = ) Undefined <When operating as a 16-bit pulse width modulator> (b15) (b8) WO n fi fi: Frequency of count source (f2, f16, f64, or f512) <When operating as an 8-bit pulse width modulator> (b15) b7 b0 b7 b0 (b8) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 7 to 0 15 to 8 Undefined Undefined These bits can be set to “0016” to “FF16.” Assuming that the set value = m, PWM pulse’s period output from the TAjOUT pin is expressed as follows:(m + 1)(28 – 1) fi WO These bits can be set to “0016” to “FE16.” Assuming that the set value = n, the “H” level width of the PWM pulse output from the TAj OUT pin is expressed as follows: n(m + 1) fi WO fi: Frequency of count source (f2, f16, f64, or f512) b7 b6 b5 b4 b3 b2 b1 b0 Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16) 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits 11 1 At reset RW Trigger select bits Fix this bit to “1” in PWM mode. Operating mode select bits Functions 1 1 : PWM mode b1 b0 b4 b3 16/8-bit PWM mode select bit 0 0 :Writing “1” to count start register 0 1 : (TAjIN pin functions as a pro- grammable I/O port.) 1 0 : Falling edge of TAjIN pin’s input signal 1 1 : Rising edge of TAjIN pin’s input signal 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator RW RW RW RW RW RW RW RW Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. Note: Use the LDM or STA instruction for writing to this register. Read from or write to this register in a unit of 16 bits. n16 – 1 fi Bit Bit name

Appendix 3. Control registers

7721 Group User’s Manual 17–23

(b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) FunctionsBit At reset RW 15 to 0 These bits have different functions according to the operating mode. Undefined RW (Note 1) Notes 1: The access characteristics for the timer B0 register and timer B1 register differ according to Timer B’s operating mode. 2: Read from or write to this register in a unit of 16 bits. Timer Bi mode register Nothing is assigned. These bits have different functions according to the operating mode. Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Do not select. b1 b0 Bit At reset RW 0 RW RW RW Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. RW0 –Undefined4 RO (Note) Undefined RW0 RW0 These bits have different functions according to the operating mode.

Appendix 3. Control registers

7721 Group User’s Manual17–24

This bit is invalid in timer mode; its value is undefined at reading. Nothing is assigned. Bit name Count source select bits Functions At reset RW These bits are invalid in timer mode. Operating mode select bits 0 0 : Timer mode b1 b0 0 RW RW RW RW Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)5 –Undefined4 Undefined5 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6 RW0 RW0 b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) RW 15 to 0 Bit Functions At reset These bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Undefined RW RO Note: Read from or write to this register in a unit of 16 bits.

Appendix 3. Control registers

7721 Group User’s Manual 17–25

(b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) RW 15 to 0 Bit Functions At reset RWThese bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Undefined Note: Read from or write to this register in a unit of 16 bits. 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Counts at both falling and rising edges of external signal 1 1 : Do not select. b7 b6 b5 b4 b3 b2 b1 b0 Bit Count polarity select bits Bit name These bits are invalid in event counter mode. This bit is invalid in event counter mode; its value is undefined at reading. Functions At reset RW Operating mode select bits 0 1 : Event counter mode b1 b0 RW RW RW RW RW RW Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) b3 b2 Nothing is assigned. Undefined Undefined RO

Appendix 3. Control registers

7721 Group User’s Manual17–26

Pulse period/pulse width measurement mode Measurement mode select bits Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) 1 0 : Pulse period/Pulse width measurement mode 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b3 b2 Nothing is assigned. 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : Do not select. Bit At reset Undefined RW RW RW RW RW RW RW b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) RW 15 to 0 The measurement result of pulse period or pulse width is read out. Undefined RO Timer Bj overflow flag (Note) 0 : No overflow 1 : Overflowed Undefined RO Note: The timer Bj overflow flag is cleared to “0” at the next count timing of the count source when a value is written to the timer Bj mode register with the count start bit = “1.” Note: Read from this register in a unit of 16 bits. FunctionsBit At reset

Appendix 3. Control registers

7721 Group User’s Manual 17–27

Bit Bit name Functions At reset RW Fix this bit to “0.” Software reset bit Interrupt priority detection time select bits Stack bank select bit The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. 0 : Bank 016 1 : Bank FF16 b5 b4 Processor mode register 0 (Address 5E16) b1 b0b2b3b4b5b6b7 RW WO 0 RW 0 RW Fix this bit to “0.” RW RW Nothing is assigned. The value is “1” at reading. 2 0Wait bit RW0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. Processor mode register 1 b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (Address 5F16) Bit 7 to 2 Bit name At reset RWFunctions Notes 1: For the M37721S1BFP, fix bit 1 to “0.” 2: For the M37721S2BFP, set bit 1 before setting the stack pointer. Nothing is assigned. –Undefined Internal RAM area select bit (Notes 1, 2) 0 : 512 bytes (addresses 8016 to 27F16) 1 : 1024 bytes (addresses 8016 to 47F16) Nothing is assigned. RW0 –Undefined

Appendix 3. Control registers

7721 Group User’s Manual17–28

Watchdog timer register (Address 6016) Bit Initializes Watchdog timer. When dummy data is written to this register, Watchdog timer’s value is initialized to “FFF 16.” (Dummy data: 0016 to FF16) At reset Undefined RWFunctions 7 to 0 – Watchdog timer frequency select register 0 : f512 1 : f32 At reset Undefined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit Nothing is assigned. Watchdog timer frequency select bit Bit name 7 to 1 RW

Appendix 3. Control registers

7721 Group User’s Manual 17–29

Real-time output control register b7 b6 b5 b4 b3 b2 b1 b0 Bit Nothing is assigned. The value is “0” at reading. Bit name Functions At reset RW Pulse output mode select bit Waveform output select bits See the following Table. 00 RW RW 7 to 3 RW Real-time output control register (Address 6216) –Undefined 0 : Pulse mode 0 1 : Pulse mode 1 Note: When using the P60–P67 pins as the pulse output pins for real-time output, set the corresponding bits of the port P6 direction register (address 1016) to “1.” b1 b0 When pulse mode 0 is selected 7/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port Port RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port RTP RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port Port When pulse mode 1 is selected 7/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Port RTP P67/RTP13 P66/RTP12 P65/RTP11 P64/RTP10 P63/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 RTP RTP Port : This functions as a programmable I/O port. RTP : This functions as a pulse output pin.

Appendix 3. Control registers

7721 Group User’s Manual17–30

0 0 0 0 : No DRAM area 0 0 0 1 : F0000016–FFFFFF 16 (1 Mbyte) 0 0 1 0 : E0000016–FFFFFF 16 (2 Mbytes) 0 0 1 1 : D00000 16–FFFFFF 16 (3 Mbytes) 0 1 0 0 : C00000 16–FFFFFF 16 (4 Mbytes) 0 1 0 1 : B0000016–FFFFFF 16 (5 Mbytes) 0 1 1 0 : A0000016–FFFFFF 16 (6 Mbytes) 0 1 1 1 : 90000016–FFFFFF 16 (7 Mbytes) 1 0 0 0 : 80000016–FFFFFF 16 (8 Mbytes) 1 0 0 1 : 70000016–FFFFFF 16 (9 Mbytes) 1 0 1 0 : 60000016–FFFFFF 16 (10 Mbytes) 1 0 1 1 : 50000016–FFFFFF 16 (11 Mbytes) 1 1 0 0 : 40000016–FFFFFF 16 (12 Mbytes) 1 1 0 1 : 30000016–FFFFFF 16 (13 Mbytes) 1 1 1 0 : 20000016–FFFFFF 16 (14 Mbytes) 1 1 1 1 : 10000016–FFFFFF 16 (15 Mbytes) Bit Bit name Functions At reset RW 6 to 4 DRAM area select bits DRAM validity bit (Note) 00 : Invalid (P104–P107 pins function as programmable input ports. A0– A7 pins function as address output pins. Refresh timer stops counting.) 1 : Valid (P10 4–P107 pins function as CAS, RAS, MA8, and MA9. A0–A7 function as MA0–MA 7. Refresh timer starts counting.) DRAM control register (Address 6416) b1 b0b2b3b4b5b6b7 RW 0 – RW Nothing is assigned. The value is “0” at reading. RW b3 b2 b1 b0 RW 0 RW Note: Set the refresh timer (address 6616) before setting this bit to “1.” Refresh timer b7 b0 Refresh timer (Address 6616) FunctionsBit At reset RW 7 to 0 These bits can be set to “0116” to “FF16.” Assuming that the set value = n, this register divides f16 by (n + 1). Undefined WO Note: Use the LDM or STA instruction for writing to this register. Do not set this register to “0016.”

Appendix 3. Control registers

7721 Group User’s Manual 17–31

0 : Fixed 1 : Rotating Bit Bit name Functions At reset RW Priority select bit Undefined 0 : No request 1 : Requested (Note 1) DMAC control register L (Address 6816) b1 b0b2b3b4b5b6b7 RW RW 3, 2 0 RW 0 RW TC pin validity bit 0 : Invalid (P103 pin functions as a programmable I/O port (CMOS).) 1 : Valid (P103 pin functions as TC pin (N- channel open-drain).) Nothing is assigned. – DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit 0R W 0 RW Notes 1. The state of bits 4 to 7 are not changed when writing “1” to these bits. 2. •When writing to this register while any of DMAi enable bits (bits 4 to 7 at address 6916) is “1,” set m flag to “1” and use the LDM or STA instruction. When DMAi request bit (bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to “1.”

When writing to this register while all of DMAi enable bits (bits 4 to 7 at address 6916) are “0,” m flag may be “0” or “1.” Use the LDM or STA instruction for writing to this register. When DMAi request bit (bits 4 to 7 at address 6816) must not be changed, set DMAi request bit to “1.” DMAC control register H 1 : DMA request (Valid when software DMA source is selected.) The value is “0” at reading. Bit Bit name Functions At reset RW Software DMA0 request bit 0 : Disabled 1 : Enabled DMAC control register H (Address 6916) b1 b0b2b3b4b5b6b7 WO RW 0W O

Note: When any of bits 4 to 7 is set to “1,” use the CLB or SEB instruction for writing to this register.

Appendix 3. Control registers

7721 Group User’s Manual17–32

Interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 DMA0 to DMA3, A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 6C16 to 7C16) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned. Note: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected. 0 : Interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1 : Interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when edge sense is selected. 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit Interrupt request bit (Note) Bit name At reset RWFunctions b2 b1 b0 0 : No interrupt requested 1 : Interrupt requested Interrupt priority level select bits RW RW RW RW RW0 Polarity select bit 0 : Edge sense 1 : Level sense 7, 6 5 RW Undefined Level sense/Edge sense select bit Nothing is assigned.

Appendix 3. Control registers

7721 Group User’s Manual 17–33

Source address register 0 (Addresses 1FC216 to 1FC016) Source address register 1 (Addresses 1FD216 to 1FD016) Source address register 2 (Addresses 1FE216 to 1FE016) Source address register 3 (Addresses 1FF216 to 1FF016) FunctionsBit At reset RW 23 to 0 These bits have different functions according to the operating mode. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 Destination address register i b7 b0b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) FunctionsBit At reset RW 23 to 0 These bits have different functions according to the operating mode. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 Transfer counter register i b7 b0b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) FunctionsBit At reset RW 23 to 0 These bits have different functions according to the operating mode. Undefined RW Note: When writing to this register, write to all 24 bits. Do not write “00000016” to this register. b23 b16

Appendix 3. Control registers

7721 Group User’s Manual17–34

Source address register 0 (Addresses 1FC216 to 1FC016) Source address register 1 (Addresses 1FD216 to 1FD016) Source address register 2 (Addresses 1FE216 to 1FE016) Source address register 3 (Addresses 1FF216 to 1FF016) FunctionsBit At reset RW 23 to 0 [Write] Set the transfer start address of the source. These bits can be set to “000000 16” to “FFFFFF16.” [Read] The read value indicates the source address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) FunctionsBit At reset RW 23 to 0 [Write] Set the transfer start address of the destination. These bits can be set to “000000 16” to “FFFFFF16.” [Read] The read value indicates the destination address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) FunctionsBit At reset RW 23 to 0 [Write] Set the byte number of the transfer data. These bits can be set to “000001 16” to “FFFFFF16.” [Read] The read value indicates remaining byte number of the transfer data. Undefined RW Note: When writing to this register, write to all 24 bits. Do not set this register to “00000016.” b23 b16

Appendix 3. Control registers

7721 Group User’s Manual 17–35

Source address register 0 (Addresses 1FC216 to 1FC016) Source address register 1 (Addresses 1FD216 to 1FD016) Source address register 2 (Addresses 1FE216 to 1FE016) Source address register 3 (Addresses 1FF216 to 1FF016) FunctionsBit At reset RW 23 to 0 [Write] Set the transfer start address of the source. These bits can be set to “000000 16” to “FFFFFF16.” [Read] The read value indicates the source address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) FunctionsBit At reset RW 23 to 0 [Write] Set the transfer start address of the destination. These bits can be set to “000000 16” to “FFFFFF16.” [Read] The read value indicates the destination address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) FunctionsBit At reset RW 23 to 0 [Write] Set the byte number of the transfer data. These bits can be set to “000001 16” to “FFFFFF16.” [Read] The read value indicates the remaining byte number of the block which is being transferred. Undefined RW Note: When writing to this register, write to all 24 bits. Do not write “00000016” to this register. b23 b16

Appendix 3. Control registers

7721 Group User’s Manual17–36

After a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory).
After tranfer starts, the read value indicates the source address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) FunctionsBit At reset RW 23 to 0 Need not to set. [Read] After transfer starts, the read value indicates the destination address of data which is next transferred. Undefined RW b23 b16 b7 b0b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) FunctionsBit At reset RW 23 to 0 [Write] Set the number of transfer blocks. These bits can be set to “000001 16” to “FFFFFF16.” [Read]
After a value is written to this register and until transfer starts, the read value indicates the written value (the transfer block number) .
After transfer starts, the read value indicates the remaining byte number of the block which is being transferred. Undefined RW Note: When writing to this register, write to all 24 bits. Do not write “00000016” to this register. b23 b16

Appendix 3. Control registers

7721 Group User’s Manual 17–37

Link array chain transfer mode b7 b0b15 b8 Source address register 0 (Addresses 1FC216 to 1FC016) Source address register 1 (Addresses 1FD216 to 1FD016) Source address register 2 (Addresses 1FE216 to 1FE016) Source address register 3 (Addresses 1FF216 to 1FF016) FunctionsBit At reset RW 23 to 0 [Write] Set the start address of transfer parameter memory of block which is first transferred. These bits can be set to “000000 16” to “FFFFFF16.” [Read]

After a value is written to this register and until transfer starts, the read value indicates the written value (the start address of the transfer parameter memory of block which is first transferred).
After transfer starts, the read value indicates the source address of data which is next transferred. Undefined RW Note: When writing to this register, write to all 24 bits. b23 b16 b7 b0b15 b8 Destination address register 0 (Addresses 1FC616 to 1FC416) Destination address register 1 (Addresses 1FD616 to 1FD416) Destination address register 2 (Addresses 1FE616 to 1FE416) Destination address register 3 (Addresses 1FF616 to 1FF416) FunctionsBit At reset RW 23 to 0 Need not to set. [Read] After transfer starts, the read value indicates the destination address of data which is next transferred. Undefined RW b23 b16 b7 b0b15 b8 Transfer counter register 0 (Addresses 1FCA16 to 1FC816) Transfer counter register 1 (Addresses 1FDA16 to 1FD816) Transfer counter register 2 (Addresses 1FEA16 to 1FE816) Transfer counter register 3 (Addresses 1FFA16 to 1FF816) FunctionsBit At reset RW 23 to 0 [Write] Set the dummy data. These bits can be set to “000001 16” to “FFFFFF16.” [Read]
After a value is written to this register and until transfer starts, the read value indicates the written value (dummy data).
After transfer starts, the read value indicates the remaining byte number of the block which is being transferred. Undefined RW Note: When writing to this register, write to all 24 bits. Do not write “00000016” to this register. b23 b16

Appendix 3. Control registers

7721 Group User’s Manual17–38

b7 b6 b5 b4 b3 b2 b1 b0 DMA0 mode register L (Address 1FCC16) DMA1 mode register L (Address 1FDC16) DMA2 mode register L (Address 1FEC16) DMA3 mode register L (Address 1FFC16) Note: When the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set bit 0 to “1.” 0 00 : 16 bits 1 : 8 bits 1 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer 0 : Burst transfer mode 1 : Cycle-steal transfer mode 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. RW RW Number-of-unit-transfer-bits select bit (Note) Transfer method select bit Transfer mode select bit Fix this bit to “0.” Transfer source address direction select bits Transfer destination address direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. b5b4 b7b6 RW RW RW RW RW RW DMAi mode register H Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 DMA0 mode register H (Address 1FCD16) DMA1 mode register H (Address 1FDD16) DMA2 mode register H (Address 1FED16) DMA3 mode register H (Address 1FFD16) Notes 1: Set bit 0 to “0” in 2-bus cycle transfer. 2: Bits 4 and 5 are valid to the external and internal areas. However, DRAM area is always handled with “Wait” regardless of the contents of these bits. The wait bit (bit 2 at address 5E16) is invalid in DMA transfer. 0 00 : From memory to I/O 1 : From I/O to memory 1 Refer to “Fig.13.2.7.” RW RW Transfer direction select bit (Used in 1-bus cycle transfer) (Note 1) I/O connection select bit (Valid in 1-bus cycle transfer) Fix these bits to “0.” Transfer source wait bit (Note 2) Continuous transfer mode select bits 0 0 : Single transfer 0 1 : Repeat transfer 1 0 : Array chain transfer 1 1 : Link array chain transfer b7b6 RW RW RW RW RW RW Transfer destination wait bit (Note 2) 0 : Wait 1 : No Wait

Appendix 3. Control registers

7721 Group User’s Manual 17–39

b7 b6 b5 b4 b3 b2 b1 b0 DMA0 control register (Address 1FCE16) DMA1 control register (Address 1FDE16) DMA2 control register (Address 1FEE16) DMA3 control register (Address 1FFE16) Note: When a certain source other than an external source is selected by bits 0 to 3 or when the cycle-steal transfer mode is selected, set bit 4 to “0.” Level sense can be selected only when both of the external source and the burst transfer mode are selected. 0 0 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQi) 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion 7, 6 RW RW DMA request source select bits (Note) Edge sense/Level sense select bit (Used when external source and burst transfer mode are selected) (Note) DMAACKi validity bit 0 : Invalid (The pin functions as a programmable I/O port.) 1 : Valid (The pin functions as DMAACKi.) RW RW RW RW Undefined – 0 : Edge sense (Falling edge) 1 : Level sense (“L” level) Nothing is assigned. b3b2b1b0

Appendix 4. Package outline

7721 Group User’s Manual17–40

Appendix 4. Package outline

7721 Group User’s Manual 17–41

Appendix 5. Examples of handling unused pins Appendix 5. Examples of handling unused pins Examples of handling unused pins are described below. These descriptions are just examples. The user shall modify them according to the actual application and test them. Table 1 Examples of handling unused pins Handling example Connect these pins to the Vcc or Vss pin via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1, 2). Leave this pin open. Leave this pin open. Connect these pins to the Vcc pin via resistors (These pins are pulled high.) (Note 2) Connect this pin to the Vcc pin or Vss pin. Connect this pin to the Vcc pin. Connect these pins to the Vss pin. Pins P4 3 to P47, P5 to P10 BLE, BHE, ALE, φ1, ST0, ST1 X OUT (Note 3) HOLD, RDY CNVss AVcc AVss, V REF P43–P47, P5–P10 M37721 VSS HOLD RDY AV CC CNV SS AV SS VREF VCC Left open l When setting ports to input mode l When setting ports to output mode ST0 ST1 BLE BHE ALE XOUT Left open P43–P47, P5–P10 M37721 VSS HOLD RDY AV CC CNV SS AV SS VREF VCC Left open ST0 ST1 BLE BHE ALE XOUT Left open Left open ] CNVss pin can be connected to Vcc pin. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Accordingly, set these ports to the output mode immediately after reset. Software reliability can be enhanced when the contents of the above ports’ direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 3: This applies when a clock externally generated is input to the X IN pin. Fig. 2 Examples of handling unused pins

Appendix 6. Machine instructions

7721 Group User’s Manual17–42

A CC ,C← A CC +M+C A CC ← A CC ∧ M Symbol Functions Details Adds the carry, the accumulator and the memory contents.The result is entered into the accumulator. When the D flag is “0,” binary additions is done, and when the D flag is “1,” decimal addition is done. Obtains the logical product of the contents of the accumu- lator and the contents of the memory . The result is en- tered into the accumulator. Shifts the accumulator or the memory contents one bit to the left. “0” is entered into bit 0 of the accumulator or the memory. The contents of bit 15 ( bit 7 when the m flag is “1”) of the accumulator or memory before shift is entered into the C flag. Tests the specified bit of the memory. Branches when all the contents of the specified bit is “0.” Tests the specified bit of the memory. Branches when all the contents of the specified bit is “1.” Branches when the contents of the C flag is “0.” Branches when the contents of the C flag is “1.” Branches when the contents of the Z flag is “1.” Branches when the contents of the N flag is “1.” Branches when the contents of the Z flag is “0.” Branches when the contents of the N flag is “0.” Jumps to the address indicated by the program counter plus the offset value. Executes software interruption. Branches when the contents of the V flag is “0.” Branches when the contents of the V flag is “1.” Makes the contents of the specified bit in the memory “0.” Makes the contents of the C flag “0.” Makes the contents of the I flag “0.” Specifies the bit position in the processor status register by the bit pattern of the second byte in the instruction, and sets “0” in that bit. Makes the contents of the V flag “0.” Compares the contents of the accumulator with the con- tents of the memory. Mb=0? Mb=1? C=0? C=1? Z=1? N=1? Z=0? N=0? PC ← PC±offset PG ← PG+1 when carry occurs) PG ← PG–1 (when borrow occurs) PC ← PC+2 M(S)← PG S ← S–1 M(S)← PC H S ← S–1 M(S)← PC L S ← S–1 M(S)← PS H S ← S–1 M(S)← PS L S ← S–1 I← 1 PC L← AD L PC H ← AD H PG ← 0016 V=0? V=1? C ← 0 Mb ← 0 Makes the contents of the m flag “0.” I← 0 m ← 0 PSb ← 0 V ← 0 A CC –M IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y op n n op Addressing modes AND (Notes 1,2) ADC (Notes 1,2) ASL (Note 1) BBC (Notes 3,5) BBS (Notes 3,5) BCC (Note 3) BCS (Note 3) BEQ (Note 3) BMI (Note 3) BNE (Note 3) BPL (Note 3) BRA (Note 4) BRK BVC (Note 3) BVS (Note 3) CLB (Note 5) CLC CLI CLM CLV CMP (Notes 1,2) CLP n n op n 22 2 61 72 71 2 3 42 3 42 3 42 3 42 2 35 32 2 21 31 82 43 3 42 3 42 72 16 72 C1 D1 342 m=0 m=1 C ← b7 ··· b0 ← 0 # op n# op n# op n# 69 2 65 24 43 42 75 72 22 25 47 2 3 42 6 42 0A 2 06 00 15 2 14 8 18 2 4C5 D2 7 Appendix 6. Machine instructions

Appendix 6. Machine instructions APPENDIX

7721 Group User’s Manual 17–43

Processor status registerAddressing modes L(DIR) L(DIR),Y ABL,X (ABS) STK REL SR (SR),Y BLKABS,b ABS,X ABS,Y DIR,b,R ABS,b,R (ABS,X ) 30 op op op nnnnnnnn ABS IPL N V m C 285 64 DIZn op op opn n nop op nop 10 2 3 42 4 42 4 42 5 42 op 63 5 10 3 10 2 37 12 3 42 0E 3 66 3 2F 64 3F 74 4 42 84 42 58 42 1E 83

• N V• x
• • Z C 53C 847 90 42 24 74 2C 85 24D0 10 42 50 42 IC 94
••• C Z
C3 52 8D3 2 3103742 C7 10 2 D7 11 2 CD 3 DD 63 3 13 34 D9 63 84 84 CF 64 DF 74 85 9 542 DF L(ABS)ABL #nn 77 11 2 6D 4 7D 679 6F 7F 28 3612 27 11 2 2D 3 3D 39 23 3 42 12 42 CD 6 42 DD CF 910 Specified flag be- comes “0.” N

Appendix 6. Machine instructions

7721 Group User’s Manual17–44

Symbol Functions Details IMP IMM DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y nop op op n nn op n op Addressing modes Compares the contents of the index register X with the contents of the memory. Compares the contents of the index register Y with the contents of the memory. Decrements the contents of the accumlator or memory by Decrements the contents of the index register X by 1. Decrements the contents of the index register Y by 1. The numeral that places the contents of accumlator B to the higher order and the contents of accumulator A to the lower order is divided by the contents of the memory. The quotient is entered into accumula- tor A and the remainder into accumulator B. Logical exclusive sum is obtained of the contents of the accumulator and the contents of the memory. The result is placed into the accumulator. Increments the contents of the accumulator or memory by Increments the contents of the index register X by 1. Increments the contents of the index register Y by 1. Places a new address into the program counter and jumps to that new address. X–M Y–M A CC ← A CC –1 or M ← M–1 X ← X–1 Y ← Y–1 A(quotient)← B,A/M B(remainder) A CC ← A CC ∨ M A CC ← A CC +1 or M ← M+1 X ← X+1 Y ← Y+1 ABS PC L← AD L PC H ← AD H ABL PC L← AD L PC H ← AD H PG ← AD G (ABS) PC L← (ADH , ADL) PC H ← (ADH ,ADL+1) L(ABS) PC L← (ADH , ADL) PC H ← (AD H , ADL+1) PG ← (AD H , ADL+2) (ABS, X) PC L← (ADH , ADL+X) PC H ← (AD H , ADL+X +1) ABS M(S)← PC H S ← S–1 M(S)← PC L S ← S–1 PC L← AD L PC H ← AD H ABL M(S)← PG S ← S–1 M(S)← PC H S ← S–1 M(S)← PC L S ← S–1 PC L← AD L PC H ← AD H PG ← AD G (ABS, X) M(S)← PC H S ← S–1 M(S)← PC L S ← S–1 PC L← (ADH , ADL+X) PC H ← (AD H , ADL+X +1) CPX (Note 2) CPY (Note 2) DEC (Note 1) DEX DEY DIV (Notes 2,10) EOR (Notes 1,2) INC (Note 1) INX JMP INY JSR Saves the contents of the program counter (also the con- tents of the program bank register for ABL) into the stack, and jumps to the new address. n op nn op op n op op n E0 2 E4 42 C4 4 2 1A 21 C6 72 D6 3 89 3 89 3 89 32 3 89 49 2 45 42 55 52 62 72 51 82 63 42 73 42 83 42 93 10 3 3A 21 E6 77 C8 21 A C0 22 CA 327 4152

Appendix 6. Machine instructions APPENDIX

7721 Group User’s Manual 17–45

Processor status registerAddressing modes L(DIR),Y ABL ABL,X (ABS) L(ABS) STK REL (SR),Y BLKABS,Y DIR,b,R ABS,b,R(ABS,X ) 30 op #op op op nnnnop nnn ABS op IPL N V m C 285 6410 9 DIZn nn op op nopn op nop op n nop op

• N •• x
• • Z4 op 336 EE 31 89 31 5 89 32 589 31 4 5D 63 FE 38 4F 64 5C 44 22 84 DC33 86 7C 3 3FC 8 30 3 89 333 Z L(DIR) ABS,b ABS,X SR ## ## C CC EC CE 73 DE 29 89 344D 324C 46C

Appendix 6. Machine instructions

7721 Group User’s Manual17–46

Symbol Functions Details IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y #nop n op n op n op Addressing modes A CC ← M M ← IMM DT ← IMM X ← M Y ← M m=0 m=1 0 → b7 ··· b0 → C Enters the contents of the memory into the accummulator. Enters the immediate vaiue into the memory. Enters the immediate value into the data bank regiater. Enters the contents of the memory into index register X. Enters the contents of the memory into index register Y. Shifts the contents of the accumulator or the contents of the memory one bit to the right. The bit 0 of the accumu- lator or the memory is entered into the C flag. “0” is en- tered into bit 15 (bit 7 when the m flag is “1.”) B, A← A ] M Mn+i← Mm+i Mn–i← Mm–i PC ← PC+1 A CC ← A CC VM M(S)← IMM 2 S ← S–1 M(S)← IMM 1 S ← S–1 M(S)← M((DPR)+IMM +1) S ← S–1 M(S)← M((DPR)+IMM) S ← S–1 EAR ← PC+IMM 2,IMM1 M(S)← EAR H S ← S–1 M(S)← EAR L S ← S–1 m=0 M(S)← A H S ← S–1 M(S)← A L S ← S–1 m=1 M(S)← A L S ← S–1 m=0 M(S)← B H S ← S–1 M(S)← B L S ← S–1 m=1 M(S)← B L S ← S–1 Transmits the data block. The transmission is done from the lower order address of the block. Advances the program counter, but pertorms nothing else. Logical sum per bit of the contents of the accumulator and the contents of the memory is obtained. The result is en- tered into the accumulator. The 3rd and the 2nd bytes of the instruction are saved into the stack, in this order. Specifies 2 sequential bytes in the direct page in the 2nd byte of the instruction, and saves the contents into the stack. Regards the 2nd and 3rd bytes of the instruction as 16-bit numerals, adds them to the program counter, and saves the result into the stack. Saves the contents of accumulator A into the stack. Saves the contents of accumuator B into the stack. LDA (Notes 1,2) LDM (Note 5) LDT LDX (Note 2) LDY (Note 2) LSR (Note 1) MPY (Notes 2,11) MVN (Note 8) MVP (Note 9) NOP ORA (Notes 1,2) PEA PEI PER PHA PHB n op nn op op op n n op op n 25 2 B2 62 2 43 74 53 A6 42 2

2 A4 42 5 2

Multiplies the contents of accumulator A and the contents of the memory. The higher order of the result of operation are entered into accumulator B, and the lower order into accumulator A. Transmits the data block. Transmission is done form the higher order address of the data block. A9 22 A5 4 B5 72 B1 B6 5 B4A0 A2 2 2289 2118 EA

Appendix 6. Machine instructions APPENDIX

7721 Group User’s Manual 17–47

Processor status registerAddressing modes ABL ABL,X (ABS) STK (SR),YABS,X ABS,Y ABS,b,R(ABS,X ) 30 op nopnnnnn ABS IPL N V m C 287 5 6410 9 DIZn nop nop nop nopop

N• x opop n op op opop op n op op op n op A7 2 B7 11 2 AD 43 3 B9 63 AF 64 BF 7 n A3 52 B3 3 13 3 42 AD BD 4 42 84 42 AF 85 42 BF 5 42 73 42 10 3 9C 54 4

43 BE 63

1D 63 19 63 0F 64 1F 74 03 52 13 82 3 42 3 42 64 42 84 42 84 42 85 42 95 42 73 42 F4 53 D4 62 62 53 48 41 54 73 i 5 72 i 5 72

• • • Z N
• Z•
Z•• N Z Z C
••• Z N BLKSRDIR,b,R RELL(ABS)ABS,bL(DIR),YL(DIR) n BD n 69E BC AE 25 18 89 20 3

Appendix 6. Machine instructions APPENDIX

7721 Group User’s Manual17–48

Symbol Functions Details IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y opnop n nn n nnn n Addressing modes PHD M(S) ← DPR H S ← S–1 M(S)← DPR L S ← S–1 Saves the contents of the direct page register into the stack. M(S)← PG S ← S–1 M(S)← PS H S ← S–1 M(S)← PS L S ← S–1 M(S)← DT S← S–1 x=0 M(S)← X H S ← S–1 M(S)← X L S ← S–1 x=1 M(S)← X L S ← S–1 x=0 M(S)← Y H S ← S–1 M(S)← Y L S ← S–1 x=1 M(S)← Y L S ← S–1 m=0 S ← S+1 A L← M(S) S ← S+1 A H ← M(S) m=1 S ← S+1 A L← M(S) m=0 S ← S+1 B L← M(S) S ← S+1 B H ← M(S) m=1 S ← S+1 B L← M(S) S ← S+1 DPR L← M(S) S ← S+1 DPR H ← M(S) S ← S+1 PS L← M(S) S ← S+1 PS H ← M(S) S ← S+1 DT ← M(S) x=0 S ← S+1 X L← M(S) S ← S+1 X H ← M(S) x=1 S ← S+1 X L← M(S) PHG PHP PHT PHX PHY Saves the contents of the program bank register into the stack. Saves the contents of the program status register into the stack. Saves the contents of the data bank register into the stack. Saves the contents of the index register X into the stack. Saves the contents of the index register Y into the stack. PLA Restores the contents of the stack on the accumulator A. Restores the contents of the stack on the accumulator B. Restores the contents of the stack on the direct page reg- ister. Restores the contents of the stack on the processor status register. Restores the contents of the stack on the data bank reg- ister. Restores the contents of the stack on the index register X. PLB PLD PLP PLT PLX

Appendix 6. Machine instructions APPENDIX

7721 Group User’s Manual 17–49

Processor status registerAddressing modes L(DIR) L(DIR),Y ABL ABL,X (ABS) L(ABS) STK SR (SR),Y BLKABS,b ABS,X ABS,Y DIR,b,R ABS,b,R (ABS,X ) 10 98 76 5 2 30 op nop op op op op op op nop nop op op op op n nnnop nnopop nnnnop nnnnn ABS 408 1 8B 3 1 5A 41 68 51 42 72 2B 1 1628 AB 61 FA 51 IPL N V m x D I C Z Value saved in stack. DA REL

Appendix 6. Machine instructions APPENDIX

7721 Group User’s Manual17–50

Symbol Functions Details IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y opnop op n op nn op op n op nn op op n op Addressing modes PLY x=0 S ← S+1 Y L← M(S) S ← S+1 Y H ← M(S) x=1 S ← S+1 Y L← M(S) Restores the contents of the stack on the index register Y. M(S)← A, B, X··· Saves the registers among accumulator, index register, direct page register, data bank register, program bank register, or processor status register, specified by the bit pattern of the second byte of the instruction into the stack. Restores the contents of the stack to the registers among accumulator, index register, direct page register, data bank register, or processor status register, specified by the bit pattern of the second byte of the instruction. m=0 n bit rotate left b15 ··· b0 ← m=1 n bit rotate left b7 ··· b0 ← A, B, X···← M(S) PSH (Note 6) PUL (Note 7) RLA (Note 13) Rotates the contents of the accumulator A, n bits to the left.m=0 m=1 ROL (Note 1) Links the accumulator or the memory to C flag, and rotates result to the left by 1 bit. m=0 m=1 → C → b7 ··· b0 → ROR (Note 1) Links the accumulator or the memory to C flag, and rotates result to the right by 1 bit. S ← S+1 PS L← M(S) S ← S+1 PS H ← M(S) S ← S+1 PC L← M(S) S ← S+1 PC H ← M(S) S ← S+1 PG ← M(S) S ← S+1 PC L← M(S) S ← S+1 PC H ← M(S) S ← S+1 PG ← M(S) S ← S+1 PC L← M(S) S ← S+1 PC H ← M(S) A CC , C← A CC –M–C RTI RTL RTS SBC (Notes 1,2) Returns from the interruption routine. Returns from the subroutine. The contents of the program bank register are also restored. Returns from the subroutine. The contents of the program bank register are not restored. Subtracts the contents of the memory and the borrow from the contents of the accumulator. 816B 60 51 40 11 1 6A 21 66 72 42 4 2 12 26 72 36 7 2 42 42 89 63

22 E5 4 2 F5 5 26 F2 2 E1 7 2 F1 2

i 1042

Appendix 6. Machine instructions APPENDIX

7721 Group User’s Manual 17–51

Processor status registerAddressing modes L(DIR) L(DIR),Y ABL ABL,X (ABS) L(ABS) STK REL SR (SR),Y BLKABS,b ABS,X ABS,Y DIR,b,R ABS,b,R (ABS,X ) 10 98 76 5 2 30 op nop op op op op op op op op op op op op n nnnopnopop nnnop nnnnn ABS IPL V m x D I C Z N If restored the contents of PS, it becomes its value. And the other cases are no change. Value saved in stack. EB 12 2 214FB 3i1+4i2 3E 83 6E 387E 2E 73 52E3 EDE7 F7

2 F7 11 210 ED 43

FD 63 F9 63 EF 6 FF 74 82F3 42 73 42 10 3 E3 F3 FD C 2i1+i2

Appendix 6. Machine instructions

7721 Group User’s Manual17–52

Symbol Functions Details IMP IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y opnop op n op nn op op n op nn op op op Addressing modes Makes the contents of the specified bit in the memory “1.” Makes the contents of the I flag “1.” Makes the contents of the m flag “1.” Set the specified bit of the processor status register's lower byte (PS L) to “1.” Stores the contents of the accumulator into the memory. Stops the oscillation of the oscillator. Stores the contents of the index register X into the memory. Stores the contents of the index register Y into the memory. Transmits the contents of the accumulator A to the direct page register. Transmits the contents of the accumulator A to the stack pointer. Transmits the contents of the accumulator A to the index register X. Transmits the contents of the accumulator A to the index register Y. Transmits the contents of the accumulator B to the direct page register. Transmits the contents of the accumulator B to the stack pointer. Transmits the contents of the accumulator B to the index register X. Transmits the contents of the accumulator B to the index register Y. Transmits the contents of the direct page register to the accumulator A. Transmits the contents of the direct page register to the accumulator B. Makes the contents of the C flag “1.” SEB (Note 5) Mb ← 1 SEC SEI SEM SEP STA (Note 1) STP STX STY TAD TAS C ← 1 I← 1 m ← 1 PSb ← 1 M ← A CC M ← X M ← Y DPR ← A S ← A X ← A Y ← A DPR ← B S ← B TAX TAY TBD TBS TDB X ← BTBX TBY TDA Y ← B A ← DPR B ← DPR 04 83 38 21 78 21 2F8 1 DB 31 2485 42 6 3 39423942742 2595 72 81 72 91 72 819295 2486 2484 5296 94 25 5B 21 1B 21 AA 21 A8 21 442 2 42 42 AA 42 4 7B 21 42 4 Transmits the contents of the stack pointer to the accumulator A. Transmits the contents of the stack pointer to the accu- mulator B. A ← S B ← S TSA TSB 3B 21 42 42 Transmits the contents of the stack pointer to the index register X. Transmits the contents of the index register X to the ac- cumulator A. X ← S A ← X TSX TXA Transmits the contents of the index register X to the ac- cumulator B. Transmits the contents of the index register X to the stack pointer. B ← X S ← X TXB TXS Transmits the contents of the index register X to the index register Y. Y ← XTXY Transmits the contents of the index register Y to the ac- cumulator A. A ← YTYA TYB B ← Y Transmits the contents of the index register Y to the index register X. Stops the internal clock. Exchanges the contents of the accumulator A and the con- tents of the accumulator B. TYX WIT XAB X ← Y A B←→ BA 21 42 24 9A 21 9B 21 98 21 42 42 Transmits the contents of the index register Y to the ac- cumulator B. BB 21 CB 31 2689 9 3 42

Appendix 6. Machine instructions APPENDIX

7721 Group User’s Manual 17–53

L(DIR) L(DIR),Y ABL ABL,X (ABS) L(ABS) STK SR (SR),Y BLKABS,b ABS,X ABS,Y DIR,b,R ABS,b,R (ABS,X ) 10 98 76 5 2 30 op nop op op op op op op nop nop op op op op n nnnop nnopop nnnnop nnnn ABS IPL V m x D I C Z N 40C 9 97 353 3 54 4 7 342 474 74 75 85 9 97 9F Processor status register 22 6 “1.” 13 42 59D 99 8F 9F 5 42 10 REL 4242 8F8D 1087

Appendix 6. Machine instructions

7721 Group User’s Manual17–54

The number of cycles shown in the table is described in the case of the fastest mode for each instruction. The number of cycles shown in the table is calculated for DPRL=0. The number of cycles in the addressing mode concerning the DPR when DPRL 0 must be incremented by 1. The number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer, or according to whether the memory read/write address is odd or even. It also differs when the external region memory is accessed by BYTE=“H.” Notes 1. The operation code at the upper row is used for accumulator A, and the operation at the lower row is used for accumulator 2. When setting flag m=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 3. The number of cycles increments by 2 when branching. 4. The operation code on the upper row is used for branching in the range of –128 to +127, and the operation code on the lower row is used for branching in the range of –32768 to +32767. 5. When handling 16-bit data with flag m=0, the byte in the table is incremented by 1. The number of cycles corresponding to the register to be pushed are added. The number of cycles when no pushing is done is 12. i 1 indicates the number of registers among A, B, X, Y, DPR, and PS to be saved, while i2 indicates the number of registers among DT and PG to be saved. The number of cycles corresponding to the register to be pulled are added. The number of cycles when no pulling is done is 14. i 1 indicates the number of registers among A, B, X, Y, DT, and PS to be restored, while i2=1 when DPR is to be restored. 8. The number of cycles is the case when the number of bytes to be transferred is even. When the number of bytes to be transferred is odd, the number is calculated as; 7 + (i/2) 5 7 + 4 Note that, (i/2) shows the integer part when i is divided by 2. 9. The number of cycles is the case when the number of bytes to be transferred is even. When the number of bytes to be transferred is odd, the number is calculated as; 9 + (i/2) 5 7 + 5 Note that, (i/2) shows the integer part when i is divided by 2. 10. The number of cycles is the case in the 16-bit ÷ 8-bit operation. The number of cycles is incremented by 16 for 32-bit ÷ 16- bit operation. 11. The number of cycles is the case in the 8-bit 5 8-bit operation. The number of cycles is incremented by 8 for 16-bit 5 16- bit operation. 12. When setting flag x=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 13. When flag m is 0, the byte in the table is incremented by 1. B A X Y DPR DT PS A B X Y DPR DT PG PS Type of register Number of cycles Type of register Number of cycles

Appendix 6. Machine instructions

7721 Group User’s Manual 17–55

Symbols in machine instructions table Description Symbol DescriptionSymbol IMP IMM A DIR DIR, b DIR, X DIR, Y (DIR) (DIR,X) (DIR), Y L (DIR) L (DIR),Y ABS ABS, b ABS, X ABS, Y ABL ABL, X (ABS) L (ABS) (ABS, X) STK REL DIR, b, REL ABS, b, REL SR (SR), Y BLK C Z I D x m V N IPL Implied addressing mode Immediate addressing mode Accumulator addressing mode Direct addressing mode Direct bit addressing mode Direct indexed X addressing mode Direct indexed Y addressing mode Direct indirect addressing mode Direct indexed X indirect addressing mode Direct indirect indexed Y addressing mode Direct indirect long addressing mode Direct indirect long indexed Y addressing mode Absolute addressing mode Absolute bit addressing mode Absolute indexed X addressing mode Absolute indexed Y addressing mode Absolute long addressing mode Absolute long indexed X addressing mode Absolute indirect addressing mode Absolute indirect long addressing mode Absolute indexed X indirect addressing mode Stack addressing mode Relative addressing mode Direct bit relative addressing mode Absolute bit relative addressing mode Stack pointer relative addressing mode Stack pointer relative indirect indexed Y addressing mode Block transfer addressing mode Carry flag Zero flag Interrupt disable flag Decimal operation mode flag Index register length selection flag Data length selection flag Overflow flag Negative flag Processor interrupt priority level Addition Subtraction Multiplication Division Logical AND Logical OR A CC ACCH ACCL A A H AL B B H BL X X H XL Y Y H YL S PC PC H PC L PG DT DPR DPR H DPR L PS PS H PS L PS b M(S) Mb AD G AD H AD L op n i i 1, i2 Exclusive OR Negation Movement to the arrow direction Accumulator Accumulator’s upper 8 bits Accumulator’s lower 8 bits Accumulator A Accumulator A’s upper 8 bits Accumulator A’s lower 8 bits Accumulator B Accumulator B’s upper 8 bits Accumulator B’s lower 8 bits Index register X Index register X’s upper 8 bits Index register X’s lower 8 bits Index register Y Index register Y’s upper 8 bits Index register Y’s lower 8 bits Stack pointer Program counter Program counter’s upper 8 bits Program counter’s lower 8 bits Program bank register Data bank register Direct page register Direct page register’s upper 8 bits Direct page register’s lower 8 bits Processor status register Processor status register’s upper 8 bits Processor status register’s lower 8 bits Processor status register’s b-th bit Contents of memory at address indicated by stack pointer b-th memory location Value of 24-bit address’s upper 8-bit (A23–A 16) Value of 24-bit address’s middle 8-bit (A15–A 8) Value of 24-bit address’s lower 8-bit (A7–A 0) Operation code Number of cycle Number of byte Number of transfer byte or rotation Number of registers pushed or pulled

Appendix 7. Hexadecimal instruction code table

7721 Group User’s Manual17–56

Appendix 7. Hexadecimal instruction code table INSTRUCTION CODE TABLE-1 D 3–D 0 D 7–D 4 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

0123456789 B C D EF

A,(DIR,X) ORA A,(DIR),Y AND A,(DIR,X) EOR A,(DIR,X) EOR A,(DIR),Y ADC A,(DIR,X) ADC A,(DIR),Y STA A,(DIR,X) LDA A,(DIR,X) AND A,(DIR),Y STA A,(DIR),Y LDA A,(DIR),Y CMP A,(DIR),Y CMP A,(DIR,X) SBC A,(DIR,X) SBC A,(DIR),Y ORA A,(DIR) JSR ABL AND A,(DIR) Note 1 EOR A,(DIR) PER ADC A,(DIR) STA A,(DIR) LDA A,(DIR) CMP A,(DIR) SBC A,(DIR) BRA REL LDX IMM CLP IMM SEP IMM ORA A,SR A ORA A,DIR SEB DIR,b ASL DIR ORA A,L(DIR) ORA A,IMM ORA A,ABS PHP PHD ASL A SEB ABS,b ASL ABS ORA A,(SR),Y ORA A,L(DIR),Y CLB DIR,b ORA A,DIR,X ASL DIR,X CLC TAS ORA A,ABS,Y DEC A CLB ABS,b ORA A,ABS,X ASL ABS,X AND A,SR BBS DIR,b,R AND A,DIR ROL DIR AND A,L(DIR) PLP PLD AND A,IMM ROL A BBS ABS,b,R AND A,ABS ROL ABS AND A,(SR),Y BBC DIR,b,R AND A,DIR,X ROL DIR,X AND A,L(DIR),Y SEC AND A,ABS,Y INC A TSA BBC ABS,b,R AND A,ABS,X ROL ABS,X EOR A,SR MVP EOR EOR EOR EOR A,DIR LSR DIR A,L(DIR) PHA A,IMM LSR A PHG JMP ABS A,ABS LSR ABS EOR A,(SR),Y A,(SR),Y A,(SR),Y A,(SR),Y A,(SR),Y A,(SR),Y MVN EOR EOR EOR EOR LSRLSR CLI TAD PHY JMP A,DIR,X A,DIR,X A,DIR,X A,DIR,X A,DIR,X A,DIR,X DIR,X DIR,X DIR,Y DIR,Y DIR,X DIR,X A,L(DIR),Y A,L(DIR),Y A,L(DIR),Y A,L(DIR),Y A,L(DIR),Y A,L(DIR),Y A,ABS,Y A,ABS,Y A,ABS,Y A,ABS,Y A,ABS,Y A,ABS,Y ABL (ABS) ABS ABS ABS ABS A,ABS,X A,ABS,X A,ABS,X A,ABS,X A,ABS,X A,ABS,X ABS,X ABS,X ABS,X ABS,Y ABS,X ABS,X ADC ADC ADC ADC ADC ROR ROR ROR JMP RTLPLA LDM A,SR A,SR A,SR A,SR A,SR DIR DIR DIR DIR DIR A,DIR A,DIR A,DIR A,DIR A,DIR DIR DIR DIR DIR DIR A,L(DIR) A,L(DIR) A,L(DIR) A,L(DIR) A,L(DIR) A,IMM A,IMM A,IMM A,IMM A A,ABS ABS A,ABS ABS A,ABS ABS A,ABS ABS A,ABS ABS ADC ADC ADC ADC ADCJMP RORRORLDM DIR,X DIR,X DIR,X SEI TDA PLY (ABS,X) STA STY STA STA STA STX STY STX DEY TXA PHTNote 2 STASTASTASTASTA STY STX TXS TXYTYA LDM LDM LDA LDALDY LDA LDA LDALDX LDX LDY PLTTAXTAY LDA LDALDY LDA LDX LDA TYXTSXCLV ABS,X LDA LDXLDY CMP CMP CMP CMP CMPCPY DEC CPY DEC CMP DEC INY DEX WIT CMP CMP CMP DEC CLM CMP PHX STP JMP L(ABS) PEI SBC SBC SBC SBC SBC ORA A,ABL ORA A,ABL,X AND A,ABL AND A,ABL,X EOR A,ABL EOR A,ABL,X A,ABL,X A,ABL,X A,ABL,X A,ABL,X A,ABL,X ADC A,ABL A,ABL A,ABL A,ABL A,ABL ADC STA STA LDA LDA CMP CMP SBC SBCSBCSBC CPX CPX INC INC INX INC SBC PEA SBC SBC INC SEM PLX NOP PSH PUL JSR ABS (ABS,X) Notes 1: 4216 specifies the contents of the INSTRUCTION CODE TABLE-2. About the second word’s codes, refer to the INSTRUCTION CODE TABLE-2. 2: 8916 specifies the contents of the INSTRUCTION CODE TABLE-3. About the second word’s codes, refer to the INSTRUCTION CODE TABLE-2.

Appendix 7. Hexadecimal instruction code table

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INSTRUCTION CODE TABLE-2 (The first word’s code of each instruction is 4216) D 3–D 0 D 7–D 4 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

0123456789 B C D E F

B,(DIR,X) ORA B,(DIR),Y AND B,(DIR,X) EOR B,(DIR,X) EOR B,(DIR),Y ADC B,(DIR,X) ADC B,(DIR),Y STA B,(DIR,X) LDA B,(DIR,X) AND B,(DIR),Y STA B,(DIR),Y LDA B,(DIR),Y CMP B,(DIR),Y CMP B,(DIR,X) SBC B,(DIR,X) SBC B,(DIR),Y ORA B,(DIR) AND B,(DIR) EOR B,(DIR) ADC B,(DIR) STA B,(DIR) LDA B,(DIR) CMP B,(DIR) SBC B,(DIR) ORA B,SR A ORA B,DIR ORA B,L(DIR) ORA B,IMM ORA B,ABS ASL B ORA B,(SR),Y ORA B,L(DIR),Y ORA B,DIR,X TBS ORA B,ABS,Y DEC B ORA B,ABS,X AND B,SR AND B,DIR AND B,L(DIR) AND B,IMM ROL B AND B,ABS AND B,(SR),Y AND B,DIR,X AND B,L(DIR),Y AND B,ABS,Y INC B TSB AND B,ABS,X EOR B,SR EOR EOR EOR EOR B,DIR B,L(DIR) PHB B,IMM LSR B B,ABS EOR B,(SR),Y B,(SR),Y B,(SR),Y B,(SR),Y B,(SR),Y B,(SR),Y EOR EOR EOR EOR TBD B,DIR,X B,DIR,X B,DIR,X B,DIR,X B,DIR,X B,DIR,X B,L(DIR),Y B,L(DIR),Y B,L(DIR),Y B,L(DIR),Y B,L(DIR),Y B,L(DIR),Y B,ABS,Y B,ABS,Y B,ABS,Y B,ABS,Y B,ABS,Y B,ABS,Y B,ABS,X B,ABS,X B,ABS,X B,ABS,X B,ABS,X B,ABS,X ADC ADC ADC ADC ADC ROR PLB B,SR B,SR B,SR B,SR B,SR B,DIR B,DIR B,DIR B,DIR B,DIR B,L(DIR) B,L(DIR) B,L(DIR) B,L(DIR) B,L(DIR) B,IMM B,IMM B,IMM B,IMM B B,ABS B,ABS B,ABS B,ABS B,ABS ADC ADC ADC ADC ADC TDB STA STA STA STA TXB STASTASTASTASTA TYB LDA LDA LDA LDA LDA TBXTBY LDA LDA LDA LDA LDA CMP CMP CMP CMP CMP CMPCMP CMP CMP CMP SBC SBC SBC SBC SBC ORA B,ABL ORA B,ABL,X AND B,ABL AND B,ABL,X EOR B,ABL EOR B,ABL,X B,ABL,X B,ABL,X B,ABL,X B,ABL,X B,ABL,X ADC B,ABL B,ABL B,ABL B,ABL B,ABL ADC STA STA LDA LDA CMP CMP SBC SBCSBCSBCSBC SBC SBC

Appendix 7. Hexadecimal instruction code table

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INSTRUCTION CODE TABLE-3 (The first word’s code of each instruction is 8916) D 3–D 0 D 7–D 4 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1101 1100 1110 1111 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 (DIR,X) MPY (DIR),Y DIV (DIR,X) DIV (DIR),Y MPY (DIR) DIV (DIR) MPY SR A MPY DIR MPY L(DIR) MPY IMM MPY ABS MPY (SR),Y MPY L(DIR),Y MPY DIR,X MPY ABS,Y MPY ABS,X DIV SR DIV DIR DIV L(DIR) DIV IMM DIV ABS DIV (SR),Y DIV DIR,X DIV L(DIR),Y DIV ABS,Y DIV ABS,X RLA IMM IMM LDT MPY ABL MPY ABL,X DIV ABL DIV ABL,X XAB

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Appendix 8. Countermeasure against noise Appendix 8. Countermeasure against noise General countermeasure examples against noise are described below. Although the effect of these countermeasure depends on each system, refer to the following when an noise-related problem occurs. 1. Short wiring length The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer. (1) Make the length of wiring connected to the RESET pin as short as possible.______ In particular, connect a capacitor between the RESET pin and the Vss pin with the shortest possible wiring (within 20 mm). Reason: If noise is input to the RESET pin, the microcomputer restarts operation before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise XIN XOUT Vss XIN XOUT Vss M37721 M37721 N ot acceptable A cceptable Fig. 4 Wiring for clock input/output pins Reset circuit Vss RESET Vss M37721 A cceptable RESETReset circuit Noise VssVss M37721 N ot acceptable Fig. 3 Wiring for RESET pin (2) Wiring for clock input/output pins l Make the length of wiring connected to the clock input/output pins as short as possible. l Make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator, and the Vss pin of the microcomputer, as short as possible (within 20 mm). l Separate the Vss pattern for oscillation from all other Vss patterns. (Refer to “Figure 11.”) Reason: The microcomputer’s operation synchronizes with a clock generated by the oscillation circuit. If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or a program runaway. Also, if the noise causes a potential difference between the Vss level of the microcomputer and the Vss level of an oscillator, the correct clock will not be input in the microcomputer.

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Appendix 8. Countermeasure against noise (3) Wiring for CNVss pin Connect CNVss pin to the Vss pin with the shortest possible wiring. Reason: The processor mode of the microcomputer is influenced by a potential at the CNVss pin when the CNVss pin and the Vcc or Vss pin are connected. If the noise causes a potential difference between the CNVss pin and the Vss or Vcc pin, the processor mode may become unstable. This may cause a microcomputer malfunction or a program runaway. Noise CNVss Vss M37721 CNVss Vss M37721 A cceptableN ot A cceptable When connecting th e C NVss and Vcc pins, connect them in the shortest possible distance, also. Fig. 5 Wiring for CNVss pin 2. Connection of bypass capacitor between Vss and Vcc lines Connect an approximate 0.1 µF bypass capacitor as follows: l Connect a bypass capacitor between the Vss and Vcc pins, at equal lengths. l The wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as possible. l Use thicker wiring for the Vss and Vcc lines than that for the other signal lines. Fig. 6 Bypass capacitor between Vss and Vcc lines Bypass capacitor VccVss M37721 Wiring pattern Wiring pattern

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Appendix 8. Countermeasure against noise 3. Wiring for analog input pins, analog power source pins, etc. (1) Processing for analog input pins l Connect a resistor to the analog signal line, which is connected to an analog input pin, in series. Additionally, connect the resistor to the microcomputer as close as possible. l Connect a capacitor between the analog input pin and the AVss pin, as close to the AVss pin as possible. Reason: A signal which is input to the analog input pin is usually an output signal from a sensor. The sensor, which detects changes in status, is installed far from the microcomputer’s printed circuit board. Therefore, this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer’s analog input pin. If a capacitor between an analog input pin and the AVss pin is grounded far away from the AVss pin, noise on the GND line may enter the microcomputer through the capacitor. Fig. 7 Countermeasure example against noise for analog input pin using thermistor AN i AVss Thermistor Noise M3772 1 RI CI Reference values RI : Approximate 100 Ω to 1000 Ω CI : Approximate 100 pF to 1000 pF Notes 1 :Design an external circuit for the ANi pin so that charge/discharge is available within 1 cycle of AD . 2 : This resistor and thermistor are used to divide resistance. (Note 2) A cceptable A cceptableN ot acceptable

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Appendix 8. Countermeasure against noise (2) Processing for analog power source pins, etc. l Use independent power sources for the Vcc, AVcc and VREF pins. l Insert capacitors between the AVcc and AVss pins, and between the VREF and AVss pins. Reasons: Prevents the A-D converter from noise on the Vcc line. Fig. 8 Processing for analog power source pins, etc. AVcc AVss M3772 1 Reference values C1 0.47 µF C2 0.47 µF Note : Connect capacitors using the thickest, shortest wiring possible. VREF AN i C1 C2 (sensor, etc.)

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Appendix 8. Countermeasure against noise 4. Oscillator protection The oscillator, which generates the basic clock for the microcomputer operations, must be protected from the affect of other signals. (1) Distance oscillator from signal lines with large current flows Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. Reason: The microcomputer is used in systems which contain signal lines for controlling motors, LEDs, thermal heads, etc. Noise occurs due to mutual inductance when a large current flows through the signal lines. (2) Distance oscillator from signal lines with frequent potential level changes l Install an oscillator and its wiring pattern away from signal lines where potential levels change frequently. l Do not cross these signal lines over the clock-related or noise-sensitive signal lines. Reason: Signal lines with frequently changing potential levels may affect other signal lines at a rising or falling edge. In particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. XIN XOUT Vss M M37721 Mutual inductance Large current XIN XOUT Vss Do not cross. M377 1 ] I/O pin for signal with frequently changing potential levels Fig. 10 Wiring for signal lines where potential levels frequently change (3) Oscillator protection using Vss pattern Print a Vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. Connect the Vss pattern to the Vss pin of the microcomputer with the shortest possible wiring, separating it from other Vss patterns. XIN XOUT Vss An example of Vss pattern on the underside of an oscillator. Mounted pattern example of oscillator unit. Separate Vss lines for oscillation and supply. M37721 Fig. 11 Vss pattern underneath mounted oscillator Fig. 9 Wiring for signal lines where large current flows

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Appendix 8. Countermeasure against noise 5. Setup for I/O ports Setup I/O ports by hardware and software as follows: <Hardware protection> l Connect a resistor of 100 Ω or more to an I/O port in series. <Software protection> l Read the data of an input port several times to confirm that input levels are equal. l Since the output data may reverse because of noise, rewrite data to the output port’s Pi register periodically. l Rewrite data to port Pi direction registers periodically. 6. Reinforcement of the power source line l For the Vss and Vcc lines, use thicker wiring than that of other signal lines. l When using a multilayer printed circuit board, the Vss and Vcc patterns must each be one of the middle layers. l The following is necessary for double-sided printed circuit boards:

On one side, the microcomputer is installed at the center, and the Vss line is looped or meshed around it. The vacant area is filled with the Vss line.
On the opposite side, the Vcc line is wired the same as the Vss line.
The power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputer's power source lines with the shortest possible wiring. Reasons: With external devices connected to the microcomputer, the levels of many of the signal lines (total external address buses: 24 bits) may change simultaneously, causing noise on the power source line. Noise Direction register Port latch Data bus Port Fig. 12 Setup for I/O ports

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Appendix 9. 7721 Group Q & A Appendix 9. 7721 Group Q & A Information which may be helpful in fully utilizing the 7721 Group is provided in Q & A format. In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each page is a question, and a box below the question is its answer. (If a question or an answer extends to two or more pages, there is a page number at the lower right corner.) At the upper right corner of each page, the main function related to the contents of description in that page is listed.

Appendix 9. 7721 Group Q & A

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Q Is there any SFR to which a certain instruction cannot be used for writing ? (1) Use the LDM or STA instruction to write to the registers or the bits listed below. Do not use read-modify-write instructions (i.e., CLB, SEB, ASL, ASR, DEC, INC, LSR, ROL, and ROR ). Pulse output data register 0, 1 (addresses 1A16, 1C16) UART0, 1 baud rate register (addresses 3116, 3916) UART0, 1 transmit buffer register (addresses 3316, 3216, 3B16, 3A16) Timer A2–A4 two-phase pulse signal processing select bit (bits 5–7 at address 4416) Timer A2–A4 register (addresses 4A16–4F 16 ; one-shot pulse mode or pulse width modulation mode) Refresh timer (address 6616) (2) Use the SEB or CLB instruction to write to the following register. DMAC control register H (address 6916 ; when any of bits 4 to 7 = “1”) A

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Appendix 9. 7721 Group Q & A Reset, STP instruction, WIT instruction Q Is it possible to distinguish power-on reset from hardware reset for terminating the stop or wait mode A The contents of the internal RAM is undefined after power-on reset. On the other hand, the contents of the internal RAM are retained when performing hardware reset in the stop or wait mode with Vcc ≥ 2 V. Accordingly, write a certain data to the internal RAM before executing STP or WIT instruction, and judge by checking the contents of the internal RAM after hardware reset.

Appendix 9. 7721 Group Q & A

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Q If an interrupt request (b) occurs while executing an interrupt routine (a), is it true that the main routine is not executed at all from when the execution of the interrupt routine (a) is completed until the execution of the INTACK sequence for the next interrupt (b) starts? (2) If the next interrupt request (b) occurs immediately after sampling pulse À is generated, the microcomputer executes one instruction of the main routine before executing the INTACK sequence for (b). It is because that the interrupt request is sampled by the next sampling pulse \` . Sampling for interrupt requests is performed by sampling pulses generated synchronously with the CPU’s op-code fetch cycles. (1) If the next interrupt request (b) occurs before sampling pulse for the RTI instruction is gener- ated, the microcomputer executes the INTACK sequence for (b) without executing the main rou- tine (not even one instruction). It is because that sampling is completed while executing the RTI instruction. A Conditions: l I is cleared to “0” by executing the RTI instruction. l Iinterrupt priority level of interrupt (b) is higher than IPL of main routine. l Interrupt priority detection time is 2 cycles of φ. Interrupt routine (a) Main routine INTACK sequence for interrupt (b) Sequence of execution RTI instruction ? INTACK sequence for interrupt (b) Interrupt request (b) Interrupt routine (a) Sampling pulse RTI instruction À Main routine Interrupt request (b) Sampling pulse À INTACK sequence for interrupt (b) One instruction executed Interrupt routine (a) RTI instruction

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Appendix 9. 7721 Group Q & A Interrupt Suppose that there is a routine which should not accept one certain interrupt request. (The other interrupt request are acceptable). Although when the interrupt priority level select bits for the above interrupt are set to “0002,” in other words, when this interrupt is set to be disabled, this interrupt request is actually accepted immediately after change of the priority level. Why did this occur and what should I do about it? As for the change of the interrupt priority level, when the following are met, the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled:

The next instruction (in the above example, it is the LDA instruction) is already stored into a instruc- tion queue buffer for the BIU.
Conditions for accepting the instruction which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed. When writing to a memory or an I/O, the CPU passes the address and data to the BIU. Then, the CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into the actual address. Detection of interrupt priority level is performed at the beginning of each instruc- tion. In the above case, the CPU executes the next instruction before the BIU completes the change of the interrupt priority level. Therefore, when the interrupt priority level is detected synchronously with the execution of the next instruction, the interrupt priority level before the change is detected and its interrupt request is accepted. Q A (1/2) Interrupt request is accepted in this interval LDM #00H, XXXIC ; Writes “0002” to interrupt priority level select bits. ; Clears interrupt request bit to “0.” LDA A,DATA ; Instruction at the beginning of the routine which should not accept one certain interrupt request. Previous instruction executed (Instruction prefetched) CPU operation BIU operation Interrupt priority detection time Sequence of execution Interrupt priority level select bits set Change of interrupt priority levels completed Interrupt request accepted Interrupt request generated LDM instruction executed LDA instruction executed

Appendix 9. 7721 Group Q & A

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(2/2) A To prevent this problem, after change of the interrupt priority level is completed, use software to execute the routine that should not accept a certain interrupt request. The following shows a sample program. [Sample program ] After an instruction which writes “0002” to the interrupt priority level select bits, fill the instruction queue buffer with the NOP instruction to make the next instruction not to be executed before the writing is completed. LDM #00H, XXXIC ; Sets the interrupt priority level select bits to “0002.” NOP ; NOP ; NOP ; LDA A,DATA ; Instruction at the beginning of the routine that should not accept a certain : interrupt request

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Appendix 9. 7721 Group Q & A Interrupt Q (1) In both the edge sense and level sense, external interrupt requests occur when the input____ signal to the INTi pin changes its level. This is independent of clock φ1. In the edge sense, the interrupt request bit is set to “1” at this time. (2) There are two methods: one uses external interrupt’s level sense, and the other uses the timer’s event counter mode. À Method using external interrupt’s level sense As for hardware, input a logical sum of multiple interrupt signals (e.g., ‘a’, ‘b’, and ‘c’) to the____ INTi pin, and input each signal to each corresponding port.___ As for software, check the ports’ input levels in the INTi interrupt routine in order to detect which signal (‘a’, ‘b’, or ‘c’) was input. A (1) ____ Which timing of clock φ1 is the external interrupts (input signals to the INTi pin) detected? (2) ____ How can four or more external interrupt input pins (INTi) be used? \` Method using timer’s event counter mode As for hardware, input interrupt signals to the TAiIN pins or TBiIN pins. As for software, set the timer’s operating mode to the event counter mode. Then, set a value “000016” into the timer register and select the valid edge. The timer’s interrupt request occurs when an interrupt signal (selected valid edge) is input. a M37721 Port Port Port INTib c

Appendix 9. 7721 Group Q & A

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What are there the stack bank select bit (bit 7 at address 5E16) for? Q Stack, DRAM A It is supposed that DRAM is used as the stack area. When connecting DRAM, the stack pointer addressing mode or stack operation instruction etc. can be used. It is because all of 64 Kbytes can be used as the stack area when bank FF16 which is assigned to DRAM is set as the stack area. (The internal RAM also functions as the temporary area or the register file which is accessed frequently because the internal RAM can be accessed with no Wait. Accordingly, it is expected that the capacity will lack to be used as the stack area. As for the M37721, DRAM area can be set as the stack area because cheap DRAM can be connected.) Use bank 0 which is assigned to the internal RAM area as the stack area when DRAM is not connected or the internal RAM is sufficient to be used as the stack area.

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Appendix 9. 7721 Group Q & A Are there methods to refresh DRAM in the wait mode? Q DRAM, WIT instruction

Appendix 9. 7721 Group Q & A

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A In the wait mode, DRAM refresh function does not operate, but the watchdog timer, timer A, and timer B operate. Accordingly, DRAM can be refreshed by using these timers and ports. (1) Method using watchdog timer Return from the wait mode by the watchdog timer interrupt. Control ports P104, P105 by____ ____ software and perform the CAS-before-RAS- refresh. Example 1: A case in 1024 refresh cycles, every 16.4 ms, f(XIN) = 16 MHz, watchdog timer count source = f32

DRAM refresh is performed 256 times. This refresh is performed by every watchdog timer interrupt. (See flow chart À .) Interval of watchdog timer interrupt f(XIN)

16 MHz

2.621 ms 4.096 ms f 512 selected 41.943 ms 65.536 ms (1/2) DRAM validity bit (bit 7 at address 6416) Bits 4, 5 of port P10 register (address 16 16) ← “1” WIT instruction Wait mode completed ? N Y Wait mode DRAMC stopped Watchdog timer count source: f 32 selected Ports P104, P105: “H” level output Note: By using 1 bit of RAM, judge whether this interrupt is for return from the wait mode or for refresh. 256 times ? N Y RTI Return to main routine ← “1” Bits 4, 5 of port P10 direction register (address 1816) ← “1” ← “0” Watchdog timer frequency select bit (bit 0 at address 6116) Main routine Flow chart À Watchdog timer interrupt routine ← “0”Bit 4 of port P10 register (address 1616) ← “0”Bit 5 of port P10 register (address 1616) ← “1”Bit 4 of port P10 register (address 1616) ← “1”Bit 5 of port P10 register (address 1616) Port P105 (RAS) “H” level output Port P104 (CAS): “H” level output Port P105 (RAS): “L” level output Port P104 (CAS): “L” level output Port P105 (RAS): “H” level output

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Appendix 9. 7721 Group Q & A DRAM, WIT instruction A (2) Method using timer A or timer B Return from the wait mode by a timer A ( or timer B) interrupt every definite time. Control____ ____ ports P104, P105 by software and perform the CAS-before-RAS-refresh. Example 2: A case in 512 refresh cycles, every 64 ms, f(XIN) = 25 MHz, timer A0 used

DRAM refresh is performed 512 times by timer A0 interrupts. This interrupt occurs every 64 ms. (See flow chart \ .) (2/2) N Y N Y Flow chart \ Main routine ← “1”Bits 4, 5 of port P10 direction register (address 1816) ← “1”Bits 4, 5 of port P10 register (address 1616) DRAM validity bit (bit 7 at address 6416) ← “0” Timer A0 mode register (address 56 16) ← “110000002” Timer A0 register (addresses 47 16, 4616) ← 3124 Timer A0 interrupt control register (address 75 16) ← “XXXX00012” Timer A0 count start bit (bit 0 at address 40 16) ← “1” Interrupt enable flag I← “0” WIT instruction Wait mode completed ? Wait mode Timer A0 interrupt routine ← “0”Bit 4 of port P10 register (address 16 16) ← “0”Bit 5 of port P10 register (address 1616) ← “1”Bit 4 of port P10 register (address 16 16) ← “1”Bit 5 of port P10 register (address 1616) 512 times ? RTI Return to main routine Port P105 (RAS): “H” level output Port P104 (CAS): “H” level output Port P105 (RAS): “L” level output Port P104 (CAS): “L” level output Ports P104, P105: “H” level output DRAMC stopped f512 counted Timer value set: One cycle = 64 ms Interrupt priority level set: Level 1 or more (Interrupt enabled) Timer A0 count started Interrupt enabled Note: By using 1 bit of RAM, judge whether this interrupt is for return from the wait mode or for refresh.

Appendix 9. 7721 Group Q & A

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How is the program execution time affected when using DRAM ? Q A (1/2) Rate occupied by DRAM refresh cycle during program execution time Rate occupied by DRAM refresh cycle f(XIN) = 25 MHz 2.6 % 0.3 % f(XIN) = 16 MHz 4.2 % 0.5 % Refresh interval 15.625 µs (Case of 512 refresh cycles, every 8 ms) 125 µs (Case of 512 refresh cycles, every 64 ms) When the M37721 uses DRAM, the execution time is affected as follows:

CPU stops and DRAM refresh cycle is inserted.
1-bus cycle becomes 3 φ when accessing DRAM. (1) Refresh method of the M37721’s DRAMC is the dispersion refresh and 5 cycles of φ are necessary for one refresh. The rate occupied by the DRAM refresh cycle during the program execution time is described below. (2) The comparison results of two sample programs’ execution times are listed below; one is for the case where SRAM is used and the other is for the case where DRAM is used. Use conditions : Execution program Sample program B (See (2/2)) f(XIN) 16 MHz External data bus width 16 bits Refresh interval 13 µs Memory used as work area SRAM SRAM DRAM (bank FF 16) DRAM (bank FF 16) Software wait valid area Nothing ROM and RAM Nothing ROM Speed comparison 1.00 1.47 1.15 1.53 Execution time 3.4 ms 5.0 ms 3.9 ms 5.2 ms

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Appendix 9. 7721 Group Q & A DRAM A (2/2) l Sample program B SEP X CLM .DATA 16 .INDEX 8 LDY #69 LOOP0: LDX #69 LOOP1: ASL SOUR, X SEM .DATA 8 ROL SOUR+2, X ROL B CLM .DATA 16 ROR A DEX DEX DEX BNE LOOP1 STA A, DEST, Y SEM .DATA 8 STA B, DEST+2, Y CLM .DATA 16 DEY DEY DEY BNE LOOP0 ] SOUR, DEST : Work areas

Appendix 9. 7721 Group Q & A

7721 Group User’s Manual17–78

When detecting the software runaway by the watchdog timer, if the same value as the contents of the reset vector address is set to the watchdog timer interrupt vector address, not performing software reset, how does it result in? When branching to the reset branch address within the watchdog timer interrupt routine, how does it result in? A The CPU registers and the SFR are not initialized in the above-mentioned way. Accordingly, the user must initialize all of them by software. Note that the processor interrupt priority level (IPL) retains “7” of the watchdog timer interrupt priority level and is not initialized. Consequently, all interrupt requests cannot be accepted. When rewriting the IPL by software, save once the 16-bit immediate value to the stack area and then restore that 16-bit immediate value to all bits of the processor status register (PS). When a software runaway occurs, we recommend to use software reset in order to initialize the microcomputer. Q

7721 Group User’s Manual 17–79

Appendix 10. Differences between 7721 Group and 7720 Group Appendix 10. Differences between 7721 Group and 7720 Group Table 2 Differences between M37721S2BFP and M37720S1AFP M37720S1AFP 512 bytes

16 MHz (maximum)

Exists (LDM , STA instructions cannot be used.) One of the following:

When setting the receive enable bit to “0”
When setting the serial I/O mode select bits to “000
When reading the receive buffer register When all of the following are satisfied:
Receive enable bit = “1”
Reception is stopped.

8 Mbytes/sec

1024 bytes (Note) 4 bits 5 2 channels, or 6 bits 5 1channel and 2 bits 5 1channel Retains the value before using real-time output Nothing (LDM , STA instructions can be used.) One of the following:

When setting the receive enable bit to “0”
When setting the serial I/O mode select bits to “000 When all of the following are satisfied:
Receive enable bit = “1”
Reception is stopped.
Dummy data is present in the transmit buffer register

12.5 Mbytes/sec

External clock input frequency Instruction execution time (minimum) Bit configuration of real–time output channel Port latch state after using real-time output Limitation for instruction used when writing to interrupt control register Timing when overrun error flag becomes “0” ____ Conditions for outputting “L” of RTS signal in clock synchronous serial I/O mode DMA shortest transfer rate (At 1-bus cycle transfer)Serial I/O Note: 512 bytes can be selected by software. For the M37721S1BFP, its internal RAM size is 512 bytes.

7721 Group User’s Manual17–80

Appendix 11. Electrical characteristics Appendix 11. Electrical characteristics The electrical characteristics of the M37721S2BFP are described below. For the latest data, inquire of addresses described last (+ “CONTACT ADDRESSES FOR FURTHER INFORMATION”) . Absolute maximum ratings Conditions Ta = 25 °C Ratings –0.3 to 7 –0.3 to 7 –0.3 to 12 –0.3 to VCC +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 Unit V V V V V mW RESET , CNV SS , BYTE A 8/D8–A 15/D15, A16/D0–A 23/D7, P4 3–P4 7, P50–P5 7, P60–P6 7, P7 0–P7 7, P80–P8 7, P90–P9 7, P10 0–P10 7, RDY, HOLD, X IN, VREF A 0/MA 0–A 7/MA 7, A8/D8–A 15/D15, A 16/D0–A 23/D7, P43–P4 7, P5 0–P5 7, P60–P6 7, P70–P7 7, P80–P8 7, P90–P9 7, P100–P10 7, φ1, RESET OUT , XOUT , E, ST0, ST1, ALE, BLE, BHE, R/W Parameter Power source voltage Analog power source voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Symbol V CC AV CC V I V I V O P d Topr Tstg

7721 Group User’s Manual 17–81

Appendix 11. Electrical characteristics APPENDIX Recommended operating conditions (VCC = 5 V ± 10 %, Ta = –20 to 85 °C, unless otherwise noted) V V V V V V V V mA mA mA mA MHz Vcc AVcc Vss AVss V IH V IH V IL V IL IOH (peak) IOH (avg) IOL (peak) IOL (avg) f(XIN) Unit LimitsParameterSymbol Min. Max.Typ. 5.5 Vcc Vcc

0.2 Vcc

0.16 Vcc

–10 5.0 Vcc 4.5

0.8 Vcc

0.5 Vcc

Analog power source voltage Power source voltage Analog power source voltage High-level input voltage High-level input voltage Low-level input voltage Low-level input voltage High-level peak output current High-level average output current Low-level peak output current Low-level average output current External clock input frequency HOLD, BYTE, CNVss, RESET, XIN, VREF A 8/D8–A 15/D15, A16/D0–A 23/D7 HOLD, BYTE, CNVSS, RESET, X IN, V REF A 8/D8–A 15/D15, A16/D0–A 23/D7 A 0/MA 0–A 7/MA 7, A8/D8–A 15/D15, A 16/D0–A 23/D7, P43–P4 7, P50–P5 7, ST0, ST1, ALE, BLE, BHE, R/W A 0/MA 0–A 7/MA 7, A8/D8–A 15/D15, A 16/D0–A 23/D7, P43–P4 7, P50–P5 7, ST0, ST1, ALE, BLE, BHE, R/W A 0/MA 0–A 7/MA 7, A8/D8–A 15/D15, A 16/D0–A 23/D7, P43–P4 7, P50–P5 7, ST0, ST1, ALE, BLE, BHE, R/W A 0/MA 0–A 7/MA 7, A8/D8–A 15/D15, A 16/D0–A 23/D7, P43–P4 7, P50–P5 7, ST0, ST1, ALE, BLE, BHE, R/W Notes 1: Average output current is the average value of a 100 ms interval. ____ 2: The sum of IOL(peak) for P8, P9, A0/MA 0–A 7/MA 7, A8/D8–A 15/D15, A16/D0–A 23/D7, ST0, ST1, ALE, BLE,____ __ BHE, and R/W must be 80 mA or less; the sum of IOH(peak) for P8, P9, A0/MA 0–A 7/MA 7, A8/D8–____ ____ __ A 15/D15, A16/D0–A 23/D7, ST0, ST1, ALE, BLE, BHE, and R/W must be 80 mA or less; the sum of IOL(peak) for P4, P5, P6, P7, P10, and φ1 must be 80 mA or less; the sum of IOH(peak) for P4, P5, P6, P7, P10, and φ1 must be 80 mA or less.

7721 Group User’s Manual17–82

Appendix 11. Electrical characteristics High-level output voltage High-level output voltage High-level output voltage High-level output voltage Low-level output voltage Low-level output voltage Low-level output voltage Low-level output voltage Hysteresis Hysteresis Hysteresis High-level input current Low-level input current RAM hold voltage Power source current

Electrical characteristics

(VCC = 5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Symbol Parameter Test conditions Unit 0.45 1.9 0.43 1.6 0.4 0.5 0.3 Limits Min. Typ. Max. V OH V OH V OH V OH V OL V OL V OL V OL VT+–VT– VT+–VT– VT+–VT– IIH IIL V RAM Icc A0/MA 0–A 7/MA 7, A8/D8–A15/D15, A16/D0–A23/D7, P43– ST1, ALE, BLE, BHE, R/W MA 9, RAS, CAS, φ1, ST0, ST1, BLE, BHE, R/W ALE E A 0/MA 0–A 7/MA 7, A8/D8–A 15/D15, A 16/D0–A 23/D7, P43–P4 7, P50–P5 7, P60–P6 7, RESET OUT , ST0, ST1, ALE, BLE, BHE, R/W A16/D0–A23/D7, MA8, MA9, RAS, CAS, φ1, ST0, ST1,____ ____ __ BLE, BHE, R/W ALE E DMAREQ0–DMAREQ3, TC RESET X IN A 8/D8–A 15/D15, A16/D0–A 23/D7, P43–P4 7, P50–P5 7, P90–P9 7, P100–P10 7, RDY, HOLD, BYTE, CNVss,______ XIN, RESET A 8/D8–A 15/D15, A16/D0–A 23/D7, P43–P4 7, P50–P5 7, RDY, HOLD, BYTE, CNVss, X IN, RESET IOH = –10 mA IOH = –400 µA IOH = –10 mA IOH = –400 µA IOH = –10 mA IOH = –400 µA IOL = 10 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA V I = 5 V V I = 0 V When clock is stopped. f(XIN) = 25 MHz (Square waveform) Ta = 25 °C (when clock is stopped) Ta = 85 °C (when clock is stopped) 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 V V V V V V V V V V V µA µA V mA µA µA A-D CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) UnitTest conditions V REF = VCC V REF = VCC V REF = VCC Bits LSB kΩ µs V V Symbol R LADDER tCONV V REF V IA Parameter Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage Min. 9.12 Max. V CC V REF Typ. Limits

7721 Group User’s Manual 17–83

Appendix 11. Electrical characteristics APPENDIX Internal peripheral devices’ timing requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Note: The limits depend on f(XIN). Table 3 lists calculation formulas for the limits. Limits tc(TA) tw(TAH) tw(TAL) TAjIN input cycle time TAjIN input high-level pulse width TAjIN input low-level pulse width Max.Parameter Timer A input (Count input in event counter mode) Timer A input (Gating input in timer mode) tc(TA) tw(TAH) tw(TAL) TAjIN input cycle time TAjIN input high-level pulse width TAjIN input low-level pulse width Symbol Parameter (Note) (Note) (Note) Symbol Min. Unit Limits Min. 320 160 160 Max. Unit Timer A input (External trigger input in one-shot pulse mode) tc(TA) tw(TAH) tw(TAL) TAjIN input cycle time TAjIN input high-level pulse width TAjIN input low-level pulse width Symbol Parameter (Note) Limits Min. 160 Max. Unit ns ns ns tw(TAH) tw(TAL) TAjIN input high-level pulse width TAjIN input low-level pulse width Symbol Parameter Limits Min. Max. Unit Timer A input (External trigger input in pulse width modulation mode) ns ns ns ns ns ns ns ns Timer A input (Up-down input in event counter mode) tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAjOUT input cycle time TAjOUT input high-level pulse width TAjOUT input low-level pulse width TAjOUT input setup time TAjOUT input hold time Symbol Parameter Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns Timer A input (Two-phase pulse input in event counter mode) tc(TA) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) TAjIN input cycle time TAjIN input setup time TAjOUT input setup time Symbol Parameter Limits Min. 800 200 200 Max. Unit ns ns ns

7721 Group User’s Manual17–84

Appendix 11. Electrical characteristics TAjIN input tc(TA) tw(TAH) tw(TAL) TAjOUT input (Up-down input) tc(UP) tw(UPH) tw(UPL) th(TIN-UP) tsu(UP-TIN) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN)

Up-down input and count input in event counter mode tc(TA) Internal peripheral devices
Count input in event counter mode
Gating input in timer mode
External trigger input in one-shot pulse mode
External trigger input in pulse width modulation mode TAj OUT input (Up-down input) TAjIN input (When counted at falling edge) TAjIN input (When counted at rising edge)
Two-phase pulse input in event counter mode TAjIN input TAjOUT input Test conditions
Vcc = 5 V ± 10 %
Input timing voltage : V IL = 1.0 V, VIH = 4.0 V

7721 Group User’s Manual 17–85

Appendix 11. Electrical characteristics APPENDIX Limits tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) TBjIN input cycle time (one edge count) TBjIN input high-level pulse width (one edge count) TBjIN input low-level pulse width (one edge count) TBjIN input cycle time (both edges count) TBjIN input high-level pulse width (both edges count) TBjIN input low-level pulse width (both edges count) Max.Parameter Timer B input (Count input in event counter mode) Symbol Min. 160 Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) tc(TB) tw(TBH) tw(TBL) TBjIN input cycle time TBjIN input high-level pulse width TBjIN input low-level pulse width Symbol Parameter (Note) (Note) (Note) Limits Min. 320 160 160 Max. Unit ns ns ns tc(TB) tw(TBH) tw(TBL) TBjIN input cycle time TBjIN input high-level pulse width TBjIN input low-level pulse width Symbol Parameter (Note) (Note) (Note) Limits Min. 320 160 160 Max. Unit ns ns ns Timer B input (Pulse width measurement mode) A-D trigger input tc(AD) tw(ADL) AD TRG input cycle time (trigger enabled minimum) AD TRG input low-level pulse width Symbol Parameter Limits Min. 1000 125 Max. Unit ns ns Serial I/O tc(CK) tw(CKH) tw(CKL) td(C–Q) th(C–Q) tsu(D–C) th(C–D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Symbol Parameter Limits Min. 200 100 100 Max. Unit ns ns ns ns ns ns ns ____ External interrupt INTi input tw(INH) tw(INL) ____ INTi input high-level pulse width ____ INTi input low-level pulse width Symbol Parameter Limits Min. 250 250 Max. Unit ns ns

7721 Group User’s Manual17–86

Appendix 11. Electrical characteristics TBjIN input tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) AD TRG input tw(INL) tw(INH) INTi input tc(CK) tw(CKH) tw(CKL) th(C-Q) tsu(D-C) CLK i input TxD i output RxD i input td(C-Q) th(C-D) Internal peripheral devices Test conditions

Vcc = 5 V ± 10 %
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V

7721 Group User’s Manual 17–87

Appendix 11. Electrical characteristics APPENDIX Ready and Hold Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Limits Unit ST0, ST1 output delay time Min. Max. 40 ns Note: Figure 13 shows the test circuit. td(φ1–STi) ns ns ns ns UnitParameter ____ RDY input setup time_____ HOLD input setup time____ HOLD input hold time Symbol tsu(RDY– φ1) tsu(HOLD– φ1) th(φ1–RDY) th(φ1–HOLD) Min. Limits Max. Symbol Parameter

7721 Group User’s Manual17–88

Appendix 11. Electrical characteristics With no Wait With Wait RDY input E output E output RDY input tsu(RDY- 1) th( 1-RDY) tsu(RDY- 1) th( 1-RDY)

Ready function Test conditions
Vcc = 5 V ± 10 %
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V HOLD input STi output th( 1-HOLD) td( 1-STi) tsu(HOLD- 1) td( 1-STi)
Hold function Test conditions
Vcc = 5 V ± 10 %
Input timing voltage : V IL = 1.0 V, VIH = 4.0 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V

17–89 Appendix 11. Electrical characteristics APPENDIX Microprocessor mode : with no Wait Note: The limits depend on f(X IN ). Table 4 lists calculation formulas for the limits. Limits t c t w(H) t w(L) t r t f t su(PiD–E) t h(E–PiD) External clock input cycle time External clock input high-level pulse width External clock input low-level pulse width External clock input rising time External clock input falling time Port Pi input setup time (i = 4–10) Port Pi input hold time (i = 4–10) Max. Parameter Timing requirements (V CC = 5 V ± 10 %, V SS = 0 V, Ta = –20 to 85 °C, f(X IN ) = 25 MHz, unless otherwise noted) Symbol Min. Unit ns ns ns ns ns ns ns Limits t d(E-PiQ) t d(AL–E) t d(E–DHQ) t pxz(E–DHZ) t d(AM–E) t d(AM–ALE) t d(E–DLQ) t pxz(E–DLZ) t d(AH–E) t d(AH–ALE) t d(ALE–E) t w(ALE) t d(BHE–E) t d(BLE–E) t d(R/W–E) t d(E– φ t h(E–AL) t h(ALE–AM) t h(E–DHQ) t pzx(E–DHZ) t h(E–AM) t h(ALE–AH) t h(E–DLQ) t pzx(E–DLZ) t h(E–BHE) t h(E–BLE) t h(E–R/W) t w(EL) t su(A–DL) t su(ALE–DL) t su(A–DH) t su(ALE–DH) Port Pi data output delay time (i = 4–10) Address low-order output delay time Data high-order output delay time (BYTE = “L”) Data high-order floating start delay time (BYTE = “L”) Address middle-order output delay time Address middle-order output delay time Data low-order output delay time Data low-order floating start delay time Address high-order output delay time Address high-order output delay time ALE output delay time ALE pulse width ____ BHE output delay time ____ BLE output delay time R/W output delay time φ output delay time Address low-order hold time Address middle-order hold time (BYTE = “L”) Data high-order hold time (BYTE = “L”) Data high-order floating release delay time (BYTE = “L”) Address middle-order hold time (BYTE = “H”) Address high-order hold time Data low-order hold time Data low-order floating release delay time ____ BHE hold time ____ BLE hold time R/W hold time E pulse width Data low-order setup time after address stabilization Data low-order setup time after rising of ALE Data high-order setup time after address stabilization Data high-order setup time after rising of ALE Max. Parameter Switching characteristics (V CC = 5 V ± 10 %, V SS = 0 V, Ta = –20 to 85 °C, f(X IN ) = 25 MHz, unless otherwise noted) Symbol Min. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: Figure 13 shows the test circuit. (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note)

7721 Group User’s Manual17–90

Appendix 11. Electrical characteristics <Write> Microprocessor mode : with no Wait f(XIN) Address output A0–A7 Port Pi output (i = 4–10) E Address/Data output A16/D0–A23/D7 ALE output R/W output td(AM-E) td(AM-E) tw(L) tw(H) tr tf tc tw(EL) td(E- 1)td(E- 1) td(AL-E) td(E-DHQ) Address Address td(E-DLQ)td(AH-E) DataAddress Address th(ALE-AM)td(AM-ALE) th(ALE-AH)td(AH-ALE) td(BHE-E) td(ALE-E) tw(ALE) td(BLE-E) td(R/W-E) th(E-BHE) th(E-R/W) td(E-PiQ) th(E-AL) th(E-AM) th(E-DHQ) th(E-DLQ) th(E-BLE) Data Address output A8–A15 (BYTE = “H”) Address/Data output A8/D8–A15/D15 (BYTE = “L”) Data input D 0–D 15 (BYTE = “L”) Data input D 0–D 7 BHE output BLE output Test conditions (port Pi)

Vcc = 5 V ± 10 %
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Test conditions (except port Pi)
Vcc = 5 V ± 10 %
Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
Data input : VIL = 0.8 V, VIH = 2.5 V

7721 Group User’s Manual 17–91

Appendix 11. Electrical characteristics APPENDIX td(AM-ALE) td(AM-E) td(AM-E) tw(L) tw(H) tr tf tc tw(EL) td(E- 1)td(E- 1) td(AL-E) tpxz(E-DHZ) Address Address Address Address th(ALE-AM) td(BHE-E) td(ALE-E)tw(ALE) td(E-PiQ) th(E-AL) th(E-AM) tpzx(E-DHZ) tpzx(E-DLZ) th(E-BLE)td(BLE-E) td(R/W-E) tsu(PiD-E) th(E-R/W) Data Data th(E-DH) tsu(DH-E)tsu(A-DH) tsu(ALE-DH) tpxz(E-DLZ) td(AH-ALE) th(ALE-AH) th(E-DL) tsu(DL-E)tsu(A-DL) tsu(ALE-DL) th(E-BHE) td(AH-E) <Read> Microprocessor mode : with no Wait f(XIN) Address output A0–A7 Port Pi input (i = 4–10) E Address/Data output A16/D0–A23/D7 ALE output R/W output Address output A8–A15 (BYTE = “H”) Address/Data output A8/D8–A15/D15 (BYTE = “L”) Data input D 8–D 15 (BYTE = “L”) Data input D 0–D 7 BHE output BLE output Test conditions (port Pi)

Vcc = 5 V ± 10 %
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Test conditions (except port Pi)
Vcc = 5 V ± 10 %
Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
Data input : VIL = 0.8 V, VIH = 2.5 V

7721 Group User’s Manual17–92

Appendix 11. Electrical characteristics Microprocessor mode : with Wait Note: The limits depend on f(XIN). Table 4 lists calculation formulas for the limits. Limits tc tw(H) tw(L) tr tf tsu(PiD–E) th(E–PiD) External clock input cycle time External clock input high-level pulse width External clock input low-level pulse width External clock input rising time External clock input falling time Port Pi input setup time (i = 4–10) Port Pi input hold time (i = 4–10) Max.Parameter Timing requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Symbol Min. Unit ns ns ns ns ns ns ns Limits Max.Parameter Switching characteristics (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Symbol Min. 135 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 130 135 130 135 Note: Figure 13 shows the test circuit. (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) t d(E-PiQ) td(AL–E) td(E–DHQ) tpxz(E–DHZ) td(AM–E) td(AM–ALE) td(E–DLQ) tpxz(E–DLZ) td(AH–E) td(AH–ALE) td(ALE–E) tw(ALE) td(BHE–E) td(BLE–E) td(R/W–E) td(E–φ1) th(E–AL) th(ALE–AM) th(E–DHQ) tpzx(E–DHZ) th(E–AM) th(ALE–AH) th(E–DLQ) tpzx(E–DLZ) th(E–BHE) th(E–BLE) th(E–R/W) tw(EL) tsu(A–DL) tsu(ALE–DL) tsu(A–DH) tsu(ALE–DH) Port Pi data output delay time Address low-order output delay time Data high-order output delay time (BYTE = “L”) Data high-order floating start delay time (BYTE = “L”) Address middle-order output delay time Address middle-order output delay time Data low-order output delay time Data low-order floating start delay time Address high-order output delay time Address high-order output delay time ALE output delay time ALE pulse width ____ BHE output delay time ____ BLE output delay time R/W output delay time φ1 output delay time Address low-order hold time Address middle-order hold time (BYTE = “L”) Data high-order hold time (BYTE = “L”) Data high-order floating release delay time (BYTE = “L”) Address middle-order hold time (BYTE = “H”) Address high-order hold time Data low-order hold time Data low-order floating release delay time ____ BHE hold time ____ BLE hold time__ R/W hold time__ E pulse width Data low-order setup time after address stabilization Data low-order setup time after rising of ALE Data high-order setup time after address stabilization Data high-order setup time after rising of ALE

7721 Group User’s Manual 17–93

Appendix 11. Electrical characteristics APPENDIX td(AM-E) td(AM-E) tw(L) tw(H) tr tf tc tw(EL) td(E- 1)td(E- 1) td(AL-E) td(E-DHQ) Address td(E-DLQ)td(AH-E) Address th(ALE-AM)td(AM-ALE) th(ALE-AH)td(AH-ALE) th(E-BHE)td(BHE-E) td(ALE-E) tw(ALE) th(E-R/W) td(E-PiQ) th(E-AL) th(E-AM) th(E-DHQ) th(E-DLQ) th(E-BLE)td(BLE-E) td(R/W-E) Data <Write> Microprocessor mode : with Wait f(XIN) Address output A0–A7 Port Pi output (i = 4–10) E Address/Data output A16/D0–A23/D7 ALE output R/W output Address output A8–A15 (BYTE = “H”) Address/Data output A8/D8–A15/D15 (BYTE = “L”) Data input D 0–D 15 (BYTE = “L”) Data input D 0–D 7 BHE output BLE output Test conditions (port Pi)

Vcc = 5 V ± 10 %
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Test conditions (except port Pi)
Vcc = 5 V ± 10 %
Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
Data input : VIL = 0.8 V, VIH = 2.5 V Address Address Data

7721 Group User’s Manual17–94

Appendix 11. Electrical characteristics tsu(ALE-DH) td(AM-ALE) td(AM-E) td(AM-E) tw(L) tw(H) tr tf tc tw(EL) td(E- 1)td(E- 1) td(AL-E) tpxz(E-DHZ) Address Address Address th(ALE-AM) td(BHE-E) td(ALE-E)tw(ALE) td(E-PiQ) th(E-AL) th(E-AM) tpzx(E-DHZ) tpzx(E-DLZ) th(E-BLE)td(BLE-E) td(R/W-E) tsu(PiD-E) th(E-R/W) Data Data th(E-DH) tsu(DH-E)tsu(A-DH) tpxz(E-DLZ) td(AH-ALE) th(ALE-AH) th(E-DL) tsu(DL-E)tsu(A-DL) tsu(ALE-DL) th(E-BHE) td(AH-E) <Read> Microprocessor mode : with Wait f(XIN) Address output A0–A7 Port Pi input (i = 4–10) E Address/Data output A16/D0–A23/D7 ALE output R/W output Address output A8–A15 (BYTE = “H”) Address/Data output A8/D8–A15/D15 (BYTE = “L”) Data input D 8–D 15 (BYTE = “L”) Data input D 0–D 7 BHE output BLE output Test conditions (port Pi)

Vcc = 5 V ± 10 %
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Test conditions (except port Pi)
Vcc = 5 V ± 10 %
Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
Data input : VIL = 0.8 V, VIH = 2.5 V Address

7721 Group User’s Manual 17–95

Appendix 11. Electrical characteristics APPENDIX DRAM control switching characteristics (VCC = 5 V ± 10 %, V SS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Note: The limits depend on f(XIN). Table 5 lists calculation formulas for the limits. Limits tw(RASL) tw(CASL) tw(RASH) td(RAS–CAS) td(RA–RAS) th(RAS–RA) td(CA–CAS) th(CAS–CA) td(R/W–RAS) th(CAS–R/W) td(E–CA) td(E–RASL) td(E–CASL) td(E–RASH) td(E–CASH) ____ RAS low–level pulse width ____ CAS low–level pulse width____ RAS–CAS delay time ____ Row address delay time before RAS ____ Row address hold time after RAS ____ Column address delay time before CAS____ Column address hold time after CAS R/W delay time before RAS R/W hold time after CAS __ Column address delay time after E’s low level RAS delay time after E’s low level____ __ CAS delay time after E’s low level____ __ RAS delay time after E’s high level CAS delay time after E’s high level Max.Parameter Read Symbol Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: Figure 13 shows the test circuit. Limits tw(RASL) tw(CASL) tw(RASH) td(RAS–CAS) td(RA–RAS) th(RAS–RA) td(CA–CAS) th(CAS–CA) td(R/W–RAS) th(CAS–R/W) td(E–RASL) td(E–CASL) td(E–RASH) td(E–CASH) ____ RAS low–level pulse width ____ CAS low–level pulse width____ CAS high–level pulse width Row address delay time before RAS ____ Row address hold time after RAS____ Column address delay time before CAS____ Column address hold time afrer CAS R/W delay time before RAS R/W hold time after CAS____ __ RAS delay time after E’s low level____ __ CAS delay time after E’s low level____ __ RAS delay time after E’s high level CAS delay time after E’s high level Max.Parameter Write Symbol Min. 120 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 115 Note: Figure 13 shows the test circuit. Limits tw(RASL) tw(CASL) td(CAS–RAS) th(RAS–CAS) ____ RAS low–level pulse width ____ CAS hold time after RAS Max.Parameter Refresh state Symbol Min. 120 17.5 17.5 Unit ns ns ns ns (Note) (Note) (Note) (Note) Note: Figure 13 shows the test circuit. 77.5 Min. 120 92.5 100

7721 Group User’s Manual17–96

Appendix 11. Electrical characteristics R/W output tw(RASH) Row address td(RAS-CAS) td(RA-RAS) td(R/W-RAS) tw(RASL) td(E-RASH) th(CAS-R/W)td(E-CASH) tw(CASL) th(CAS-CA) td(E-CA) td(CA-CAS) th(RAS-RA) td(E-RASL) td(E-CASL) MA 0–MA 9 output At read tw(RASH) Column addressRow address td(RAS-CAS) td(RA-RAS) td(R/W-RAS) tw(RASL) td(E-RASH) th(CAS-R/W)td(E-CASH) tw(CASL) th(CAS-CA)td(CA-CAS) th(RAS-RA) td(E-RASL) td(E-CASL) tw(RASL) td(CAS-RAS)At refreshing th(RAS-CAS) tw(CASL) At DRAM control E At write CAS output RAS output R/W output MA 0–MA 9 output CAS output RAS output CAS output RAS output Column address Test conditions

Vcc = 5 V ± 10 %
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
D0–D 15 input : VIL = 0.8 V, VIH = 2.5 V

7721 Group User’s Manual 17–97

Appendix 11. Electrical characteristics APPENDIX DMAC switching characteristics (VCC = 5 V ±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Note: The limits depend on f(XIN). Table 6 lists calculation formulas for the limits. Limits tsu(DRQ- φ1) tw(DRQ) td(φ1–STi) td(φ1–DAK) td(AL–E) td(E–DHQ) tpxz(E–DHZ) td(AM–E) td(E–DLQ) tpxz(E–DLZ) td(AH–E) td(ALE–E) tw(ALE) td(BHE–E) td(BLE–E) td(R/W–E) th(E–AL) th(ALE–AM) th(E–DHQ) tpzx(E–DHZ) th(E–AM) th(ALE–AH) th(E–DLQ) tpzx(E–DLZ) th(E–BHE) th(E–BLE) th(E–R/W) tw(EL) td(data) td(φ1–TC) tw(TC) tsu(TCIN) tw(TC IN) DMAREQi input setup time DMAREQi input pulse width DMAACKi output delay time Address low-order output delay time Data high-order output delay time (BYTE = “L”) Data high-order floating start delay time (BYTE = “L”) Address middle-order output delay time Data low-order output delay time Data low-order floating start delay time Address high-order output delay time ALE output delay time ALE pulse width____ BHE output delay time ____ BLE output delay time R/W output delay time Address low-order hold time Address middle-order hold time (BYTE = “L”) Data high-order hold time (BYTE = “L”) Data high-order floating release delay time (BYTE = “L”) Address middle-order hold time (BYTE = “H”) Address high-order hold time Data low-order hold time Data low-order floating release delay time ____ BHE hold time ____ BLE hold time__ R/W hold time__ E pulse width Copy delay time ___ TC output delay time___ TC output pulse width ___ TC input setup time ___ TC input pulse width Max.ParameterSymbol Min. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) Note: Figures 13 and 14 show the test circuits.

7721 Group User’s Manual17–98

Appendix 11. Electrical characteristics Test conditions

Vcc = 5 V ± 10 %
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
D0–D 15 input : VIL = 0.8 V, VIH = 2.5 V
DMAREQi input : VIL = 0.8 V, VIH = 2.5 V At DMA transfer
Burst transfer timing (External source DMAREQi) tw(EL) tsu(DRQ- 1) Address Data Ad- dress tw(DRQ) td( 1-STi) td( 1-DAK) td(AL-E) th(E-AL) td(AM-E) th(E-AM) th(ALE-AM) td(E-DHQ) td(E-DLQ) td(ALE-E)tw(ALE) td(BHE-E) td(BLE-E) td(R/W-E) td(AH-E) th(ALE-AH) th(E-BHE) th(E-BLE) th(E-R/W) BHE output E ALE output R/W output DMAREQi ST0 DMAACKi A 0–A7 output A8/D8–A15/D15 output (BYTE = “L”) A8/D8–A15/D15 output (BYTE = “H”) A16/D0–A23/D7 output BLE output Address Address Address Address Address Address Address Data Address Address Address Address Address Address Address Address Data Data Ad- dress Ad- dress Ad- dress

7721 Group User’s Manual 17–99

Appendix 11. Electrical characteristics APPENDIX tw(EL) tsu(DRQ- 1) Address Data Ad- dress tw(DRQ) td( 1-STi) td( 1-DAK) td(AL-E) th(E-AL) td(AM-E) th(E-AM) td(ALE-E)tw(ALE) td(BHE-E) td(BLE-E) td(R/W-E) td(AH-E) th(E-BHE) th(E-BLE) td( 1-DAK) td( 1-STi) At DMA transfer

Cycle-steal transfer timing (External source DMAREQi) BHE output E ALE output R/W output ST0 A0–A7 output A8/D8–A15/D15 output (BYTE = “L”) A8/D8–A15/D15 output (BYTE = “H”) A16/D0–A23/D7 output BLE output Test conditions
Vcc = 5 V ± 10 %
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
D0–D 15 input : VIL = 0.8 V, VIH = 2.5 V
DMAREQi input : VIL = 0.8 V, VIH = 2.5 V DMAREQi DMAACKi Address Address Address Address Address Address Address Address Address Address Address Address Data AddressAddress Address Ad- dress Ad- dress Ad- dress

7721 Group User’s Manual17–100

Appendix 11. Electrical characteristics Address tpzx(E-DHZ) th(E-AL) th(E-DH) td(ALE-E)tw(ALE) td(BHE-E) td(BLE-E) td(R/W-E) td( 1-DAK) td( 1-DAK) td(AL-E) tpxz(E-DHZ) tsu(DH-E) Data th(E-BHE) th(E-BLE) th(E-R/W) td(data) tpzx(E-DLZ) th(E-AL) td(ALE-E)tw(ALE) td(BHE-E) td(BLE-E) td(R/W-E) td( 1-DAK) td( 1-DAK) td(AL-E) th(E-BHE) th(E-BLE) th(E-R/W) tpxz(E-DLZ) th(E-DL)tsu(DL-E) td(data) At DMA transfer

1-bus transfer timing BHE output E ALE output R/W output A0–A7 output A8/D8–A15/D15 output (BYTE = “L”) A16/D0–A23/D7 output BLE output Test conditions
Vcc = 5 V ± 10 %
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
D0–D 15 input : VIL = 0.8 V, VIH = 2.5 V DMAACKi D 0–D 15 input D 0–D 7 output Ad- dress Address Data Ad- dress Ad- dress Ad- dress

7721 Group User’s Manual 17–101

Appendix 11. Electrical characteristics APPENDIX td(BLE-E) tw(TC) Address td( 1-DAK) th(E-AL) td(AL-E) th(E-BHE) th(E-BLE) th(E-R/W) td(BHE-E) td( 1-STi) th(E-AM) td(AM-E) td( 1-TC) Data th(E-DHQ) th(E-DLQ) td(AH-E) td(R/W-E) At DMA transfer

Transfer complete timing BHE output E ALE output R/W output A0–A7 output A8/D8–A15/D15 output (BYTE = “L”) A16/D0–A23/D7 output BLE output Test conditions
Vcc = 5 V ± 10 %
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
D0–D 15 input : VIL = 0.8 V, VIH = 2.5 V DMAACKi TC ST0 A8/D8–A15/D15 output (BYTE = “H”) Address Address Address Address Address Address Address Address Address Address Address Data Data Data Ad- dress Ad- dress Ad- dress Ad- dress

7721 Group User’s Manual17–102

Appendix 11. Electrical characteristics Destination address Source address Address Data td( 1-STi) td(AL-E) td(AM-E) th(ALE-AM) td(E-DHQ) td(E-DLQ) td(ALE-E)tw(ALE) td(R/W-E) td(AH-E) th(ALE-AH) th(E-R/W) tsu(TCIN) td( 1-DAK) tw(TC IN) th(E-AL) th(E-AM) When DMA transfer is forcedly completed by TC input

TC input timing E ALE output R/W output A0–A7 output A8/D8–A15/D15 output (BYTE = “L”) A16/D0–A23/D7 output Test conditions
Vcc = 5 V ± 10 %
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
D0–D 15 input : VIL = 0.8 V, VIH = 2.5 V
TC input : VIL = 0.8 V, VIH = 2.5 V DMAACKi TC input ST0 A8/D8–A15/D15 output (BYTE = “H”) Destination address Destination address Destination address Address Address AddressData Data Data Source address Destination address Source address Destination address Source address

7721 Group User’s Manual 17–103

Appendix 11. Electrical characteristics APPENDIX Table 3 Calculation formulas for internal peripheral devices’ input/output timing depending on f(XIN) (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C) Timer A input (Gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) Calculation formula Unit ns ns ns4 5 109 f(XIN) 4 5 109 f(XIN) 8 5 109 f(XIN) Symbol tc(TA) Unit ns4 5 109 f(XIN) Timer A input (External trigger input in one-shot pulse mode) Timer B input (Pulse period measurement mode) Timer B input (Pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) Unit ns ns ns4 5 109 f(XIN) 4 5 109 f(XIN) 8 5 109 f(XIN) Symbol tc(TB) tw(TBH) tw(TBL) Unit ns ns ns4 5 109 f(XIN) 4 5 109 f(XIN) 8 5 109 f(XIN) Calculation formula Calculation formula Calculation formula

7721 Group User’s Manual17–104

Appendix 11. Electrical characteristics td(AL–E) td(AM–E) td(AH–E) td(AM–ALE) td(AH–ALE) tw(ALE) td(BLE–E) td(BHE–E) td(R/W–E) th(E–AL) th(E–AM) th(E–DLQ) th(E–DHQ) tpzx(E–DLZ) tpzx(E–DHZ) th(E–BLE) th(E–BHE) th(E–R/W) tw(EL) tsu(A–DL) tsu(A–DH) tsu(ALE–DL) tsu(ALE–DH) Table 4 Calculation formulas for bus timing depending on f(XIN) (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C) Wait bit = “1” Wait bit = “0” Wait bit = “1” Wait bit = “0” Wait bit = “1” Wait bit = “0” Symbol Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 2 5 109 f(XIN) 4 5 109 f(XIN) 3 5 109 f(XIN) 5 5 109 f(XIN) 3 5 109 f(XIN) 5 5 109 f(XIN) – 25 – 35 – 18 – 20 – 22 – 22 – 20 – 22 – 25 – 65 – 70 – 25 – 70 – 65 Calculation formula

7721 Group User’s Manual 17–105

Appendix 11. Electrical characteristics APPENDIX Table 5 Calculation formulas for DRAM control bus timing depending of f(XIN) (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C) Read Symbol tw(RASL) tw(CASL) tw(RASH) td(RAS–CAS) td(RA–RAS) th(RAS–RA) Calculation formula Unit ns ns ns ns ns ns 3 5 109 f(XIN) 4 5 109 f(XIN) 2 5 109 f(XIN) – 40 – 27.5 – 20 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) – 12 – 22 – 35 Unit ns ns ns ns ns 1 5 109 f(XIN) 4 5 109 f(XIN) 1 5 109 f(XIN) – 60 – 22 – 22 1 5 109 f(XIN) + 25 Symbol th(CAS–CA) td(R/W–RAS) th(CAS–R/W) td(E–CA) td(E–CASL) Calculation formula 1 5 109 f(XIN) + 37.5 Write Symbol tw(RASL) tw(CASL) tw(RASH) td(RAS–CAS) td(RA–RAS) th(RAS–RA) Unit ns ns ns ns ns ns 2 5 109 f(XIN) 4 5 109 f(XIN) 2 5 109 f(XIN) – 40 – 25 – 20 1 5 109 f(XIN) 2 5 109 f(XIN) 1 5 109 f(XIN) – 20 – 22 – 35 Unit ns ns ns ns ns 3 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) – 30 – 60 – 22 1 5 109 f(XIN) – 22 Symbol td(CA–CAS) th(CAS–CA) td(R/W–RAS) th(CAS–R/W) td(E–CASL) Calculation formula 2 5 109 f(XIN) + 35(0)] ] The value within ( ) is for the minimum value. Refresh Symbol tw(RASL) tw(CASL) Unit ns ns 2 5 109 f(XIN) 4 5 109 f(XIN) – 40 Unit ns ns1 5 109 f(XIN) 1 5 109 f(XIN) Symbol td(CAS–RAS) th(RAS–CAS) Calculation formula – 25 Calculation formula Calculation formula – 22.5 – 22.5

7721 Group User’s Manual17–106

Appendix 11. Electrical characteristics Fig. 13 Test circuit for each pin ___ Fig. 14 Test circuit for TC output delay time and___ TC output pulse width A0/MA0–A7/MA7 A8/D8–A15/D15 A16/D0–A23/D7 P10 E 100 pF 100 pF TC 3 kΩ Table 6 Calculation formulas for DMA transfer bus timing depending on f(XIN) (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C) td(AL–E) td(AM–E) td(AH–E) tw(ALE) td(BLE–E) td(BHE–E) td(R/W–E) th(E–AL) th(E–AM) th(E–DLQ) th(E–DHQ) tpzx(E–DLZ) tpzx(E–DHZ) th(E–BLE) th(E–BHE) th(E–R/W) tw(EL) tw(TC) Symbol Unit 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 1 5 109 f(XIN) 2 5 109 f(XIN) 4 5 109 f(XIN) 2 5 109 f(XIN) – 25 – 18 – 20 – 22 – 22 – 25 – 22 – 20 – 25 – 30 ns ns ns ns ns ns ns ns ns ns f(XIN) 1 5 109 Transfer source/Transfer destination wait bit = “1” Transfer source/Transfer destination wait bit = “0” Calculation formula

7721 Group User’s Manual 17–107

Appendix 12. Standard characteristics Appendix 12. Standard characteristics Standard characteristics described below are just examples of the M37721S2BFP’s characteristics and are not guaranteed. For each parameter’s limits, refer to section “Appendix 11. Electrical characteristics.” 1. Programmable I/O port (CMOS output) standard characteristics (1) P-channel IOH –V OH characteristics (2) N-channel IOL –V OL characteristics 30.0 24.0 18.0 12.0 6.0 VOL [V] IOL [mA] Ta = 25 °C Ta = 85 °C 30.0 24.0 18.0 12.0 6.0 VOH [V] IOH [mA] Ta = 25 °C Ta = 85 °C

Appendix 12. Standard characteristics

7721 Group User’s Manual17–108

Icc–f(XIN) standard characteristics (1) Icc–f(XIN) characteristics on operating and at reset (2) Wait mode 0 5 10 15 20 25 30 f(X IN) [MHz] Icc [mA] Measurement condition (Vcc = 5.0 V, Ta = 25 °C, f(XIN) : square waveform, microprocessor mode) At reset On operating 0 5 10 15 20 25 30 f(XIN) [MHz] Icc [mA] Measurement condition (Vcc = 5.0 V, Ta = 25 °C, f(XIN) : square waveform, microprocessor mode)

7721 Group User’s Manual 17–109

Appendix 12. Standard characteristics 3. A-D converter standard characteristics The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in output code from 0 to 1 should occur at 10 mV, but the measured value is +2 mV. Accordingly, the measured point of change is 10 + 2 = 12 mV. The upper lines of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is 15 is 24 mV, so that the differential non-linear error is 24 – 20 = 4 mV (0.2 LSB). [Measurement conditions]

Vcc = 5 V, V REF = 5.12 V, f(XIN) = 25 MHz, Ta = 25 °C, φAD = f2 divided by 2 1LSB WIDTH ERROR [mV][mV] STEP No. –10 –20 –30 8 1 62 43 24 04 85 66 47 28 08 89 6 1 0 4 1 1 2 1 2 0 1 2 8 128 1LSB WIDTH ERROR STEP No. –10 –20 –30 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 [mV] [mV]

Appendix 12. Standard characteristics

7721 Group User’s Manual17–110

7721 Group User’s Manual2

This section briefly explains the terms used in this user’s manual. The terms defined here apply to this manual only. Term Access Access space Access characteristics Branch Bus control signal Countdown Count source Countup External area External bus External device Internal area Interrupt routine Overflow Read-modify-write instruction Signal required for access to external device Stop mode UART Underflow Wait mode Meaning Means performing read, write, or read and write. In DRAMC, also means performing DRAM refresh. An accessible memory space of up to 16 Mbytes. Means whether accessible or not. Means moving the program’s execution point (= address) to another location. A generic name for ALE, E , R/W , BLE , BHE , RDY , HOLD , HLDA, BYTE, ST0, and ST1 signals. Means decreasing by 1 and counting. A signal that is counted by timers A and B, the UARTi baud rate register (BRGi) and the watchdog timer. That is f 2, f16, f64, f512 selected by the count source select bits and others. Means increasing by 1 and counting. An accessible area for external devices connected. It is up to 16- Mbyte external area. A generic name for the external address bus and the external data bus. Devices connected externally to the microcomputer. A generic name for a memory, an I/O device and a peripheral IC. An accessible internal area. A generic name for areas of the internal RAM and the SFR. A routine that is automatically executed when an interrupt request is accepted. Set the start address of this routine into the interrupt vector table. A state where the countup resultant is greater than the counter resolution. An instruction that reads the memory contents, modifies them and writes back to the same address. Relevant instructions are the ASL , ASR , CLB , DEC , INC , LSR , ROL , ROR , SEB instructions. A generic name for bus control, address bus, and data bus signals. A state where the oscillation circuit halts and the program execution is stopped. By executing the STP instruction, the microcomputer enters the stop mode. Clock asynchronous serial I/O. When used to designate the name of a functional block, this term also means the serial I/O which can be switched to the cock synchronous serial I/O. A state where the countdown resultant is greater than the counter resolution. A state where the oscillation circuit is operating, however, the program execution is stopped. By executing the WIT instruction, the microcomputer enters the wait mode. Relevant term Access Access Countup Countdown Internal area External area Underflow Countup Bus control signal Wait mode Clock synchronous serial I/O Overflow Countdown Stop mode

USER’S MANUAL Sep. First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1997 MITSUBISHI ELECTRIC CORPORATION

Product Information

7721 specifications and overview.

Summary

16-BIT SINGLE-CHIP MICROCOMPUTER

Description

16-BIT SINGLE-CHIP MICROCOMPUTER

Source title 7721 Datasheet(PDF) - Renesas Technology Corp

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