7702

7702 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER

7700 FAMILY / 7700 SERIES

User’s Manual

Keep safety first in your circuit designs ! l Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials l These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. l Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. l Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. l If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. l Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

This manual describes the hardware of the Mitsubishi CMOS 16-bit microcomputers 7702 Group and 7703 Group. After reading this manual, the user will be able to understand the functions, so that they can utilize their capabilities fully. For details concerning the software, refer to the 7700 Family Software Manual. Preface

1. Constitution This user’s manual consists of the following chapters. Refer to the chapters relevant to used products and the processor mode. l Chapter 1. DESCRIPTION to Chapter 17. APPLICATION Functions which are common to all products and all processor modes are explained, using the M37702M2BXXXFP as an example. When there are functional differences between the low voltage version, PROM version and the 7703 Group, the referential section is indicated. Refer to that section about differences and to “Chapter. 1 to Chapter. 17” about the common functions. l Chapter 18. LOW VOLTAGE VERSION Refer to this chapter when using the products of which difference of electrical characteristics identification code (see on page 1–2) is “L,” the M37702M2 LXXXGP for example. This chapter mainly explains the differences from the M37702M2BXXXFP, using the M37702M2LXXXGP as an example. l Chapter 19. PROM VERSION Refer to this chapter when using the products of which memory identification code (see on page 1– 2) is “E,” the M37702 E2BXXXFP for example. This chapter mainly explains the differences from the M37702M2BXXXFP, using the M37702E2BXXXFP as an example. l Chapter 20. 7703 GROUP Refer to this chapter when using the 7703 Group. This chapter mainly explains the differences from the 7702 Group, using the M37703M2BXXXSP as an example. l Appendix Useful information for 7702 and 7703 Groups usage is shown. 2. Remark l 25 MHz version and 16 MHz version The 25 MHz version products are distinguished from the 16 MHz version products in part of Chapters as the case may be. Refer to it as follows:

• Products of which difference of electrical characteristics identification code is “B,” M37702M2 BXXXFP
• Products of which difference of electrical characteristics identification code is “A,” M37702M2AXXXFP l Product expansion See the latest data book and data sheets. Additionally, ask the contact addresses on the last page. l Electrical characteristics See also the latest data book or data sheet. l Development support tools See the latest data book and data sheet. l Software See “7700 Family Software Manual.”

l Mask ROM Confirmation Form, PROM Confirmation Form, Mark Specification Form Copy the form in the latest data book and use it. Or, ask the contact addresses on the last page. 3. Register structure The view of the register structure is described below: XXX register (Address XX16) b1 b0b2b3b4b5b6b7 ]2 ]3 1 : ... 1 : ... The value is “0” at reading. 0 : ... 1 : ... Fix this bit to “0.” 7 to 5Nothing is assigned. RW WO RO RW RW Bit Bit name This bit is ignored in ... mode. Functions At reset RW ... flag Undefined Undefined Blank 5 : This bit is not used in the specific mode or state. It may be either “0” or “1.” : Nothing is assigned. Undefined RW data. RO invalid. Accordingly, the written value may be either “0” or “1.” WO The value is undefined at reading. However, the bit with the commentaries of “ The value is “0” at reading” in the functions column or the notes is always “0” at reading.(See to ]4 above.) It is no possible to read the bit state. The value is undefined at reading. However, the bit with the commentaries of “The value is “0” at reading” in the functions column or the notes is always “0” at reading.(See to ]4 above.) The written value becomes invalid. Accordingly, the written value may be “0” or “1.” : Set to “0” or “1” to meet the purpose. : Set to “0” at writing. : Set to “1” at writing. : “0” immediately after a reset. : “1” immediately after a reset. :Undefined immediately after a reset. : It is possible to read the bit state at reading. The written value becomes valid It is possible to read the bit state at reading. The written value becomes: : The written value becomes valid data. It is not possible to read the bit state. — :

i7702/7703 Group User’s Manual Table of Contents CHAPTER 1. DESCRIPTION CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) CHAPTER 3. INPUT/OUTPUT PINS CHAPTER 4. INTERRUPTS

ii 7702/7703 Group User’s Manual CHAPTER 5. TIMER A CHAPTER 6. TIMER B

iii7702/7703 Group User’s Manual CHAPTER 7. SERIAL I/O

7.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers 7-14

CHAPTER 8. A-D CONVERTER

iv 7702/7703 Group User’s Manual CHAPTER 9. WATCHDOG TIMER CHAPTER 10. STOP MODE CHAPTER 11. WAIT MODE CHAPTER 12. CONNECTION WITH EXTERNAL DEVICES

v7702/7703 Group User’s Manual CHAPTER 13. RESET CHAPTER 14. CLOCK GENERATING CIRCUIT CHAPTER 15. ELECTRICAL CHARACTERISTICS CHAPTER 16. STANDARD CHARACTERISTICS CHAPTER 17. APPLICATIONS 17.2.2 Comparison software Wait (f(XIN) = 20 MHz) with software Wait + Ready (f(XIN) = 25 MHz) ..17-31 CHAPTER 18. LOW VOLTAGE VERSION

vi 7702/7703 Group User’s Manual CHAPTER 19. PROM VERSION CHAPTER 20. 7703 GROUP

vii7702/7703 Group User’s Manual APPENDIX GLOSSARY

viii 7702/7703 Group User’s Manual MEMORANDUM

DESCRIPTION

1.1 Performance overview

1.2 Pin configuration

1.3 Pin description

1.4 Block diagram

7702/7703 Group User’s Manual1–2 The 16-bit single-chip microcomputers 7702 Group and 7703 Group are suitable for office, business, and industrial equipment controllers that require high-speed processing of large amounts of data. These microcomputers develop with the M37702M2BXXXFP as the base chip. This manual describes the functions about the M37702M2BXXXFP unless there is a specific difference and refers to the M37702M2BXXXXFP as “M37702.” Notes 1: About details concerning each microcomputer’s development status of the 7702/7703 Group, inquire of “CONTACT ADDRESSES FOR FURTHER INFORMATION” described last. Notes 2: How the 7702/7703 Group’s type name see is described below. M 3 77 02 M 2 B XXX FP Mitsubishi integrated prefix Represent an original single-chip microcomputer Series designation using 2 digits Circuit function identification code using 2 digits Memory identification code using a digit M: Mask ROM E: EPROM S: External ROM Memory size identification code using a digit Difference of electrical characteristics identification code using a digit Mask ROM number Package style FP: Plastic molded QFP GP: Plastic molded QFP HP: Plastic molded fine-pitch QFP SP: Plastic molded SDIP FS: Ceramic QFN

7702/7703 Group User’s Manual 1–3 160 ns (the minimum instruction at f(XIN) = 25 MHz) 250 ns (the minimum instruction at f(XIN) = 16 MHz)

25 MHz (maximum)

16 MHz (maximum)

(UART or clock synchronous serial I/O) 5 2 8-bit successive approximation method 5 1 (8 channels) 12 bits 5 1 3 external, 16 internal (priority levels 0 to 7 can be set for each interrupt with software) Built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator)

5 V ±10 %

60 mW (at f(X IN) = 16 MHz frequency, typ.) 5 V 5 mA Maximum 16 Mbytes –20°C to 85°C CMOS high-performance silicon gate process 80-pin plastic molded QFP Parameters Number of basic instructions Instruction execution time External clock input frequency f(XIN) Memory size Programmable Input/Output ports Multifunction timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation Port Input/Output characteristics Memory expansion Operating temperature range Device structure M37702M2BXXXFP M37702M2AXXXFP M37702M2BXXXFP M37702M2AXXXFP ROM RAM P0–P2, P4–P8 TA0–TA4 TB0–TB2 UART0, UART1 Notes 1: All of the 7702 Group microcomputers are the same except for the package type, memory type, memory size, and electric characteristics. 2: For the low voltage version, refer to “Chapter 18. LOW VOLTAGE VERSION.” Table 1.1.1 shows the performance overview of the M37702.

7703 Group

Refer to “Chapter 20. 7703 GROUP. ” Table 1.1.1 M37702 performance overview Input/Output withstand voltage Output current Package

7702/7703 Group User’s Manual1–4 pin configuration. Note: For the low voltage version of the 7702 Group, refer to “Chapter 18. LOW VOLTAGE VERSION.” Refer to “Chapter 20. 7703 GROUP.” Fig. 1.2.1 M37702M2BXXXFP pin configuration (top view) 25 2726 28 34 29 30 31 32 33 35 36 37 38 39 40 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TAIN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 0/HOLDBYTECNV SS RESET X IN X OUT E V ss 3/HLDA 2/ALE 1/BHE 0/R/W 7/A 6/A 5/A 4/A 4/AN 5/AN 6/AN 7/AN 7/AD TRG V SS AV SS V REF AV CC V CC 0/CTS 0/RTS 1/CLK 2/R XD 3/T XD P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 80 79 78 77 76 75 74 73 72 71 69 68 67 66 6570 Outline 80P6N-A P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 P22/A18/D2 P23/A19/D3 M37702M2BXXXFP P41/RDY P47 P46 P45 P44 P43 P42/ 1 1/AN 2/AN 3/AN

7702/7703 Group User’s Manual 1–5 E CNV SS RESET 0/HOLD Outline 80P6D-A P86/RxD 1 P87/TxD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 75 74 73 72 71 69 68 67 66 657080 79 78 77 76 64 63 62 61 3026 27 28 29 31 32 33 34 35 3621 2322 24 25 37 38 39 40 1/RDY BYTE X IN V SS 0/R/W 7/A 6/A 5/A 4/A 3/A 2/A P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 5/CLK 4/CTS 1/RTS 3/T XD 2/R XD 1/CLK 0/CTS 0/RTS V CC AV CC V REF AV SS V SS 6/AN 5/AN 4/AN 3/AN 2/AN 1/AN 0/AN 7/TB2 IN M37702M2BXXXHP P43 P44 P45 P46 7/AN 7/AD TRG ] : The M37702M2BXXXHP have the pin configuration shifted to 2 pins assignment from the M37702M2BXXXFP. ] ] Fig. 1.2.2 M37702M2BXXXHP pin configuration (top view)

7702/7703 Group User’s Manual1–6 in PROM version is described to section “19.2 EPROM mode.” The 7703 Group does not have part of pins. Refer to “Chapter 20. 7703 GROUP.” Table 1.3.1 Pin description (1) Supply 5 V ±10 %] to Vcc pin and 0 V to Vss pin. This pin controls the processor mode. [Single-chip mode] [Memory expansion mode] Connect to Vss pin. [Microprocessor mode] Connect to Vcc pin. The microcomputer is reset when supplying “L” level to this pin. These are I/O pins of the internal clock generating circuit. Connect a ceramic resonator or quartz-crystal oscillator between pins X IN and XOUT . When using an external clock, the clock source should be input to XIN pin and XOUT pin should be left open. This pin outputs E signal. Data/instruction code read or data write is performed when output from this pin is “L” level. [Single-chip mode] Connect to Vss. [Memory expansion mode] [Microprocessor mode] Input level to this pin determines whether the external data bus has a 16-bit width or 8-bit width. The width is 16 bits when the level is “L”, and 8 bits when the level is “H”. The power supply pin for the A-D converter. Externally connect AVcc to Vcc pin. The power supply pin for the A-D converter. Externally connect AVss to Vss pin. This is a reference voltage input pin for the A-D converter. Pin Vcc, Vss CNVss RESET X IN X OUT E BYTE AVcc AVss V REF Input/Output Input Input Input Output Output Input Input ] : In the low voltage version, supply 2.7–5.5V to Vcc. Name Power supply CNVss Reset input Clock input Clock output Enable output Bus width selection input Analog supply Reference voltage input

7702/7703 Group User’s Manual 1–7 Table 1.3.2 Pin description (2) [Single-chip mode] Port P0 is an 8-bit CMOS I/O port. This port has an I/O direction register and each pin can be programmed for input or output. [Memory expansion mode] [Microprocessor mode] Low-order 8 bits (A 0–A7) of the address are output. [Single-chip mode] Port P1 is an 8-bit I/O port with the same function as P0. [Memory expansion mode] [Microprocessor mode] l External bus width = 8 bits (When the BYTE pin is “H” level) Middle-order 8 bits (A 8–A15) of the address are output. l External bus width = 16 bits (When the BYTE pin is “L” level) Data (D8 to D15) input/output and output of the middle- order 8 bits (A8–A 15) of the address are performed with the time sharing system. [Single-chip mode] Port P2 is an 8-bit I/O port with the same function as P0. [Memory expansion mode] [Microprocessor mode] Data (D 0 to D7) input/output and output of the high- order 8 bits (A16–A 23) of the address are performed with the time sharing system. [Single-chip mode] Port P3 is a 4-bit I/O port with the same function as P0. [Memory expansion mode] [Microprocessor mode] P30–P3 3 respectively output R/W, BHE, ALE, and HLDA signals. l R/W The Read/Write signal indicates the data bus state. The state is read while this signal is “H” level, and write while this signal is “L” level. ____ l BHE “L” level is output when an odd-numbered address is accessed. l ALE This is used to obtain only the address from address and data multiplex signals. l HLDA This is the signal to externally indicate the state when the microcomputer is in Hold state. “L” level is output during Hold state. Input/Output I/O Output I/O I/O I/O Output Pin P00–P0 7 A 0–A 7 P10–P1 7 A 8/D8– A 15/D15 P20–P2 7 A 16/D0– A 23/D7 P30–P3 3] R/W, ____ BHE, ALE, HLDA ] \\ : The 7703 Group does not have the P33/HLDA pin. Name I/O port P0 I/O port P1 I/O port P2 I/O port P3

7702/7703 Group User’s Manual1–8 Table 1.3.3 Pin description (3) Pin P4 0–P4 7\\ HOLD, ____ RDY, P4 2–P4 7\\ HOLD, ____ RDY, φ1, P4 3–P4 7\\ P5 0–P5 7 P6 0–P6 7\\ P7 0–P7 7\\ P8 0–P8 7\\ Functions [Single-chip mode] Port P4 is an 8-bit I/O port with the same function as P0. P4 2 can be programmed as the clock φ1 output pin. [Memory expansion mode] P4 0 functions as the HOLD input pin, P41 as the RDY input pin. The microcomputer is in Hold state while “L” level is input to the HOLD pin. The microcomputer is in Ready state while “L” level is ____ input to the RDY pin. P4 2–P4 7 function as I/O ports with the same functions as P0. 2 can be programmed for the clock φ1 output pin. [Microprocessor mode] P4 0 functions as the HOLD input pin, P41 as the RDY input pin. P42 always functions as the clock φ1 output pin. P4 3–P4 7 function as I/O ports with the same functions as P0. Port P5 is an 8-bit I/O port with the same function as P0. These pins can be programmed as I/O pins for Timers A0–A3. Port P6 is an 8-bit I/O port with the same function as P0. These pins can be programmed as I/O pins for Timer A4, input pins for external interrupt and input pins for Timers B0–B2. Port P7 is an 8-bit I/O port with the same function as P0. These pins can be programmed as input pins for A-D converter. Port P8 is an 8-bit I/O port with the same function as P0. These pins can be programmed as I/O pins for Serial I/O. Name I/O port P4 I/O port P5 I/O port P6 I/O port P7 I/O port P8 \\ : The 7703 Group does not have the P43–P4 6, P60, P61, P66, P67, P73–P7 6, P84, and P85 pins. Input/Output I/O Input Input I/O Input Input Output I/O I/O I/O I/O I/O

7702/7703 Group User’s Manual 1–9

1.3.1 Example for processing unused pins

Examples for processing unused pins are described below. These descriptions are just examples. The user shall modify them according to the user’s actual application and test them. (1) In single-chip mode Table 1.3.4 Example for processing unused pins in single-chip mode Example of processing Set for input mode and connect these pins to Vcc or Vss via a resistor; or set for output mode and leave these pins open. (Notes 1, 3) Leave it open. Connect this pin to Vcc. Connect these pins to Vss. Pin name Ports P0 to P8 E X OUT (Note 2) AVcc AVss, V REF , BYTE Notes 1: When setting these ports to the output mode and leave them open, they remain set to the input mode until they are switched to the output mode by software after reset. While ports remain set to the input mode, consequently, voltage levels of pins are unstable, and a power source current can increase. The contents of the direction register can be changed by noise or a program runaway generated by noise. To improve its reliability, we recommend to periodically set the contents of the direction register by software. When processing unused pins, use the possible shortest wiring (within 20 mm from the microcomputer). 2: This applies when a clock externally generated is input to the X IN pin. 3: In the 7703 Group, the following ports does not have the corresponding pins and have only the direction registers. Fix the bit of these direction registers to “1” (output mode).

• Ports P33, P43–P4 6, P60, P61, P66, P67, P73–P7 6, P84, P85 P0–P8 AV SS VREF BYTE M37702 VSS AV CC E XOUT VCC P0–P8 AV SS VREF M37702 VSS AV CC E XOUT VCC Left open l When setting ports for input mode l When setting ports for output mode Left open Left open BYTE Fig. 1.3.1 Example for processing unused pins in single-chip mode

7702/7703 Group User’s Manual1–10 (2) In memory expansion mode Table 1.3.5 Example for processing unused pins in memory expansion mode Pin name Ports P42 to P47, P5 to P8 ____ BHE ( Note 2) ALE (Note 3) HLDA ( Note 6) X OUT (Note 5) HOLD, RDY (Note 8) AVcc AVss, VREF Example of processing Set for input mode and connect these pins to Vcc or Vss via a resistor; or set for output mode and leave these pins open. (Notes 1, 6, 7) Leave them open. (Note 4) Leave it open. Connect these pins to Vcc via a resistor (pull-up). Connect this pin to Vcc. Connect these pins to Vss. Notes 1: When setting these ports to the output mode and leave them open, they remain set to the input mode until they are switched to the output mode by software after reset. While ports remain set to the input mode, consequently, voltage levels of pins are unstable, and a power source current can increase. The contents of the direction register can be changed by noise or a program runaway generated by noise. To improve its reliability, we recommend to periodically set the contents of the direction register by software. When processing unused pins, use the possible shortest wiring (within 20 mm from the microcomputer). 2: This applies when “H” level is input to the BYTE pin. 3: This applies when “H” level is input to the BYTE pin and the access space is 64 Kbytes. 4: When supplying Vss level to the CNVss pin, these pins remain set to the input mode until they are switched to the output mode by software after reset. While pins remain set to the input mode, consequently, voltage levels of pins are unstable, and a power source current can increase. 5: This applies when a clock externally generated is input to the X IN pin. 6: In the 7703 Group, the following ports does not have the corresponding pins and have only the direction registers. Fix the bit of these direction registers to “1” (output mode).

• Ports P43–P4 6, P60, P61, P66, P67, P73–P7 6, P84, P85 There is not the HLDA pin. 7: Set the P42/φ1 pin to the P42 function (clock φ1 output disabled), and perform the same processing as ports P43–P4 7, P5–P8. 8: When processing unused pins, use the possible shortest wiring (within 20 mm from the microcomputer). P42–P47, P5–P8 AV SS VREF HOLD RDY M37702 VCC VSS AV CC XOUT BHE ALE HLDA P42–P47, P5–P8 AV SS VREF HOLD RDY VSS AV CC XOUT BHE ALE HLDA VCC M37702 Left open l When setting ports for input mode l When setting ports for output mode Left open Left open Left open Left open Fig. 1.3.2 Example for processing unused pins in memory expansion mode

7702/7703 Group User’s Manual 1–11 (3) In microprocessor mode Table 1.3.6 Example for processing unused pins in microprocessor mode Example of processing Set for input mode and connect these pins to Vcc or Vss via a resistor; or set for output mode and leave these pins open. (Notes 1, 6) Leave it open. (Note 4) Leave it open. Connect these pins to Vcc via a resistor (pull-up). Connect this pin to Vcc. Connect these pins to Vss. Pin name Ports P43 to P47, P5 to P8 ____ BHE ( Note 2) ALE (Note 3) HLDA, φ1 (Note 6) X OUT (Note 5) HOLD, RDY ( Note 7) AVcc AVss, VREF Notes 1: When setting these ports to the output mode and leave them open, they remain set to the input mode until they are switched to the output mode by software after reset. While ports remain set to the input mode, consequently, voltage levels of pins are unstable, and a power source current can increase. The contents of the direction register can be changed by noise or a program runaway generated by noise. To improve its reliability, we recommend to periodically set the contents of the direction register by software. When processing unused pins, use the possible shortest wiring (within 20 mm from the microcomputer). 2: This applies when “H” level is input to the BYTE pin. 3: This applies when “H” level is input to the BYTE pin and the access space is 64 Kbytes. 4: When supplying Vss level to the CNVss pin, these pins remain set to the input mode until they are switched to the output mode by software after reset. While pins remain set to the input mode, consequently, voltage levels of pins are unstable, and a power source current can increase. 5: This applies when a clock externally generated is input to the X IN pin. 6: In the 7703 Group, the following ports does not have the corresponding pins and have only the direction registers. Fix the bit of these direction registers to “1” (output mode).

• Ports P43–P4 6, P60, P61, P66, P67, P73–P7 6, P84, P85 There is not the HLDA pin. 7: When processing unused pins, use the possible shortest wiring (within 20 mm from the microcomputer). Fig. 1.3.3 Example for processing unused pins in microprocessor mode P43–P47, P5–P8 AV SS VREF HOLD RDY M37702 VCC VSS AV CC XOUT BHE ALE HLDA P43–P47, P5–P8 AV SS VREF HOLD RDY VSS AV CC XOUT BHE ALE HLDA VCC M37702 l When setting ports for input mode l When setting ports for output mode Left open Left open Left open Left open Left open

7702/7703 Group User’s Manual1–12 Figure 1.4.1 shows the M37702 block diagram. Fig. 1.4.1 M37702 block diagram Clock input Clock outputEnable output XIN XOUT E Reset input RESET Reference voltage input VREF Clock Generating Circuit Data Buffer DBH (8) Data Buffer DBL(8) Instruction Queue Buffer Q0(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q2(8) Data Bank Register DT(8) Program Counter PC(16) Incrementer/Decrementer(24) Program Bank Register PG(8) Input Buffer Register IB(16) Direct Page Register DPR(16) Stack Pointer S(16) Index Register Y(16) Index Register X(16) Arithmetic Logic Unit(16) Accumulator B(16) Accumulator A(16) Instruction Register(8) Data Bus(Even) Data Bus(Odd) Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P3 Input/Output port P4 P2(8) Input/Output port P2 P1(8) Input/Output port P0 Watchdog Timer CNVss BYTE External data bus width selection input Timer TB1(16) Timer TB2(16) P0(8) Input/Output port P1 Timer TB0(16) Timer TA1(16) Timer TA2(16) Timer TA3(16) Timer TA4(16) Timer TA0(16) ROM

16 Kbytes

512 bytes UART1(9) UART0(9) AV SS (0V) AV CC Central Processing Unit (CPU) Incrementer(24) Program Address Register PA(24) Data Address Register DA(24) Address Bus Bus Interface Unit (BIU) (0V) VSSVCC Processor Status Register PS(11) A-D Converter(8) Note: The 7703 Group does not have the P33, P43–P46, P60, P61, P66, P67, P73–P76, P84, and P85 pins.

(CPU)

2.1 Central processing unit

2.2 Bus interface unit

2.3 Access space

2.4 Memory assignment

2.5 Processor modes

CENTRAL PROCESSING UNIT (CPU) 2–2 7702/7703 Group User’s Manual The CPU (Central Processing Unit) has the ten registers as shown in Figure 2.1.1. Fig. 2.1.1 CPU registers structure b0b7b8b15 AH AL b0b7b8b15 BH BL b0b7b8b15 XH XL b0b7b8b15 YH YL b0b7b8b15 SH SL b0b7b8b15 b7 b0 b8b23 b16 b15 b7 b0 PC H PC LPG b0b7 DT b0b7b8b15 b0b1b2b3b4b5b6b7b8b10

00000 C ZIDxmVNIPL

Accumulator A (A) Accumulator B (B) Index register X (X) Index register Y (Y) Stack pointer (S) Data bank register (DT) Program counter (PC) Program bank register (PG) Direct page register (DPR) Processor status register (PS) Processor interrupt priority level Carry flag Zero flag Interrupt disable flag Index register length flag Decimal mode flag Data length flag Overflow flag Negative flag DPR LDPR H PS LPS H b9b15

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–3

2.1.1 Accumulator (Acc)

Accumulators A and B are available. (1) Accumulator A (A) Accumulator A is the main register of the microcomputer. The transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits, and the low-order 8 bits can also be used separately. The data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. Flag m is a part of the processor status register which is described later. When an 8-bit register is selected, only the low-order 8 bits of accumulator A are used and the contents of the high-order 8 bits is unchanged. (2) Accumulator B (B) Accumulator B is a 16-bit register with the same function as accumulator A. Accumulator B can be used instead of accumulator A. The use of accumulator B, however except for some instructions, requires more instruction bytes and execution cycles than that of accumulator A. Accumulator B is also controlled by the data length flag (m) just as in accumulator A.

2.1.2 Index register X (X)

Index register X consists of 16 bits and the low-order 8 bits can also be used separately. The index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. Flag x is a part of the processor status register which is described later. When an 8-bit register is selected, only the low-order 8 bits of index register X are used and the contents of the high-order 8 bits is unchanged. In an addressing mode in which index register X is used as an index register, the address obtained by adding the contents of this register to the operand’s contents is accessed. In the MVP or MVN instruction, a block transfer instruction, the contents of index register X indicates the low-order 16 bits of the source address. The third byte of the instruction is the high-order 8 bits of the source address. Note: Refer to “7700 Family Software Manual” for addressing modes.

2.1.3 Index register Y (Y)

Index register Y is a 16-bit register with the same function as index register X. Just as in index register X, the index register length flag (x) determines whether this register is used as a 16-bit register or as an 8-bit register. In the MVP or MVN instruction, a block transfer instruction, the contents of index register Y indicate the low-order 16 bits of the destination address. The second byte of the instruction is the high-order 8 bits of the destination address.

CENTRAL PROCESSING UNIT (CPU) 2–4 7702/7703 Group User’s Manual

2.1.4 Stack pointer (S)

The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when addressing modes using the stack are executed. The contents of S indicate an address (stack area) for storing registers during subroutine calls and interrupts. Bank 0 16 is specified for the stack area. (Refer to “2.1.6 Program bank register (PG).”) When an interrupt request is accepted, the microcomputer stores the contents of the program bank register (PG) at the address indicated by the contents of S and decrements the contents of S by 1. Then the contents of the program counter (PC) and the processor status register (PS) are stored. The contents of S after accepting an interrupt request is equal to the contents of S decremented by 5 before the accepting of the interrupt request. (Refer to Figure 2.1.2.) When completing the process in the interrupt routine and returning to the original routine, the contents of registers stored in the stack area are restored into the original registers in the reverse sequence (PS→ PC → PG) by executing the RTI instruction. The contents of S is returned to the state before accepting an interrupt request. The same operation is performed during a subroutine call, however, the contents of PS is not automatically stored. (The contents of PG may not be stored. This depends on the addressing mode.) The user should store registers other than those described above with software when the user needs them during interrupts or subroutine calls. Additionally, initialize S at the beginning of the program because its contents are undefined at reset. The stack area changes when subroutines are nested or when multiple interrupt requests are accepted. Therefore, make sure of the subroutine’s nesting depth not to destroy the necessary data. Note: Refer to “7700 Family Software Manual” for addressing modes. Fig. 2.1.2 Stored registers of the stack area l “S” is the initial address that the stack pointer (S) indicates at accepting an interrupt request. The S’s contents become “S–5” after storing the above registers. Address S–4 S–3 S–2 S–1 S Stack area S–5 Processor status register’s low-order byte (PSL) Processor status register’s high-order byte (PSH ) Program counter’s low-order byte (PCL) Program counter’s high-order byte (PCH ) Program bank register (PG)

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–5

2.1.5 Program counter (PC)

The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. The contents of the high-order program counter (PCH ) become “FF16,” and the low-order program counter (PCL) becomes “FE16” at reset. The contents of the program counter becomes the contents of the reset’s vector address (addresses FFFE16, FFFF16) immediately after reset. Figure 2.1.3 shows the program counter and the program bank register. Fig. 2.1.3 Program counter and program bank register

2.1.6 Program bank register (PG)

The program bank register is an 8-bit register. This register indicates the high-order 8 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. These 8 bits are called bank. When a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others, the contents of the program bank register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the program counter, the contents of the program bank register is automatically decremented by 1. Accordingly, there is no need to consider bank boundaries in programming, usually. In the single-chip mode, make sure to prevent the program bank register from being set to the value other than “00 16” by executing the branch instructions and others. It is because the access space of the single- chip mode is the internal area within the bank 016. This register is cleared to “0016” at reset. PC H PC L b7 b0 b15 b8 b7 b0 (b16)(b23) PG

CENTRAL PROCESSING UNIT (CPU) 2–6 7702/7703 Group User’s Manual

2.1.7 Data bank register (DT)

The data bank register is an 8-bit register. In the following addressing modes using the data bank register, the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed. Use the LDT instruction to set a value to this register. In the single-chip mode, make sure to fix this register to “00 16”. It is because the access space of the single-chip mode is the internal area within the bank 016. This register is cleared to “0016” at reset. l Addressing modes using data bank register

• Direct indirect
• Direct indexed X indirect
• Direct indirect indexed Y
• Absolute
• Absolute bit
• Absolute indexed X
• Absolute indexed Y
• Absolute bit relative
• Stack pointer relative indirect indexed Y

2.1.8 Direct page register (DPR)

The direct page register is a 16-bit register. The contents of this register indicate the direct page area which is allocated in bank 0 16 or in the space across banks 016 and 116. The following addressing modes use the direct page register. The contents of the direct page register indicate the base address (the lowest address) of the direct page area. The space which extends to 256 bytes above that address is specified as a direct page. The direct page register can contain a value from “0000 16” to “FFFF16.” When it contains a value equal to or more than “FF0116,” the direct page area spans the space across banks 016 and 116. When the contents of low-order 8 bits of the direct page register is “0016,” the number of cycles required to generate an address is 1 cycle smaller than the number when its contents are not “0016.” Accordingly, the access efficiency can be enhanced in this case. This register is cleared to “000016” at reset. Figure 2.1.4 shows a setting example of the direct page area. l Addressing modes using direct page register

• Direct
• Direct bit
• Direct indexed X
• Direct indexed Y
• Direct indirect
• Direct indexed X indirect
• Direct indirect indexed Y
• Direct indirect long
• Direct indirect long indexed Y
• Direct bit relative

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–7 Direct page area when DPR = “000016” Direct page area when DPR = “012316” (Note 1) Direct page area when DPR = “FF1016” (Note 2) Bank 016 Bank 116 016 FF16 12316 22216 FF1016 1000F16 016 FFFF 16 1000016 Notes 1 : The number of cycles required to generate an address is 1 cycle smaller when the low-order 8 bits of the DPR are “0016.” 2: The direct page area spans the space across banks 016 and 116 when the DPR is “FF0116” or more. Fig. 2.1.4 Setting example of direct page area

CENTRAL PROCESSING UNIT (CPU) 2–8 7702/7703 Group User’s Manual

2.1.9 Processor status register (PS)

The processor status register is an 11-bit register. Figure 2.1.5 shows the structure of the processor status register. Note: “0” is always read from each of bits 15–11. b15 b8 b7 b0 b1b2b3b4b5b6b14 b9b10b11b12b13 0N C ZIDxmV0 IPL 000 Processor staus register (PS) Fig. 2.1.5 Processor status register structure (1) Bit 0: Carry flag (C) It retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic operation. This flag is also affected by shift and rotate instructions. When the BCC or BCS instruction is executed, this flag’s contents determine whether the program causes a branch or not. Use the SEC or SEP instruction to set this flag to “1,” and use the CLC or CLP instruction to clear it to “0.” (2) Bit 1: Zero flag (Z) It is set to “1” when a result of an arithmetic operation or data transfer is “0,” and cleared to “0” when otherwise. When the BNE or BEQ instruction is executed, this flag’s contents determine whether the program causes a branch or not. Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” Note: This flag is invalid in the decimal mode addition (the ADC instruction). (3) Bit 2: Interrupt disable flag (I) It disables all maskable interrupts (interrupts other than watchdog timer, the BRK instruction, and zero division). Interrupts are disabled when this flag is “1.” When an interrupt request is accepted, this flag is automatically set to “1” to avoid multiple interrupts. Use the SEI or SEP instruction to set this flag to “1,” and use the CLI or CLP instruction to clear it to “0.” This flag is set to “1” at reset. (4) Bit 3: Decimal mode flag (D) It determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic is performed when this flag is “0.” When it is “1,” decimal arithmetic is performed with each word treated as two or four digits decimal (determined by the data length flag). Decimal adjust is automatically performed. Decimal operation is possible only with the ADC and SBC instructions. Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” This flag is cleared to “0” at reset. (5) Bit 4: Index register length flag (x) It determines whether each of index register X and index register Y is used as a 16-bit register or an 8-bit register. That register is used as a 16-bit register when this flag is “0,” and as an 8-bit register when it is “1.” Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” This flag is cleared to “0” at reset. Note: When transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the TXA , TYA , TXB , TYB and TXS instructions. Refer to “7700 Family Software Manual” for details.

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–9 (6) Bit 5: Data length flag (m) It determines whether to use a data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16- bit unit when this flag is “0,” and as an 8-bit unit when it is “1.” Use the SEM or SEP instruction to set this flag to “1,” and use the CLM or CLP instruction to clear it to “0.” This flag is cleared to “0” at reset. Note: When transferring data between registers which are different in bit length, the data is transferred with the length of the destination register, but except for the TXA , TYA , TXB , TYB and TXS instructions. Refer to “7700 Family Software Manual” for details. (7) Bit 6: Overflow flag (V) It is used when adding or subtracting with a word regarded as signed binary. When the data length flag (m) is “0,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range between –32768 and +32767, and cleared to “0” in all other cases. When the data length flag (m) is “1,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range between –128 and +127, and cleared to “0” in all other cases. The overflow flag is also set to “1” when a result of division exceeds the register length to be stored in the DIV instruction, a division instruction. When the BVC or BVS instruction is executed, this flag’s contents determine whether the program causes a branch or not. Use the SEP instruction to set this flag to “1,” and use the CLV or CLP instruction to clear it to “0.” Note: This flag is invalid in the decimal mode. (8) Bit 7: Negative flag (N) It is set to “1” when a result of arithmetic operation or data transfer is negative. (Bit 15 of the result is “1” when the data length flag (m) is “0,” or bit 7 of the result is “1” when the data length flag (m) is “1.”) It is cleared to “0” in all other cases. When the BPL or BMI instruction is executed, this flag determines whether the program causes a branch or not. Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” Note: This flag is invalid in the decimal mode. (9) Bits 10 to 8: Processor interrupt priority level (IPL) These three bits can determine the processor interrupt priority level to one of levels 0 to 7. The interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each interrupt control register, is higher than IPL. When an interrupt request is accepted, IPL is stored in the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request. There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the new IPL into the stack area and updating the processor status register with the PUL or PLP instruction. The contents of IPL is cleared to “000 2” at reset.

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual2–10 A bus interface unit (BIU) is built-in between the central processing unit (CPU) and memory•I/O devices. BIU’s function and operation are described below. When externally connecting devices, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”

2.2.1 Overview

Transfer operation between the CPU and memory•I/O devices is always performed via the BIU. Figure 2.2.1 shows the bus and bus interface unit (BIU). À The BIU reads an instruction from the memory before the CPU executes it. \` When the CPU reads data from the memory• I/O device, the CPU first specifies the address from which data is read to the BIU. The BIU reads data from the specified address and passes it to the CPU. ´ When the CPU writes data to the memory I/O device, the CPU first specifies the address to which data is written to the BIU and write data. The BIU writes the data to the specified address. ˆ To perform the above operations À to ´ , the BIU inputs and outputs the control signals, and control the bus.

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2–11 Fig. 2.2.1 Bus and bus interface unit (BIU) M377 Internal bus D 8 to D Central processing unit (CPU) SFR : Special Function RegisterNotes 1: The CPU bus, internal bus, and external bus are independent of one another. Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” about control signals of the external bus. Internal bus A 0 to A External device Internal control signal CPU bus Internal bus Internal bus D 0 to D Internal memory Internal peripheral device(SFR) External busA 0 to A A 0 to A Control signals Bus interface unit(BIU) A 8/D 8 to A Bus conversion circuit

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual2–12

2.2.2 Functions of bus interface unit (BIU)

of each register. Program address register Instruction queue buffer Data address register Data buffer PA DA Q 0 Q 1 Q 2 DB H DB L b23 b0 b23 b15 Table 2.2.1 Functions of each register Functions Indicates the storage address for the instruction which is next taken into the instruction queue buffer. Temporarily stores the instruction which has been taken in. Indicates the address for the data which is next read from or written to. Temporarily stores the data which is read from the memory•I/O device by the BIU or which is written to the memory•I/O device by the CPU. Name Program address register Instruction queue buffer Data address register Data buffer Fig. 2.2.2 Register structure of bus interface unit (BIU)

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2–13 The CPU and the bus send or receive data via BIU because each operates based on different clocks (Note). The BIU allows the CPU to operate at high speed without waiting for access to the memory•I/O devices that require a long access time. The BIU’s functions are described bellow. Note: The CPU operates based on φCPU . The period of φCPU is normally the same as that of the internal clock φ. The internal bus operates based on the E signal. The period of the E signal is twice that of the internal clock φ at a minimum. (1) Reading out instruction (Instruction prefetch) When the CPU does not require to read or write data, that is, when the bus is not in use, the BIU reads instructions from the memory and stores them in the instruction queue buffer. This is called instruction prefetch. The CPU reads instructions from the instruction queue buffer and executes them, so that the CPU can operate at high speed without waiting for access to the memory which requires a long access time. When the instruction queue buffer becomes empty or contains only 1 byte of an instruction, the BIU performs instruction prefetch. The instruction queue buffer can store instructions up to 3 bytes. The contents of the instruction queue buffer is initialized when a branch or jump instruction is executed, and the BIU reads a new instruction from the destination address. When instructions in the instruction queue buffer are insufficient for the CPU’s needs, the BIU extends the pulse duration of clock φCPU in order to keep the CPU waiting until the BIU fetches the required number of instructions or more. (2) Reading data from memory•I/O device The CPU specifies the storage address of data to be read to the BIU’s data address register, and requires data. The CPU waits until data is ready in the BIU. The BIU outputs the address received from the CPU onto the address bus, reads contents at the specified address, and takes it into the data buffer. The CPU continues processing, using data in the data buffer. However, if the BIU uses the bus for instruction prefetch when the CPU requires to read data, the BIU keeps the CPU waiting. (3) Writing data to memory•I/O device The CPU specifies the address of data to be written to the BIU’s data address register. Then, the CPU writes data into the data buffer. The BIU outputs the address received from the CPU onto the address bus and writes data in the data buffer into the specified address. The CPU advances to the next processing without waiting for completion of BIU’s write operation. However, if the BIU uses the bus for instruction prefetch when the CPU requires to write data, the BIU keeps the CPU waiting. (4) Bus control To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses the memory•I/O device is called the bus cycle. Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES ” about the bus cycle at accessing the external devices.

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual2–14

2.2.3 Operation of bus interface unit (BIU)

Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU). About signals which are input/output externally when accessing external devices, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.” (1) When fetching instructions into the instruction queue buffer À When the instruction which is next fetched is located at an even address, the BIU fetches 2 bytes at a time with the timing of waveform (a). However, when accessing an external device which is connected with the 8-bit external data bus width (BYTE = “H”), only 1 byte is fetched. \ When the instruction which is next fetched is located at an odd address, the BIU fetches only 1 byte with the timing of waveform (a). The contents at the even address are not taken. (2) When reading or writing data to and from the memory•I/O device À When accessing a 16-bit data which begins at an even address, waveform (a) is applied. The 16 bits of data are accessed at a time. \ When accessing a 16-bit data which begins at an odd address, waveform (b) is applied. The 16 bits of data are accessed separately in 2 operations, 8 bits at a time. Invalid data is not fetched into the data buffer. ´ When accessing an 8-bit data at an even address, waveform (a) is applied. The data at the odd address is not fetched into the data buffer. ˆ When accessing an 8-bit data at an odd address, waveform (a) is applied. The data at the even address is not fetched into the data buffer. For instructions that are affected by the data length flag (m) and the index register length flag (x), operation À or \` is applied when flag m or x = “0”; operation ´ or ˆ is applied when flag m or x = “1.”

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2–15 Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU) Address (a) Data (Even address) Data (Odd address) E Internal address bus (A0 to A23) Internal data bus (D0 to D 7) Internal data bus (D8 to D 15) (b) Address (Odd address) Address (Even address) Data (Even address) Data (Odd address) Invalid data Invalid data Internal address bus (A0 to A23) Internal data bus (D0 to D 7) Internal data bus (D8 to D 15) E

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–16 Figure 2.3.1 shows the M37702’s access space. By combination of the program counter (PC), which is 16 bits of structure, and the program bank register (PG), a 16-Mbyte space from addresses 00000016 to FFFFFF16 can be accessed. For details about access of an external area, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.” The memory and I/O devices are allocated in the same access space. Accordingly, it is possible to perform transfer and arithmetic operations using the same instructions without discrimination of the memory from I/O devices. :Indicates the memory allocaton of the internal areas. :Indicates that nothing is allocated. Note : Memory assignment of internal area varies according to the type of microcomputer. This figure shows the case of the M37702M2BXXXFP. Refer to “Appendix 1. Memory assignment” for other products. SFR :Special Function Register 00000016 00008016 00FFFF 16 01000016 0E000016 FF000016 FFFFFF 16 SFR area Internal RAM area Bank 016 Internal ROM area 02000016 00027F16 00007F16 Bank 116 Bank FF16 Bank FE16 00C000 16 Fig. 2.3.1 M37702’s access space

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2–17

2.3.1 Banks

The access space is divided in units of 64 Kbytes. This unit is called “bank.” The high-order 8 bits of address (24 bits) indicate a bank, which is specified by the program bank register (PG) or data bank register (DT). Each bank can be accessed efficiently by using an addressing mode that uses the data bank register (DT). If the program counter (PC) overflows at a bank boundary, the contents of the program bank register (PG) is incremented by 1. If a borrow occurs in the program counter (PC) as a result of subtraction, the contents of the program bank register (PG) is decremented by 1. Normally, accordingly, the user can program without concern for bank boundaries. SFR (Special Function Register), internal RAM, and internal ROM are assigned in bank 0 16. For details, refer to section “2.4 Memory assignment.”

2.3.2 Direct page

A 256-byte space specified by the direct page register (DPR) is called “direct page.” A direct page is specified by setting the base address (the lowest address) of the area to be specified as a direct page into the direct page register (DPR). By using a direct page addressing mode, a direct page can be accessed with less instruction cycles than otherwise. Note: Refer also to section “2.1 Central processing unit.”

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–18 This section describes the internal area’s memory assignment. For more information about the external area, refer also to section “2.5 Processor modes.”

2.4.1 Memory assignment in internal area

SFR (Special Function Register), internal RAM, and internal ROM are assigned in the internal area. Figure 2.4.1 shows the internal area’s memory assignment. (1) SFR area The registers for setting internal peripheral devices are assigned at addresses 016 to 7F16. This area is called SFR (Special Function Register). Figure 2.4.2 shows the SFR area’s memory assignment. For each register in the SFR area, refer to each functional description in this manual. For the state of the SFR area immediately after a reset, refer to section “13.1.2 State of CPU, SFR area, and internal RAM area.” (2) Internal RAM area The M37702M2BXXXFP (See Note) assigns the 512-byte static RAM at addresses 8016 to 27F16. The internal RAM area is used as a stack area, as well as an area to store data. Accordingly, note that set the nesting depth of a subroutine and multiple interrupts’ level not to destroy the necessary data. (3) Internal ROM area The M37702M2BXXXFP (See Note) assigns the 16-Kbyte mask RAM at addresses C00016 to FFFF16. Its addresses FFD616 to FFFF16 are the vector addresses, which are called the interrupt vector table, for reset and interrupts. In the microprocessor mode and the external ROM version where use of the internal ROM area is inhibited, assign a ROM at addresses FFD6 16 to FFFF16. Note : Refer to “Appendix 1. Memory assignment ” for other products.

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2–19 L H L H L H L H L H L H L H H L H Timer A4 L H LTimer A3 H Timer A2 L H Timer A1 L H L H L H L H L H L H Timer B2 L H Timer B1 L H Timer B0 L H A-D conversion UART1 transmit UART1 recieve UART0 transmit UART0 recieve INT2 INT1 INT0 Watchdog timer DBC (Note 1) BRK instruction zero divide RESET FFD6 16 FFD8 16 FFDA 16 FFDC 16 FFDE 16 FFE0 16 FFE2 16 FFE8 16 FFEC 16 FFE4 16 FFE6 16 FFEA 16 FFEE 16 FFF0 16 FFF2 16 FFF4 16 FFF6 16 FFF8 16 FFFA 16 FFFC 16 FFFE 16 Interrupt vector table 00007F16 00000016 00008016 00FFFF 16 00FFD6 16 Internal RAM area Refer to Figure 2.4.2. L Notes 1: DBC is an interrupt only for debugging; do not use this interrupt. 2: Access to the internal ROM area is disabled in the microprocessor mode. (Refer to section “2.5 Processor modes.”) 3: Memory assignment of internal area varies according to the type of microcomputer. Refer to “Appendix 1. Memory assignment” for other products. Internal ROM area SFR area 00C000 16 00027F16 M37702M2BXXXFP : The internal memory is not allocated. Fig. 2.4.1 Internal area’s memory assignment

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–20 Fig. 2.4.2 SFR area’s memory map 016 116 216 316 416 516 616 716 816 916 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C 16 2D 16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 3F16 B16 C 16 D 16 E16 F16 A16 Address 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C 16 6D 16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 Address 4E16 4F16 4C 16 4D 16 4A16 4B16 4816 4916 4616 4716 4416 4516 4216 4316 4016 4116 Port P8 direction register Timer A1 register Timer A4 register Timer A2 register Timer A3 register Timer B0 register Timer B1 register Timer B2 register Count start register One-shot start register Up-down register Timer A0 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register Watchdog timer register Watchdog timer frequency select register A-D conversion interrupt control register UART0 receive interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit/receive control register 1 UART0 receive buffer register UART1 transmit buffer register UART1 receive buffer register A-D sweep pin select register A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 UART0 transmit interrupt control register UART1 transmit interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register A-D register 6 A-D register 7 Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2–21 The M37702 can operate in 3 processor modes: single-chip mode, memory expansion mode, and microprocessor mode. Some pins’ functions, memory assignment, and access space vary according to the processor modes. This section describes the differences between the processor modes. Figure 2.5.1 shows a memory assignment in each processor mode. (Note 1) : External area; Accessing this area make it possible to access external connected devices. Notes 1: Addresses 216 to 916 become a external area in the memory expansion mode and microprocessor mode. 2: Refer to “Appendix 1. Memory assignment” for products other than M37702M2BXXXFP. 00027F16 00C000 16 00028016 00BFFF 16 Memory expansion mode Microprocessor mode Fig. 2.5.1 Memory assignment in each processor mode for M37702M2BXXXFP

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–22

2.5.1 Single-chip mode

Use this mode when not using external devices. In this mode, ports P0 to P8 function as programmable I/O ports (when using an internal peripheral device, they function as its I/O pins). In the single-chip mode, only the internal area (SFR, internal RAM, and internal ROM) can be accessed.

2.5.2 Memory expansion and microprocessor modes

Use these modes when connecting devices externally. In these modes, an external device can be connected to any required location in the 16-Mbyte access space. For access to external devices, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.” The memory expansion and microprocessor modes have the same functions except for the following:

• In the microprocessor mode, access to the internal ROM area is disabled by force, and the internal ROM area is handled as an external area.
• In the microprocessor mode, port P4 2 always functions as the clock φ1 output pin. In the memory expansion and microprocessor modes, P0 to P3, P40, and P41 when the external data bus width is 16 bits function as the I/O pins for the signals required for accessing external devices. Consequently, these pins cannot be used as programmable I/O ports. If an external device is connected with an area with which the internal area overlaps, when this overlapping area is read, data in the internal area is taken in the CPU, but data in the external area is not taken in. If data is written to an overlapping area, the data is written to the internal area, and a signal is output externally at the same timing as writing to the internal area. in each processor mode. For the function of each pin, refer to section “1.3 Pin description,” “Chapter 3. INPUT/OUTPUT PINS,” each descriptions of internal peripheral devices and “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2–23 Fig. 2.5.2 Pin configuration in each processor mode (top view) P8 4/CTS 1/RTS 1 P8 5/CLK1 P8 6/RXD 1 P8 7/TXD 1 P70/AN P6 7/TB2 IN P6 6/TB1 IN P6 5/TB0 IN P6 4/INT P6 3/INT P6 2/INT P6 1/TA4 IN P6 0 /T A4OUT P5 7/TA3 IN P5 6 /TA3 OUT P5 5/TA2 IN P5 4/TA2 OUT 3/TA1 IN 2/TA1 OUT P5 1/TA0 IN 0/TA0OUT 14 325 P2 4 P2 5 P2 6 P2 7 P3 0 P3 1 P3 2 P3 3 Vss E XOUT XIN RESET CNV SS ]1 BYTE P8 3/TXD 0 P8 2/RXD 0 P8 1/CLK 0 P8 0/CTS 0/RTS 0 VCC AV CC VREF AV SS VSS P7 7/AN 7/AD TRG P7 6 /AN 6 P7 5 /AN 5 P7 4 /AN 4 P7 3 /AN 3 P7 2 /AN 2 P7 1 /AN 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 43 42 41 M37702M2BXXXFP 22 23 24 P0 0 P0 1 P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 P1 0 P1 1 P1 2 0/AN 7/TB2 IN 6/TB1 IN 5/TB0 IN 4/INT2 3/INT 2/INT 1/TA4 IN 0/TA4 OUT 7/TA3 IN 6/TA3 OUT 5/TA2 IN 4/TA2 OUT 3/TA1 IN 2/TA1 OUT 1/TA0 IN P5 0/TA0 OUT 1 432 5 A20/D4 A21/D5 A22/D6 A23/D7 R/W BHE ALE HL DA V ss E X OUT XIN RESET CNV SS BYTE HOL D 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 A A A A A A A A A 43 42 41 M37702M2 BXXXFP 22 23 24 RDY ]2 P4 4/CTS 1/RTS 5/CLK 6/R XD 7/T XD A A A A A A A A A 8/D A 9/D A P83/TXD 0 P82/RXD 0 P81/CLK0 P80/CTS0/RTS0 VCC AV CC VREF AV SS VSS P77/AN7/ADTRG P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 ]1 Connect these pins to Vss pin in the single-chip mode. : These pins have different functions between the single-chip and the memory expansion/micropro- cessor modes. ]2 This pin functions as 1 in the microprocessor mode. : These pins have different functions between the single-chip and the memory expansion/micropro- cessor modes. l Memory expansion/Microprocessor mode l Single-chip mode

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–24 Table 2.5.1 Functions of ports P0 to P4 in each processor mode P: Functions as a programmable I/O port. (Note 2) P P: Functions as a programmable I/O port. P Single-chip mode P: Functions as a programmable I/O port. P

• When external data bus width is 16 bits (BYTE = “L”) Memory expansion/Microprocessor mode D(even) D (even): Data at even address D(odd) D (odd): Data at odd address A0 – A7 (Note 1) HLDA P31 P32 P30 P33 ALE BHE Notes 1: P42 also functions as the clock 1 output pin. (Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES. ”) 2: P42 functions as a programmable I/O port in the memory expansion mode, and that functions as the clock 1 output pin by software selection. (Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES. ”) 3: This table lists a switch of pins’ functions by switching the processor mode. Refer to the following section about the input/output timing of each signal:
• “Chapter 12. CONNECTION WITH EXTERNAL DEVICES. ”
• “Chapter 15. ELECTRICAL CHARACTERISTICS. ” 4: The 7703 group does not have P33/HLDA pin. P: Functions as a programmable I/O port. P P: Functions as a programmable I/O port. P
• When external data bus width is 8 bits (BYTE = “H”) A8 – A15 A8 – A15
• When external data bus width is 16 bits (BYTE = “L”)
• When external data bus width is 8 bits (BYTE = “H”) A16 – A23 A16 – A23 R/W P: Functions as a programmable I/O port. RDY HOLD P41 P42 P40 P43 – P47 P (Note 4) D D : Data

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2–25

2.5.3 Setting processor modes

The voltage supplied to the CNVss pin and the processor mode bits (bits 1 and 0 at address 5E16) set the processor mode. l When Vss level is supplied to CNVss pin After a reset, the microcomputer starts operating in the single-chip mode. The processor mode is switched by the processor mode bits after the microcomputer starts operating. When the processor mode bits are set to “01 2,” the microcomputer enters the memory expansion mode; when these bits are set to “102,” the microcomputer enters the microprocessor mode. _ The processor mode is switched at the rising edge of signal E after writing to the processor mode bits. Figure 2.5.3 shows the timing when pin functions are switched by switching the processor mode from the single-chip mode to the memory expansion or microprocessor mode with the processor mode bits. When the processor mode is switched during the program execution, the contents of the instruction queue buffer is not initialized. (Refer to “Appendix 6. Q & A.”) l When Vcc level is supplied to CNVss pin After a reset, the microcomputer starts operating in the microprocessor mode. In this case, the microcomputer cannot operate in the other modes. (Fix the processor mode bits to “10 2.”) mode register (address 5E16). External address bus A0P00 E Written to processor mode bits Programmable I/O port P00 Note: Functions of pins P01 to P07, P1 to P3, P40 to P42 are switched at the same timing shown above. Function of pin P42 is, however, switched only when the processor mode is switched to the microprocessor mode. Fig. 2.5.3 Timing when pin functions are switched

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–26 Processor mode CNVss pin level Processor mode bits b1 b0 Single-chip mode Vss (0 V) ( Note 1) 0 Memory expansion mode Vss (0 V) ( Note 1) 0 Microprocessor mode Vss (0 V) ( Note 1) 1 Vcc (5 V) (Note 2) Notes 1:The microcomputer starts operating in the single-chip mode after a reset. The microcomputer can be switched to the other processor modes by setting the processor mode bits. 2:The microcomputer starts operating in the microprocessor mode after a reset. The microcomputer cannot operate in the other modes, so that fix the processor mode bits as follows: Table 2.5.2 Methods for setting processor modes Bit Bit name Functions At reset RW Processor mode bits Software reset bit Interrupt priority detection time select bits Clock 1 output select bit (Note 2) 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not selected The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Not selected 0 : Clock 1 output disabled (P42 functions as a programmable I/O port.) 1 : Clock 1 output enabled (P42 functions as a clock 1 out- put pin.) b1 b0 b5 b4 Processor mode register (Address 5E16) (Note1) Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1” after a reset. (Fixed to “1.”) 2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”) b1 b0b2b3b4b5b6b7 RW RW Wait bit RW WO 0 RW 0 RW Fix this bit to “0.” RW RW 0 : Software Wait is inserted when accessing external area. 1 : No software wait is inserted when accessing external area. : Bits 7 to 2 are not used for setting of the processor mode. Fig. 2.5.4 Structure of processor mode register

CENTRAL PROCESSING UNIT (CPU) 7702/7703 Group User’s Manual 2–27 [Precautions when selecting the processor mode] [Precautions when selecting processor mode] 1. For the products operating only in the single-chip mode, be sure to set the following:

• Connect the CNVss pin with Vss.
• Fix the processor mode bits (bits 1 and 0 at address 5E16) to “002.” 2. The external ROM version is only for the microprocessor mode. Accordingly, be sure to set the following:
• Connect the CNVss pin with Vcc.
• Fix the processor mode bits (bits 1 and 0 at address 5E 16) to “102.” 3. When using the memory expansion mode or microprocessor mode, be sure to set bits 0 and 1 of the Set the above setting whether using P40/HOLD pin as HOLD pin and P41/RDY pin as RDY pin. For also the external ROM version, set the above setting. Additionally, it is not need to set the port P0 to P3 direction registers.

7702/7703 Group User’s Manual CENTRAL PROCESSING UNIT (CPU) 2–28 [Precautions when selecting the processor mode] MEMORANDUM

3.1 Programmable I/O ports

3.2 I/O pins of internal peripheral devices

3–2 7702/7703 Group User’s Manual This chapter describes the programmable I/O ports in the single-chip mode. For P0 to P4, which change their functions according to the processor mode, refer also to the section “2.5 Processor modes ” and “Chapter 12. CONNECTION WITH EXTERNAL DEVICES. ” P42 and P5 to P8 also function as the I/O pins of the internal peripheral devices. For the functions, refer to the section “3.2 I/O pins of internal peripheral devices” and relevant sections of each internal peripheral devices. The 7703 Group varies with the 7702 Group in the number of pins, pins’ assignment and others. Refer to the section “Chapter 20. 7703 GROUP .” The 7702 Group has 68 programmable I/O ports, P0 to P8. The programmable I/O ports have direction registers and port registers in the SFR area. Figure 3.1.1 shows the memory map of direction registers and port registers. Fig. 3.1.1 Memory map of direction registers and port registers Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register 816 916 A16 B16 C 16 D 16 E16 F16 1016 1116 1216 1316 1416 Addresses Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register 316 416 516 616 716

7702/7703 Group User’s Manual 3–3 INPUT/OUTPUT PINS

3.1.1 Direction register

This register determines the input/output direction of the programmable I/O port. Each bit of this register corresponds one for one to each pin of the microcomputer. Figure 3.1.2 shows the structure of port Pi (i = 0 to 8) direction register. 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Port Pi5 direction bit Port Pi direction register (i = 0 to 8) (Addresses 416, 516, 816, 916, C16, D16, 1016, 1116, 1416) b1 b0b2b3b4b5b6b7 Port Pi1 direction bit Port Pi7 direction bit At reset RW RW RW RW RW RW RW RW RW Notes 1: Bits 7 to 4 of the port P3 direction register cannot be written (they may be either “0” or “1”) and are fixed to “0” at reading. 2: In the memory expansion mode or the microprocessor mode, fix bits 0 and 1 of the port P4 direction register to “0”. Fix the following bits which do not have the corresponding pin to “1”.

• Bit 3 of port P3 direction register
• Bits 3 to 6 of port P4 direction register
• Bits 0, 1, 6, and 7 of port P6 direction register
• Bits 3 to 6 of port P7 direction register
• Bits 4 and 5 of port P8 direction register Bit Corresponding pin b7 b6 b5 b4 b3 b2 b1 b0 Pi7 Pi6 Pi5 Pi4 Pi3 Pi2 Pi1 Pi0 Fig. 3.1.2 Structure of port Pi (i = 0 to 8) direction register

3–4 7702/7703 Group User’s Manual

3.1.2 Port register

Data is input/output to/from externals by writing/reading data to/from the port register. The port register consists of a port latch which holds the output data and a circuit which reads the pin state. Each bit of the port register corresponds one for one to each pin of the microcomputer. Figure 3.1.3 shows the structure of the port Pi (i = 0 to 8) register. l When outputting data from programmable I/O ports set to output mode À By writing data to the corresponding bit of the port register, the data is written into the port latch. \ The data is output from the pin according to the contents of the port latch. By reading the port register of a port set to output mode, the contents of the port latch is read out, instead of the pin state. Accordingly, the output data is correctly read without being affected by an l When inputting data from programmable I/O ports set to input mode À The pin which is set to input mode enters the floating state. \ By reading the corresponding bit of the port register, the data which is input from the pin can be read out. By writing data to the port register of a programmable I/O port set to input mode, the data is only written into the port latch and is not output to externals. The pin retains floating.

7702/7703 Group User’s Manual 3–5 INPUT/OUTPUT PINS Data is input/output to/from a pin by reading/writing from/to the corres- ponding bit. Port Pi Port Pi register (i = 0 to 8) (Addresses 216, 316, 616, 716, A16, B16, E16, F16, 1216) b1 b0b2b3b4b5b6b7 Port Pi1 Port Pi7 At reset RW Undefined Note: Bits 7 to 4 of the port P3 register cannot be written (they may be either “0” or “1”) and are fixed to “0” at reading. Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 : “L” level 1 : “H” level RW RW RW RW RW RW RW RW Fig. 3.1.3 Port Pi (i = 0 to 8) register structure

3–6 7702/7703 Group User’s Manual Fig. 3.1.4 Port peripheral circuits (1) Ports P00/A0 to P07/A7, P10/A8/D8 to P17/A15/D15, P20/A16/D0 to P27/A23/D7, P30/R/W to P33/HLDA, P43 to P46 [Inside dotted-line not included] Data bus Direction register Port latch Ports P42/ 1, P83/TxD0, P87/TxD1 [Inside dotted-line not included. ] Ports P50/TA0OUT , P52/TA1OUT , P54/TA2OUT , P56/TA3OUT , P60/TA4OUT [Inside dotted-line included. ] Data bus “1” Output Port latch Direction register P82/RxD0, P86/RxD1 Ports P40/HOLD, P41/RDY, P47, P51/TA0 IN, P53/TA1IN, P55/TA2 IN, P57/TA3 IN, [Inside dotted-line included] P61/TA4IN, P62/INT0 to P64/INT2, P65/TB0IN to P67/TB2IN, (There is no hysteresis for P82/RxD0 and P86/RxD1.) Ports P70/AN0 to P76/AN6 Port P77/AN7/ADTRG Data bus Analog input Direction register Port latch [Inside dotted-line not included. ] [Inside dotted-line included. ] There are not pins P33, P43 – P46, P60, P61, P66, P67, P73 – P76.

7702/7703 Group User’s Manual 3–7 INPUT/OUTPUT PINS E output pin Ports P80/CTS0/RTS0, P81/CLK0, P84/CTS1/RTS1, P85/CLK1 /LiteDiagLines /LiteDiagLines /LiteDiagLines “1” Output “0” Direction register Port latchData bus There are not pins P84 and P85. Fig. 3.1.5 Port peripheral circuits (2)

3–8 7702/7703 Group User’s Manual P42 and P5 to P8 also function as the I/O pins of the internal peripheral devices. Table 3.2.1 lists I/O pins for the internal peripheral devices. For their functions, refer to relevant sections of each internal peripheral devices. For the clock φ1 output pin, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES. ” Table 3.2.1 I/O pins for internal peripheral devices I/O pins for internal peripheral devices Clock φ1 output pin I/O pins of Timer A Input pins of external interrupts Input pins of Timer B Input pins of A-D converter I/O pins of Serial I/O Port P4 2 0, P61 P6 2 to P64 P6 5 to P67

4.1 Overview

4.2 Interrupt sources

4.3 Interrupt control

4.4 Interrupt priority level

4.5 Interrupt priority level detection circuit

4.6 Interrupt priority level detection time

4.7 Sequence from acceptance of interrupt request to execution of interrupt routine

4.8 Return from interrupt routine

4.9 Multiple interrupts

____

4.10 External interrupts (INTi interrupt)

4.11 Precautions when using interrupts

7702/7703 Group User’s Manual INTERRUPTS 4–2 The suspension of the current operation in order to perform another operation owing to a certain factor is referred to as “Interrupt.” This chapter describes the interrupts. The M37702 has 19 interrupt sources to generate interrupt requests. Figure 4.1.1 shows the interrupt processing sequence. When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set in the interrupt vector table (addresses FFD616 to FFFF16). Set the start address of each interrupt routine at each interrupt vector address in the interrupt vector table. Fig. 4.1.1 Interrupt processing sequence Interrupt routine Accept interrupt request Resume processing Suspend processing Return to original routine RTI instruction Process interrupt Executing routine Branch to start address of interrupt routine

7702/7703 Group User’s Manual 4–3 INTERRUPTS When an interrupt request is accepted, the contents of the registers listed below immediately preceding the acceptance of the interrupt request are automatically saved to the stack area in order of registers À → \ → ´ . À Program bank register (PG) \ Program counter (PCL, PCH) ´ Processor status register (PSL, PSH ) Figure 4.1.2 shows the state of the stack area just before entering the interrupt routine. Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer was executing before the interrupt request was accepted. As the RTI instruction is executed, the register contents saved in the stack area are restored in order of registers ´ → \` → À , and a return is made to the routine executed before the acceptance of interrupt request and processing is resumed from it. When an interrupt request is accepted and the RTI instruction is executed, the only above registers À to ´ are automatically saved and restored. When there are any other registers of which contents are necessary to be kept, use software to save and restore them. Fig. 4.1.2 State of stack area just before entering interrupt routine [S] is an initial value that the stack pointer (S) indicates at accepting an interrupt request. The S’s contents become [S] – 5 after saving the above registers. Address [S] – 4 [S] – 3 [S] – 2 [S] – 1 [S]] Processor status register’s low-order byte (PSL) Stack area [S] – 5 Processor status register’s high-order byte (PSH ) Program counter’s low-order byte (PCL) Program counter’s high-order byte (PCH ) Program bank register (PG)

7702/7703 Group User’s Manual INTERRUPTS 4–4 Remarks Non-maskable Non-maskable software interrupt Non-maskable software interrupt Not used usually Non-maskable interrupt ____ External interrupt due to INT0 pin input signal ____ External interrupt due to INT1 pin input signal ____ External interrupt due to INT2 pin input signal Internal interrupt from Timer A0 Internal interrupt from Timer A1 Internal interrupt from Timer A2 Internal interrupt from Timer A3 Internal interrupt from Timer A4 Internal interrupt from Timer B0 Internal interrupt from Timer B1 Internal interrupt from Timer B2 Internal interrupt from UART0 Internal interrupt from UART1 Internal interrupt from A-D converter Table 4.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start address of each interrupt routine at the vector addresses listed in this table. Table 4.2.1 Interrupt sources and interrupt vector addresses High-order address FFFF 16 FFFD 16 FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 FFDB 16 FFD9 16 FFD7 16 Interrupt source Reset Zero division BRK instruction ____ DBC (Note) Watchdog timer ____ INT0 ____ INT1 ____ INT2 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 receive UART0 transmit UART1 receive UART1 transmit A-D conversion ____ Note: The DBC interrupt source is used exclusively for debugger control.

7702/7703 Group User’s Manual 4–5 INTERRUPTS Table 4.2.2 lists occurrence factors of internal interrupt request, which occur due to internal operation. Table 4.2.2 Occurrence factors of internal interrupt request Interrupt Zero division interrupt BRK instruction interrupt Watchdog timer interrupt Timer Ai interrupt (i = 0 to 4) Timer Bi interrupt (i = 0 to 2) UARTi receive interrupt (i = 0, 1) UARTi transmit interrupt (i = 0, 1) A-D conversion interrupt Interrupt request occurrence factors Occurs when “0” is specified as the divisor for the DIV instruction (Division instruction). (Refer to “7700 Family Software Manual.”) Occurs when the BRK instruction is executed. (Refer to “7700 Family Software Manual.”) Occurs when the most significant bit of the watchdog timer becomes “0.” (Refer to “Chapter 9. WATCHDOG TIMER.” ) Differs according to the timer Ai’s operating modes. (Refer to “Chapter 5. TIMER A.”) Differs according to the timer Bi’s operating modes. (Refer to “Chapter 6. TIMER B.”) Occurs at serial data reception. (Refer to “Chapter 7. SERIAL I/O.”) Occurs at serial data transmission. (Refer to “Chapter 7. SERIAL I/O.”) Occurs when A-D conversion is completed. (Refer to “Chapter 8. A-D CONVERTER.” )

7702/7703 Group User’s Manual INTERRUPTS 4–6 The enabling and disabling of maskable interrupts are controlled by the following :

• Interrupt request bit
• Interrupt priority level select bits
• Processor interrupt priority level (IPL)
• Interrupt disable flag (I) The interrupt disable flag (I) and the processor interrupt priority level (IPL) are assigned to the processor status register (PS). The interrupt request bit and the interrupt priority level select bits are assigned to the interrupt control register of each interrupt. Figure 4.3.1 shows the memory assignment of the interrupt control registers, and Figure 4.3.2 shows their structure. l Maskable interrupt: An interrupt of which request’s acceptance can be disabled by software. l Non-maskable interrupt (including Zero division, BRK instruction, Watchdog timer interrupts): An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their interrupt control registers and are independent of the interrupt disable flag (I).

Fig. 4.3.1 Memory assignment of interrupt control registers A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT 0 interrupt control register INT1 interrupt control register INT2 interrupt control register Address 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16

7702/7703 Group User’s Manual 4–7 INTERRUPTS Fig. 4.3.2 Structure of interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit Interrupt request bit (Note 1) Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request 0 : Edge sense 1 : Level sense Notes 1: The INT 0 to INT2 interrupt request bits are invalid when selecting the level sense. 2: Use the SEB or the CLB instruction to set the INT0 to INT2 interrupt control registers. Interrupt priority level select bits 7, 6 RW RW RW RW RW RW Undefined Polarity select bit 0 : Set the interrupt request bit at “H” level for level sense and at falling edge for edge sense. 1 : Set the interrupt request bit at “L” level for level sense and at rising edge for edge sense. Level sense/Edge sense select bit Nothing is allocated. b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 7016 to 7C16) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request Note: Use the SEB or CLB instruction to set each interrupt control register. Interrupt priority level select bits RW RW RW RW –Undefined Nothing is allocated.

7702/7703 Group User’s Manual INTERRUPTS 4–8

4.3.1 Interrupt disable flag (I)

All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts are disabled; when the flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1” at reset, clear the flag to “0” when enabling interrupts.

4.3.2 Interrupt request bit

When an interrupt request occurs, this bit is set to “1.” The bit remains set to “1” until the interrupt request is accepted, and it is cleared to “0” when the interrupt request is accepted. This bit also can be set to “0” or “1” by software. Use the SEB or CLB instruction to set this bit. For the INTi interrupt request bit (i = 0 to 2), when using the INTi interrupt with level sense, the bit is ignored.

4.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL)

The interrupt priority level select bits are used to determine the priority level of each interrupt. Use the SEB or CLB instruction to set these bits. When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition. Accordingly, an interrupt can be disabled by setting its interrupt priority level to 0. Each interrupt priority level > Processor interrupt priority level (IPL) Table 4.3.1 lists the setting of interrupt priority level, and Table 4.3.2 lists the interrupt enabled level corresponding to IPL contents. All the interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor interrupt priority level (IPL) are independent of one another; they do not affect one another. Interrupt requests are accepted only when the following conditions are satisfied.

• Interrupt disable flag (I) = “0”
• Interrupt request bit = “1”
• Interrupt priority level > Processor interrupt priority level (IPL)

7702/7703 Group User’s Manual 4–9 INTERRUPTS Table 4.3.1 Setting of interrupt priority level Level 0 (Interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High Interrupt priority levelInterrupt priority level select bits Priority IPL2 Enabled interrupt priority level Enable level 1 and above interrupts. Enable level 2 and above interrupts. Enable level 3 and above interrupts. Enable level 4 and above interrupts. Enable level 5 and above interrupts. Enable level 6 and level 7 interrupts. Enable only level 7 interrupt. Disable all maskable interrupts. IPL IPL Table 4.3.2 Interrupt enabled level corresponding to IPL contents IPL0: Bit 8 in processor status register (PS) IPL1: Bit 9 in processor status register (PS) IPL2: Bit 10 in processor status register (PS)

7702/7703 Group User’s Manual INTERRUPTS 4–10 When two or more interrupt requests are detected at the same sampling timing, at which whether an interrupt request exists or not is checked, in the case of the interrupt disable flag (I) = “0” (interrupts enabled); they are accepted in order of priority levels, with the highest priority interrupt request accepted first. Among a total of 19 interrupt sources, the user can set the desired priority levels for 16 interrupt sources except software interrupts (zero division and BRK instruction interrupts) and the watchdog timer interrupt. Use the interrupt priority level select bits to set their priority levels. Additionally, the reset, which is handled as one that has the highest priority of all interrupts, and the watchdog timer interrupt have their priority levels set by hardware. Figure 4.4.1 shows the interrupt priority levels set by hardware. Note that software interrupts are not affected by interrupt priority levels. Whenever the instruction is executed, a branch is certain to be made to the interrupt routine. Fig. 4.4.1 Interrupt priority levels set by hardware 16 interrupt sources except software interrupts and watchdog timer interrupt The user can set the desired priority levels inside of the dotted line. Priority levels determined by hardware HighLow Priority level

7702/7703 Group User’s Manual 4–11 INTERRUPTS The interrupt priority level detection circuit selects the interrupt having the highest priority level when more than one interrupt request occurs at the same sampling timing. Figure 4.5.1 shows the interrupt priority level detection circuit. Fig. 4.5.1 Interrupt priority level detection circuit A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2 INT1 INT0 IPL Processor interrupt priority level The highest priority level interrupt Interrupt disable flag (I) Watchdog timer interrupt Reset Accepting of interrupt request Interrupt priority levelInterrupt priority level Level 0 (initial value)

7702/7703 Group User’s Manual INTERRUPTS 4–12 The following explains the operation of the interrupt priority detection circuit using Figure 4.5.2. The interrupt priority level of a requested interrupt (Y in Figure 4.5.2) is compared with the resultant priority level sent from the preceding comparator (X in Figure 4.5.2); whichever interrupt of the higher priority level is sent to the next comparator (Z in Figure 4.5.2). (Initial comparison value is “0.”) For interrupts for which no interrupt request occurs, the priority level sent from the preceding comparator is forwarded to the next comparator. When the two priority levels are found the same by comparison, the priority level sent from the preceding comparator is forwarded to the next comparator. Accordingly, when the same priority level is set by software, the interrupt requests are subject to the following relation about priority: A-D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0 receive > Timer B2____ ____ ____ > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 > INT2 > INT1 > INT0 Among the multiple interrupt requests sampled at the same time, one that has the highest priority level is detectedd by the above comparison. Then this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable flag (I) is “0,” the interrupt request is accepted. A interrupt request which is not accepted here is retained until it is accepted or its interrupt request bit is cleared to “0” by software. The interrupt priority is detected when the CPU fetches an op code, which is called the CPU’s op-code fetch cycle. However, when an op-code fetch cycle is generated during detection of an interrupt priority, new detection of that does not start. (Refer to Figure 4.6.1.) Since the state of the interrupt request bit and interrupt priority levels are latched during detection of interrupt priority, even if the bit state and priority levels change, the detection is performed on the previous state before it has changed. Fig. 4.5.2 Interrupt priority level detection model Y X Z Comparator (Priority level comparison) l When X Y then Z = X l When X Y then Z = Y Interrupt source Y X : Resultant priority level sent from the preceding comparator (Highest priority at this point) Y : Priority level of interrupt source Y Z : Highest priority at this point Time

7702/7703 Group User’s Manual INTERRUPTS 4–13 After sampling had started, an interrupt priority level detection time has elapses before an interrupt request is accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the interrupt priority level detection time. As the interrupt priority level detection time, normally select “2 cycles of internal clock φ.” Fig. 4.6.1 Interrupt priority level detection time (2) Interrupt priority level detection time Op code fetch cycle Sampling pulse (a) 7 cycles (b) 4 cycles (c) 2 cycles Interrupt priority level detection time (Note) Note: Pulse exists when “2 cycles of ” is selected. b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 1 1 0 1 1 Processor mode register (Address 5E 16) Processor mode bits Software reset bit Fix to “0.” Clock 1 output select bit 7 cycles of [(a) shown below] 4 cycles of [(b) shown below] 2 cycles of [(c) shown below] Interrupt priority detection time select bits Do not select (1) Interrupt priority detection time select bits b5, b4 Wait bit

7702/7703 Group User’s Manual INTERRUPTS 4–14

4.7 Sequence from acceptance of interrupt request to execution of interrupt routine

The sequence from the acceptance of interrupt request to the execution of the interrupt routine is described below. When an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt is cleared to “0,” and then the interrupt processing starts from the next cycle of completion of the instruction which is being executed at accepting the interrupt request. Figure 4.7.1 shows the sequence from acceptance of interrupt request to execution of interrupt routine. After execution of an instruction at accepting the interrupt request is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine allocated in addresses 0 16 to FFFF16. The INTACK sequence is automatically performed in the following order. À The contents of the program bank register (PG) just before performing the INTACK sequence are stored to stack. \` The contents of the program counter (PC) just before performing the INTACK sequence are stored to stack. ´ The contents of the processor status register (PS) just before performing the INTACK sequence is stored to stack. ˆ The interrupt disable flag (I) is set to “1.” ˜ The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL). ¯ The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt vector address are set into the program counter (PC). Performing the INTACK sequence requires at least 13 cycles of internal clock φ. Figure 4.7.2 shows the INTACK sequence timing. Execution is started beginning with an instruction at the start address of the interrupt routine after completing the INTACK sequence.

7702/7703 Group User’s Manual INTERRUPTS 4–15 Fig. 4.7.2 INTACK sequence timing (at minimum) Fig. 4.7.1 Sequence from acceptance of interrupt request to execution of interrupt routine @ : Duration for detecting interrupt priority level Interrupt request occurs. Interrupt request is accepted. Instruction Instruction INTACK sequence Instructions in interrupt routine Interrupt response time Time@ À Time from the occurrence of an interrupt request until the completion of executing an instruction which is being executed at the occurrence. \ Time from the instruction next to À (Note) until the completion of executing an instruction which is being done at the end of priority detection Note : At this time, interrupt priority detection starts. ´ Time required to execute the INTACK sequence (13 cycles of at minimum) À \ ´ l When stack pointer (S)’s contents is even and no Wait PG PC H 00 00 00 00 00 00 00 00 ([S]–1)H FF16 AD HPC H PS HFF16D H AP AH Interrupt disable flag (I) Internal clock CPU PCLPG PS LXX 16D L AD H AD L PC L 00 XX16AL AD L [S]H [S]L INTACK sequence Op-code Op-code : Not used [S] XX 16 AD H AD L : Contents of stack pointer (S) : Low-order 8 bits of vector address : Contents of vector address (High-order address) : Contents of vector address (Low-order address) CPU AP AH AL D H D L : CPU standard clock : High-order 8 bits of CPU internal address bus : Middle-order 8 bits of CPU internal address bus : Low-order 8 bits of CPU internal address bus : CPU internal data bus for odd address : CPU internal data bus for even address

7702/7703 Group User’s Manual INTERRUPTS 4–16

4.7.1 Change in IPL at acceptance of interrupt request

When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the interrupt priority level of the accepted interrupt. This results in easy control of multiple interrupts. (Refer to section “4.9 Multiple interrupts.”) When at reset or the watchdog timer or the software interrupt is accepted, the value shown in Table 4.7.1 is set in the IPL. Table 4.7.1 Change in IPL at interrupt request acceptance Change in IPL Level 0 (“000 2”) is set. Level 7 (“1112”) is set. No change No change Interrupt priority level of the accepted interrupt request is set. Interrupt source Reset Watchdog timer Zero division BRK instruction Other interrupts

7702/7703 Group User’s Manual INTERRUPTS 4–17

4.7.2 Storing registers

The register storing operation performed during INTACK sequence depends on whether the contents of the stack pointer (S) at accepting interrupt request are even or odd. When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the processor status register (PS) are stored as a 16-bit unit simultaneously at each other. When the contents of the stack pointer (S) are odd, they are stored with twice by an 8-bit unit for each. Figure 4.7.3 shows the register storing operation. In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and processor status register (PS) are stored to the stack area. The other necessary registers must be stored by software at the beginning of the interrupt routine. Using the PSH instruction can store all CPU registers except the stack pointer (S). Fig. 4.7.3 Register storing operation Storing is completed with 3 times. ´ Stores 16 bits at a time. À \` Stores 16 bits at a time. (1) Content of stack pointer (S) is even Low-order byte of processor status register (PSL) Program bank register (PG) Address [S] – 4 (even) [S] – 3 (odd) [S] – 2 (even) [S] – 1 (odd) [S] (even) Storing order[S] – 5 (odd) Address [S] – 4 (odd) [S] – 3 (even) [S] – 2 (odd) [S] – 1 (even) [S] (odd) À ˆ Stores by each 8 bits. Storing order Storing is completed with 5 times. [S] – 5 (even) High-order byte of processor status register (PSH ) Low-order byte of program counter (PCL) High-order byte of program counter (PCH ) (2) Content of stack pointer (S) is odd Low-order byte of processor status register (PSL) Program bank register (PG) High-order byte of processor status register (PSH ) Low-order byte of program counter (PCL) High-order byte of program counter (PCH ) [S] is an initial value that the stack pointer (S) indicates at accepting an interrupt request. The S’s contents become [S] – 5 after storing the above registers.

7702/7703 Group User’s Manual INTERRUPTS 4–18 When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank register (PG), program counter (PC), and processor status register (PS) immediately before performing the INTACK sequence, which were saved to the stack area, are automatically restored, and control returns to the routine executed before the acceptance of interrupt request and processing is resumed from it left off. For any register that is saved by software in the interrupt routine, restore it with the same data length and same register length as it was saved by using the PUL instruction and others before executing the RTI instruction. When a branch is made to the interrupt routine, the microcomputer becomes the following situation:

• Interrupt disable flag (I) = “1” (interrupts disabled)
• Interrupt request bit of the accepted interrupt = “0”
• Processor interrupt priority level (IPL) = interrupt priority level of the accepted interrupt Accordingly, as long as the IPL remains unchanged, the microcomputer can accept the interrupt request that has higher priority than the interrupt request being executed now by clearing the interrupt disable flag (I) to “0” in the interrupt routine. This is multiple interrupts. Figure 4.9.1 shows the multiple interrupt mechanism. The interrupt requests that have not been accepted owing to their low priority levels are retained. When the RTI instruction is executed, the interrupt priority level of the routine that the microcomputer was executing before accepting the interrupt request is restored to the IPL. Therefore, one of the interrupt requests being retained is accepted when the following condition is satisfied at next detection of interrupt priority level: Interrupt priority level of interrupt request being retained > Restored processor interrupt priority level (IPL) 4.8 Return from interrupt routine 4.9 Multiple interrupts

7702/7703 Group User’s Manual INTERRUPTS 4–19 Fig. 4.9.1 Multiple interrupt mechanism Main routineReset I = 1 IPL = 0 I = 0 Interrupt 1 I = 1 IPL = 3 I = 0 I = 1 IPL = 5 RTI I = 0 IPL = 3 RTI I = 0 IPL = 0 I = 1 IPL = 2 RTI I = 0 IPL = 0 Interrupt 1 Interrupt priority level=3 This request cannot be accepted because its priority level is lower than interrupt 1’s. Request Nesting Time : They are set automatically. : Set by software. I : Interrupt disable flag IPL : processor interrupt priority level Multiple interruptInterrupt 2 Interrupt priority level=5 Interrupt 3 Interrupt priority level=2 Interrupt 2 Interrupt 3 Interrupt 3 The instruction of main routine is not executed then.

7702/7703 Group User’s Manual INTERRUPTS 4–20 ___ ___ An external interrupt request occurs by input signals to the INTi (i = 0 to 2) pin. The occurrence factor of interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits___ When using P6 2/INT0 to P64/INT2 pins as input pins of external interrupts, set the corresponding bits at address 1016 (port P6 direction register) to “0.” (Refer to Figure 4.10.2.)___ The signals input to the INTi pin require “H” or “L” level width of 250 ns or more independent of the f(XIN).___ ___ Additionally, even when using the pins P62/INT0 to P64/INT2 as the input pins of external interrupt, the user can obtain the pin’s state by reading bits 2 to 4 at address E16 (port P6 register). Note: When selecting an input signal’s falling or “L” level as the occurrence factor of an interrupt request, make sure that the input signal is held “L” for 250 ns or more. When selecting an input signal’s rising or “H” level as that, make sure that the input signal is held “H” for 250 ns or more. ___ ___ Table 4.10.1 Occurrence factor of INTi interrupt request ___ INTi interrupt request occurrence factor The INTi interrupt request occurs by always detecting the INTi pin’s state. Accordingly, when the user does___ ___ not use the INTi interrupt, set the INTi interrupt’s priority level to level 0. ___ Interrupt request occurs at falling of the signal input to the INTi pin (edge sense). ___ Interrupt request occurs at rising of the signal input to the INTi pin (edge sense). ___ Interrupt request occurs while the INTi pin level is “H” (level sense). ___ Interrupt request occurs while the INTi pin level is “L” (level sense).

7702/7703 Group User’s Manual INTERRUPTS 4–21 ___ INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit Interrupt request bit (Note 1) Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request 0 : Edge sense 1 : Level sense Notes 1: The INT 0 to INT2 interrupt request bits are invalid when selecting the level sense. 2: Use the SEB or CLB instruction to set the INT0 to INT2 interrupt control registers. Interrupt priority level select bits 7, 6 RW RW RW RW RW RW Undefined Polarity select bit 0 : Set the interrupt request bit at “H” level for level sense and at falling edge for edge sense. 1 : Set the interrupt request bit at “L” level for level sense and at rising edge for edge sense. Level sense/Edge sense select bit Nothing is allocated. ___ Fig. 4.10.1 Structure of INTi (i=0 to 2) interrupt control register

7702/7703 Group User’s Manual INTERRUPTS 4–22 ___ Bit Corresponding pin Functions TA4 OUT pin INT0 pin INT1 pin INT2 pin TB1 IN pin TB0 IN pin Port P6 direction register (Address 1016) b1 b0b2b3b4b5b6b7 TA4 IN pin TB2 IN pin At reset RW RW RW RW RW RW RW RW RW 0 : Input mode 1 : Output mode When using pins as external interrupt input pins,set the corresponding bits to “0.” : Bits 0, 1 and bits 5 to 7 are not used for external interrupts. Fig. 4.10.2 Relationship between port P6 direction register and input pins of external interrupt

7702/7703 Group User’s Manual INTERRUPTS 4–23 ___

4.10.1 Function of INT

i interrupt request bit (1) Selecting edge sense mode The interrupt request bit has the same function as that of internal interrupts. That is, when an interrupt request occurs, the interrupt request bit is set to “1.” The bit remains set to “1” until the interrupt request is accepted; it is cleared to “0” when the interrupt request is accepted. By software, this bit also can be set to “0” in order to clear the interrupt request or “1” in order to generate the interrupt request. (2) Selecting level sense mode ___ The INT i interrupt request bit becomes ignored. ___ In this case, the interrupt request occurs continuously while the level of the INT i pin is valid level ___ ___ When the INT i pin level changes from the valid level to the invalid level before the INT i interrupt request is accepted, this interrupt request is not retained. (Refer to Figure 4.10.4.) Valid level : This means the level which is selected by the polarity select bit (bit 4 at addresses 7D to 7F Invalid level : This means the reversed level of a valid level. ___

4.10 External interrupts (INT

i interrupt) INT i pin Edge detection circuit Interrupt request Level sense/Edge sense select bit Data bus Interrupt request bit “0” “1” ___ Fig. 4.10.3 Circuit of INT i Interrupt

7702/7703 Group User’s Manual INTERRUPTS 4–24 ___ Fig. 4.10.4 Occurrence of INTi interrupt request in level sense mode ___ Interrupt request is accepted. Return to main routine. Second interrupt routine Third interrupt routine Main routine When the INTi pin’s level changes to an invalid level before an interrupt request is accepted, the interrupt request is not retained.

7702/7703 Group User’s Manual INTERRUPTS 4–25 ___ ___

4.10.2 Switch of occurrence factor of INTi interrupt request___

To switch the occurrence factor of INTi interrupt request from the level sense to the edge sense, set the___ INTi interrupt control register in the sequence shown in Figure 4.10.5 (1). To change the polarity, set the___ INTi interrupt control register in the sequence shown in Figure 4.10.5 (2). Clear level sense/edge sense select bit to “0” ( Select edge sense ) Clear interrupt request bit to “0” Set the interrupt priority level to level 0 ( Disable INTi interrupt ) Set polarity select bit Clear interrupt request bit to “0” (2) Changing polarity(1) Switching from level sense to edge sense Set the interrupt priority level to level 1–7 (Enable acceptance of INTi interrupt request) Set the interrupt priority level to level 1–7 (Enable acceptance of INTi interrupt request) Set the interrupt priority level to level 0 ( Disable INTi interrupt ) Notes 1: Use the SEB or CLB instruction when setting the INTi interrupt control register (i = 0 to 2). 2: Perform the above setting separately. Do not perform 2 or more setting at the same time, with 1 instruction. ___ Fig. 4.10.5 Switching flow of occurrence factor of INTi interrupt request

7702/7703 Group User’s Manual INTERRUPTS 4–26

1. Use the SEB or CLB instruction when setting the interrupt control registers (addresses 7016 to 7F16.) 2. To change the interrupt priority level select bits (bits 0 to 2 at addresses 7016 to 7F16), 2 to 7 cycles of φ are required after executing an write-instruction until completion of the interrupt priority level’s change. Accordingly, it is necessary to reserve enough time by software when changing the interrupt priority level of which interrupt source is the same within a very short execution time consisting of a few instructions. Figure 4.11.1 shows a program example to reserve time required for changing interrupt priority level. The time for change depends on the interrupt priority detection timer select bits (bits 4 and 5 at address 5E 16). Table 4.11.1 lists the relation between the number of instructions to be inserted with program example of Figure 4.11.1 and the interrupt priority detection time select bits. Fig. 4.11.1 Program example to reserve time required for changing interrupt priority level Table 4.11.1 Relation between number of instructions to be inserted with program example of Figure 4.11.1 and interrupt priority detection time select bits ; Write to interrupt priority level select bits ; Insert NOP instruction (Note) ; Write to interrupt priority level select bits Note: All instructions (other than instructions for writing to address 7X 16) which have the same cycles as NOP instruction can also be inserted. Confirm the number of instructions to be inserted by Table 4.11.1. SEB .B #0XH, 007XH NOP NOP NOP CLB.B #0XH, 007XH Interrupt priority detection time select bits (Note) Interrupt priority level detection time 7 cycles of φ 4 cycles of φ 2 cycles of φ Do not select. Number of inserted instructions NOP instruction 4 or more NOP instruction 2 or more NOP instruction 1 or more Note: We recommend [b5 = “1”, b4 = “0”].

5.1 Overview

5.2 Block description

5.3 Timer mode

5.4 Event counter mode

5.5 One-shot pulse mode

5.6 Pulse width modulation (PWM) mode

7702/7703 Group User’s Manual TIMER A 5–2 Timer A is used primarily for output to externals. It consists of five counters, timers A0 to A4, each equipped with a 16-bit reload function. Timers A0 to A4 operate independently of one another. Timer A4’s function of the 7703 Group varies from the 7702 Group’s. Refer to “Chapter 20. 7703 GROUP .” Timer Ai (i = 0 to 4) has four operating modes listed below. Except for the event counter mode, Timers A0 to A4 all have the same functions. l Timer mode The timer counts an internally generated count source. Following functions can be used in this mode:

• Gate function
• Pulse output function l Event counter mode The timer counts an external signal. Following functions can be used in this mode:
• Pulse output function
• Two-phase pulse signal processing function (Timers A2, A3, and A4) l One-shot pulse mode The timer outputs a pulse which has an arbitrary width once. l Pulse width modulation (PWM) mode Timer outputs pulses which have an arbitrary width in succession. The timer functions as which pulse width modulator as follows:
• 16-bit pulse width modulator
• 8-bit pulse width modulator

7702/7703 Group User’s Manual 5–3 Figure 5.2.1 shows the block diagram of Timer A. Explanation of relevant registers to Timer A is described below. However, for the following registers, refer to the relevant section:

• Up-down register (address 44 Fig. 5.2.1 Block diagram of Timer A Data bus (odd) Data bus (even) f 2 f 16 f 64 f 512 Count source Timer mode One- shot pulse mode PWM mode Polarity switching Timer mode (Gate function) Event counter mode Trigger Count start bit Down-count Up-down bit ( Low-order 8 bits ) (High-order 8 bits) Timer Ai reload register (16) Timer Ai counter(16) Timer Ai interrupt request bit Up-count/down-count switching (Always down-count except for event counter mode) Toggle F.F. Pulse output function select bit TAi IN TAi OUT select bits

7702/7703 Group User’s Manual5–4

5.2.1 Counter and reload register (timer Ai register)

Each of timer Ai counter and reload register consists of 16 bits. The counter down-counts each time the count source is input. In the event counter mode, it can also function as an up-counter. The reload register is used to store the initial value of the counter. When the counter underflows or overflows, the reload register’s contents are reloaded into the counter. Values are set to the counter and reload register by writing a value to the timer Ai register. Table 5.2.1 lists the memory assignment of the timer Ai register. The value written into the timer Ai register when counting is not in progress is set to the counter and reload register. The value written into the timer Ai register when counting is in progress is set to only the reload register. In this case, the reload register’s updated contents are transferred to the counter at the next reload time. The value got when reading out the timer Ai register varies according to the operating mode. Table 5.2.2 lists reading and writing from and to the timer Ai register. Table 5.2.2 Reading and writing from and to timer Ai register Write <During counting> Written to only reload register. <When not counting> Written to both counter and reload register. Operating mode Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode Note: When reset, the contents of the timer Ai register are undefined. Notes 1:Also refer to “[Precautions when operating in timer mode]” and “[Precautions when oper- ating in event counter mode].” 2:When reading and writing to/from the timer Ai register, perform them in an unit of 16 bits. Read Counter value is read out. (Note 1) Undefined value is read out. Table 5.2.1 Memory assignment of timer Ai register Timer Ai register High-order byte Low-order byte Timer A0 register Address 4716 Address 4616 Timer A1 register Address 4916 Address 4816 Timer A2 register Address 4B16 Address 4A16 Timer A3 register Address 4D16 Address 4C16 Timer A4 register Address 4F16 Address 4E16

7702/7703 Group User’s Manual 5–5

5.2.2 Count start register

This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure 5.2.2 shows the structure of the count start register. Bit Timer B2 count start bit Timer B1 count start bit Timer B0 count start bit Timer A4 count start bit Timer A3 count start bit Timer A2 count start bit Timer A1 count start bit Timer A0 count start bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) 0 : Stop counting 1 : Start counting RW RW RW RW RW RW RW RW : Bits 7 to 5 are not used for Timer A. Fig. 5.2.2 Structure of count start register

7702/7703 Group User’s Manual5–6

5.2.3 Timer Ai mode register

Figure 5.2.3 shows the structure of the timer Ai mode register. Operating mode select bits are used to select the operating mode of timer Ai. Bits 2 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. Fig. 5.2.3 Structure of timer Ai mode register Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot pulse mode 1 1 : Pulse width modulation (PWM) mode b1 b0 These bits have different functions according to the operating mode. Operating mode select bits 0 RW RW RW RW RW RW RW RW

7702/7703 Group User’s Manual 5–7

5.2.4 Timer Ai interrupt control register

Figure 5.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” Fig. 5.2.4 Structure of timer Ai interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select a timer Ai interrupt’s priority level. When using timer Ai interrupts, select priority levels 1 to 7. When a timer Ai interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable timer Ai interrupts, set these bits to “000 2” (level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when the timer Ai interrupt request occurs. This bit is automatically cleared to “0” when the timer Ai interrupt request is accepted. This bit can be set to “1” or “0” by software. b7 b6 b5 b4 b3 b2 b1 b0 Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned. Note: Use the SEB or CLB instruction to set each interrupt control register. Timer Ai interrupt control registers (i = 0 to 4) (Addresses 7516 to 7916)

7702/7703 Group User’s Manual5–8

5.2.5 Port P5 and port P6 direction registers

The I/O pins of Timers A0 to A3 are shared with port P5, and the I/O pins of Timer A4 are shared with port P6. When using these pins as Timer Ai’s input pins, set the corresponding bits of the port P5 and port P6 direction registers to “0” to set these ports for the input mode. When used as Timer Ai’s output pins, these pins are forcibly set to output pins of Timer Ai regardless of the direction registers’s contents. Figure 5.2.5 shows the relationship between the port P5 and port P6 direction registers and the Timer Ai’s I/O pins. Fig. 5.2.5 Relationship between port P5 and port P6 direction registers and Timer Ai’s I/O pins Bit Correspondingpin name Functions TA0 OUT pin TA1 OUT pin TA1 IN pin TA2 OUT pin TA3 OUT pin 0: Input mode 1: Output mode When using these pins as Timer Ai’s input pins, set the corresponding bits to “0.” TA2 IN pin Port P5 direction register (Address D16) b1 b0b2b3b4b5b6b7 TA0 IN pin TA3 IN pin At reset RW TA4 OUT pin INT0 pin INT1 pin INT2 pin TB1 IN pin TB0 IN pin Port P6 direction register (Address 1016) b1 b0b2b3b4b5b6b7 TA4 IN pin TB2 IN pin RW : Bits 7 to 2 are not used for Timer A. Corresponding pin name FunctionsBit At reset 0: Input mode 1: Output mode When using these pins as Timer Ai’s input pins, set the corresponding bits to “0.” RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

7702/7703 Group User’s Manual 5–9 shows the structures of the timer Ai mode register and timer Ai register in the timer mode. Table 5.3.1 Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request occurrence timing TAiIN pin function TAiOUT pin function Read from timer Ai register Write to timer Ai register Specifications f 2, f16, f64, or f512

• Down-count
• When the counter underflows, reload register’s contents are reloaded and counting continues. When count start bit is set to “1.” When count start bit is cleared to “0.” When the counter underflows. Programmable I/O port or gate input Programmable I/O port or pulse output Counter value can be read out. l While counting is stopped When a value is written to timer Ai register, it is written to both reload register and counter. l While counting is in progress When a value is written to timer Ai register, it is written to only reload register. (Transferred to counter at next reload timing.) n : Timer Ai register setting value (n + 1)

7702/7703 Group User’s Manual5–10 Fig. 5.3.1 Structures of timer Ai mode register and timer Ai register in timer mode b7 b0 b7 b0 (b15) (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 These bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by n + 1. When reading, the register indicates the counter value. Undefined RW Gate function select bits Pulse output function select bit Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 0 0 : Timer mode 0 : No pulse output (TAiOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b4 b3 0 0 : No gate function 0 1 : (TAiIN pin functions as a prog- rammable I/O port.) 1 0 : Gate function (Counter counts only while TAiIN pin’s input signal is “L” level.) 1 1 : Gate function (Counter counts only while TAiIN pin’s input signal is “H” level.) Bit At reset RW 0 RW 0 RW 0 RW 3 0 RW 0 RW 5 0 RW 0 RW 0 RW Fix this bit to “0” in the timer mode.

7702/7703 Group User’s Manual 5–11

5.3.1 Setting for timer mode

Note that when using interrupts, set up to enable the interrupts. For details, refer to section “Chapter 4. INTERRUPTS.” Fig. 5.3.2 Initial setting example for registers relevant to timer mode (1) Note : Counter divides the count source frequency by n + 1. Setting divide ratio b7 b0 Can be set to “000016” to “FFFF16” (n). (b15) (b8) b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Continue to Figure 5.3.3 on next page. b7 b0 Pulse output function select bit 0: No pulse output. 1: Pulses output. Selecting timer mode and each function Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Count source select bits 0 0: f2 0 1: f16 1 0: f64 1 1: f512 b7 b6 Gate function select bits 0 0: 0 1: 1 0: Gate function (Counter counts only while TAiIN pin’s input signal is “L” level.) 1 1: Gate function (Counter counts only while TAiIN pin’s input signal is “H” level.) b4 b3 Selection of timer mode No gate function

7702/7703 Group User’s Manual5–12 Fig. 5.3.3 Initial setting example for registers relevant to timer mode (2) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Count starts Setting count start bit to “1.” b7 b0 Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Interrupt priority level select bits When using interrupts, set these bits to level 1–7. When disabling interrupts, set these bits to level 0. From preceding Figure 5.3.2. Setting port P5 and port P6 direction registers b7 b0 Port P5 direction register (Address D16) TA0 IN pin TA1 IN pin TA2 IN pin b7 b0 Port P6 direction register (Address 1016) When gate function is selected, set the bit corresponding to the TAiIN pin to “0.” TA4 IN pin TA3 IN pin

7702/7703 Group User’s Manual 5–13

5.3.2 Count source

In the timer mode, the count source select bits (bits 6 and 7 at addresses 5616 to 5A16) select the count source. Table 5.3.2 lists the count source frequency. Table 5.3.2 Count source frequency Count source select bits b7 b6 Count source frequency f(X IN) = 8 MHz f(X IN) = 16 MHz f(X IN) = 25 MHz 4 MHz 8 MHz 12.5 MHz 500 kHz 1 MHz 1.5625 MHz 125 kHz 250 kHz 390.625 kHz 15625 Hz 31250 Hz 48.8281 kHz Count source f f16 f64 f512

7702/7703 Group User’s Manual5–14

5.3.3 Operation in timer mode

À When the count start bit is set to “1,” the counter starts counting of the count source. \ When the counter underflows, the reload register’s contents are reloaded and counting continues. ´ The timer Ai interrupt request bit is set to “1” when the counter underflows in \ . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 5.3.4 shows an example of operation in the timer mode. Fig. 5.3.4 Example of operation in timer mode (without pulse output and gate functions) Stops counting. Restarts counting. FFFF 16 n 000016 Time Count start bit Timer Ai interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. “0” “0” 1 / fi 5 (n+1) fi = frequency of count source 2, f16, f64, f512 ) Cleared to “0” by software.Set to “1” by software.

7702/7703 Group User’s Manual 5–15

5.3.4 Select function

The following describes the selective gate and pulse output functions. (1) Gate function The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 5616 to 5A16 ) to “102” or “112.” The gate function makes it possible to start or stop counting depending on the TAiIN pin’s input signal. Table 5.3.3 lists the count valid levels. Figure 5.3.5 shows an example of operation selecting the gate function. When selecting the gate function, set the port P5 and port P6 direction registers’ bits which correspond to the TAi IN pin for the input mode. Additionally, make sure that the TAiIN pin’s input signal has a pulse width equal to or more than two cycles of the count source. Table 5.3.3 Count valid levels Gate function select bits Count valid level (Duration when counter counts) b4 b3 1 0 While TAi IN pin’s input signal is “L” level 1 1 While TAi IN pin’s input signal is “H” level Note:The counter does not count while the TAiIN pin’s input signal is not at the count valid level.

7702/7703 Group User’s Manual5–16 n 000016 Time “1” “1” “0” “0” À Starts counting. n = Reload register’s contents Counter contents (Hex.) \ Stops counting. Set to “1” by software. Count start bit TAiIN pin’s input signal Count valid level Timer Ai interrupt request bit Cleared to “0” when interrupt request is accepted or cleared by software. À The counter counts when the count start bit = “1” and the TAi IN pin’s input signal is at the count valid level. \ The counter stops counting while the TAiIN pin’s input signal is not at the count valid level, and the counter value is retained. Invalid level Fig. 5.3.5 Example of operation selecting gate function

7702/7703 Group User’s Manual 5–17 (2) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 5616 to 5A16) to “1.” When this function is selected, the TAiOUT pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 and port P6 direction registers. The TAiOUT pin outputs pulses of which polarity is inverted each time the counter underflows. When the count start bit (address 40 16) is “0” (count stopped), the TAiOUT pin outputs “L” level. Figure 5.3.6 shows an example of operation selecting the pulse output function. Fig. 5.3.6 Example of operation selecting pulse output function FFFF 16 n 000016 Time Count start bit Timer Ai interrupt request bit “1” “1” counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Pulse output from TAiout pin “H” “0” “L” “0” Set to “1” by software.Cleared to “0” by software. Starts counting. Restarts counting.

7702/7703 Group User’s Manual5–18 [Precautions when operating in timer mode] By reading the timer Ai register, the counter value can be read out at any timing while counting is in progress. However, if the timer Ai register is read at the reload timing shown in Figure 5.3.7, the value “FFFF 16” is read out. When reading the timer Ai register after setting a value to the register while counting is not in progress and before the counter starts counting, the set value is read out correctly. Fig. 5.3.7 Reading timer Ai register 210 n n – 1Counter value (Hex.) 21 0 FFFF n – 1Read value (Hex.) Reload Timen = Reload register’s contents

7702/7703 Group User’s Manual 5–19 (n + 1) n: Timer Ai register setting value structures of the timer Ai mode register and timer Ai register in the event counter mode. Table 5.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing function) (FFFF 16 – n + 1) Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request occurrence timing TAiIN pin function TAiOUT pin function Read from timer Ai register Write to timer Ai register Specifications l External signal input to the TAiIN pin l The count source’s valid edge can be selected between the falling and the rising edges by software. l Up-count or down-count can be switched by external signal or software. l When the counter overflows or underflows, reload register’s contents are reloaded and counting continues. l For down-count l For up-count When count start bit is set to “1.” When count start bit is cleared to “0.” When the counter overflows or underflows. Count source input Programmable I/O port, pulse output, or up-count/down-count switch signal input Counter value can be read out. l While counting is stopped When a value is written to timer Ai register, it is written to both reload register and counter. l While counting is in progress When a value is written to timer Ai register, it is written to only reload register. (Transferred to counter at next reload time.)

7702/7703 Group User’s Manual5–20 Interrupt request occurrence timing TAjIN, TAjOUT (j = 2 to 4) pin function Read from timer Aj register Write to timer Aj register Table 5.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function with timers A2, A3, and A4) (n + 1) n: Timer Aj register setting value Specifications External signal (two-phase pulse) input to the TAjIN or TAjOUT pin (j = 2 to 4) l Up-count or down-count can be switched by external signal (two- phase pulse). l When the counter overflows or underflows, reload register’s contents are reloaded and counting is continued. l For down-count l For up-count When count start bit is set to “1.” When count start bit is cleared to “0.” When the counter overflows or underflows. Two-phase pulse input Counter value can be read out. l While counting is stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter. l While counting is in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) (FFFF 16 – n + 1)

7702/7703 Group User’s Manual 5–21 Fig. 5.4.1 Structures of timer Ai mode register and timer Ai register in event counter mode b7 b6 b5 b4 b3 b2 b1 b0 00 1 Bit Up-down switching factor select bit Count polarity select bit Bit name These bits are ignored in event counter mode. Fix this bit to “0” in event counter mode. 5 : It may be either “0” or “1.” Functions 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 : Contents of up-down register 1 : Input signal to TAi OUT pin At reset RW Pulse output function select bit Operating mode select bits 0 : No pulse output (TAiOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) 0 1 : Event counter mode b1 b0 RW RW RW RW RW RW RW RW Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) b7 b0 b7 b0 (b15) (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) RW 15 to 0 Bit Functions At reset RWThese bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by n + 1 when down-counting, or by FFFF 16 – n + 1 when up-counting. When reading, the register indicates the counter value. Undefined

7702/7703 Group User’s Manual5–22

5.4.1 Setting for event counter mode

Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Fig. 5.4.2 Initial setting example for registers relevant to event counter mode (1) ] The counter divides the count source frequency by n + 1 when down-counting, or by FFFF16 –n + 1 when up- counting. Continue to Figure 5.4.3 on next page. b7 b0 010 Selecting event counter mode and each function Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Pulse output function select bit 0: No pulse output 1: Pulse output Count polarity select bit 0: Counts at falling edge of external signal. 1: Counts at rising edge of external signal. Up-down switching factor select bit 0: Contents of up-down register 1: Input signal to TAi OUT pin 5 : It may be either “0” or “1.” Selection of event counter mode Setting divide ratio b7 b0 Can be set to “000016” to “FFFF 16” (n). (b15) (b8) b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) b7 b0 Setting up–down register Up–down register (Address 4416) Timer A0 up–down bit Timer A1 up–down bit Timer A2 up–down bit Timer A3 up–down bit Timer A4 up–down bit Timer A2 two–phase pulse signal processing select bit Timer A3 two–phase pulse signal processing select bit Timer A4 two–phase pulse signal processing select bit Set the corresponding up–down bit when the contents of the up-down register are selected as the up-down switching factor. Set the corresponding bit to “1” when the two–phase pulse signal processing function is selected for timers A2 to A4. 0: Down–count 1: Up–count 0: Two–phase pulse signal processing function disabled 1: Two–phase pulse signal processing function enabled

7702/7703 Group User’s Manual 5–23 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Setting the count start bit to “1” b7 b0 Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Count starts From preceding Figure 5.4.2. Setting port P5 and port P6 direction registers b7 b0 Port P5 direction register (Address D16) TA0 IN pin TA1 OUT pin TA1 IN pin TA2 OUT pin TA2 IN pin TA3 OUT pin b7 b0 Port P6 direction register (Address 1016) Clear the bit corresponding to the TAiIN pin to “0.” When selecting the TAiOUT pin’s input signal as up-down switching factor, set the bit corresponding to the TAiOUT pin to “0.” When selecting the two–phase pulse signal processing function, set the bit corresponding to the TAjOUT (j = 2 to 4) pin to “0.” TA4 OUT pin TA4 IN pin TA3 IN pin TA0 OUT pin Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 75 16 to 7916) Interrupt priority level select bits When using interrupts, set these bits to level 1-7. When disabling interrupts, set these bits to level 0. Fig. 5.4.3 Initial setting example for registers relevant to event counter mode (2)

7702/7703 Group User’s Manual5–24 n 000016 Time Count start bit“1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Up-down bit“1” Note: The above applies when the up-down bit’s contents are selected as the up-down switching factor (i.e., up-down switching factor select bit = “0” ). “0” “0” “0” Set to “1” by software.

5.4.2 Operation in event counter mode

À When the count start bit is set to “1,” the counter starts counting of the count source. \` The counter counts the count source’s valid edges. ´ When the counter underflows or overflows, the reload register’s contents are reloaded and counting continues. ˆ The timer Ai interrupt request bit is set to “1” when the counter underflows or overflows in ´ . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 5.4.4 shows an example of operation in the event counter mode. Fig. 5.4.4 Example of operation in event counter mode (without pulse output function and two-phase pulse signal processing function)

7702/7703 Group User’s Manual 5–25 (1) Switching between up-count and down-count The up-down register (address 4416) or the input signal from the TAiOUT pin is used to switch the up- count from and to the down-count. This switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 5616 to 5A16) is “0,” and by the input signal from the TAiOUT pin when the up-down switching factor select bit is “1.” When switching the up-count/down-count, this switching is actually performed when the count source’s next valid edge is input. l Switching by up-down bit The counter down-counts when the up-down bit is “0,” and up-counts when the up-down bit is “1.” Figure 5.4.5 shows the structure of the up-down register. l Switching by TAi OUT pin’s input signal The counter down-counts when the TAiOUT pin’s input signal is at “L” level, and up-counts when the TAiOUT pin’s input signal is at “H” level. When using the TAiOUT pin input signal to switch the up-count/down-count, set the port P5 and P6 direction registers’ bits which correspond to the TAiOUT pin for the input mode. Fig. 5.4.5 Structure of up-down register Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Up-down register (Address 4416) Timer A4 up-down bit Timer A3 up-down bit Timer A2 up-down bit Timer A1 up-down bit Timer A0 up-down bit Timer A2 two-phase pulse signal processing select bit (Note) Timer A3 two-phase pulse signal processing select bit (Note) Timer A4 two-phase pulse signal processing select bit (Note) 0 : Down-count 1 : Up-count This function is valid when the contents of the up-down register are selected as the up-down switching factor. 0 : Disabled Two-phase pulse signal processing function 1 : Enabled Two-phase pulse signal processing function When not using the two-phase pulse signal processing function, make sure to set the bit to “0.” The value is “0” at reading. Note: Use the LDM or STA instruction when writing to bits 5 to 7. RW RW RW RW RW WO WO WO

7702/7703 Group User’s Manual5–26

5.4.3 Select functions

The following describes the selective pulse output, and two-phase pulse signal processing functions. (1) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 5616 to 5A16) to “1.” When this function is selected, the TAiOUT pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 and port P6 direction registers. The TAiOUT pin outputs pulses of which polarity is inverted each time the counter underflows or overflows. (Refer to Figure 5.3.6.) When the count start bit (address 4016) is “0” (count stopped), the TAiOUT pin outputs “L” level.

7702/7703 Group User’s Manual 5–27 (2) Two-phase pulse signal processing function (Timers A2 to A4) For timers A2 to A4, the two-phase pulse signal processing function is selected by setting the two- phase pulse signal processing select bits (bits 5 to 7 at address 4416) to “1.” (Refer to Figure 5.4.5.) Figure 5.4.6 shows the timer A2, A3, and A4 mode registers when the two-phase pulse signal processing function is selected. With timers selecting the two-phase pulse signal processing function, the timer counts two kinds of pulses of which phases differ by 90 degrees. There are two types of the two-phase pulse signal processing: normal processing and quadruple processing. In timers A2 and A3, normal processing is performed; in timer A4, quadruple processing is performed. For some bits of the port P5 and P6 direction registers correspond to pins used for two-phase pulse input, set these bits for the input mode. l Normal processing The timer up-counts the rising edges to the TAkIN pin when the phase has the relationship that the TAk IN pin’s input signal level goes from “L” to “H” while the TAkOUT (k = 2 and 3) pin’s input signal is “H” level. The timer down-counts the falling edges to the TAkIN pin when the phase has the relationship that the TAkIN pin’s input signal level goes from “H” to “L” while the TAkOUT pin’s input signal is “H” level. (Refer to Figure 5.4.7.) Fig. 5.4.6 Timer A2, A3, and A4 mode registers when two-phase pulse signal processing function is selected 100 0 0 1 Timer A2 mode register (Address 5816) Timer A3 mode register (Address 5916) Timer A4 mode register (Address 5A16) b7 b6 b5 b4 b3 b2 b1 b0 5 : It may be either “0” or “1.” Fig. 5.4.7 Normal processing TAkOUT TAkIN (k=2, 3) “H” “H” “L” Up count +1 +1 +1 –1 –1 –1 Down- count “L” Up- count Up- count Up- count Down- count Down- count

7702/7703 Group User’s Manual5–28 The timer up-counts all rising and falling edges to the TA4OUT and TA4IN pins when the phase has the relationship that the TA4IN pin’s input signal level goes from “L” to “H” while the TA4OUT pin’s input signal is “H” level. The timer down-counts all rising and falling edges to the TA4OUT and TA4IN pins when the phase has the relationship that the TA4IN pin’s input signal level goes from “H” to “L” while the TA4OUT pin’s input signal is “H” level. (Refer to Figure 5.4.8.) Table 5.4.3 lists the input signals to the TA4 OUT and TA4IN pins when the quadruple processing is selected. Table 5.4.3 TA4 OUT and TA4 IN pins’ input signals when quadruple operation is selected Input signal to TA4OUT pin Input signal to TA4IN pin “H” level “L” level Rising Falling “H” level “L” level Rising Falling Rising Falling “L” level “H” level Falling Rising “H” level “L” level Up-count Down-count Fig. 5.4.8 Quadruple processing TA4 OUT TA4 IN “H” “H” “L” “L” Up-count all edges Down-count all edges Up-count all edges Down-count all edges

7702/7703 Group User’s Manual 5–29 [Precautions when operating in event counter mode] 1. By reading the timer Ai register, the counter value can be read out at any timing while counting is in progress. However, when the timer Ai register is read at the reload timing shown in Figure 5.4.9, a value “FFFF16” (at the underflow) or “000016” (at the overflow) is read out. When reading the timer Ai register after setting a value to the register while counting is not in progress and before the counter starts counting, the set value is read out correctly. Fig. 5.4.9 Reading timer Ai register 2. The TAiOUT pin is used for all functions listed below. Accordingly, only one of these functions can be selected for each timer.

• Switching between up-count and down-count by TAiOUT pin’s input signal
• Pulse output function
• Two-phase pulse signal processing function for timers A2 to A4 210 n n – 1 Counter value (Hex.)

210 FFFF n – 1

(Hex.) Reload Time n = Reload register’s contents (1) For down-count FFFD FFFE FFFF n n + 1 FFFD FFFE FFFF 0000 n + 1 (2) For up-count Counter value (Hex.) Read value (Hex.) Reload Time n = Reload register’s contents

7702/7703 Group User’s Manual5–30 In this mode, the timer outputs a pulse which has an arbitrary width once. (Refer to Table 5.5.1.) When a trigger occurs, the timer outputs “H” level from the TAiOUT pin for an arbitrary time. Figure 5.5.1 shows the structures of the timer Ai mode register and timer Ai register in the one-shot pulse mode. Table 5.5.1 Specifications of one-shot pulse mode [s] n : Timer Ai register setting value Item Count source Count operation Output pulse width (“H”) Count start condition Count stop condition Interrupt request occurrence timing TAiIN pin function TAiOUT pin function Read from timer Ai register Write to timer Ai register Specifications f 2, f16, f64, or f512 l Down-count l When the counter value becomes “000016,” reload register’s con- tents are reloaded and counting stops. l If a trigger occurs during counting, reload register’s contents are reloaded then and counting continues. l When a trigger occurs. (Note) l Internal or external trigger can be selected by software. l When the counter value becomes “0000 l When count start bit is cleared to “0” When counting stops. Programmable I/O port or trigger input One-shot pulse output An undefined value is read out. l While counting is stopped When a value is written to timer Ai register, it is written to both reload register and counter. l While counting is in progress When a value is written to timer Ai register, it is written to only reload register. (Transferred to counter at next reload time.) Note:The trigger is generated with the count start bit = “1.” n fi

7702/7703 Group User’s Manual 5–31 (b15) (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 These bits can be set to “000116” to “FFFF16.” Assuming that the set value = n, the “H” level width of the one-shot pulse output from the TAi OUT pin is expressed as follows : n / fi. Undefined fi: Frequency of count source (f2, f16, f64, or f512) WO Trigger select bits Fix this bit to “1” in one-shot pulse mode. Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 1 0 : One-shot pulse mode 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b4 b3 Fix this bit to “0” in one-shot pulse mode. 10 1 0 0 : Writing “1” to one-shot start bit 0 1 : IN pin functions as a progra- mmable I/O port.) 1 0 : Falling edge of TAiIN pin’s input signal 1 1 : Rising edge of TAiIN pin’s input signal Bit At reset RW RW RW RW RW RW RW RW RW Operating mode select bits Fig. 5.5.1 Structures of timer Ai mode register and timer Ai register in one-shot pulse mode (TAi

7702/7703 Group User’s Manual5–32

5.5.1 Setting for one-shot pulse mode

Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Fig. 5.5.2 Initial setting example for registers relevant to one-shot pulse mode (1) Continue to Figure 5.5.3. Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Interrupt priority level select bits When using interrupts, set these bits to level 1-7. When disabling interrupts, set these bits to level 0. b7 b0 100 Selecting one-shot pulse mode and each function Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)1 Trigger select bits 0 0 : 0 1 : 1 0 : Falling of TAi IN pin’s input signal: External trigger 1 1 : Rising of TAiIN pin’s input signal: External trigger b4 b3 Count source select bits 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6 Selection of one-shot pulse mode Setting “H” level width of one-shot pulse b7 b0 Can be set to “000116” to “FFFF16” (n). (b15) (b8) b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) “H” level width = Writing “1” to one-shot start bit: Internal trigger fi Note. n

7702/7703 Group User’s Manual 5–33 Fig. 5.5.3 Initial setting example for registers relevant to one-shot pulse mode (2) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Count starts Trigger generated Trigger input to TAiIN pin When internal trigger is selected When external trigger is selected From preceding Figure 5.5.2. b7 b0 One-shot start register (Address 4216) Setting one-shot start bit to “1” Timer A0 one-shot start bit Timer A1 one-shot start bit Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit Setting count start bit to “1” b7 b0 Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count start register (Address 4016) b7 b0 Port P5 direction register (Address D16) Setting port P5 and port P6 direction registers TA0 IN pin TA1 IN pin TA2 IN pin TA3 IN pin Port P6 direction register (Address 10 16) TA4 IN pin b7 b0 Set the corresponding bit to “0.” Setting count start bit to “1” b7 b0 Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count start register (Address 4016)

7702/7703 Group User’s Manual5–34

5.5.2 Count source

In the one-shot pulse mode, the count source select bits (bits 6 and 7 at addresses 5616 to 5A16) select the count source. Table 5.5.2 lists the count source frequency. Table 5.5.2 Count source frequency Count source select bits b7 b6 Count source frequency f(X IN) = 8 MHz f(X IN) = 16 MHz f(X IN) = 25 MHz 4 MHz 8 MHz 12.5 MHz 500 kHz 1 MHz 1.5625 MHz 125 kHz 250 kHz 390.625 kHz 15625 Hz 31250 Hz 48.8281 kHz Count source f f16 f64 f512

7702/7703 Group User’s Manual 5–35

5.5.3 Trigger

The counter is enabled for counting when the count start bit (address 4016) is set to “1.” The counter starts counting when a trigger is generated after it has been enabled. An internal or an external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 5616 to 5A16) are “002” or “012”; an external trigger is selected when the bits are “102” or “112.” If a trigger is generated during counting, the reload register’s contents are reloaded and the counter continues counting. If generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timer’s count source or more has passed between the previous generated trigger and a new generated trigger. (1) When selecting internal trigger A trigger is generated when writing “1” to the one-shot start bit (address 42 16). Figure 5.5.4 shows the structure of the one-shot start register. (2) When selecting external trigger A trigger is generated at the falling of the TAiIN pin’s input signal when bit 3 at addresses 5616 to 5A16 is “0,” or at its rising when bit 3 is “1.” When using an external trigger, set the port P5 and P6 direction registers’ bits which correspond to the TAi IN pins for the input mode. Fig. 5.5.4 Structure of one-shot start register Bit 7 to 5Nothing is assigned. Timer A4 one-shot start bit Timer A3 one-shot start bit Timer A2 one-shot start bit Timer A1 one-shot start bit Timer A0 one-shot start bit Bit name At reset Undefined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register (Address 4216) 1 : Start outputting one-shot pulse (valid when selecting internal trigger.) The value is “0” at reading. WO WO WO WO WO

7702/7703 Group User’s Manual5–36

5.5.4 Operation in one-shot pulse mode

À When the one-shot pulse mode is selected with the operating mode select bits, the TAiOUT pin outputs “L” level. \ When the count start bit is set to “1,” the counter is enabled for counting. After that, counting starts when a trigger is generated. ´ When the counter starts counting, the TAiOUT pin outputs “H” level. ˆ When the counter value becomes “000016,” the output from the TAiOUT pin becomes “L” level. Additionally, the reload register’s contents are reloaded and the counter stops counting there. ˜ Simultaneously at ˆ , the timer Ai interrupt request bit is set to “1.” This interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 5.5.5 shows an example of operation in the one-shot pulse mode. When a trigger is generated after ˆ above, the counter and TAi OUT pin perform the same operations beginning from \ again. Furthermore, if a trigger is generated during counting, the counter down-counts once after this generated new trigger, and it continues counting with the reload register’s contents reloaded. If generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timer’s count source or more has passed between the previous generated trigger and a new generated trigger. The one-shot pulse output from the TAi OUT pin can be disabled by clearing the timer Ai mode register’s bit 2 to “0.” Accordingly, timer Ai can be also used as an internal one-shot timer that does not perform the pulse output. In this case, the TAiOUT pin functions as a programmable I/O port.

7702/7703 Group User’s Manual 5–37 Fig. 5.5.5 Example of operation in one-shot pulse mode (selecting external trigger) Stops counting. Starts counting. FFFF 16 n 000116 Time À Count start bit Timer Ai interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. TAiIN pin input signal “H” One-shot pulse output from TAiOUT pin “H” \ Trigger during counting 1 / fi 5 (n) Note: The above applies when an external trigger (rising of TAiIN pin’s input signal) is selected. “0” “L” “L” “0” 1 / fi 5 (n+1) À When the count start bit = “0” (counting stopped), the TAiOUT pin outputs “L” level. \ When a trigger is generated during counting, the counter counts the count source n + 1 times after a new trigger is generated. fi = Frequency of count source (f2, f16, f64, or f512) Stops counting. Reloaded Reloaded

7702/7703 Group User’s Manual5–38 [Precautions when operating in one-shot pulse mode] 1. If the count start bit is cleared to “0” during counting, the counter stops counting and the reload register’s contents are reloaded into the counter, and the TAiOUT pin’s output level becomes “L.” At the same time, the timer Ai interrupt request bit is set to “1.” 2. A one-shot pulse is output synchronously with an internally generated count source. Accordingly, when selecting an external trigger, there will be a delay equivalent to one cycle of count source at maximum from when a trigger is input to the TAiIN pin till when a one-shot pulse is output. Fig. 5.5.6 Output delay in one-shot pulse output 3. When setting the timer’s operating mode in one of the followings, the timer Ai interrupt request bit is set to “1.” l When the one-shot pulse mode is selected after a reset l When the operating mode is switched from the timer mode to the one-shot pulse mode l When the operating mode is switched from the event counter mode to the one-shot pulse mode Therefore, when using the timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt request bit to “0” after above setting. 4. Do not set “0000 16” to the timer Ai register. Note: The above applies when an external trigger (falling of TAiIN pin’s input signal) is selected. TAiIN pin’s input signal “H” “L” Count source Trigger input Starts outputting of one-shot pulse One-shot pulse output from TAiOUT pin Output delay

7702/7703 Group User’s Manual 5–39 In this mode, the timer continuously outputs pulses which have an arbitrary width. (Refer to Table 5.6.1.) Figure 5.6.1 shows the structures of the timer Ai mode register and timer Ai register in the PWM mode. Table 5.6.1 Specifications of PWM mode Item Count source Count operation PMW period/“H” level width Count start condition Count stop condition Interrupt request occurrence timing TAiIN pin function TAiOUT pin function Read from timer Ai register Write to timer Ai register Specifications f2, f16, f64, or f512 l Down-count (operating as an 8-bit or 16-bit pulse width modulator) l Reload register’s contents are reloaded at rising of PWM pulse and counting continues. l A trigger generated during counting does not affect the counting. <16-bit pulse width modulator> “H” level width = [s] n: Timer Ai register setting value <8-bit pulse width modulator> “H” level width = [s] m: Timer Ai register low-order 8 bits setting value n: Timer Ai register high-order 8 bits setting value l When a trigger is generated. (Note) l Internal or external trigger can be selected by software. When count start bit is cleared to “0.” At falling of PWM pulse Programmable I/O port or trigger input PWM pulse output An undefined value is read out. l While counting is stopped When a value is written to timer Ai register, it is written to both reload register and counter. l While counting is in progress When a value is written to timer Ai register, it is written to only reload register. (Transferred to counter at next reload time.) Period = [s](216 – 1) fi Period = [s](m + 1)(28 – 1) fi n fi n(m + 1) fi Note: The trigger is generated with the count start bit = “1.”

7702/7703 Group User’s Manual5–40 Fig. 5.6.1 Structures of timer Ai mode registers and timer Ai registers in PWM mode b7 b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0These bits can be set to “000016” to “FFFE16.” Assuming that the set value = n, the “H” level width of the PWM pulse output from the TAiOUT pin is expressed as follows: PWM pulse’s period is expressed as follows: Undefined <When operating as a 16-bit pulse width modulator> (b15) (b8) WO n fi n16 – 1 fi fi: Frequency of count source (f2, f16, f64, or f512) <When operating as an 8-bit pulse width modulator> (b15) b7 b0 b7 b0 (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 7 to 0 15 to 8 Undefined Undefined These bits can be set to “0016” to “FF16.” Assuming that the set value = m, PWM pulse’s period output from the TAiOUT pin is expressed as follows:(m + 1)(28 – 1) fi WO These bits can be set to “0016” to “FE16.” Assuming that the set value = n, the “H” level width of the PWM pulse output from the TAi OUT pin is expressed as follows: n(m + 1) fi WO fi: Frequency of count source (f2, f16, f64, or f512) b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits 11 1 At reset RW Trigger select bits Fix this bit to “1” in PWM mode. Operating mode select bits Bit name Functions 1 1 : PWM mode b1 b0 b4 b3 16/8-bit PWM mode select bit 0 0 : Writing “1” to count start bit 0 1 : (TAiIN pin functions as a pro- grammable I/O port.) 1 0 : Falling edge of TAiIN pin’s input signal 1 1 : Rising edge of TAiIN pin’s input signal Bit 0 : As a 16-bit pulse width modulator 1 : As an 8-bit pulse width modulator RW RW RW RW RW RW RW RW

7702/7703 Group User’s Manual 5–41

5.6.1 Setting for PWM mode

Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Fig. 5.6.2 Initial setting example for registers relevant to PWM mode (1) Note: When operating as 8-bit pulse width modulator (m+1) (28 – 1) fi n(m+1) fi fi : Frequency of count source However, if n = “0016”, the pulse width modulator does not operate and the TAiOUT pin outputs “L” level. At this time, no timer Ai request occurs. b7 b0 Count source select bits 0 0 : f 0 1 : f16 1 0 : f64 1 1 : f512 Selecting PWM mode and each function Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) b7 b6 16/8-bit PWM mode select bit 0 : Operates as 16-bit pulse width modulator 1 : Operates as 8-bit pulse width modulator Continue to Figure 5.6.3. Trigger select bits 0 0 : 0 1 : 1 0 : Falling of TAi IN pin’s input signal 1 1 : Rising of TAiIN pin’s input signal b3b4 Selection of PWM mode Setting PWM pulse’s period and “H” level width b7 b0 Can be set to “000016” to “FFFE16” (n) (b15) (b8) b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Note: When operating as 16-bit pulse width modulator (216 – 1) fi n fi fi : Frequency of count source However, if n = “000016”, the pulse width modulator does not operate and the TAiOUT pin outputs “L” level. At this time, no timer Ai request occurs. l When operating as 16-bit pulse width modulator b7 b0 Can be set to “0016” to “FF16” (m) (b15) (b8) b7 b0 l When operating as 8-bit pulse width modulator Can be set to “0016” to “FE16” (n) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Writing “1” to count start bit: Internal trigger : External trigger : External trigger Period = “H” level width = Period = “H” level width =

7702/7703 Group User’s Manual5–42 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Count starts Trigger input to TAiIN pin When external trigger is selected When internal trigger is selected From preceding Figure5.6.2. Trigger generated b7 b0 Port P5 direction register (Address D 16) Setting port P5 and port P6 direction registers TA0 IN pin TA1 IN pin TA2 IN pin TA3 IN pin TA4 IN pin b7 b0 Clear the corresponding bit to “0.” Port P6 direction register (Address 10 16) Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 75 16 to 7916) Interrupt priority level select bits When using interrupts, set these bits to level 1 – 7. When disabling interrupts, set these bits to level 0. Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer A0 count start bit Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer A0 count start bit Fig. 5.6.3 Initial setting example for registers relevant to PWM mode (2)

7702/7703 Group User’s Manual 5–43

5.6.2 Count source

In the PWM mode, the count source select bits (bits 6 and 7 at addresses 5616 to 5A16) select the count source. Table 5.6.2 lists the count source frequency. Table 5.6.2 Count source frequency Count source select bits b7 b6 Count source frequency f(X IN) = 8 MHz f(X IN) = 16 MHz f(X IN) = 25 MHz 4 MHz 8 MHz 12.5 MHz 500 kHz 1 MHz 1.5625 MHz 125 kHz 250 kHz 390.625 kHz 15625 Hz 31250 Hz 48.8281 kHz Count source f f16 f64 f512

5.6.3 Trigger

When a trigger is generated, the TAiOUT pin starts outputting PWM pulses. An internal or an external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 5616 to 5A16) are “002” or “012”; an external trigger is selected when the bits are “102” or “112.” A trigger generated during outputting of PWM pulses is ignored and it does not affect the pulse output operation. (1) When selecting internal trigger A trigger is generated when writing “1” to the count start bit (at address 4016). (2) When selecting external trigger A trigger is generated at the falling of the TAiIN pin’s input signal when bit 3 at addresses 5616 to 5A16 is “0,” or at its rising when bit 3 is “1.” However, the trigger input is accepted only when the count start bit is “1.” When using an external trigger, set the port P5 and P6 direction registers’ bits which correspond to the TAi IN pins for the input mode.

7702/7703 Group User’s Manual5–44

5.6.4 Operation in PWM mode

À When the PWM mode is selected with the operating mode select bits, the TAiOUT pin outputs “L” level. \` When a trigger is generated, the counter (pulse width modulator) starts counting and the TAiOUT pin outputs a PWM pulse (Notes 1 and 2). ´ The timer Ai interrupt request bit is set to “1” each time the PWM pulse level goes from “H” to “L.” The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. ˆ Each time a PWM pulse has been output for one period, the reload register’s contents are reloaded and the counter continues counting. The following explains operation of the pulse width modulator. [16-bit pulse width modulator] When the 16/8-bit PWM mode select bit is set to “0,” the counter operates as a 16-bit pulse width [8-bit pulse width modulator] When the 16/8-bit PWM mode select bit is set to “1,” the counter is divided into 8-bit halves. Then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit Notes 1: If a value “0000 16” is set into the timer Ai register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output from the TAiOUT pin remains “L” level. The timer Ai interrupt request does not occur. Similarly, if a value “0016” is set into the high-order 8 bits of the timer Ai register when the counter operates as an 8- bit pulse width modulator, the same is performed. 2: When the counter operates as an 8-bit pulse width modulator, the TAi OUT pin outputs “L” level of the PWM pulse which has the same width as set “H” level of the PWM pulse after a trigger generated. After that, the PWM pulse output starts from the TAi OUT pin.

7702/7703 Group User’s Manual 5–45 Fig. 5.6.4 Operation example of 16-bit pulse width modulator Fig. 5.6.5 Operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 1 / fi 5 (216 – 1) 1 / fi 5 (n) Count source TAiIN pin’s input signal PWM pulse output from TAiOUT pin Note: The above applies when reload register (n) = “000316” and an external trigger (rising of TAiIN pin’s input signal) is selected. Trigger is not generated by this signal. “H” “H” “L” “L” Timer Ai interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted or cleared by software. fi: Frequency of count source (f2, f16, f64, or f512) À When an arbitrary value is set to the timer Ai register after setting “000016” to it, the timing at which the PWM pulse goes “H” depends on the timing at which the new value is set. Note: The above applies when an external trigger (rising of TAiIN pin’s input signal) is selected. FFFE 16 n 000116 TAiIN pin’s input signal “H” Counter contents (Hex.) “L” “H” “L” (216 –1) – n PWM pulse output from TAiOUT pin “000016” is set to timer Ai register. “200016” is set to timer Ai register. 200016 “FFFE16” is set to timer Ai register. n = Reload register’s contents fi: Frequency of count source (f2, f16, f64, or f512) Restarts counting.Stops counting. Time À

7702/7703 Group User’s Manual5–46 Fig. 5.6.6 Operation example of 8-bit pulse width modulator À Count source TAiIN pin’s input signal PWM pulse output from TAiOUT pin Note: The above applies when the reload register’s high-order 8 bits (n) = “0216” and low-order 8 bits (m) = “0216” and an external trigger (falling of TAiIN pin input signal) is selected. “H” “H” “H” “L” “L” “L” “1” “0” Timer Ai interrupt request bit Cleared to “0” when interrupt request is accepted or cleared by software.fi: Frequency of count source (f2, f16, f64, or f512) À The 8-bit prescaler counts the count source. \ The 8-bit pulse width modulator counts the 8-bit prescaler’s underflow signal. \ 8-bit prescaler’s underflow signal 1 / fi 5 (m+1)

7702/7703 Group User’s Manual 5–47 Fig. 5.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) “H” “L” “H” “L” PWM pulse output from TAiOUT pin À Count source TAiIN pin’s input signal 0016 Prescaler's contents (Hex.) 0216 Time Stops counting. 0116 Counter’s contents (Hex.) 0416 0A16 Time À When an arbitrary value is set to the timer Ai register after setting “0016” to it, the timing at which the PWM pulse level goes “H” depends on the timing at which the new value is set. “000216” is set to timer Ai register. “0A0216” is set to timer Ai register. “040216” is set to timer Ai register. Restarts counting. Note: The above applies when an external trigger (falling of TAiIN pin’s input signal) is selected. fi: Frequency of count source (f2, f16, f64, or f512) m: Contents of reload register’s low-order 8 bits

7702/7703 Group User’s Manual5–48 [Precautions when operating in PWM mode] 1. If the count start bit is cleared to “0” while outputting PWM pulses, the counter stops counting. When the TAiOUT pin was outputting “H” level at that time, the output level becomes “L” and the timer Ai interrupt request bit is set to “1.” When the TAiOUT pin was outputting “L” level, the output level does not change and the timer Ai interrupt request does not occur. 2. When setting the timer’s operating mode in one of the followings, the timer Ai interrupt request bit is set to “1.” l When the PWM mode is selected after a reset l When the operating mode is switched from the timer mode to PWM mode l When the operating mode is switched from the event counter mode to the PWM mode Therefore, when using the timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt request bit to “0” after the above setting.

6.1 Overview

6.2 Block description

6.3 Timer mode

6.4 Event counter mode

6.5 Pulse period/pulse width mea-

7702/7703 Group User’s Manual6–2 Timer B consists of three counters (Timers B0 to B2) each equipped with a 16-bit reload function. Timers B0 to B2 have identical functions and operate independently of each other. Timers B1 and B2s’ function of the 7703 Group varies from the 7702 Group’s. Refer to “Chapter 20. 7703 GROUP .” Timer Bi (i = 0 to 2) has three operating modes listed below. l Timer mode The timer counts an internally generated count source. l Event counter mode The timer counts an external signal. l Pulse period/pulse width measurement mode The timer measures an external signal’s pulse period or pulse width. Figure 6.2.1 shows the block diagram of Timer B. Explanation of registers relevant to timer B is described below. 6.1 Overview 6.2 Block description Fig. 6.2.1 Block diagram of Timer B f 2 f 16 f 64 f 512 Count source select bits Timer mode Pulse period/Pulse width measurement mode Polarity switching and edge pulse generating circuit Event counter mode Count start bit Counter reset circuit Data bus (odd) Data bus (even) (Low-order 8 bits) (High-order 8 bits) Timer Bi reload register (16) Timer Bi counter (16) Timer Bi interrupt request bit TBi IN Timer Bi overflow flag (Valid in pulse period/pulse width measurement mode)

7702/7703 Group User’s Manual TIMER B 6–3

6.2.1 Counter and reload register (timer Bi register)

Each of timer Bi counter and reload register consists of 16 bits and has the following functions. (1) Functions in timer mode and event counter mode The counter down-counts each time count source is input. The reload register is used to store the initial value of the counter. When the counter underflows, the reload register’s contents are reloaded into the counter. Values are set to the counter and reload register by writing a value to the timer Bi register. Table 6.2.1 lists the memory assignment of the timer Bi register. The value written into the timer Bi register when the counting is not in progress is set to the counter and reload register. The value written into the timer Bi register when the counting is in progress is set to only the reload register. In this case, the reload register’s updated contents are transferred to the counter when the counter underflows next time. The counter value is read out by reading out the timer Bi register. Note: When reading and writing from/to the timer Bi register, perform them in an unit of 16 bits. For more information about the value got by reading the timer Bi register, refer to “[Precautions when operating in timer mode]” and “[Precautions when operating in event counter mode].” (2) Functions in pulse period/pulse width measurement mode The counter up-counts each time count source is input. The reload register is used to hold the pulse period or pulse width measurement result. When a valid edge is input to the TBi IN pin, the counter value is transferred to the reload register. In this mode, the value got by reading the timer Bi register is the reload register’s contents, so that the measurement result is obtained. Note: When reading from the timer Bi register, perform it in an unit of 16 bits. Timer Bi register Timer B0 register Timer B1 register Timer B2 register Low-order byte Address 50 Address 5216 Address 5416 High-order byte Address 51 Address 5316 Address 5516 Note: When reset, the contents of the timer Bi reg- ister are undefined. Table 6.2.1 Memory assignment of timer Bi registers

7702/7703 Group User’s Manual6–4

6.2.2 Count start register

This register is used to start and stop counting. Each bit of this register corresponds each timer. Figure 6.2.2 shows the structure of the count start register. Fig. 6.2.2 Structure of count start register Bit Timer B2 count start bit Timer B1 count start bit Timer B0 count start bit Timer A4 count start bit Timer A3 count start bit Timer A2 count start bit Timer A1 count start bit Timer A0 count start bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) 0 : Stop counting 1 : Start counting RW RW RW RW RW RW RW RW : Bits 0 to 4 are not used for Timer B.

7702/7703 Group User’s Manual TIMER B 6–5

6.2.3 Timer Bi mode register

Figure 6.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used to select the operating mode of timer Bi. Bits 2 and 3 and bits 5 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. Fig. 6.2.3 Structure of timer Bi mode register Nothing is assigned. These bits have different functions according to the operating mode. Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Not selected b1 b0 Bit At reset RW 0 RW RW RW Note: Bit 5 is ignored in the timer mode and event counter mode; its value is undefined at reading. RW0 –Undefined4 RO (Note) Undefined RW0 RW0 These bits have different functions according to the operating mode.

7702/7703 Group User’s Manual6–6

6.2.4 Timer Bi interrupt control register

Figure 6.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned. Note: Use the SEB or CLB instruction to set each interrupt control register. Timer Bi interrupt control registers (i = 0 to 2) (Addresses 7A16 to 7C16) Fig. 6.2.4 Structure of timer Bi interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select a timer Bi interrupt’s priority level. When using timer Bi interrupts, select priority levels 1 to 7. When the timer Bi interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable bit (I) = “0.”) To disable timer Bi interrupts, set these bits to “000 2” (level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when the timer Bi interrupt request occurs. This bit is automatically cleared to “0” when the timer Bi interrupt request is accepted. This bit can be set to “1” or cleared to “0” by software.

7702/7703 Group User’s Manual TIMER B 6–7

6.2.5 Port P6 direction register

Timer Bi’s input pins are shared with port P6. When using these pins as Timer Bi’s input pins, set the corresponding bits of the port P6 direction register to “0” to set these pins for the input mode. Figure 6.2.5 shows the relationship between port P6 direction register and Timer Bi’s input pins. Fig. 6.2.5 Relationship between port P6 direction register and Timer Bi’s input pins TA4 OUT pin INT0 pin INT1 pin INT2 pin TB1 IN pin TB0 IN pin Port P6 direction register (Address 1016) b1 b0b2b3b4b5b6b7 TA4 IN pin TB2 IN pin RW : Bits 0 to 4 are not used for Timer B. Corresponding pin name FunctionsBit At reset 0: Input mode 1: Output mode When using these pins as Timer Bi's input pins, set the corresponding bits to " 0." RW RW RW RW RW RW RW RW

6–8 7702/7703 Group User’s Manual shows the structures of the timer Bi mode register and timer Bi register in the timer mode. Table 6.3.1 Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request occurrence timing TBi IN pin function Read from timer Bi register Write to timer Bi register Specifications f 2, f16, f64, or f512

• Down-count
• When the counter underflows, reload register’s contents are reloaded and counting continues. When count start bit is set to “1.” When count start bit is cleared to “0.” When the counter underflows. Programmable I/O port Counter value can be read out. l While counting is stopped When a value is written to the timer Bi register, it is written to both reload register and counter. l While counting is in progress When a value is written to the timer Bi register, it is written to only reload register. (Transferred to counter at next reload time.) (n + 1) n: Timer Bi register setting value

7702/7703 Group User’s Manual 6–9 Fig. 6.3.1 Structures of timer Bi mode register and timer Bi register in timer mode b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) RW 15 to 0 Bit Functions At reset These bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by n + 1. When reading, the register indicates the counter value. Undefined RW b7 b6 b5 b4 b3 b2 b1 b0 Bit This bit is ignored in timer mode. Nothing is assigned. Bit name Count source select bits Functions At reset RW These bits are ignored in timer mode. Operating mode select bits 0 0 : Timer mode b1 b0 RW RW RW RW Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)5 –Undefined4 Undefined5 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6 RW0 RW0

6–10 7702/7703 Group User’s Manual

6.3.1 Setting for timer mode

Figure 6.3.2 shows an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Fig. 6.3.2 Initial setting example for registers relevant to timer mode Count starts b7 b0 Count source select bits 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Selecting timer mode and count source Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit b7 b6 Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to level 1–7. When disabling interrupts, set these bits to level 0. 5 : It may be either “0” or “1.” Selection of timer mode Note: The counter divides the count source by n + 1. Setting divide ratio b7 b0 Can be set to “000016” to “FFFF16” (n). (b15) (b8) b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) 00555

7702/7703 Group User’s Manual 6–11

6.3.2 Count source

In the timer mode, the count source select bits (bits 6 and 7 at addresses 5B16 to 5D16) select the count source. Table 6.3.2 lists the count source frequency. Table 6.3.2 Count source frequency Count source select bits b7 b6 Count source frequency f(XIN) = 8 MHz f(X IN) = 16 MHz f(X IN) = 25 MHz 4 MHz 8 MHz 12.5 MHz 500 kHz 1 MHz 1.5625 MHz 125 kHz 250 kHz 390.625 kHz 15625 Hz 31250 Hz 48.8281 kHz Count source f16 f64 f512

6–12 7702/7703 Group User’s Manual

6.3.3 Operation in timer mode

À When the count start bit is set to “1,” the counter starts counting of the count source. \ When the counter underflows, the reload register’s contents are reloaded and counting continues. ´ The timer Bi interrupt request bit is set to “1” when the counter underflows in \ . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 6.3.3 shows an example of operation in the timer mode. Stops counting. Restarts counting. FFFF 16 n 000016 Time Count start bit Timer Bi interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Set to “1” by software. “0” “0” 1 / fi 5 (n+1) fi = frequency of count source (f2, f16, f64, f512 ) Cleared to “0” by software. Fig. 6.3.3 Example of operation in timer mode

7702/7703 Group User’s Manual 6–13 [Precautions when operating in timer mode] By reading the timer Bi register, the counter value can be read out at any timing while counting is in progress. However, if the timer Bi register is read at the reload timing shown in Figure 6.3.4, the value “FFFF16” is read out. When reading the timer Bi register after setting a value to the register while counting is not in progress and before the counter starts counting, the set value can be read out correctly. Fig. 6.3.4 Reading timer Bi register 210 n n – 1Counter value (Hex.)

210 FFFF n – 1Read value

(Hex.) /LiteDiagLines/LiteDiagLines Reload Timen = Reload register’s contents

6–14 7702/7703 Group User’s Manual of the timer Bi mode register and the timer Bi register in the event counter mode. Table 6.4.1 Specifications of event counter mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request occurrence timing TBi IN pin function Read from timer Bi register Write to timer Bi register Specifications

• External signal input to the TBi IN pin
• The count source’s effective edge can be selected from the falling edge, the rising edge, or both of the falling and rising edges by software.
• Down-count
• When the counter underflows, reload register’s contents are reloaded and counting continues. When count start bit is set to “1.” When count start bit is cleared to “0.” When the counter underflows. Count source input Counter value can be read out. l While counting is stopped When a value is written to the timer Bi register, it is written to both reload register and counter. l While counting is in progress When a value is written to the timer Bi register, it is written to only reload register. (Transferred to counter at next reload time.) (n + 1) 1 n: Timer Bi register setting value

7702/7703 Group User’s Manual 6–15 Fig. 6.4.1 Structures of timer Bi mode register and timer Bi register in event counter mode b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 51 , 50 Timer B1 register (Addresses 53 , 52 Timer B2 register (Addresses 55 , 54 RW 15 to 0 Bit Functions At reset RW These bits can be set to “0000 ” to “FFFF Assuming that the set value = n, the counter divides the count source frequency by n + 1. When reading, the register indicates the counter value. Undefined 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Counts at both falling and rising edges of external signal 1 1 : Not selected b7 b6 b5 b4 b3 b2 b1 b0 Bit Count polarity select bit Bit name These bits are ignored in event counter mode. This bit is ignored in event counter mode. Functions At reset Undefined RW Operating mode select bits 0 1 : Event counter mode b1 b0 RW RW RW RW RW RW Timer Bi mode register (i = 0 to 2) (Addresses 5B to 5D b3 b2 Nothing is assigned. Undefined

6–16 7702/7703 Group User’s Manual

6.4.1 Setting for event counter mode

Figure 6.4.2 shows an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to section “Chapter 4. INTERRUPTS.” Fig. 6.4.2 Initial setting example for registers relevant to event counter mode Note: The counter divides the count source by n + 1. Setting divide ratio b7 b0 Can be set to “000016” to “FFFF16” (n). (b15) (b8) b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Count starts b7 b0 0 0 : Counts at falling of external signal. 0 1 : Counts at rising of external signal. 1 0 : Counts at both of falling and rising of external signal. 1 1 : Not selected. Selecting event counter mode and count polarity Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit b3 b2 Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to level 1–7. When disabling interrupts, set these bits to level 0.Setting port P6 direction register b7 b0 Port P6 direction register (Address 1016) Clear the corresponding bit to “0.” TB0 IN pin TB1 IN pin TB2 IN pin 5 : It may be either “0” or “1.” Selection of event counter mode Count polarity select bits

7702/7703 Group User’s Manual 6–17

6.4.2 Operation in event counter mode

À When the count start bit is set to “1,” the counter starts counting of the count source. \` The counter counts the count source’s valid edges. ´ When the counter underflows, the reload register’s contents are reloaded and counting continues. ˆ The timer Bi interrupt request bit is set to “1” when the counter underflows in ´ . The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. Figure 6.4.3 shows an example of operation in the event counter mode. Stops counting. Restarts counting . FFFF 16 n 000016 Time Count start bit Timer Bi interrupt request bit “1” “1” Counter contents (Hex.) n = Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Set to “1” by software. Starts counting. Cleared to “0” by software. “0” “0” Set to “1” by software. Fig. 6.4.3 Example of operation in event counter mode

6–18 7702/7703 Group User’s Manual [Precautions when operating in event counter mode] By reading the timer Bi register, the counter value can be read out at any timing while counting is in progress. However, if the timer Bi register is read at the reload timing shown in Figure 6.4.4, the value “FFFF 16” is read out. When reading the timer Bi register after setting a value to the register while counting is not in progress and before the counter starts counting, the set value can be read out correctly. Fig. 6.4.4 Reading timer Bi register 21 0 n n – 1Counter value (Hex.) 21 0 FFFF n – 1Read value (Hex.) /LiteDiagLines/LiteDiagLines Reload Timen = Reload register’s contents

7702/7703 Group User’s Manual 6–19

6.5 Pulse period/pulse width measurement mode

In these mode, the timer measures an external signal’s pulse period or pulse width. (Refer to Table 6.5.1.) Figure 6.5.1 shows the structures of the timer Bi mode register and timer Bi register in the pulse period/ pulse width measurement mode. l Pulse period measurement The timer measures the pulse period of the external signal that is input to the TBiIN pin. l Pulse width measurement The timer measures the pulse width (“L” level and “H” level widths) of the external signal that is input to the TBi IN pin. Table 6.5.1 Specifications of pulse period/pulse width measurement mode Item Count source Count operation Count start condition Count stop condition Interrupt request occurrence timing TBi IN pin function Read from timer Bi register Write to timer Bi register Specifications f 2, f16, f64, or f512 l Up-count l Counter value is transferred to reload register at valid edge of mea- surement pulse, and counting continues after clearing the counter value to “0000 16.” When count start bit is set to “1” When count start bit is cleared to “0” l When valid edge of measurement pulse is input (Note 1). l When counter overflows (overflow flag ] is set to “1” simultaneously). Measurement pulse input The value got by reading timer Bi register is the reload register’s contents, measurement result (Note 2). Impossible. Overflow flag]: The bit used to identify the source of an interrupt request occurrence. Notes 1: This interrupt request does not occur when the first valid edge is input after the timer starts counting. 2: The value read out from the timer Bi register is undefined until the second valid edge is input after the timer starts counting.

6–20 7702/7703 Group User’s Manual (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) FunctionsBit At reset RW 15 to 0 The measurement result of pulse period or pulse width is read out. Undefined RO Measurement mode select bits Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) 1 0 : Pulse period/Pulse width measurement mode 0 0 : f 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b3 b2 Nothing is assigned. 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from falling edge to rising edge, and from rising edge to falling edge of measurement pulse) 1 1 : Not selected Bit At reset Undefined RW RW RW RW RW RW RW Timer Bi overflow flag (Note) 0 : No overflow 1 : Overflow Undefined RO Note: The timer Bi overflow flag is cleared to “0” by writing to the timer Bi mode register with the count start bit = “1.” Fig. 6.5.1 Structures of timer Bi mode register and timer Bi register in pulse period/pulse width measurement mode

7702/7703 Group User’s Manual 6–21

6.5.1 Setting for pulse period/pulse width measurement mode

Figure 6.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.”

6–22 7702/7703 Group User’s Manual Fig. 6.5.2 Initial setting example for registers relevant to pulse period/pulse width measurement mode /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Count starts b7 b0 Measurement mode select bits Selecting pulse period/pulse width measurement mode and each function Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Setting count start bit to “1” b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit b3 b2 Count source select bits b7 b6 Timer Bi overflow flag (Note) 0: No overflow 1: Overflow Setting port P6 direction register b7 b0 Port P6 direction register (Address 1016) Clear the corresponding bit to “0.” TB0 IN pin TB1 IN pin TB2 IN pin 0 0 : Pulse period measurement (Interval between falling edges of measured pulse) 0 1 : Pulse period measurement (Interval between rising edges of measured pulse) 1 0 : Pulse width measurement 1 1 : Not selected. 0 0 : f 0 1 : f16 1 0 : f64 1 1 : f512 Note: The timer Bi overflow flag is a read-only bit. This bit is undefined after reset. This bit is cleared to "0" by writing to the timer Bi mode register with the count start bit = “1.” Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to level 1–7. When disabling interrupts, set these bits to level 0. Selection of pulse period/pulse width measurement mode

7702/7703 Group User’s Manual 6–23

6.5.2 Count source

In the pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses 5B 16 to 5D16) select the count source. Table 6.5.2 lists the count source frequency. Table 6.5.2 Count source frequency Count source select bits b7 b6 Count source frequency f(X IN) = 8 MHz f(X IN) = 16 MHz f(X IN) = 25 MHz 4 MHz 8 MHz 12.5 MHz 500 kHz 1 MHz 1.5625 MHz 125 kHz 250 kHz 390.625 kHz 15625 Hz 31250 Hz 48.8281 kHz Count source f16 f64 f512

6–24 7702/7703 Group User’s Manual

6.5.3 Operation in pulse period/pulse width measurement mode

À When the count start bit is set to “1,” the counter starts counting of the count source. \ The counter value is transferred to the reload register when an valid edge of the measurement pulse is detected. (Refer to section “(1) Pulse period/pulse width measurement.”) ´ The counter value is cleared to “000016” after the transfer in \ , and the counter continues counting. ˆ The timer Bi interrupt request bit is set to “1” when the counter value is cleared to “000016” in ´ (Note). The interrupt request bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0” by software. ˜ The timer repeats operations \` to ˆ above. Note:The timer Bi interrupt request does not occur when the first valid edge is input after the timer starts counting. (1) Pulse period/pulse width measurement The measurement mode select bits (bits 2 and 3 at addresses 5B16 to 5D16) specify whether the pulse period of an external signal is measured or its pulse width is done. Table 6.5.3 lists the relationship between the measurement mode select bits and the pulse period/pulse width measurements. Make sure that the measurement pulse interval from the falling to the rising, and from the rising to the falling are two cycles of the count source or more. Additionally, use software to identify whether the measurement result indicates the “H” level or the “L” level width. Table 6.5.3 Relationship between measurement mode select bits and pulse period/pulse width measurements Pulse period/pulse width measurement Pulse period measurement Pulse width measurement Not selected Measurement interval (Valid edges) From falling to falling (Falling) From rising to rising (Rising) From falling to rising, and from rising to falling (Falling and rising)

7702/7703 Group User’s Manual 6–25 (2) Timer Bi overflow flag The timer Bi interrupt request occurs when the measurement pulse’s valid edge is input or the counter overflows. The timer Bi overflow flag is used to identify the cause of the interrupt request, that is, whether it is an overflow occurrence or an effective edge input. The timer Bi overflow flag is set to “1” by an overflow. Accordingly, the cause of the interrupt request occurrence is identified by checking the timer Bi overflow flag in the interrupt routine. When a value is written to the timer Bi mode register with the count start bit = “1,” the timer Bi overflow flag is cleared to “0” at the next count timing of the count source The timer Bi overflow flag is a read-only bit. Use the timer Bi interrupt request bit to detect the overflow timing. Do not use the timer Bi overflow flag to do that. during pulse width measurement. Fig. 6.5.3 Operation during pulse period measurement Count source Measurement pulse Timing at which counter is cleared to “0000 “1” “H” “1” Note: The above applies when measurement is performed for an interval from one falling to the next falling of the measurement pulse. Reload register counter Transfer timing “L” “0” “0” Count start bit “1” “0” À Counter is initialized by completion of measurement. Counter overflow. À Cleared to “0” when interrupt request is accepted or cleared by software. Timer Bi interrupt request bit Timer Bi overflow flag Transferred (undefined value) Transferred (measured value)

6–26 7702/7703 Group User’s Manual Fig. 6.5.4 Operation during pulse width measurement Measurement pulse“H” Count source Reload register counter Transfer timing Timing at which counter is cleared to “000016” “1” “1” Transferred (measured value) “L” “0” “0” “1” “0” Cleared to “0” when interrupt request is accepted or cleared by software. À Counter is initialized by completion of measurement. \ Counter overflow. À \ÀÀÀ Count start bit Timer Bi interrupt request bit Timer Bi overflow flag Transferred (measured value) Transferred (measured value) Transferred (undefined value)

7702/7703 Group User’s Manual 6–27 [Precautions when operating in pulse period/pulse width measurement mode] 1. The timer Bi interrupt request occurs by the following two causes: l Input of measured pulse’s valid edge l Counter overflow When the overflow is the cause of the interrupt request occurrence, the timer Bi overflow flag is set to “1.” 2. After reset, the timer Bi overflow flag is undefined. When writing to the timer Bi mode register with the count start bit = “1,” this flag can be cleared to “0” at the next count timing of the count source. 3. An undefined value is transferred to the reload register when the first valid edge is input after the counter starts counting. In this case, the timer Bi interrupt request does not occur. 4. The counter value at start of counting is undefined. Accordingly, the timer Bi interrupt request may occur by the overflow immediately after the counter starts counting. 5. If the contents of the measurement mode select bits are changed after the counter starts counting, the timer Bi interrupt request bit is set to “1.” When writing the same value which has been set yet to the measurement mode select bits, the timer Bi interrupt request bit is not changed, that is, the bit retains the state. 6. If the input signal to the TBi IN pin is affected by noise, etc., the counter may not perform the exact measurement. We recommend to verify, by software, that the measurement values are within a constant range.

6–28 7702/7703 Group User’s Manual

7.1 Overview

7.2 Block description

7.3 Clock synchronous serial I/O mode

7.4 Clock asynchronous serial I/O

(UART) mode

7702/7703 Group User’s Manual7–2 This chapter describes the Serial I/O. The Serial I/O consists of 2 channels: UART0 and UART1. They each have a transfer clock generating timer for the exclusive use of them and can operate independently. UART0 and UART1 have the same functions. UART1’s function of the 7703 Group varies from the 7702 Group’s. Refer to “Chapter 20. 7703 GROUP. ” UARTi (i = 0 and 1) has the following 2 operating modes: l Clock synchronous serial I/O mode Transmitter and receiver use the same clock as the transfer clock. Transfer data has the length of 8 bits. l Clock asynchronous serial I/O (UART) mode Transfer rate and transfer data format can arbitrarily be set. The user can select a 7-bit, 8-bit, or 9-bit length as the transfer data length. Figure 7.1.1 shows the transfer data formats in each operating mode. l Clock synchronous serial I/O mode Transfer data length of 8 bits l UART mode Transfer data length of 7 bits Transfer data length of 8 bits Transfer data length of 9 bits Fig. 7.1.1 Transfer data formats in each operating mode

7702/7703 Group User’s Manual 7–3 Figure 7.2.1 shows the block diagram of Serial I/O. Registers relevant to Serial I/O are described below. Fig. 7.2.1 Block diagram of Serial I/O Data bus (odd) Data bus (even) 0000000 UARTi receive register UARTi receive buffer register UARTi transmit buffer register Receive control circuit Transmit control circuit 1 / (n+1) BRGi Clock synchronous (internal clock selected) UART Clock synchronous UARTClock synchronous (internal clock selected) Clock synchronous (external clock selected) Data bus (odd) Data bus (even) TxD i Transfer clock Transfer clock CLK i BRG count source select bits CTS i / RTSi UARTi transmit register n: Values set in UARTi baud rate register (BRGi) Clock synchronous D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 f16 f64 f512 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

7702/7703 Group User’s Manual7–4

7.2.1 UARTi transmit/receive mode register

Figure 7.2.2 shows the structure of UARTi transmit/receive mode register. The serial I/O mode select bits is used to select UARTi’s operating mode. Bits 4 to 6 are described in the section “7.4.2 Transfer data format,” and bit 7 is done in the section “7.4.8 Sleep mode.” Fig. 7.2.2 Structure of UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Bit Bit name At reset RWFunctions b2 b1 b0 RW RW RW RW RW RW RW RW Serial I/O mode select bits 0 0 0: Serial I/O disabled (P8 functions as a programmable I/O port.) 0 0 1: Clock synchronous serial I/O mode 0 1 0: Not selected 0 1 1: Not selected 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Not selected Sleep select bit (Valid in UART mode) (Note) Parity enable bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit is “1”) (Note) Stop bit length select bit (Valid in UART mode) (Note) Internal/External clock select bit UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode cleared (ignored) 1 : Sleep mode selected 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits

7702/7703 Group User’s Manual 7–5 (1) Internal/External clock select bit (bit 3) [Clock synchronous serial I/O mode] By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the count source of BRGi (described later). The BRGi output of which frequency is divided by 2 becomes the transfer clock. Additionally, the transfer clock is output from the CLK i pin. By setting this bit to “1” in order to select an external clock, the clock input to the CLKi pin becomes the transfer clock. [UART mode] By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 34 16, 3C16) becomes the count source of the BRGi (described later). Then, the CLKi pin functions as a programmable I/O port. By setting this bit to “1” in order to select an external clock, the clock input to the CLKi pin becomes the count source of BRGi. Always in the UART mode, the BRGi output of which frequency is divided by 16 is the transfer clock. BRGi: UARTi baud rate register (Refer to section “7.2.6 UARTi baud rate register (BRGi).”)

7702/7703 Group User’s Manual7–6

7.2.2 UARTi transmit/receive control register 0

Figure 7.2.3 shows the structure of UARTi transmit/receive control register 0. For bits 0 and 1, refer to “7.2.1 (1) Internal/External clock select bit.” CTS/RTS select bit Bit BRG count source select bits Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b1 b0 0 : CTS function selected. 1 : RTS function selected. Transmit register empty flag0 : Data present in transmit register. (During transmitting) 1 : No data present in transmit register. (Transmitting completed) 7 to 4 RW RW RO3 RW Nothing is assigned. Undefined – Fig. 7.2.3 Structure of UARTi transmit/receive control register 0 (1) By clearing this bit to “0” in order to select the CTS function, pins P80 and P84 function as CTS input pins, and the input signal of “L” level to these pins becomes one of the transmission conditions.____ ____ By setting this bit to “1” in order to select the RTS function, pins P80 and P84 become RTS output____ pins. When the receive enable bit (bit 2 at addresses 3516, 3D16) is “0” (reception disabled), the RTS output pin outputs “H” level. The output level of this pin becomes “L” when the receive enable bit is set to “1.” It becomes “H” when reception starts and it becomes “L” when reception is completed. (2) Transmit register empty flag (bit 3) This flag is cleared to “0” when the UARTi transmit buffer register’s contents are transferred to the UARTi transmit register. When transmission is completed and the UARTi transmit register becomes empty, this flag is set to “1.”

7702/7703 Group User’s Manual 7–7

7.2.3 UARTi transmit/receive control register 1

Figure 7.2.4 shows the structure of UARTi transmit/receive control register 1. For bits 4 to 7, refer to each operation mode’s description. Fig. 7.2.4 Structure of UARTi transmit/receive control register 1 Bit Bit name At reset

5 Framing error flag

(Valid in UART mode) 00 : No framing error 1 : Framing error detected RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Notes 1: Bits 7 to 4 are cleared to “0” when clearing the receive enable bit to “0” or when reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16) out. 2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode.

0 Transmit enable bit 00 : Transmission disabled

1 : Transmission enabled

1 Transmit buffer empty flag 1

0 : Data present in transmit buffer register. 1 : No data present in transmit buffer register.

2 Receive enable bit 0

0 : Reception disabled 1 : Reception enabled

3 Receive complete flag 0

0 : No data present in receive buffer register. 1 : Data present in receive buffer register.

4 Overrun error flag 0

0 : No overrun error 1 : Overrun error detected

6 Parity error flag

(Valid in UART mode) 00 : No parity error 1 : Parity error detected

7 Error sum flag

(Valid in UART mode) 0 : No error 1 : Error detected (Notes 1, 2) (Notes 1, 2) (Notes 1, 2) (Note 1) RW RO RW RO RO RO RO RO

7702/7703 Group User’s Manual7–8 (1) Transmit enable bit (bit 0) By setting this bit to “1,” UARTi enters the transmission enable state. By clearing this bit to “0” during transmission, UARTi enters the transmission disable state after the transmission which is performed at that time is completed. (2) Transmit buffer empty flag (bit 1) This flag is set to “1” when data set in the UARTi transmit buffer register is transferred from the UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to “0” when data is set in the UARTi transmit buffer register. (3) Receive enable bit (bit 2) By setting this bit to “1,” UARTi enters the reception enable state. By clearing this bit to “0” during reception, UARTi quits the reception then and enters the reception disable state. (4) Receive complete flag (bit 3) This flag is set to “1” when data is ready in the UARTi receive register and that is transferred to the UARTi receive buffer register (i.e., when reception is completed). This flag is cleared to “0” when the low-order byte of the UARTi receive buffer register is read out or when the receive enable bit (bit 2) is cleared to “0.”

7702/7703 Group User’s Manual 7–9

7.2.4 UARTi transmit register and UARTi transmit buffer register

Figure 7.2.5 shows the block diagram of transmit section; Figure 7.2.6 shows the structure of UARTi transmit buffer register. Fig. 7.2.6 Structure of UARTi transmit buffer register Fig. 7.2.5 Block diagram of transmit section SP SP PAR “0” 2SP 1SP UART 7-bit UART 8-bit UART 7-bit UART 9-bit UART Clock sync. Clock sync. Clock sync. Data bus (even) Data bus (odd) TxD i UARTi transmit register Parity enabled Parity disabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP : Stop bit PAR : Parity bit UARTi transmit buffer register 8-bit UART 9-bit UART b7 b0 Bit 8 to 0 At reset Undefined RWFunctions WO b7 b0 (b15) (b8) 15 to 9 –Undefined UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) Nothing is assigned. Transmit data is set.

7702/7703 Group User’s Manual7–10 The UARTi transmit buffer register is used to set transmit data. Set the transmit data into the low-order byte of this register when operating in the clock synchronous serial I/O mode or when a 7-bit or 8-bit length of transfer data is selected in the UART mode. When a 9-bit length of transfer data is selected in the UART mode, set the transmit data into the UARTi transmit buffer register as follows:

• Bit 8 of the transmit data into bit 0 of high-order byte of this register.
• Bits 7 to 0 of the transmit data into the low-order byte of this register. The transmit data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit register when the transmission conditions are satisfied, and then it is output from the TxD i pin synchronously with the transfer clock. The UARTi transmit buffer register becomes empty when the data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit register. Accordingly, the user can set next transmit data. When quitting the transmission which is in progress and setting the UARTi transmit buffer register again, follow the procedure described bellow: À Clear the serial I/O mode select bits (bits 2 to 0 at addresses 30 16, 3816) to “0002” (Serial I/O disabled). \` Set the serial I/O mode select bits again. ´ Set the transmit enable bit (bit 0 at addresses 3516, 3D16) to “1” (transmission enabled) and set transmit data in the UARTi transmit buffer register.

7702/7703 Group User’s Manual 7–11

7.2.5 UARTi receive register and UARTi receive buffer register

Figure 7.2.7 shows the block diagram of receive section; Figure 7.2.8 shows the structure of UARTi receive buffer register. Fig. 7.2.8 Structure of UARTi receive buffer register Fig. 7.2.7 Block diagram of receive section Clock sync. SPSP PAR 2SP 1SP UART 0000000 RxD i D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP : Stop bit PAR : Parity bit 8-bit UART 9-bit UART 7-bit UART 9-bit UART Clock sync. Clock sync. 7-bit UART 8-bit UART Data bus (even) Data bus (odd) UARTi receive register Parity enabled Parity disabled UARTi receive buffer register b7 b0 Bit 8 to 0 At reset Undefined RWFunctions RO b7 b0 (b15) (b8) 15 to 9 – UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) Nothing is assigned. The value is “0” at reading. Receive data is read out from here.

7702/7703 Group User’s Manual7–12 The UARTi receive register is used to convert serial data which is input to the RxDi pin into parallel data. This register takes in the input signal to the RxDi pin synchronously with the transfer clock, one bit at a time. The UARTi receive buffer register is used to read out receive data. When reception is completed, receive data which is taken in the UARTi receive register is automatically transferred to the UARTi receive buffer register. The contents of UARTi receive buffer register is updated when the next data is ready before reading out the data which has been transferred to the UARTi receive buffer register (i.e., an overrun error occurs). The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 35 16, 3D 16) to “1” after clearing it to “0.” Figure 7.2.9 shows the contents of UARTi receive buffer register when reception is completed. Fig. 7.2.9 Contents of UARTi receive buffer register when reception is completed b7 b0 b7 b0 0000000 0000000 0000000 Receive data (9 bits) Receive data (8 bits) Receive data (7 bits) In UART mode (Transfer data length : 9 bits) In clock synchronous serial I/O mode In UART mode (Transfer data length : 8 bits) In UART mode (Transfer data length : 7 bits) Same value as bit 7 in low-order byte Same value as bit 6 in low-order byte High-order byte (addresses 3716, 3F16) Low-order byte (addresses 36 16, 3E16)

7702/7703 Group User’s Manual 7–13

7.2.6 UARTi baud rate register (BRGi)

The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer clock. It has a reload register. Assuming that a value set in the BRGi is “n” (n = “0016” to “FF16”), the BRGi divides the count source frequency by n + 1. In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and a clock of which frequency is the BRGi output’s frequency divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and a clock of which frequency is the BRGi output’s frequency divided by 16 becomes the transfer clock. The data which is written to the addresses 31 16 and 3916 is written to both the timer register and the reload register whether transmission/reception is stopped or in progress. Accordingly, writing to their addresses, perform it while that is stopped. Figure 7.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 7.2.11 shows the block diagram of transfer clock generating section. Fig. 7.2.10 Structure of UARTi baud rate register (BRGi) b7 b0 UART0 baud rate register (Address 3116) UART1 baud rate register (Address 3916) FunctionsBit At reset RW 7 to 0 Can be set to “0016” to “FF16.” Assuming that the set value = n, BRGi divides the count source frequency by n + 1. Undefined WO BRGi 1/2 Transmit control circuit Receive control circuit Transfer clock for transmit operation Transfer clock for receive operation Transmit control circuit Receive control circuit Transfer clock for transmit operation Transfer clock for receive operation BRGi <Clock synchronous serial I/O mode> <UART mode> fi : Clock selected by BRG count source select bits (f2, f16, f64, or f512) fEXT : Clock input to CLKi pin (external clock) fi fEXT fEXT fi Fig. 7.2.11 Block diagram of transfer clock generating section

7702/7703 Group User’s Manual7–14

7.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers

When using UARTi, 2 types of interrupts, which are UARTi transmit and UARTi receive interrupts, can be used. Each interrupt has its corresponding interrupt control register. Figure 7.2.12 shows the structure of UARTi transmit interrupt control and UARTi receive interrupt control registers. b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit interrupt control register (Address 7116) UART0 receive interrupt control register (Address 7216) UART1 transmit interrupt control register (Address 7316) UART1 receive interrupt control register (Address 7416) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request Interrupt priority level select bits RW RW RW RW –Undefined Nothing is allocated. Note: Use the SEB or CLB instruction to set each interrupt control registers. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” Fig. 7.2.12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers

7702/7703 Group User’s Manual 7–15 (1) Interrupt priority level select bits (bits 0 to 2) These bits select the priority level of the UARTi transmit interrupt or UARTi receive interrupt. When using UARTi transmit/receive interrupt, select priority levels 1 to 7. When the UARTi transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable the UARTi transmit/receive interrupt, set these bits to “000 2” (level 0). (2) Interrupt request bit (bit 3) The UARTi transmit interrupt request bit is set to “1” when data is transferred from the UARTi transmit buffer register to the UARTi transmit register. The UARTi receive interrupt request bit is set to “1” when data is transferred from the UARTi receive register to the UARTi receive buffer register. However, when an overrun error occurs, it does not change. Each interrupt request bit is automatically cleared to “0” when its corresponding interrupt request is accepted. This bit can be set to “1” or “0” by software.

7702/7703 Group User’s Manual7–16

7.2.8 Port P8 direction register

I/O pins of UARTi are shared with port P8. When using pins P82 and P86 as serial data input pins (RxDi), set the corresponding bits of the port P8 direction register to “0” to set these pins for the input mode. When____ ____ using pins P80, P81, P83 to P85 and P87 as I/O pins (CTSi/RTSi, CLKi, TxDi) of UARTi, these pins are forcibly set as I/O pins of UARTi regardless of port P8 direction register’s contents. Figure 7.2.13 shows the relationship between the port P8 direction register and UARTi’s I/O pins. Fig. 7.2.13 Relationship between port P8 direction register and UARTi’s I/O pins Bit Corresponding pin Functions CTS 0/RTS 0 pin RxD 0 pin TxD 0 pin CTS 1/RTS 1 pin RxD 1 pin 0 : Input mode 1 : Output mode When using pins P82 and P86 as serial data input pins (RxD0, RxD1), set the corresponding bits to “0.” CLK 1 pin Port P8 direction register (Address 1416) b1 b0b2b3b4b5b6b7 CLK 0 pin TxD 1 pin At reset RW RW RW RW RW RW RW RW RW

7702/7703 Group User’s Manual 7–17 Table 7.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 7.3.2 lists the functions of I/O pins in this mode. Table 7.3.1 Performance overview in clock synchronous serial I/O mode Item Transfer data format Transfer rate Transmit/Receive control When selecting internal clock When selecting external clock Functions Transfer data has a length of 8 bits. LSB first Clock which is BRGi output’s divided by 2. Maximum 5 Mbps (f(X IN) = 25 MHz) Maximum 4 Mbps (f(X IN) = 16 MHz) Maximum 2 Mbps (f(X IN) = 8 MHz) CTS function or RTS function can be selected by software. Table 7.3.2 Functions of I/O pins in clock synchronous serial I/O mode Functions Serial data output Serial data input Transfer clock output Transfer clock input ____ CTS input ____ RTS output Pin name TxD i (P83, P87) RxD i (P82, P86) CLK i (P81, P85) CTS i/RTS i (P80, P84) Method of selection Fixed (Dummy data is output when performing only reception.) Port P8 direction register \\1’s corresponding bit = “0” Internal/External clock select bit\\ 2 = “0” Internal/External clock select bit = “1” CTS/RTS select bit\\ 3 = “0” CTS/RTS select bit = “1” Port P8 direction register\\ 1: Address 1416 Internal/External clock select bit\\ 2: bit 3 at addresses 3016, 3816____ ____ CTS/RTS select bit\\3: bit 2 at addresses 3416, 3C16 Notes 1: The TxDi pin outputs “H” level until transmission starts after UARTi’s operating mode is selected. 2: The RxD i pin can be used as a programmable I/O port when performing only transmission.

7702/7703 Group User’s Manual7–18

7.3.1 Transfer clock (synchronizing clock)

Data transfer is performed synchronously with the transfer clock. For the transfer clock, the user can select whether to generate the transfer clock internally or to input it from an external. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, set the transmit enable bit to “1,” and set dummy data in the UARTi transmit buffer register in order to make the transmit control circuit active. (1) Generating transfer clock internally The count source selected with the BRG count source select bits is divided by the BRGi, and its BRGi output is further divided by 2. This is the transfer clock. The transfer clock is output from the CLK i pin. [Setting relevant registers]

• Select an internal clock (bit 3 at addresses 30 16, 3816 = “0”).
• Select the BRGi’s count source (bits 0 and 1 at addresses 3416, 3C16)
• Set “divide value – 1” to the BRGi (addresses 3116, 3916). Transfer clock frequency =
• Enable transmission (bit 0 at addresses 3516, 3D16 = “1”).
• Set data to the UARTi transmit buffer register (addresses 3216, 3A16) [Pin’s state]
• A transfer clock is output from the CLKi pin.
• Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.) (2) Inputting transfer clock from an external A clock input from the CLKi pin is the transfer clock. [Setting relevant registers]
• Select an external clock (bit 3 at addresses 3016, 3816 = “1”).
• Enable transmission (bit 0 at addresses 3516, 3D16 = “1”).
• Set data to the UARTi transmit buffer register (addresses 3216, 3A16). [Pin’s state]
• A transfer clock is input from the CLK i pin.
• Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.) n: Setting value to BRGi fi: Frequency of BRGi’s count source (f2, f16, f64, f512 ) fi 2 (n+1)

7702/7703 Group User’s Manual 7–19

7.3.2 Method of transmission

Figures 7.3.1 shows an initial setting example for relevant registers when transmitting. Transmission is started when all of the following conditions (À to ´ ) are satisfied. When an external clock is selected, satisfy conditions À to ´ with the following precondition satisfied. <Precondition> The CLK i pin’s input is “H” level (external clock selected). Note: When an internal clock is selected, above precondition is ignored. <Transmission conditions> À Transmission is enabled (transmit enable bit = “1”). \` Transmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”) ´ CTS i pin’s input is “L” level (when CTS function selected).____ Note: When the CTS function is not selected, this condition is ignored. When using interrupts, it is necessary to set the relevant register to enable interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Figure 7.3.2 shows writing data after start of transmission, and Figure 7.3.3 shows detection of transmission’s completion.

7702/7703 Group User’s Manual7–20 UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Set transmit data here. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Transmit enable bit 1: Transmission enabled (In the case of selecting the CTS function, transmission starts when the CTS i pin’s input level is “L.”) UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 BRG count source select bits 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b1 b0 1000 UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 Internal/External clock select bit 0: Internal clock 1: External clock 5 : It may be “0” or “1.” Clock synchronous serial I/O mode 555 UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to level 1-7. When disabling interrupts, set these bits to level 0. UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Set to “0016” to “FF16 .” ] Necessary only when internal clock is selected. Transmission starts. CTS / RTS select bit 0: CTS function selected. 1: RTS function selected Fig. 7.3.1 Initial setting example for relevant registers when transmitting

7702/7703 Group User’s Manual 7–21 Fig. 7.3.2 Writing data after start of transmission [When not using interrupts] [When using interrupts] The UARTi transmit interrupt request occurs when the UARTi transmit buffer register becomes empty. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi transmit interrupt Note : UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Writing of next transmit data Set transmit data here. UART0 transmit/receive control register 1 (Address 35 ) UART1 transmit/receive control register 1 (Address 3D ) Transmit buffer empty flag 0: Data present in transmit buffer register 1: No data present in transmit buffer register (Writing of next transmit data is possible.) Checking state of UARTi transmit buffer register This figure shows the bits and registers required for processing. Refer to Figure 7.3.5 about the change of flag state and the occurrence timing of an interrupt request.

7702/7703 Group User’s Manual7–22 Fig. 7.3.3 Detection of transmission’s completion [When not using interrupts] [When using interrupts] /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi transmit interrupt UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 Interrupt request bit Checking start of transmission UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 Checking completion of transmission. Transmit register empty flag 0: During transmitting 1: Transmitting completed Processing at completion of transmission No interrupt request Interrupt request (Transmission has started.) The UARTi transmit interrupt request occurs when the transmission starts. Note :This figure shows the bits and registers required for processing. Refer to Figure 7.3.5 about the change of flag state and the occurrence timing of an interrupt request.

7702/7703 Group User’s Manual 7–23

7.3.3 Transmit operation

When the transmit conditions described in page 7-19 are satisfied, the following operations are automatically performed simultaneously.

• The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
• 8 transfer clocks are generated (when an internal clock is selected).
• The transmit buffer empty flag is set to “1.”
• The transmit register empty flag is cleared to “0.”
• The UARTi transmit interrupt request occurs, and the interrupt request bit is set to “1.” The transmit operations are described below. À Data in the UARTi transmit register is transmitted from the TxD i pin synchronously with the falling of the transfer clock. \` This data is transmitted bit by bit sequentially beginning with the least significant bit. ´ When 1-byte data has been transmitted, the transmit register empty flag is set to “1,” indicating completion of the transmission. Figure 7.3.4 shows the transmit operation. In the case of an internal clock is selected, when the transmit conditions for the next data are satisfied at completion of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the transmit register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the transfer clock stops at “H” level. Figures 7.3.5 shows an example of transmit timing (when selecting an internal clock).

7702/7703 Group User’s Manual 7–24 Fig. 7.3.4 Transmit operation Transfer clock UARTi transmit buffer register D D D D D D D D D D D D D D D D D D D D D D D D D D Transmit data MSB b7 b0 D D D D LSB UARTi transmit register D D D D D D D D D D D D D D D D D D D D D D D D Tc T CLK CTS i CLK i T END i TxD i “H” “L” “0” “1” “0” “1” “0” “1” “0” “1” T ENDi : Next transmit conditions are examined when this signal level is “H.” ENDi is an internal signal. Accordingly, it cannot be read from an external.) Tc = T CLK = 2(n+1) /fi fi: BRGi count source frequency (f , f , f , f 512 n: Value set to BRGi Transfer clock Transmit enable bit Transmit buffer empty flag Transmit register empty flag UARTi transmit interrupt request bit Data is set in UARTi transmit buffer register. UARTi transmit register UARTi transmit buffer register. Stopped because CTSi = “H.” Stopped because transmit enable bit = “0.” Cleared to “0” when interrupt request is accepted or cleared by software. The above timing diagram applies to the following conditions: l Internal clock selected l CTS function selected. Fig. 7.3.5 Example of transmit timing (when selecting internal clock)

7702/7703 Group User’s Manual 7–25

7.3.4 Method of reception

started when all of the following conditions (À to ´ ) are satisfied. When an external clock is selected, satisfy conditions À to ´ with the following precondition satisfied. <Precondition> The CLKi pin’s input is “H” level. Note: When an internal clock is selected, above precondition is ignored. <Reception conditions> À Reception is enabled (receive enable bit = “1”). \` Transmission is enabled (transmit enable bit = “1”). ´ Dummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”) When using interrupts, it is necessary to set the relevant register to enable interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Figure 7.3.8 shows processing after reception’s completion.

7702/7703 Group User’s Manual7–26 ] Necessary only when an internal clock is selected. UART0 baud rate register (BRG0) (Address 3116 ) UART1 baud rate register (BRG1) (Address 3916 ) b7 b0 Set to 0016 to FF16 . 1000 UART0 transmit/receive mode register (Address 30 ) UART1 transmit/receive mode register (Address 38 ) b7 b0 Internal/External clock select bit 0: Internal clock 1: External clock 5 : It may be “0” or “1.” Clock synchronous serial I/O mode Continued to Figure 7.3.7 on next page. UART0 transmit/receive control register 0 (Address 34 ) UART1 transmit/receive control register 0 (Address 3C ) b7 b0 CTS / RTS select bit 0: CTS function selected 1: RTS function selected 55 5 BRG count source select bits 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 b1 b0 Fig. 7.3.6 Initial setting example for relevant registers when receiving (1)

7702/7703 Group User’s Manual 7–27 Fig. 7.3.7 Initial setting example for relevant registers when receiving (2) Port P8 direction register (Address 14 b7 b0 R X D pin R X D pin From preceding Figure 7.3.6 UART0 receive interrupt control register (Address 72 UART1 receive interrupt control register (Address 74 b7 b0 Interrupt priority level select bits When using interrupts, set these bits to level 1–7. When disabling interrupts, set these bits to level 0. UART0 transmit buffer register (Address 32 UART1 transmit buffer register (Address 3A b7 b0 Set dummy data here. UART0 transmit/receive control register 1 (Address 35 UART1 transmit/receive control register 1 (Address 3D b7 b0 Transmit enable bit 1 : Transmission enabled Receive enable bit 1 : Reception enabled Reception starts. Note: When selecting the internal clock, set this register with either of the following setting.

• Set the receive enable bit and the transmit enable bit to “1” simultaneously.
• Set the receive enable bit to “1” and next the transmit enable bit to “1.”

7702/7703 Group User’s Manual7–28 [When not using interrupts] [When using interrupts] The UARTi receive interrupt request occurs when reception is completed. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi receive interrupt Processing after reading out receive data UART0 receive buffer register (Address 3616) UART1 receive buffer register (Address 3E16) b7 b0 Reading of receive data Read out receive data. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Receive complete flag 0: Reception not completed 1: Reception completed Checking completion of reception Note :This figure shows the bits and registers required for processing. Refer to Figure 7.3.11 about the change of flag state and the occurrence timing of an interrupt request. b7 b0 Checking error Overrun error flag 0: No overrun error 1: Overrun error detected UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Fig. 7.3.8 Processing after reception’s completion

7702/7703 Group User’s Manual 7–29

7.3.5 Receive operation

When the receive conditions listed on page 7-25 are satisfied, the UARTi enters the receive enable state. The receive operations are described below. À The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register synchronously with the rising of the clock. \ The contents of the UARTi receive register are shifted by 1 bit to the right. ´ Steps À and \ are repeated at each rising of the transfer clock. ˆ When 1-byte data is prepared in the UARTi receive register, the contents of this register are transferred to the UARTi receive buffer register. ˜ Simultaneously with step ˆ , the receive complete flag is set to “1,” and the UARTi receive interrupt request occurs and its interrupt request bit is set to “1.” The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register timing (when selecting an external clock).

7702/7703 Group User’s Manual7–30 Fig. 7.3.9 Connection example Fig. 7.3.10 Receive operation TxD i RxD i CLK i TxD i RxD i CLK i Transmitter side Receiver side UARTi receive register D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 0 D 1 D 0 Receive data MSB b7 b0 LSB D 2 D 1 D 0 Transfer clock UARTi receive buffer register

• ••
• ••

7702/7703 Group User’s Manual 7–31 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 1/fEXT RTS i CLK i RxD i “H” “L” “0” “1” “0” “1” “0” “1” “0” “1” “0” “1” : When the CLKi pin’s input level is “H,” safisfy the following cinditions: l Transmit enable bit → “1” l Receive enable bit → “1” l Writing of dummy data to UARTi transmit buffer register Receive enable bit Transmit enable bit Transmit buffer empty flag Dummy data is set to UARTi transmit buffer register. UARTi transmit register¨← UARTi transmit buffer register Received data taken in UARTi receive register → UARTi receive buffer registerUARTi receive buffer register is read out. Receive complete flag UARTi receive interrupt request bit The above timing diagram applies to the following setting conditions: Cleared to “0” when interrupt request is accepted or cleared by software. l External clock selected. l RTS function selected. fEXT : Frequency of external clock Fig. 7.3.11 Example of receive timing (when selecting external clock)

7702/7703 Group User’s Manual7–32

7.3.6 Process on detecting overrun error

In the clock synchronous serial I/O mode, an overrun error can be detected. (However it is impossible to detect an overrun error as the case may be. Refer to 6 in “[Precautions when operating in clock synchronous serial I/O mode].” An overrun error occurs when the next data is prepared in the UARTi receive register with the receive complete flag = “1” (data is present in the UARTi receive buffer register) and that is transferred to the receive buffer register, in other words, when the next data is prepared before reading out the contents of the UARTi receive buffer register. When an overrun error occurs, the next receive data is written into the UARTi receive buffer register, and the UARTi receive interrupt request bit is not changed. An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register and the overrun error flag is set to “1.” The overrun error flag is cleared to “0” by reading out the low-order byte of the UARTi receive buffer register or clearing the receive enable bit to “0.” When an overrun error occurs during reception, initialize the overrun error flag and the UARTi receive buffer register before performing reception again. When it is necessary to perform retransmission owing to an overrun error which occurs in the receiver side, set the UARTi transmit buffer register again before starting transmission again. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below. (1) Method of initializing UARTi receive buffer register À Clear the receive enable bit to “0” (reception disabled). \ Set the receive enable bit to “1” again (reception enabled). (2) Method of setting UARTi transmit buffer register again À Clear the serial I/O mode select bits to “000 2” (serial I/O ignored). \ Set the serial I/O mode select bits to “0012” again. ´ Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi transmit buffer register.

7702/7703 Group User’s Manual 7–33 [Precautions when operating in clock synchronous serial I/O mode] 1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, transmit operation (setting for transmission) must be performed. In this case, dummy data is output from the TxDi pin. 2. When an internal clock is selected during reception, the transfer clock is generated by setting the transmit enable bit to “1” (transmission enabled) and setting dummy data to the UARTi transmission buffer register. When an external clock is selected , the transfer clock is generated by setting the transmit enable bit to “1” and inputting a clock to the CLKi pin after setting dummy data to the UARTi transmission buffer register. 3. When selecting an external clock, satisfy the following 3 conditions with the input to CLKi pin = “H” level. <When transmitting> À Set the transmit enable bit to “1.” \ Write transmit data to the UARTi transmit buffer register. ´ Input “L” level to the CTS i pin (when selecting the CTS function). <When receiving> À Set the receive enable bit to “1.” \ Set the transmit enable bit to “1.” ´ Write dummy data to the UARTi transmit buffer register. 4. When receiving data, write dummy data to the low-oreder byte of the UARTi transmission buffer register for each reception of 1-byte data. ____ 5. The output level of the RTSi pin becomes “L” simultaneously at setting the receive enable bit to “1.” The output level of this pin becomes “H” when receive starts, and it becomes “L” when receive is completed. The output level of this pin changes regardless of the contents of the transmit enable bit, the transmission buffer empty flag, and the receive complete flag.

7702/7703 Group User’s Manual7–34

1. When receiving data continuously, an overrun error cannot be detected in the following situation: when the next data reception is completed between reading the error flag by software and reading the UARTi receive buffer register. Fig. 7.3.12 Case of overrun error cannot be detect (using clock synchronous seriai I/O mode) Data reading Data A error flag (No error ) Data B reading Receive complete flag Overrun error flag UARTi receive interruput request bit Software management Undefined Data A Error flag reading D 0 D 1 D 6 D 7 D 0 D 1 D 6 D 7 À When checking this error flag by software, the microcomputer judges errors nothing because errors do not have occurred at data A receiving. \` When receiving the data B, the data B is written to the UARTi receive buffer register and the data A is cleard and the overrun error flag becomes “1” simultaneously. The UARTi receive interrupt request bit does not change. ´ When reading the UARTi receive buffer register by software, the data B is read and the overrun error flag becomes “0” simultaneously. Accordingly, the overrun error cannot may be detected and it is possible that the data B is managed as the data A. Transfer clock RxD UARTi receive buffer register Data B À

7702/7703 Group User’s Manual 7–35 SERIAL I/O

7.4 Clock asynchronous serial I/O (UART) mode

Table 7.4.1 lists the performance overview in the UART mode, and Table 7.4.2 lists the functions of I/O pins in this mode. Table 7.4.1 Performance overview in UART mode Item Transfer data format Transfer rate Error detection Start bit Character bit (Transfer data) Parity bit Stop bit When selecting internal clock When selecting external clock Functions 1 bit 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (Odd or even can be selected.) 1 bit or 2 bits Clock of BRGi output divided by 16 Maximum 312.5 kbps (f(X IN) = 25 MHz) Maximum 250 kbps (f(XIN) = 16 MHz) Maximum 125 kbps (f(XIN) = 8 MHz) 4 types (Overrun, Framing, Parity, and Summing) Presence of error can be detected only by checking error sum flag. Table 7.4.2 Functions of I/O pins in UART mode Method of selection Fixed Port P8 direction register\\1’s corresponding bit = “0” Internal/External clock select bit\\2 = “1” CTS/RTS select bit\\3 = “0” CTS/RTS select bit = “1” Pin name TxD i (P83, P87) RxD i (P82, P86) CLK i (P81, P85) CTS i/RTS i (P80, P84) Functions Serial data output Serial data input BRGi’s count source input ____ CTS input ____ RTS output Port P8 direction register\\ 1: Address 1416 Internal/External clock select bit\\ 2: bit 3 at addresses 3016, 3816____ ____ CTS/RTS select bit\\3: bit 2 at addresses 3416, 3C16 Notes 1: The TxDi pin outputs “H” level while not transmitting after selecting UARTi’s operating mode. 2: The RxDi pin can be used as a programmable I/O port when performing only transmission. 3: The CLKi pin can be used as a programmable I/O port when selecting internal clock.___ ___ ___ 4: The CTSi/RTSi pin can be used as a input port when performing only reception and not using RTS___ function (when selecting CTS function).

7702/7703 Group User’s Manual7–36

7.4.1 Transfer rate (frequency of transfer clock)

The transfer rate is determined by the BRGi (addresses 3116, 3916). When setting “n” into BRGi (n = “0016” to “FF16”), BRGi divides the count source frequency by n + 1. The divided clock by BRGi is further divided by 16 and the resultant clock becomes the transfer clock. Accordingly, the value “n” is expressed by the following formula. n = — 1F 16 5 B n: Value set into BRGi F: BRGi’s count source frequency B: Transfer rate Transfer rate (bps) 110 134.5 150 300 600 1200 2400 4800 9600 19200 31250 62500 125000 250000 500000 An internal clock or an external clock can be selected as the BRGi’s count source with the internal/external clock select bit (bit 3 at addresses 30 16, 3816). When an internal clock is selected, the clock selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the BRGi’s count source. When an external clock is selected, the clock input to the CLKi pin becomes the BRGi’s count source. the transmitter and the receiver. Table 7.4.3 Setting examples of transfer rate (1) BRGi setting value : n 12 (0C 16) 70 (4616) 57 (3916) 51 (3316) 25 (1916) 12 (0C16) 25 (1916) 12 (0C16) 51 (3316) 25 (1916) 12 (0C16) 7 (0716) 3 (0316) 1 (0116) 0 (0016) Actual time (bps) 75.12 110.04 134.70 150.24 300.48 600.96 1201.92 2403.85 4807.69 9615.39 19230.77 31250.00 62500.00 125000.00 250000.00 BRGi count source f 512 f64 f64 f64 f64 f64 f16 f16 BRGi setting value : n 25 (1916) 141 (8D16) 115 (7316) 103 (6716) 51 (3316) 25 (1916) 51 (3316) 25 (1916) 103 (6716) 51 (3316) 25 (1916) 15 (0F16) 7 (0716) 3 (0316) 1 (0116) 0 (0016) Actual time (bps) 75.12 110.04 134.70 150.24 300.48 600.96 1201.92 2403.85 4807.69 9615.39 19230.77 31250.00 62500.00 125000.00 250000.00 500000.00 BRGi count source f512 f64 f64 f64 f64 f64 f16 f16 f(XIN) = 8 MHz f(XIN) = 16 MHz

7702/7703 Group User’s Manual 7–37 SERIAL I/O Table 7.4.4 Setting examples of transfer rate (2) Transfer rate (bps) 150 300 600 1200 2400 4800 9600 19200 31250 BRGi setting value : n 159 (9F 16) 79 (4F16) 159 (9F16) 79 (4F16) 39 (2716) 159 (9F16) 79 (4F16) 39 (2716) Actual time (bps) 150.00 300.00 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 BRGi count source f f64 f16 f16 f16 BRGi setting value : n 162 (A216) 80 (5016) 162 (A216) 80 (5016) 40 (2816) 162 (A216) 80 (5016) 40 (2816) 24 (1816) Actual time (bps) 149.78 301.41 599.12 1205.63 2381.86 4792.94 9645.06 19054.88 31250.00 BRGi count source f64 f64 f16 f16 f16 f(XIN) = 24.576 MHz f(XIN) = 25 MHz

7702/7703 Group User’s Manual7–38

7.4.2 Transfer data format

The transfer data format can be selected from formats shown in Figure 7.4.1. Bits 4 to 6 at addresses 3016 and 3816 select the transfer data format. (Refer to Figure 7.2.2.) Set the same transfer data format for both transmitter and receiver sides. Transfer data length of 7 bits 1ST—7DATA 1SP 1ST—7DATA 2SP 1ST—7DATA—1PAR—1SP 1ST—7DATA—1PAR—2SP Transfer data length of 8 bits 1ST—8DATA 1SP 1ST—8DATA 2SP 1ST—8DATA—1PAR—1SP 1ST—8DATA—1PAR—2SP Transfer data length of 9 bits 1ST—9DATA 1SP 1ST—9DATA 2SP 1ST—9DATA—1PAR—1SP 1ST—9DATA—1PAR—2SP ST : Start bit DATA : Character bit (transfer data) PAR : Parity bit SP : Stop bit Fig. 7.4.1 Transfer data format

7702/7703 Group User’s Manual 7–39 SERIAL I/O Fig. 7.4.2 Example of transfer data format Table 7.4.5 Each bit in transmit data Name ST Start bit DATA Character bit PAR Parity bit ST Stop bit Functions “L” signal equivalent to 1 character bit which is added immediately before the character bits. It indicates start of data transmission. Transmit data which is set in the UARTi transmit buffer register. A signal that is added immediately after the character bits in order to improve data reliability. The level of this signal changes according to selection of odd/even parity in such a way that the sum of “1”s in this bit and character bits is always an odd or even number. “H” level signal equivalent to 1 or 2 character bits which is added immediately after the character bits (or parity bit when parity is enabled). It indicates finish of data transmission. Time

• Example of 1ST–8DATA–1PAR–1SP ST LSB MSB PAR SP ST Transmit/Receive data “H” DATA (8 bits) Next transmit/receive data (When continuously transferring)

7702/7703 Group User’s Manual7–40

7.4.3 Method of transmission

Figure 7.4.3 shows an initial setting example for relevant registers when transmitting. The difference due to selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data length. When selecting a 7- or 8-bit data length, set the transmit data into the low-order byte of the UARTi transmit buffer register. When selecting a 9-bit data length, set the transmit data into that low-order byte and bit 0 of that high-order byte. Transmission is started when all of the following conditions (À to ´ ) are satisfied: À Transmit is enabled (transmit enable bit = “1”). \` Transmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”). ´ CTSi pin’s input is “L” level (when CTS function selected).____ Note: When the CTS function is not selected, this condition is ignored. When using interrupts, it is necessary to set the corresponding register to enable interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Figure 7.4.4 shows writing data after start of transmission, and Figure 7.4.5 shows detection of transmission’s completion.

7702/7703 Group User’s Manual 7–41 SERIAL I/O Fig. 7.4.3 Initial setting example for relevant registers when transmitting UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Set to 0016 to FF16. Interrupt priority level select bits When using interrupts, set these bits to level 1–7. When disabling interrupts, set these bits to level 0. UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Transmit enable bit 1: Transmission enabled Transmission starts. UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) b7 b0 Set transmit data here. b15 UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 Internal/External clock select bit 0: Internal clock 1: External clock 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity disabled 1: Parity enabled Sleep select bit 0: Sleep mode cleared (ignored) 1: Sleep mode selected b2 b1 b0 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 BRG count source select bits CTS /RTS select bit 0: CTS function selected 1: RTS function selected (CTS function disabled) 0 0: f2 0 1: f16 1 0: f64 1 1: f512 b1 b0 (In the case of selecting the CTS function, transmission starts when the CTS i pin’s input level is “L.”) The CTS /RTS select bit is valid when the CTS /RTS enable bit is “0” and the D-Ai output enable bit (bits 6 and 7 at address 1F16) is “0.” Note :

7702/7703 Group User’s Manual7–42 Fig. 7.4.4 Writing data after start of transmission [When not using interrupts] [When using interrupts] The UARTi transmit interrupt request occurs when the UARTi transmit buffer register becomes empty. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi transmit interrupt Note : UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) b7 b0 Writing of next transmit data Set transmit data here. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Transmit buffer empty flag 0: Data present in transmit buffer register 1: No data present in transmit buffer register (Writing of next transmit data is possible.) Checking state of UARTi transmit buffer register This figure shows the bits and registers required for processing. Refer to Figures 7.4.6 and 7.4.7 about the change of flag state and the occurrence timing of an interrupt request. b8b15

7702/7703 Group User’s Manual 7–43 SERIAL I/O Fig. 7.4.5 Detection of transmission’s completion [When not using interrupts] [When using interrupts] /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi transmit interrupt UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 Interrupt request bit Checking start of transmission UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 Checking completion of transmission. Transmit register empty flag 0: During transmitting 1: Transmitting completed Processing at completion of transmission No interrupt request Interrupt request (Transmission has started.) The UARTi transmit interrupt request occurs when the transmission starts. Note :This figure shows the bits and registers required for processing. Refer to Figures 7.4.6 to 7.4.7 about the change of flag state and the occurrence timing of an interrupt request.

7702/7703 Group User’s Manual7–44

7.4.4 Transmit operation

Simultaneously when the transmit conditions listed on page 7-40 are satisfied, the following operations are automatically performed.

• The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
• The transmit buffer empty flag is set to “1.”
• The transmit register empty flag is cleared to “0.”
• The UARTi transmit interrupt request occurs and the interrupt request bit is set to “1.” The transmit operations are described below. À Data in the UARTi transmit register is transmitted from the TxD i pin. \` This data is transmitted bit by bit sequentially in order of ST→ DATA (LSB) → •••→ DATA (MSB) → PAR → SP according to the set transfer data format. ´ When the stop bit has been transmitted, the transmission register empty flag is set to “1,” indicating completion of transmission. When the transmit conditions for the next data are satisfied at completion of transmission, the start bit is generated following the stop bit, and the next data is transmitted. When performing transmission continuously, set the next transmit data in the UARTi transmit buffer register during transmission (when the transmit register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the TxD i pin outputs “H” level. Figures 7.4.6 shows example of transmit timing when the transfer data length is 8 bits, and Figure 7.4.7 shows an example of transmit timing when the transfer data length is 9 bits.

7702/7703 Group User’s Manual 7–45 SERIAL I/O Fig. 7.4.6 Example of transmit timing when transfer data length is 8 bits (when parity enabled, selecting 1 stop bit) Fig. 7.4.7 Example of transmit timing when transfer data length is 9 bits (when parity disabled, selecting 2 stop bits) Tc D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP D 0 D 1D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP ST TENDi TxD i CTS i “0” “1” “0” “1” “L” “H” “0” “1” “0” “1” TENDi: Next transmit conditions are examined when this signal level is “H.” (TENDi is an internal signal. Accordingly, it cannot be read from an external.) Tc: 16(n + 1)/fi or 16(n + 1)/fEXT fi: BRGi count source frequency (f2, f16, f64, f512) fEXT : BRGi count source frequency (external clock) n: Value set to BRGi Transfer clock Transmit enable bit Transmit buffer empty flag Transmit register empty flag UARTi transmit interrupt request bit Data is set in UARTi transmit buffer register. Start bit Parity bit Cleared to “0” when interrupt request is accepted or cleared by software. The above timing diagram applies to the following conditions: l Parity enabled l 1 stop bit l CTS function selected UARTi transmit register UARTi transmit buffer register Stopped because transmit enable bit = “0” Stop bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SP D 0 D 1STD 8 SP SP SP “0” “1” “0” “1” “0” “1” Tc “0” “1” TENDi TxD i TENDi: Next transmit conditions are examined when this signal level is “H.” (TENDi is an internal signal. Accordingly, it cannot be read from an external.) Tc: 16(n + 1)/fi or 16(n + 1)/fEXT fi: BRGi count source frequency (f2, f16, f64, f512) fEXT : BRGi count source frequency (external clock) n: Value set to BRGi Transfer clock Transmit enable bit Transmit buffer empty flag Transmit register empty flag UARTi transmit interrupt request bit Data is set in UARTi transmit buffer register. Start bit Cleared to “0” when interrupt request is accepted or cleared by software. The above timing diagram applies to the following conditions: l Parity disabled l 2 stop bits l CTS function disabled UARTi transmit register UARTi transmit buffer register Stopped because transmit enable bit = “0” Stop bitStop bit

7702/7703 Group User’s Manual7–46

7.4.5 Method of reception

Figure 7.4.8 shows an initial setting example for relevant registers when receiving. Reception is started when all of the following conditions (À and \ ) are satisfied: À Reception is enabled (receive enable bit = “1”). \ The start bit is detected. When using interrupts, it is necessary to set the corresponding register to enable interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Figure 7.4.9 shows processing after reception’s completion.

7702/7703 Group User’s Manual 7–47 SERIAL I/O Fig. 7.4.8 Initial setting example for relevant registers when receiving Reception starts when the start bit is detected. Port P8 direction register (Address 1416) b7 b0 RxD 0 pin RxD 1 pin UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Set to 00 to FF . UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to level 1–7. When disabling interrupts, set these bits to level 0. Note: Set the transfer data format in the same way as set on the transmitter side. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Receive enable bit 1: Reception enabled UART0 transmit/receive mode register (Address 30 ) UART1 transmit/receive mode register (Address 38 ) b7 b0 Internal/External clock select bit 0: Internal clock 1: External clock 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity disabled 1: Parity enabled Sleep select bit 0: Sleep mode cleared (ignored) 1: Sleep mode selected b2b1b0 UART0 transmit/receive control register 0 (Address 34 ) UART1 transmit/receive control register 0 (Address 3C ) b7 b0 BRG count source select bits CTS /RTS select bit 0 : CTS function selected 1 : RTS function selected 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b1b0 16 16

7702/7703 Group User’s Manual7–48 Fig. 7.4.9 Processing after reception’s completion [When not using interrupts] [When using interrupts] The UARTi receive interrupt request occurs when reception is completed. UARTi receive interrupt Processing after reading out receive data UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) b15 b8 Reading of receive data Read out receive data. b7 b0 0000000 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Receive complete flag 0 : Reception not completed 1 : Reception completed Checking completion of reception UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 Checking error Framing error flag Parity error flag Error sum flag 0 : No error 1 : Error detected Note :This figure shows the bits and registers required for processing. Refer to Figure 7.4.11 about the change of flag state and the occurrence timing of an interrupt request. Overrun error flag This figure shows the bits and registers required for processing. Refer to Figure 7.4.11 about the change of flag state and the occurrence timing of an interrupt request.

7702/7703 Group User’s Manual 7–49 SERIAL I/O

7.4.6 Receive operation

When the receive enable bit is set to “1,” the UARTi enters the reception enabled state and reception starts at detecting ST. The receive operation is described below. À The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register synchronously with the transfer clock’s rising. \ The contents of UARTi receive register are shifted by 1 bit to the right. ´ Steps À and \ are repeated at each rising of the transfer clock. ˆ When one set of data has been prepared, in other words, the shift according to the selected data format has been completed; the UARTi receive register’s contents are transferred to the UARTi receive buffer register. ˜ Simultaneously with step ˆ , the receive complete flag is set to “1,” and the UARTi receive interrupt request occurs and its interrupt request bit is set to “1.” The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register is read out. Figure 7.4.11 shows an example of receive timing when the transfer data length is 8 bits. TxD i RxD i TxD i RxD i Transmitter side Receiver side Fig. 7.4.10 Connection example

7702/7703 Group User’s Manual7–50 Fig. 7.4.11 Example of receive timing when transfer data length is 8 bits (when parity disabled, selecting 1 stop bit) D 0 D 1 D 7RxD i RTS i “1” “0” “0” “1” “H” “L” “0” “1” The above timinig diagram applies to the following conditions: l Parity disabled l 1 stop bit l RTS function selected BRGi count source Receive enable bit Transfer clock Receive complete flag UARTi receive interrupt request bit Start bit Sampled “L” Receive data taken in Stop bit Reception started at falling of start bitUARTi receive register UARTi receive buffer register Cleared to “0” when interrupt request is accepted or cleared by software.

7702/7703 Group User’s Manual 7–51 SERIAL I/O

7.4.7 Process on detecting error

Errors listed below can be detected in the UART mode: l Overrun error An overrun error occurs when the next data is prepared in the UARTi receive register with the receive completion flag = “1” (that is, data present in the UARTi receive buffer register) and that data is transferred to the UARTi receive buffer register. In other words, when the next data is prepared before the contents of the UARTi receive buffer register is read out, an overrun error occurs. When an overrun error occurs, the next receive data is written into the UARTi receive buffer register, and the UARTi receive interrupt request bit is not changed. However it is impossible to detect an overrun error as the case may be. Refer to 1 in “ [Precautions when operating in clock asynchronous serial I/O mode].” l Framing error A framing error occurs when the number of detected stop bits does not match the number of stop bits set. (The UARTi interrupt request bit becomes “1.”) l Parity error A parity error occurs when the sum of “1”s in the parity bit and character bits does not match the number of “1”s set. (The UARTi interrupt request bit becomes “1.”) Each error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register, and the corresponding error flag is set to “1.” Furthermore, when any of the above errors occurs, the error sum flag is set to “1.” Accordingly, the error sum flag informs the user whether any error has occurred or not. Error flags such as the overrun error flag, the framing error flag, the parity error flag, the error sum flag are cleared to “0” by reading the contents of the UARTi receive buffer register low-order byte or clearing the receive enable bit to “0.” When errors occur during reception, initialize the error flags and the UARTi receive buffer register, and then perform reception again. When it is necessary to perform retransmission owing to an error which occurs in the receiver side, set the UARTi transmit buffer register again, and then starts transmission again. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below. (1) Method of initializing UARTi receive buffer register À Clear the receive enable bit to “0” (reception disabled). \ Set the receive enable bit to “1” again (reception enabled). (2) Method of setting UARTi transmit buffer register again À Clear the serial I/O mode select bits to “000 2” (serial I/O ignored). \ Set the serial I/O mode select bits again. ´ Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi transmit buffer register.

7702/7703 Group User’s Manual7–52

7.4.8 Sleep mode

This mode is used to transfer data between the specified microcomputers, which are connected by using UARTi. The sleep mode is selected by setting the sleep select bit (bit 7 at addresses 3016, 3816) to “1” when receiving. In the sleep mode, receive operation is performed when the MSB (D 8 when the transfer data length is 9 bits, D7 when it is 8 bits, D6 when it is 7 bits) of the receive data is “1.” Receive operation is not performed when the MSB is “0.” (The UARTi receive register’s contents are not transferred to the UARTi receive buffer register. Additionally, the receive complete flag and error flags do not change and the UARTi receive interrupt request does not occur.) The following shows an usage example of sleep mode when the transfer data length is 8 bits. À Set the same transfer data format for the master and slave microcomputers. Select the sleep mode for the slave microcomputers. \ Transmit data, which has “1” in bit 7 and the address of the slave microcomputer with which communicates in bits 0 to 6, from the master microcomputer to all slave microcomputers. ´ All slave microcomputers receive data of step \ . (At this time, the UARTi receive interrupt request occurs.) ˆ In all slave microcomputers, check in the interrupt routine whether bits 0 to 6 in the receive data match their addresses. ˜ In the slave microcomputer of which address matches bits 0 to 6 in the receive data, clear the sleep mode. (Do not clear the sleep mode for the other slave microcomputers.) By performing steps \ to ˜ , “specification of the microcomputer performing transfer” is realized. ¯ Transmit data, which has “0” in bit 7, from the master microcomputer. (Only the microcomputer specified in steps \ to ˜ can receive this data. The other microcomputers do not receive this data.) ˘ By repeating step ¯ , transfer can be performed between the same microcomputers continuously. When communicating with another microcomputer, perform steps \` to ˜ in order to specify the new slave microcomputer. Fig. 7.4.12 Sleep mode Master Slave BSlave A Slave DSlave C Transfer data between the master microcomputer and one slave microcomputer selected from multiple slave microcomputers.

7702/7703 Group User’s Manual 7–53 SERIAL I/O [Precautions when operating in clock asynchronous serial I/O mode] When receiving data continuously, an overrun error cannot be detected in the following situation: when the next data reception is completed between reading the error flag by software and reading the UARTi receive buffer register. Fig. 7.4.13 Case of overrun error cannot be detect (using clock asynchronous seriai I/O mode) D 1 D 6 D 7D 0ST SP ST D 1 D 7 SPD 0 Data reading Data A error flag (No error ) Data B reading Receive complete flag Overrun error flag UARTi receive interruput request bit Software management Undefined Data A Error flag reading À When checking this error flag by software, the microcomputer judges errors nothing because errors do not have occurred at data A receiving. \` When receiving the data B, the data B is written to the UARTi receive buffer register and the data A is cleard and the overrun error flag becomes “1” simultaneously. The UARTi receive interrupt request bit does not change. ´ When reading the UARTi receive buffer register by software, the data B is read and the overrun error flag becomes “0” simultaneously. Accordingly, the overrun error cannot may be detected and it is possible that the data B is managed as the data A. Transfer clock RxD UARTi receive buffer register Data B À l 8-bit data length, parity disabled, 1 stop bit

7702/7703 Group User’s Manual7–54

8.1 Overview

8.2 Block description

8.3 A-D conversion method

8.4 Absolute accuracy and differential

8.5 One-shot mode

8.6 Repeat mode

8.7 Single sweep mode

8.8 Repeat sweep mode

8.9 Precautions when using A-D converter

7702/7703 Group User’s Manual8–2 This chapter describes the A-D converter. The 7702 Group has a built-in 8-bit A-D converter. The A-D converter performs successive approximation conversion. The 7702 Group has the 8 analog input pins. The number of the 7703 Group’s analog input pins is different from the 7702 Group’s. Refer to “Chapter 20. 7703 GROUP ” for more information. The A-D converter has the performance specifications listed in Table 8.1.1. Table 8.1.1 Performance specifications of A-D converter Conversion rate per analog input pin Performance specifications Successive approximation conversion method 8 bits ±3 LSB 8 pins (AN 0 to AN7) (Note) 57 φAD ] cycles φAD ] : A-D converter’s operation clock Note: In the 7703 Group, the analog input pins are 4 pins, AN0 to AN2, AN7. Refer to “Chapter 20. 7703 GROUP ” for more information. The A-D converter has the 4 operation modes listed below.

• One-shot mode This mode is used to perform the operation once for a voltage input from one selected analog input pin.
• Repeat mode This mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin.
• Single sweep mode This mode is used to perform the operation for voltages input from multiple selected analog input pins, one at a time.
• Repeat sweep mode This mode is used to perform the operation repeatedly for voltages input from multiple selected analog input pins.

7702/7703 Group User’s Manual 8–3 Figure 8.2.1 shows the block diagram of the A-D converter. Registers relevant to the A-D converter are described below. Fig. 8.2.1 Block diagram of A-D converter AV SS VREF Vref AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7/ADTRG VIN 1/2f2 1/2 AD Decoder Resistor ladder network Successive approximation register A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 A-D register 0 A-D register 1 A-D control register Comparator Selector Data bus (even) A-D sweep pin select register

7702/7703 Group User’s Manual8–4

8.2.1 A-D control register

Figure 8.2.2 shows the structure of the A-D control register. The A-D operation mode select bit selects the operation mode of the A-D converter. The other bits are described below. Fig. 8.2.2 Structure of A-D control register (1) Analog input select bits (bits 2 to 0) These bits are used to select an analog input pin in the one-shot mode and repeat mode. Pins which are not selected as analog input pins function as programmable I/O ports. These bits must be set again when the user switches the A-D operation mode to the one-shot mode or repeat mode after performing the operation in the single sweep mode or repeat sweep mode. b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (Address 1E16) Bit A-D conversion frequency ( AD ) select bit A-D conversion start bit Trigger select bit A-D operation mode select bits Bit name At reset Undefined RWFunctions 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected (Note 2) b2 b1 b0 0 : Internal trigger 1 : External trigger 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 : Stop A-D conversion 1 : Start A-D conversion b4 b3 Notes 1: These bits are ignored in the single sweep and repeat sweep mode. (They may be either “0” or “1.”) 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts. Analog input select bits (Valid in one-shot and repeat modes) (Note 1) Undefined Undefined RW RW RW RW RW RW RW RW 0 : f2 divided by 4 1 : f2 divided by 2

7702/7703 Group User’s Manual 8–5 (2) Trigger select bit (bit 5) This bit is used to select the source of trigger occurrence. (Refer to “(3) A-D conversion start bit.”) (3) A-D conversion start bit (bit 6) l When internal trigger is selected Setting this bit to “1” generates a trigger, causing the A-D converter to start operating. Clearing this bit to “0” causes the A-D converter to stop operating. In the one-shot mode or single sweep mode, this bit is cleared to “0” after the operation is completed. In the repeat mode or repeat sweep mode, the A-D converter continues operating until this bit is cleared to “0” by software. l When external trigger is selected When the AD TRG pin level goes from “H” to “L” with this bit = “1,” a trigger occurs, causing the A-D converter to start operating. The A-D converter stops when this bit is cleared to “0.” In the one-shot mode or single sweep mode, this bit remains set to “1” even after the operation is completed. In the repeat mode or repeat sweep mode, the A-D converter continues operating until this bit is cleared to “0” by software. (4) A-D conversion frequency ( φAD ) select bit (bit 7) As shown in Table 8.2.1, the operating time of the A-D converter varies depending on the selected operating clock ( φAD ) by this bit. Since the A-D converter’s comparator consists of capacity coupling amplifiers, keep that φAD ≥ 250 kHz during A-D conversion. Table 8.2.1 Time for performance to one analog input pin (unit: µs) f2/2 28.5 14.25 9.12 f2/4 57.0 28.5 18.24 A-D conversion frequency (φAD ) select bit φAD Conversion time f(XIN) = 8 MHz f(XIN) = 16 MHz f(XIN) = 25 MHz

7702/7703 Group User’s Manual8–6

8.2.2 A-D sweep pin select register

Figure 8.2.3 shows the structure of the A-D sweep pin select register. Fig. 8.2.3 Structure of A-D control register 1 (1) A-D sweep pin select bits (bits 1 and 0) These bits are used to select analog input pins in the single sweep mode or repeat sweep mode. In the single sweep mode and repeat sweep mode, pins which are not selected as analog input pins function as programmable I/O ports. b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select register (Address 1F16) Bit Bit name At reset Undefined RWFunctions Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”) 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit of the A-D sweep pin select register must be performed while the A-D converter halts. 7 to 2 RW0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) (Note 2) A-D sweep pin select bits (Valid in single sweep and repeat sweep mode ) (Note 1) b1 b0 1 RW Nothing is assigned. –

7702/7703 Group User’s Manual 8–7

8.2.3 A-D register i (i = 0 to 7)

Figure 8.2.4 shows the structure of the A-D register i. When the A-D conversion is completed, the conversion result (contents of the successive approximation register) is stored into this register. Each A-D register i corresponds to an analog input pin (ANi). Table 8.2.2 lists the correspondence of an analog input pin to A-D register i. A-D register 0 (Addresses 2016) A-D register 1 (Addresses 2216) A-D register 2 (Addresses 2416) A-D register 3 (Addresses 2616) A-D register 4 (Addresses 2816) A-D register 5 (Addresses 2A16) A-D register 6 (Addresses 2C16) A-D register 7 (Addresses 2E16) Bit 7 to 0 At reset Undefined RWFunctions ROReads an A-D conversion result. b7 b6 b5 b4 b3 b2 b1 b0 Fig. 8.2.4 Structure of A-D register i A-D register i where conversion result is stored A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 Table 8.2.2 Correspondence of analog input pin and A-D register i Analog input pin AN 0 pin AN 1 pin AN 2 pin AN 3 pin AN 4 pin AN 5 pin AN 6 pin AN 7 pin

7702/7703 Group User’s Manual8–8

8.2.4 A-D conversion interrupt control register

Figure 8.2.5 shows the structure of the A-D conversion interrupt control register. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” Fig. 8.2.5 Structure of A-D conversion interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select the A-D conversion interrupt’s priority level. When using A-D conversion interrupts, select priority levels 1 to 7. When an A-D conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL) and the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable the A-D conversion interrupt, set these bits to “000 2” (level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when an A-D conversion interrupt request occurs. This bit is automatically cleared to “0” when the A-D conversion interrupt request is accepted. This bit can be set to “1” or cleared to “0” by software. b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion interrupt control register (Address 7016) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned. Note : Use the SEB or CLB instruction to set the A-D conversion interrupt control register.

7702/7703 Group User’s Manual 8–9

8.2.5 Port P7 direction register

The A-D converter and port P7 use the same pins in common. When using these pins as the A-D converter’s input pins, set the corresponding bits of the port P7 direction register to “0” to set these ports for the input mode. Figure 8.2.6 shows the relationship between the port P7 direction register and A-D converter’s input pins. Fig. 8.2.6 Relationship between port P7 direction register and A-D converter’s input pins Bit Corresponding pin Functions AN 0 pin 0 : Input mode 1 : Output mode When using these pins as A-D converter’s input pins, set the corresponding bits to “0.” Port P7 direction register (Address 1116) b1 b0b2b3b4b5b6b7 At reset RW RW RW RW RW RW RW RW RW AN 1 pin AN 2 pin AN 3 pin AN 4 pin AN 5 pin AN 6 pin AN 7/ADTRG pin

7702/7703 Group User’s Manual8–10 A-D CONVERTER The A-D converter compares the comparison voltage (Vref), which is internally generated according to the contents of the successive approximation register, with the analog input voltage (VIN), which is input from the analog input pin (ANi). By reflecting the comparison result on the successive approximation register, VIN is converted into a digital value. When a trigger is generated, the A-D converter performs the following processing: À Determining bit 7 of the successive approximation register The A-D converter compares Vref with VIN. At this time, the contents of the successive approximation register is “100000002” (initial value). Bit 7 of the successive approximation register changes according to the comparison result as follows: When V ref < VIN, bit 7 = “1” When V ref > VIN, bit 7 = “0” \ Determining bit 6 of the successive approximation register After setting bit 6 of the successive approximation register to “1,” the A-D converter compares Vref with VIN. Bit 6 changes according to the comparison result as follows: When V ref < VIN, bit 6 = “1” When V ref > VIN, bit 6 = “0” ´ Determining bits 5 to 0 of the successive approximation register Operations in \ are performed for bits 5 to 0. When bit 0 is determined, the contents (conversion result) of the successive approximation register is transferred to the A-D register i. The comparison voltage (Vref) is generated according to the latest contents of the successive approximation register. Table 8.3.1 lists the relationship between the successive approximation register’s contents and Vref. Table 8.3.2 lists changes of the successive approximation register and Vref during the A-D conversion. Figure 8.3.1 shows the ideal A-D conversion characteristics. Table 8.3.1 Relationship between successive approximation register’s contents and Vref V REF ] 256 Successive approximation register’s contents: n 1 to 255 5 (n – 0.5) V ref (V) V REF ]: Reference voltage

7702/7703 Group User’s Manual 8–11 A-D CONVERTER Table 8.3.2 Change in successive approximation register and Vref during A-D conversion Successive approximation register C hange of Vref A-D converter halt 1st comparison 2nd comparison 3rd comparison 8th comparison Conversion complete VREF 512 VREF VREF VREF VREF – 512 VREF VREF VREF VREF – 512 VREF ± ±2 VREF VREF 256 – 512 VREF [V] [V] [V] [V] [V] VREF•n7=1 VREF

• n7=0 VREF VREF
• n6=1
• n6=0 : : Fig. 8.3.1 Ideal A-D conversion characteristics 0016 0116 0216 0316 FE 16 FF16 Analog input voltage VREF 256 5 1 VREF 256 5 2 VREF 256 5 3 5 253VREF 256 VREF 256 5 254 VREF 256 5 255 VREF VREF 256 5 0.5 ldeal A-D conversion characteristics A-D conversion result FD 16

7702/7703 Group User’s Manual8–12 A-D CONVERTER

8.4 Absolute accuracy and differential non-linearity error

The A-D converter’s accuracy is described below.

8.4.1 Absolute accuracy

The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result and the output code of an A-D converter with ideal characteristics. The analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an A-D converter with ideal characteristics. For example, when V REF = 5.12 V, 1 LSB width is 20 mV, and 0 mV, 20 mV, 40 mV, 60 mV, 80 mV, ... are selected as the analog input voltages. The absolute accuracy = ±3 LSB indicates that when the analog input voltage is 100 mV, the output code expected from an ideal A-D conversion characteristics is “005 16,” however the actual A-D conversion result is between “00216” to “00816.” The absolute accuracy includes the zero error and the full-scale error. The absolute accuracy degrades when VREF is lowered. The output code for analog input voltages VREF to AV CC is “FF16.” Fig. 8.4.1 Absolute accuracy of A-D converter 0016 0116 0216 0316 0416 0516 0616 0 20 40 60 80 100 120 140 160 180 200 220 0716 0816 0916 0A16 0B16 +3 LSB –3 LSB Ideal A-D conversion characteristics Analog input voltage (mV) Output code (A-D conversion result)

7702/7703 Group User’s Manual 8–13 A-D CONVERTER

8.4.2 Differential non-linearity error

The differential non-linearity error indicates the difference between the 1 LSB step width (the ideal analog input voltage width while the same output code is expected to output) of an A-D converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). For example, when V REF = 5.12 V, the 1 LSB width of an A-D converter with ideal characteristics is 20 mV, however when the differential non-linearity error is ±1 LSB, the actual measured 1 LSB width is 0 to 40 mV. (Refer to section “16.1.3 A-D converter standard characteristics.”) Fig. 8.4.2 Differential non-linearity error 0016 0116 0216 0316 0416 0516 0616 0 20 40 60 80 100 120 140 160 180 0716 0816 0916 Output code (A-D conversion result) Differential non-linearity error Analog input voltage (mV)

1 LSB width with ideal

A-D conversion characteristics

7702/7703 Group User’s Manual8–14 A-D CONVERTER In the one-shot mode, the operation for the input voltage from the one selected analog input pin is performed once, and the A-D conversion interrupt request occurs when the operation is completed.

8.5.1 Settings for one-shot mode

Figure 8.5.1 shows an initial setting example of the one-shot mode. When using an interrupt, it is necessary to set the relevant registers to enable the interrupt. Refer to “Chapter 4. INTERRUPTS” for more descriptions.

7702/7703 Group User’s Manual 8–15 A-D CONVERTER Fig. 8.5.1 Initial setting example of one-shot mode b7 b0 A-D control register (address 1E16)000 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected b1 b0b2 Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0: Stop A-D conversion Analog input select bits A-D conversion frequency (AD ) select bit 0 : f2 divided by 4 1 : f2 divided by 2 l A-D control register One-shot mode Note : Write each bit (except bit 6) of the A-D control register when the A-D conversion stops (before trigger occurs). l Interrupt priority level b7 b0 A-D conversion interrupt control register (address 7016) Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt. Set to a level 0 when disabling this interrupt. l Set A-D conversion start bit to “1” b7 b0 A-D control register (address 1E16)1 A-D conversion start bit Selecting external trigger Selecting internal trigger Input falling edge to AD TRG pin Trigger occur Operation start b7 b0 Port P7 direction register (address 1116) l Port P7 direction register Set the bits corresponding to analog input pins to “0.” Set bit 7 to “0” when selecting external trigger. AN AN 2 AN 3 AN 5 AN 6 AN 7 AN 4 AN 0

7702/7703 Group User’s Manual8–16 A-D CONVERTER

8.5.2 One-shot mode operation description

(1) When an internal trigger is selected À The A-D converter starts operation when the A-D conversion start bit is set to “1.” \ The A-D conversion is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. ´ At the same time as step \ , the A-D conversion interrupt request bit is set to “1.” ˆ The A-D conversion start bit is cleared to “0” and the A-D converter stops operation. (2) When an external trigger is selected _____ À The A-D converter starts operation when the input level to the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.” \ The A-D conversion is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. ´ At the same time as step \ , the A-D conversion interrupt request bit is set to “1.” ˆ The A-D conversion stops operation. The A-D conversion start bit remains set to “1” after the operation is completed. Accordingly, the_____ operation of the A-D converter can be performed again from step À when the level of the ADTRG pin When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point is cancelled and is restarted from step À . Figure 8.5.2 shows the conversion operation in the one-shot mode. Fig. 8.5.2 Conversion operation in one-shot mode Trigger occur Convert input voltage from AN i pin Conversion result A-D register i A-D conversion interrupt request occurs. A-D converter stops.

7702/7703 Group User’s Manual 8–17 A-D CONVERTER In the repeat mode, the operation for the input voltage from the one selected analog input pin is performed repeatedly. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E 16) remains set to “1” until it is cleared to “0” by software, and the operation is performed repeatedly while the A-D conversion start bit is “1.”

8.6.1 Settings for repeat mode

Figure 8.6.1 shows an initial setting example of repeat mode.

7702/7703 Group User’s Manual8–18 A-D CONVERTER Fig. 8.6.1 Initial setting example of repeat mode b7 b0 Port P7 direction register (address 1116) l Port P7 direction register Set the bits corresponding to analog input pins to “0.” Set bit 7 to “0” when selecting external trigger. l Set A-D conversion start bit to “1” b7 b0 A-D control register (address 1E16)1 A-D conversion start bit Selecting external trigger Selecting internal trigger Trigger occur Operation start Note : Write the each bit (except bit 6) of the A-D control regiter when the A-D conversion stops (before trigger occurs). Input falling edge to AD TRG pin AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 b7 b0 A-D control register (address 1E16)010 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected b1 b0b2 A-D conversion start bit 0: Stop A-D conversion Analog input select bits A-D conversion frequency (AD ) select bit l A-D control register Repeat mode Trigger select bit 0 : Internal trigger 1 : External triggeer 0 : f 2 divided by 4 1 : f2 divided by 2

7702/7703 Group User’s Manual 8–19 A-D CONVERTER

8.6.2 Repeat mode operation description

(1) When an internal trigger is selected À The A-D converter starts operation when the A-D conversion start bit is set to “1.” \ The first A-D conversion is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. ´ The A-D converter repeats operation until the A-D conversion start bit is cleared to “0” by software. The conversion result is transferred to the A-D register i each time the conversion is completed. (2) When an external trigger is selected ____ À The A-D converter starts operation when the input level to the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.” \ The first A-D conversion is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. ´ The A-D converter repeats operation until the A-D conversion start bit is cleared to “0” by software. The conversion result is transferred to the A-D register i each time the conversion is completed. When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point is cancelled and is restarted from step À . Figure 8.6.2 shows the conversion operation in the repeat mode. Trigger occur Convert input voltage from AN i pin Conversion result A-D register i Fig. 8.6.2 Conversion operation in repeat mode

7702/7703 Group User’s Manual8–20 A-D CONVERTER In the single sweep mode, the operation for the input voltage from multiple selected analog input pins is performed, one at a time. The A-D converter is operated in ascending sequence from the AN0 pin. The A-D conversion interrupt request occurs when the operation for all selected input pins are completed.

8.7.1 Settings for single sweep mode

Figure 8.7.1 shows an initial setting example of single sweep mode. When using an interrupt, it is necessary to set the relevant registers to enable the interrupt. Refer to “Chapter 4. INTERRUPTS” for more information.

7702/7703 Group User’s Manual 8–21 A-D CONVERTER Fig. 8.7.1 Initial setting example of single sweep mode b7 b0 Port P7 direction register (address 1116) l Port P7 direction register Set the bits corresponding to analog input pins to “0.” Set bit 7 to “0” when selecting external trigger. l Set A-D conversion start bit to “1” b7 b0 A-D control register (address 1E16)1 A-D conversion start bit l Interrupt priority level b7 b0 A-D conversion interrupt control register (address 7016) Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt. Set to a level 0 when disabling this interrupt. Selecting external trigger Selecting internal trigger Trigger occur Operation start Note : Write each bit (except bit 6) of the A-D control register and each bit of the A-D sweep pin select register when the A-D conversion stops (before trigger occurs). Input falling edge to AD TRG pin AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 A-D control register (address 1E16) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0–AN 3 (4 pins) 1 0 : AN0–AN 5 (6 pins) 1 1 : AN0–AN 7 (8 pins) b1 b0 Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0: Stop A-D conversion A-D conversion frequency (AD ) select bit 0 : f 2 divided by 4 1 : f2 divided by 2 b7 b0 l A-D control register and A-D sweep pin select register A-D sweep pin select register (address 1F16) b7 b0 100 555 A-D sweep pin select bits 5 : “0” or “1” Single sweep mode

7702/7703 Group User’s Manual8–22 A-D CONVERTER

8.7.2 Single sweep mode operation description

(1) When an internal trigger is selected À The operation for the input voltage from the AN0 pin starts when the A-D conversion start bit is set to “1.” \ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. ´ The operation to all selected analog input pins is performed. The conversion result is transferred to the A-D register i each time each pin is converted. ˆ When the step ´ is completed, the A-D conversion interrupt request bit is set to “1.” ˜ The A-D conversion start bit is cleared to “0” and the A-D converter stops operation. (2) When an external trigger is selected À The A-D converter starts operation for the input voltage from the AN0 pin when the input level to_____ the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.” \ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. ´ The operation to all selected analog input pins is performed. The conversion result is transferred to the A-D register i each time each pin is converted. ˆ When the step ´ is completed, the A-D conversion interrupt request bit is set to “1.” ˜ The A-D conversion stops operation. The A-D conversion start bit remains set to “1” after the operation is completed. Accordingly, the operation of the A-D converter can be performed again from step À when the level of the ADTRG pin When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point is cancelled and is restarted from step À . Figure 8.7.2 shows the conversion operation in the single sweep mode.

7702/7703 Group User’s Manual 8–23 A-D CONVERTER Convert input voltage from AN 0 pin Conversion result A-D register 0 A-D register i A-D register 1 Conversion result Conversion result A-D converter halt A-D converter interrupt request occur Convert input voltage from AN 1 pin Convert input voltage from AN i pin Fig. 8.7.2 Conversion operation in single sweep mode

7702/7703 Group User’s Manual8–24 A-D CONVERTER In the repeat sweep mode, the operation for the input voltage from the multiple selected analog input pins is performed repeatedly. The A-D converter is operated in ascending sequence from the AN0 pin. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E 16) remains set to “1” until it is cleared to “0” by software, and the operation is performed repeatedly while the A-D conversion start bit is “1.”

8.8.1 Settings for repeat sweep mode

Figure 8.8.1 shows an initial setting example of repeat sweep mode.

7702/7703 Group User’s Manual 8–25 A-D CONVERTER Fig. 8.8.1 Initial setting example of repeat sweep mode b7 b0 Port P7 direction register (address 1116) l Port P7 direction register Set the bits corresponding to analog input pins to “0.” Set bit 7 to “0” when selecting external trigger. l Set A-D conversion start bit to “1” b7 b0 A-D control register (address 1E16)1 A-D conversion start bit Selecting external trigger Selecting internal trigger Trigger occur Operation start Note : Write each bit (except bit 6) of the A-D control register and each bit of the A-D sweep pin select register when the A-D conversion stops (before trigger occurs). Input falling edge to AD TRG pin AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 A-D control register (address 1E16) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0–AN 3 (4 pins) 1 0 : AN0–AN 5 (6 pins) 1 1 : AN0–AN 7 (8 pins) b1 b0 Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0: Stop A-D conversion A-D conversion frequency (AD ) select bit 0 : f 2 divided by 4 1 : f2 divided by 2 b7 b0 l A-D control register and A-D sweep pin select register A-D sweep pin select register (address 1F16) b7 b0 110 555 A-D sweep pin select bits 5 : “0” or “1” Repeat sweep mode

7702/7703 Group User’s Manual8–26 A-D CONVERTER

8.8.2 Repeat sweep mode operation description

(1) When an internal trigger is selected À The operation for the input voltage from the AN0 pin starts when the A-D conversion start bit is set to “1.” \ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. ´ The operation to all selected analog input pins is performed. The conversion result is transferred to the A-D register i each time each pin is converted. ˆ The operation to all selected analog input pins is performed again. ˜ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by software. (2) When an external trigger is selected À The A-D converter starts operation for the input voltage from the AN0 pin when the input level to______ the ADTRG pin changes from “H” to “L” while the A-D conversion start bit is “1.” \ The A-D conversion of the input voltage from the AN0 pin is completed after 57 cycles of φAD . Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. ´ The operation to all selected analog input pins is performed. The conversion result is transferred to the A-D register i each time each pin is converted. ˆ The operation to all selected analog input pins is performed again. ˜ The operation is performed repeatedly until the A-D conversion start bit is cleared to “0” by software. When the level of the ADTRG pin changes from “H” to “L” during operation, the operation at that point is cancelled and is restarted from step À . Figure 8.8.2 shows the conversion operation in the repeat sweep mode.

7702/7703 Group User’s Manual 8–27 A-D CONVERTER Convert input voltage from AN0 pin Conversion result A-D register 0 A-D register i A-D register 1Conversion result Conversion result Convert input voltage from AN1 pin Convert input voltage from ANi pin Fig. 8.8.2 Conversion operation in repeat sweep mode

7702/7703 Group User’s Manual8–28 A-D CONVERTER

8.9 Precautions when using A-D converter

1. Write to each bit (except bit 6) of the A-D control regisrer and each bit of the A-D sweep pin select register before a trigger occurs (while the A-D converter stops operation). 2. When selecting the AN7 pin as an analog input pin while an external trigger is selected, A-D conversion_____ is performed for a trigger input, which is the input voltage on the ADTRG pin, and the conversion result is stored into the A-D register 7. Consequently, the user cannot use the AN7 pin as an analog input pin while an external trigger is selected. 3. Refer to “Appendix.6 Countermeasures against noise” when using the A-D converter.

9.1 Block description

9.2 Operation description

9.3 Precaution when using watchdog timer

7702/7703 Group User’s Manual9–2 This chapter describes Watchdog timer. Watchdog timer has the following functions: l Detection of a program runaway. l Measurement of a certain time when oscillation starts owing to terminating Stop mode. (Refer to “Chapter 10. STOP MODE.” ) Figure 9.1.1 shows the block diagram of the watchdog timer. Fig. 9.1.1 Block diagram of watchdog timer 2Vcc detection circuit “FFF16” is set. Writing to watchdog timer register (address 6016) STP instruction Hold request Watchdog timer interrupt request RESET S Q R f32 f512 Watchdog timer

7702/7703 Group User’s Manual 9–3

9.1.1 Watchdog timer

Watchdog timer is a 12-bit counter that down-counts the count source which is selected with the watchdog timer frequency select bit (bit 0 at address 6116). A value “FFF16” is automatically set in Watchdog timer in the cases listed below. An arbitrary value cannot be set to Watchdog timer. l When dummy data is written to the watchdog timer register (Refer to Figure 9.1.2.) l When the most significant bit of Watchdog timer becomes “0” l When the STP instruction is executed (Refer to “Chapter 10. STOP MODE.” ) l At reset Fig. 9.1.2 Structure of watchdog timer register b7 b0 Watchdog timer register (Address 6016) Bit Initializes the watchdog timer. When a dummy data is written to this register, the watchdog timer’s value is initialized to “FFF 16.” (Dummy data: 0016 to FF16) At reset Undefined RWFunctions 7 to 0 –

7702/7703 Group User’s Manual9–4

9.1.2 Watchdog timer frequency select register

This is used to select the watchdog timer’s count source. Figure 9.1.3 shows the structure of the watchdog timer frequency select register. Fig. 9.1.3 Structure of watchdog timer frequency select register 0 : f512 1 : f32 At reset Undefined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit Nothing is allocated. Watchdog timer frequency select bit Bit name 7 to 1 RW

7702/7703 Group User’s Manual 9–5 The operation of Watchdog timer is described below.

9.2.1 Basic operation

À Watchdog timer starts down-counting from “FFF16.” \ When the Watchdog timer’s most significant bit becomes “0” (counted 2048 times), the watchdog timer interrupt request occurs. (Refer to Table 9.2.1.) ´ When the interrupt request occurs at above \ , a value “FFF16” is set to Watchdog timer. The watchdog timer interrupt is a nonmaskable interrupt. When the watchdog timer interrupt request is accepted, the processor interrupt priority level (IPL) is set to “1112.” Table 9.2.1 Occurrence interval of watchdog timer interrupt request f(XIN) = 25 MHzWatchdog timer frequency select bit Count source f512 f32 Occurrence interval 41.94 ms 2.62 ms

7702/7703 Group User’s Manual9–6 (1) Example of program runaway detection Write to the address 6016 (watchdog timer register) before the most significant bit of Watchdog timer becomes “0.” In the case that Watchdog timer is used to detect a program runaway, if writing to address 6016 is not performed owing to a program runaway, the watchdog timer interrupt request occurs when the most significant bit of Watchdog timer becomes “0.” It means that a program runaway has occurred. To reset the microcomputer after a program runaway, write “1” to the software reset bit (bit 3 at address 5E 16) in the watchdog timer interrupt routine. Fig. 9.2.1 Example of program runaway detection by Watchdog timer RTI Main routine Watchdog timer interrupt routine Watchdog timer register (Address 6016) 8-bit dummy data Watchdog timer interrupt request occur (program runaway detected) Watchdog timer initialized Value of watchdog timer : “FFF 16” (Note 1) Software reset bit (Address 5E 16, b3) “1” (Note 2) Reset microcomputer Notes 1: Initialize (write to address 6016) Watchdog timer before the most significant bit of Watchdog timer becomes “0” (the watchdog timer interrupt request occurs). 2: When the program runaway occurs, values of the data bank register (DT) and direct page register (DPR) may be changed. When “1” is written to the software reset bit by the addressing mode using DT and DPR, set values to DT and DPR again.

7702/7703 Group User’s Manual 9–7

9.2.2 Operation in Stop mode

In Stop mode, Watchdog timer stops operating. Immediately after Stop mode is terminated, Watchdog timer operates as follows. (1) When Stop mode is terminated by a hardware reset Supply of the φ and φCPU starts immediately after Stop mode is terminated, and the microcomputer performs the “operation after a reset.” (Refer to “Chapter 13. RESET.”) The watchdog timer frequency select bit becomes “0,” and Watchdog timer starts counting of f512 from “FFF16.” (2) When Stop mode is terminated by an interrupt request occurrence Immediately after the stop mode is terminated, Watchdog timer starts counting of the count source f32 from “FFF16.” Supply of the φ and φCPU starts when the Watchdog timer’s most significant bit becomes “0.” (At this time, the watchdog timer interrupt request does not occur.) Supply of the φCPU starts immediately after Stop mode is terminated, and the microcomputer executes the routine of the interrupt which is used to terminate Stop mode. Watchdog timer restarts counting of the count source (Note) from “FFF 16.” Note: Clock f32 or f512 which was counted just before executing the STP instruction.

9.2.3 Operation in Hold state

Watchdog timer stops operating in Hold state. When Hold state [ is terminated, Watchdog timer restarts counting in the same state where it stopped operating. Hold state[: Refer to section “12.4 Hold function.”

7702/7703 Group User’s Manual9–8

9.3 Precautions when using watchdog timer

1. When a dummy data is written to address 6016 with the 16-bit data length, writing to address 6116 is simultaneously performed. Accordingly, when the user does not want to change a value of the watchdog timer frequency select bit (bit 0 at address 6116), write the previous value to the bit simultaneously with writing to address 6016. 2. When the STP instruction (refer to “Chapter 10. STOP MODE” ) is executed, Watchdog timer stops. When Watchdog timer is used to detect the program runaway, select “STP instruction disable” with mask option. 3. To stop Watchdog timer in Hold state, the count source which is actually counted by Watchdog timer is_____ the logical AND product of two signals. One is the inverted signal input from the HOLD pin, and the other_____ is the count source (f32 or f512)(Note). Accordingly, when the HOLD pin’s input signal level changes in a duration which is shorter than 1 cycle of the count source (Note), counting by Watchdog timer can be performed. (Refer to Figure 9.3.1.) Note: It is selected with the watchdog timer frequency select bit. Fig. 9.3.1 Watchdog timer’s count source Clock f32 or f512 HOLD pin input signal Count source actually counted by Watchdog timer When HOLD pin’s input signal level changes in duration which is shorter than 1 cycle of f 32 or f512

10.1 Clock generating circuit

10.2 Operation description

10.3 Precautions for Stop mode

7702/7703 Group User’s Manual STOP MODE 10–2 This chapter describes Stop mode. Stop mode is used to stop oscillation when there is no need to operate the central processing unit (CPU). The microcomputer enters Stop mode when the STP instruction is executed. Stop mode can be terminated by an interrupt request occurrence or the hardware reset. Figure 10.1.1 shows the clock generating circuit. Fig. 10.1.1 Clock generating circuit Q XIN XOUT R S Q R S Q R S CPU 1/8 1/2 1/2 1/8 f16 f64 f512 f32 f512 Interrupt request STP instruction Reset WIT instruction Ready request Request of CPU wait from BIU (acceptance of Hold request included) Operation clock for internal peripheral devices Hold request Watchdog timer CPU : Central Processing Unit Watchdog timer frequency select bit : Bit 0 at address 6116 Note: This is the signal generated when the watchdog timer’s most significant bit becomes “0.” Watchdog timer’s underflow signal (Note) Watchdog timer frequency select bit BIU : Bus Interface Unit

7702/7703 Group User’s Manual 10–3 When the STP instruction is executed, the oscillator stops oscillating. This state is called “Stop mode.” In Stop mode, the contents of the internal RAM can be retained intact when the Vcc, power source voltage, is 2 V or more. Additionally, the microcomputer’s power consumption is reduced. It is because the CPU and all internal peripheral devices using clocks f 2 to f512 stop the operation. Table 10.2.1 lists the microcomputer state and operation in and after Stop mode. Table 10.2.1 Microcomputer state and operation in and after Stop mode State and OperationItem Oscillation φCPU , φ, clock φ1, f2 to f512 Timer A Timer B Serial I/O A-D converter Watchdog timer Pins State in Stop mode Operation after termi- nating Stop mode Stopped Operating enabled only in event counter mode Operating enabled only when selecting external clock Stopped Retains the same state in which the STP instruction was executed Supply of φCPU and φ starts after a certain time measured by watchdog timer has passed. Internal peripheral devices By interrupt request occurrence By hardware reset Operates in the same way as hardware reset

7702/7703 Group User’s Manual STOP MODE 10–4

10.2.1 Termination by interrupt request occurrence

When terminating Stop mode by interrupt request occurrence, instructions are executed after a certain time measured by the watchdog timer has passed. À When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of clock φ1, f2 to f512 starts. \` The watchdog timer starts counting owing to the oscillation start. The watchdog timer counts f32. ´ When the watchdog timer’s MSB becomes “0,” supply of φCPU , φBIU starts. At the same time, the watchdog timer’s count source returns to f32 or f512 that is selected by the watchdog timer frequency select bit (bit 0 at address 6116). ˆ The interrupt request which occurs in À is accepted. Table 10.2.2 lists the interrupts used to terminate Stop mode. Table 10.2.2 Interrupts used to terminate Stop mode Conditions for using each function to generate interrupt requestInterrupt ____ INTi interrupt (i = 0 to 2) Timer Ai interrupt (i = 0 to 4) Timer Bi interrupt (i = 0 to 2) UARTi transmit interrupt (i = 0, 1) UARTi receive interrupt (i = 0, 1) Enabled in event counter mode Enabled when selecting external clock Notes 1: Since the oscillator has stopped oscillating, each function does not work unless they are operated under the above condition. Also, the A-D converter does not work. 2: Since the oscillator has stopped oscillating, no interrupts other than those above can be used. 3: Refer to “Chapter 4. INTERRUPT” and the description of each internal peripheral device for details about each interrupt. Before executing the STP instruction, enable interrupts used to terminate Stop mode. In addition, the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the processor interrupt priority level (IPL) of the routine where the STP instruction is executed. When multiple interrupts in Table 10.2.2 are enabled, Stop mode is terminated by the first interrupt request. There is possibility that all interrupt requests occur after the oscillation starts in À and until supply of φCPU and φBIU starts in ´ . The interrupt requests which occur during this time are accepted in order of priority (Note) after the watchdog timer’s MSB becomes “0.” For interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled) before executing the STP instruction. Note : The interrupt request which has the highest priority is accepted first.

7702/7703 Group User’s Manual 10–5 Fig. 10.2.1 Stop mode terminating sequence by interrupt request occurrence

10.2.2 Termination by hardware reset______

Supply “L” level to the RESET pin by using the external circuit until the oscillation of the oscillator is stabilized. The CPU and the SFR area are initialized in the same way as a system reset. However, the internal RAM area retains the same contents as that before executing the STP instruction. The termination sequence is the same as the internal processing sequence which is performed after a reset. To determine whether a hardware reset was performed to terminate Stop mode or a system reset was performed, use software after a reset. Refer to “Chapter 13. RESET” for details about a reset. “7FF16” “FFF16” “0” “1” Stop mode f(XIN) Operating Stopped Stopped Internal peripheral devices Operating Value of watchdog timer f32 5 2048 counts Interrupt request used to terminate Stop mode (Interrupt request bit) Stopped Operating Operating Operating l Interrupt request used to terminate Stop mode occurs. l Oscillation starts.(When an external clock is input from the X IN pin, clock input starts.) l Watchdog timer starts counting. l STP instruction is executed l Watchdog timer’s MSB = “0” (However, watchdog timer interrupt request does not occur.) l Supply of CPU , BIU starts. l Interrupt request which has been used to terminate Stop mode is accepted. CPU , BIU

7702/7703 Group User’s Manual STOP MODE 10–6

1. When using the STP instruction with the mask ROM version, select “STP instruction enable” with the STP instruction option on the MASK ROM ORDER CONFIRMATION FORM. The STP instruction is always enabled in the built-in PROM version and the external ROM version. 2. When executing the STP instruction after writing to the internal area or an external area, the three NOP instructions must be inserted to complete the write operation before the STP instruction is executed. STA NOP NOP NOP STP A, 5555 ; Writing instruction NOP instruction insertion STP instruction Fig. 10.3.1 NOP instruction insertion example

11.1 Clock generating circuit

11.2 Operation description

11.3 Precautions for Wait mode

7702/7703 Group User’s Manual WAIT MODE 11–2 This chapter describes Wait mode. Wait mode is used to stop φCPU and φ when there is no need to operate the central processing unit (CPU). The oscillator continues its oscillation. The microcomputer enters Wait mode when the WIT instruction is executed. Wait mode can be terminated by an interrupt request occurrence or the hardware reset. Figure 11.1.1 shows the clock generating circuit. Fig. 11.1.1 Clock generating circuit Q XIN XOUT R S Q R S Q R S CPU 1/8 1/2 1/2 1/8 f16 f64 f512 f32 f512 Interrupt request STP instruction Reset WIT instruction Ready request Request of CPU wait from BIU (acceptance of Hold request included) Operation clock for internal peripheral devices Hold request Watchdog timer CPU: Central Processing Unit BIU: Bus Interface Unit Watchdog timer frequency select bit: Bit 0 at address 6116 Note: This is the signal generated when the watchdog timer’s most significant bit becomes “0.” Watchdog timer’s underflow signal (Note) Watchdog timer frequency select bit

7702/7703 Group User’s Manual 11–3 When the WIT instruction is executed, φCPU and φ stop. The oscillator’s oscillation is not stopped. This state is called “Wait mode.” In Wait mode, the microcomputer’s power consumption is reduced though the Vcc is, power source voltage, is maintained. Table 11.2.1 lists the microcomputers state and operation in and after Wait mode. Table 11.2.1 Microcomputer state and operation in and after Wait mode State and OperationItem Operating Stopped Operating Operating Retains the same state in which the WIT instruction was executed State in Wait mode Operation after termi- nating Wait mode Oscillation φCPU , φ Clock φ1, f2 to f512 Timer A Timer B Serial I/O A-D converter Watchdog timer Pins Internal peripheral devices By interrupt request occurrence By hardware reset Supply of φCPU and φ starts just after the termination. Operates in the same way as hardware reset

7702/7703 Group User’s Manual WAIT MODE 11–4

11.2.1 Termination by interrupt request occurrence

À When an interrupt request occurs, supply of clock φCPU and φ starts. \` The interrupt request which occurs in À is accepted. The following interrupts are used to terminate Wait mode. The occurrence of the watchdog timer interrupt request also terminates Wait mode. ____

• INTi interrupt (i = 0 to 2)
• Timer Ai interrupt (i = 0 to 4)
• Timer Bi interrupt (i = 0 to 2)
• UARTi transmit interrupt (i = 0, 1)
• UARTi receive interrupt (i = 0, 1)
• A-D converter interrupt Note : Refer to “Chapter 4. INTERRUPTS ” and each functional description about interrupts. Before executing the WIT instruction, enable interrupts used to terminate Wait mode. In addition, the interrupt priority level of the interrupt used to terminate Wait mode must be higher than the processor interrupt priority level (IPL) of the routine where the WIT instruction is executed. When the above multiple interrupts are enabled, Wait mode is terminated by the first interrupt request.

11.2.2 Termination by hardware reset

The CPU and the SFR area are initialized in the same way as a system reset. However, the internal RAM area retains the same contents as that before executing the WIT instruction. The termination sequence is the same as the internal processing sequence which is performed after a reset. To determine whether a hardware reset was performed to terminate Wait mode or a system reset was performed, use software after a reset. Refer to “Chapter 13. RESET” for details about a reset.

7702/7703 Group User’s Manual 11–5 When executing the WIT instruction after writing to the internal area or an external area, the three NOP instructions must be inserted to complete the write operation before the WIT instruction is executed. A, 5555 ; Writing instruction NOP instruction insertion WIT instruction Fig. 11.3.1 NOP instruction insertion example

7702/7703 Group User’s Manual WAIT MODE 11–6

12.1 Signals required for accessing

12.2 Software Wait

12.3 Ready function

12.4 Hold function

CONNECTION WITH EXTERNAL DEVICES

12.1 Signals required for accessing external devices

7702/7703 Group User’s Manual12–2 This chapter describes functions to connect devices externally. The functions and operation of the signals which are required for accessing external devices are described below. When connecting an external device that requires a long access time, refer to sections “12.2 Software Wait,” “12.3 Ready function,” and “12.4 Hold function,” as well as this section.

12.1.1 Descriptions of signals

When an external device is connected, operate the microcomputer in the memory expansion or microprocessor_ mode. (Refer to section “2.5 Processor modes.”) In these modes, pins P0 to P4 and the E pin function as I/O pins for the signals required for accessing external devices. Figure 12.1.1 shows the pin configuration in the memory expansion and microprocessor modes. Table 12.1.1 lists the functions of pins P0 to P4 and the E pin in the memory expansion and the microprocessor modes.

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual 12–3 Fig. 12.1.1 Pin configuration in memory expansion and microprocessor modes (top view) RDY A20/D4 A21/D5 A22/D6 A23/D7 R/W BHE ALE HLDA V ss E X OUT XIN RESET CNV SS BYTE HOLD P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 A8/D8 A9/D9 A10 /D10 A11 /D11 A12 /D12 A13 /D13 A14 /D14 A15 /D15 A16 /D0 A17 /D1 A18 /D2 A19 /D3 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 14 325 P83/TXD 0 P82/RXD 0 P81/CLK0 P80/CTS0/RTS0 VCC AV CC VREF AV SS VSS P77/AN7/ADTRG P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 70 43 42 41 M37702M2BXXXFP 22 23 24 P47 P46 P45 P44 P43 ] P42/ 1 l External data bus width = 16 bits (BYTE = “L”) ] : As 1 in microprocessor mode : External address bus, external data bus, bus control signal RDY A20/D4 A21/D5 A22/D6 A23/D7 R/W BHE ALE HLDA V ss E X OUT XIN RESET CNV SS BYTE HOLD A11 A12 A13 A14 A15 A16 /D0 A17 /D1 A18 /D2 A19 /D3 P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 A10 14 32 56789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P83/TXD 0 P82/RXD 0 P81/CLK0 P80/CTS0/RTS0 VCC AV CC VREF AV SS VSS P77/AN7/ADTRG P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 70 43 42 41 M37702M2BXXXFP P47 P46 P45 P44 P43 ] P42/ 1 l External data bus width = 8 bits (BYTE = “H”) ] : As 1 in microprocessor mode : External address bus, external data bus, bus control signal

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual12–4 Table 12.1.1 Functions of pins P0 to P4 and E pin in memory expansion and microprocessor modes Notes 1:The 7703 Group does not have the HLDA pin. 2:In the memory expansion mode, this pin functions as a programmable I/O port and can be programmed as the clock 1 output pin by software. 3:This table shows the pins’ functions. Refer to the following about the input/output timing of each signal: “Chapter 15. Electrical characteristics.” 4:Fix bits 0 and 1 of the Port P4 direction register to “0.” Perform the setup regardless of whether using the P40/HOLD and P41 /RDY pins as the HOLD or RDY pins or not. For the external ROM version, perform the same setup. HL DA BHE ALE R/W HL DA D ALE BHE R/W P RDY HOL D RDY HOL D E E E Pin External data bus width 16 bits (BYTE = “L”) A7 — A0 (P0) A7 — A0 A7 — A0 8 bits (BYTE = “H”) A15/D15 — A8/D8 (P1) A23/D7 — A16/D0 (P2) ALE (P32) BHE (P31) R/W (P30) D(odd): Data at odd address D(odd)A15 — A8A15/D15 — A8/D8 A15 — A8 A15— A 8 A23/D7 — A16/D0 A23 — A16 D(even): Data at even address D(even) A23/D7 — A16/D0 A23— A 16 D: Data (Note 1) 1 (P42) P47 — P43 RDY (P41) HOLD (P4 0) P47 — P43 P: Functions as a programmable I/O port. (Note 2) (Note 4) (Note 4) HLDA (P33)

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual 12–5 (1) External bus (A0 to A7, A8/D8 to A15/D15, A16/D0 to A23/D7) External areas are specified by the address (A0 to A23) output. Figure 12.1.2 shows the external area. Pins A8 to A23 of the external address bus and pins D0 to D15 of the external data bus are assigned to the same pins. When the BYTE pin level, described later, is “L” (i.e., external data bus width is 16 bits), the A8/D8 to A15/D15 and A16/D0 to A23/D7 pins perform address output and data input/output with time-sharing. When the BYTE pin level is “H” (i.e., external data bus width is 8 bits), the A 16/D0 to A23/D7 pins perform address output and data input/output with time-sharing, and pins A8 to A 15 output addresses. Fig. 12.1.2 External area : External area Note: Addresses 216 to 916 become an external area. Internal RAM area SFR area (Note) 016 FFFFFF 16 8016 Microprocessor mode 016 Memory expansion mode 1000016 FFFFFF 16 8016 Internal ROM area Internal RAM area SFR area (Note) C000 16 28016 28016

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual12–6 (2) External data bus width switching signal (BYTE pin level) This signal is used to select the external data bus width between 8 bits and 16 bits. When this signal level is “L,” the external data bus width is 16 bits; when the level is “H,” the bus width is 8 bits (refer to Table 12.1.1.) Fix this signal to either “H” or “L” level. This signal is valid only for the external areas. When accessing the internal areas, the data bus width is always 16 bits. (3) Enable signal (E) This signal becomes “L” level while reading or writing data to and from the data bus. (See Table 12.1.2.) (4) Read/Write signal (R/W) This signal indicates the state of the data bus. This signal becomes “L” level while writing to the data__ _ bus. Table 12.1.2 lists the state of the data bus indicated with the E and R/W signals. Table 12.1.2 State of data bus indicated with E__ and R/W signals R/W H L H L E H L State of data bus Not used Read data Write data (5) ____ Byte high enable signal (BHE) This signal indicates the access to an odd address. This signal becomes “L” level when accessing an only odd address or when simultaneously accessing odd and even addresses. This signal is used to connect memories or I/O devices of which data bus width is 8 bits when the external data bus width is 16 bits. ____ Table 12.1.3 lists levels of the external address bus A0 and the BHE signal and access addresses. ____ Table 12.1.3 Levels of A0 and BHE signal and access addresses Access address A 0 ____ BHE Even and odd addresses (Simultaneous 2-byte access) L L Even address (1-byte access) L H Odd address (1-byte access) H L (6) Address latch enable signal (ALE) This signal is used to obtain the address from the multiplexed signal of address and data that is input and output to and from the A8/D8 to A15/D15 and A16/D0 to A23/D7 pins. Make sure that when this signal is “H,” latch the address and simultaneously output the addresses. When this signal is “L,” retain the latched address. (7) ____ Ready function-related signal (RDY ) This is the signal to use the Ready function. (Refer to section “12.3 Ready function.”) (8) Hold function-related signals (HOLD , HLDA ) These are the signals to use the Hold function. (Refer to section “12.4 Hold function.”)

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual 12–7 (9) Clock φ1 This signal has the same period as φ. In the memory expansion mode, this signal is output externally by setting the clock φ1 output select bit (bit 7 at address 5E16) to “1.” Figure 12.1.3 shows the output start timing of clock φ1. In the microprocessor mode, this signal is always output externally. Note: Even in the single-chip mode, the clock φ1 can be output externally. This signal is output externally by setting the clock φ1 output select bit to “1” just as in the memory expansion mode. Fig. 12.1.3 Output start timing of clock φ1 Writing “1” to clock 1 output select bit E Clock 1(P42) Notes 1: The 1st cycle of clock 1 may be shortened; indicated by . 2: This applies when writing to clock 1 output select bit while P42 pin is outputting “L” level. Bit Bit name Functions At reset RW Processor mode bits Software reset bit Interrupt priority detection time select bits Clock 1 output select bit (Note 2) 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not selected The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Not selected 0 : Clock 1 output disabled (P42 functions as a programmable I/O port.) 1 : Clock 1 output enabled (P42 functions as a clock 1 out- put pin.) b1 b0 b5 b4 Processor mode register (Address 5E16) (Note 1) Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1” after a reset. (Fixed to “1.”) 2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”) b1 b0b2b3b4b5b6b7 RW RW Wait bit RW WO 0 RW 0 RW Fix this bit to “0.” RW RW 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. : Bits 0 to 6 are not used for setting of clock 1 output. Fig. 12.1.4 Structure of processor mode register

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual12–8

12.1.2 Operation of bus interface unit (BIU)

Figures 12.1.5 and 12.1.6 show the examples of operating waveforms of the signals input and output to /from externals when accessing external devices. The following explains these waveforms compared with the basic operating waveform (refer to section “2.2.3 Operation of bus interface unit (BIU).”) (1) When fetching instructions into instruction queue buffer À When the instruction which is next fetched is located at an even address in the 16-bit external data bus width, the BIU fetches 2 bytes at a time with the waveform (a). When in the 8-bit external data bus width, the BIU fetches only 1 byte with the first half of waveform (e). \ When the instruction which is next fetched is located at an odd address in the 16-bit external data bus width, the BIU fetches only 1 byte with the waveform (d). When in the 8-bit external data bus width, the BIU fetches only 1 byte with the first half of waveform (f). When a branch to an odd address is caused by a branch instruction and others in the 16-bit external data bus width, the BIU first fetches 1 byte in waveform (d), and after that, fetches each two bytes at a time in waveform (a). (2) When reading or writing data to and from memory•I/O device À When accessing 16-bit data which begins at an even address, waveform (a) or (e) is applied. \ When accessing 16-bit data which begins at an odd address, waveform (b) or (f) is applied. ´ When accessing 8-bit data at an even address, waveform (c) or the first half of (e) is applied. ˆ When accessing 8-bit data at an odd address, waveform (d) or the first half of (f) is applied. For instructions that are affected by the data length flag (m) and the index register length flag (x), operation À or \` is applied when flag m or x = “0”; operation ´ or ˆ is applied when flag m or x = “1.” The setup of flags m and x and the selection of the external data bus width do not affect each other.

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual 12–9 Fig. 12.1.5 Example of operating waveforms of signals input and output to/from externals (1) A0 — A7 A16 /D0 — A23 /D7 E ALE BHE A8 /D8 — A15 /D15 A0 — A7 A16 /D0 — A23 /D7 E ALE BHE A8 /D8 — A15 /D15 A0 — A7 A8 /D8 — A15 /D15 BHE E ALE A16 /D0 — A23 /D7 A0 — A7 A8 /D8 — A15 /D15 BHE E ALE A16 /D0 — A23 /D7 (a) Access from even address <16-bit data access> l External data bus width = 16 bits (BYTE = “L”) Address Data(odd) Data(even) Address Address (b) Access from odd address Address Address Address Data(odd) Address Address Address Data(even) <8-bit data access> (c) Access to even address Address Address Data(even) Address Address (d) Access to odd address Data(odd)Address Address

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual12–10 Fig. 12.1.6 Example of operating waveforms of signals input and output to/from externals (2) E ALE A0 — A 7 BHE A8 — A 15 A16 /D0 — A 23 /D7 E ALE A0 — A 7 BHE A8 — A 15 A16 /D0 — A 23 /D7 l External data bus width = 8 bits (BYTE = “H”) <8/16-bit data access> (e) Access from even address Address Address Data Data 8-bit data access 16-bit data access Address Address Address Address DataAddressData Address Address Address Address Address 8-bit data access 16-bit data access (f) Access from odd address Note: When accessing 16-bit data, 2 times of access are performed in the sequence of the low-order 8 bits and high-order 8 bits.

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual 12–11 Software Wait provides a function to facilitate access to external devices that require a long access time. To select the software Wait, use the wait bit (bit 2 at address 5E16). Figure 12.2.1 shows the structure of the processor mode register (address 5E16). Figure 12.2.2 shows an example of bus timing when the software Wait is used. Software Wait is valid only for the external area. The internal areas is always accessed with no Wait. Bit Bit name Functions At reset RW Processor mode bits Software reset bit Interrupt priority detection time select bits Clock 1 output select bit (Note 2) 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not selected The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Not selected 0 : Clock 1 output disabled (P42 functions as a programmable I/O port.) 1 : Clock 1 output enabled (P42 functions as a clock 1 out- put pin.) b1 b0 b5 b4 Processor mode register (Address 5E16) (Note1) Notes 1: While supplying the Vcc level to the CNVss pin, bit 1 becomes “1” after a reset. (Fixed to “1.”) 2: Bit 7 is ignored in the microprocessor mode. (It may be either “0” or “1.”) b1 b0b2b3b4b5b6b7 RW RW Wait bit RW WO 0 RW 0 RW Fix this bit to “0.” RW RW 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. : Bits 3 to 6 are not used when accessing the external area. Fig. 12.2.1 Structure of processor mode register

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual12–12 Fig. 12.2.2 Example of bus timing when software Wait is used (BYTE = “L”) <No Wait> Clock 1 A0— A7 A8/D8— A15/D15, A16/D0— A23/D7 E ALE Address 1 bus cycle (N ote) Note: When the external data bus is 8 bits width (BYTE = “H”), A8/D8 to A15/D15 operate with the same bus timing as A0 to A7. Address DataData AddressAddress l Internal areas are always accessed in this waveform. <Wait> Clock 1 A0— A7 A8/D8— A15/D15, A16/D0— A23/D7 E ALE (N ote) 1 bus cycle Address Address DataData AddressAddress

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual 12–13 Ready function provides a function to facilitate access to external devices that require a long access time. Fix bit 1 of the port P4 direction register to “0.”____ By supplying “L” level to the RDY pin in the memory expansion or microprocessor mode, the microcomputer____ enters Ready state and retains this state while the RDY pin is at “L” level. Table 12.3.1 lists the microcomputer’s state in Ready state. In Ready state, the oscillator’s oscillation does not stop, so that the internal peripheral devices can operate. Ready function is valid for the internal and external areas. Table 12.3.1 Microcomputer’s state in Ready state State Operating Stopped at “L” Retains the state when Ready request was accepted. In the memory expansion mode:

• When clock φ1 output select bit] = “1,” this pin outputs clock φ1.
• When clock φ1 output select bit = “0,” this pin retains the state when Ready request was accepted. In the microprocessor mode:
• This pin outputs clock φ1. Operating Item Oscillation φCPU , φ Pins A0 to A7, A8/D8 to A 15/D15, A16/D0 to A23/D7, E, R/W, BHE, HLDA (Note 1), ALE Pins P43 to P47, P5 to P8 (Note 2) P4 2/φ1 Watchdog timer Clock φ1 output select bit] : Bit 7 at address 5E16_____ Notes 1: The 7703 Group does not have the HLDA pin. 2: When this functions as a programmable I/O port.

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual12–14

12.3.1 Operation description____

The input level of the RDY pin is judged at the falling of the clock φ1. Then, when “L” level is detected, the microcomputer enters Ready state. (This is called acceptance of Ready request.)____ In Ready state, the input level of the RDY pin is judged at every falling of the clock φ1. Then, when “H” level is detected, the microcomputer terminates Ready state next rising of the clock φ1. Figures 12.3.1 shows timing of acceptance of Ready request and termination of Ready state. Refer also to section “17.1 Memory expansion ” about use of the Ready function.

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual 12–15 Fig. 12.3.1 Timings of acceptance of Ready request and termination of Ready state ´ The “L” level which is input to the RDY pin is accepted, so that E stops at “L” level for 1 cycle of clock 1 (indicated by @ ), and CPU stops at “L” level. \ The “L” level which is input to the RDY pin is not accepted, however CPU stops at “L” level. Clock 1 CPU RDY ALE ˆÀ\ Bus not in use <No Wait> À The “L” level which is input to the RDY pin is accepted, so that E stops at “H” level for 1 cycle of clock 1 (indicated by ), and CPU stops at “L” level. RDY ALE <Wait> ´˜ˆ CPU E E RDY pin input level sampling timing ˆ ´ Bus in use ˆ The ready state is terminated. ˜ The “L” level which is input to the RDY pin is not accepted because it is sampled immediately before Wait by software Wait (indicated by @ ), however CPU stops at “L” level. Clock 1 RDY pin input level sampling timing Bus in use

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual12–16 When composing the external circuit (DMA) which accesses the bus without using the central processing unit (CPU), the Hold function is used to generate a timing for transferring the right to use the bus from the CPU to the external circuit. Fix bit 0 of the port P4 direction register to “0.” In the memory expansion or microprocessor mode, the microcomputer enters Hold state by input of “L” level_____ _____ to the HOLD pin and retains this state while the level of the HOLD pin is at “L.” Table 12.4.1 lists the microcomputer’s state in Hold state. In Hold state, the oscillation of the oscillator does not stop. Accordingly, the internal peripheral devices can operate. However, Watchdog timer stops operating. Table 12.4.1 Microcomputer’s state in Hold state Item Oscillation φ φCPU E Pins A0 to A7, A8/D8 to A15/D15, A 16/D0 to A23/D7, R/W, BHE Pins HLDA (Note 1), ALE Pin P42/φ1 Pins P43 to P47, P5 to P8 (Note 2) Watchdog timer State Operating Operating Stopped at “L” Stopped at “H” Floating Outputs “L” level. In the memory expansion mode:

• When clock φ1 output select bit\\ = “1,” this pin outputs clock φ1.
• When clock φ1 output select bit = “0,” this pin retains the state when Hold request was accepted. In the microprocessor mode:
• This pin outputs clock φ1. Retains the state when Hold request was accepted. Stopped Clock φ1 output select bit\\ : Bit 7 at address 5E16_____ Notes 1: The 7703 Group does not have the HLDA pin. 2: When this functions as a programmable I/O port.

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual 12–17

12.4.1 Operation description _____

Judgment timing of the input level of the HOLD pin depends on the state using the bus. While the bus is not in use, the judgment is performed at every falling of φ. While the bus is in use, judgment is performed at the falling of the last φ in each bus cycle. Additionally, when accessing word data starting from an odd address with 2-bus cycle, the judgment is performed only at the second bus cycle. (See Figure 12.4.1.) When “L” level is detected at judgment of the input level, the microcomputer enters Hold state. (This is called acceptance of Hold request.) When the Hold request is accepted, φCPU stops next rising of φ. At the same time, the HLDA pin’s level_____ __ ___ changes “H” to “L”. When 1 cycle of φ has passed after the level of HLDA pin becomes “L”, pins R/W, BHE, and the external bus become floating state. In Hold state, the input level of the HOLD pin is judged at every falling of φ. Then, when “H” level is_____ detected, the HLDA pin’s level changes “L” to “H” next rising of φ. When 1 cycle of φ has passed after the_____ level of HLDA pin becomes “H”, the microcomputer terminates Hold state. Note: φ has a same polarity and a same frequency as the clock φ1. However, φ stops by the Ready request,_____ or executing the STP or WIT instruction. Accordingly, judgment of the input level of the HOLD pin is not performed during Ready state. AA A AWW Judgment timing of input level to HOLD pin Clock 1 ALE Reading Writing E No judge Judge Accessing word data with 2-bus cycle. (Example of no Wait) Fig. 12.4.1 Judgment when accessing word data beginning from odd address with 2-bus cycle

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual12–18 External address bus BHE ALE E HLDA HOLD R/W Clock 1 External data bus Data length External data bus width 8, 16 Unused l State when inputting “L” level to HOLD pin 8, 16 <When inputting “L” level to HOLD pin during term unusing bus> Judgment timing of input level to HOLD pin External address bus / External data bus Floating Floating Floating À Address A Address B 1 5 11 5 1 Hold state Term using busTerm unusing bus À This is the term in which the bus is not used, so that not a new address but an address output just before is output again. ] Clock 1 has the same polarity and the same frequency as . Signals timing to be input or output externally is ordained by clock 1 as a basis. Fig. 12.4.2 Timing of acceptance of Hold request and termination of Hold state (1)

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual 12–19 Fig. 12.4.3 Timing of acceptance of Hold request and termination of Hold state (2) Judgment timing of input level to HOLD pin External address bus BHE E HLDA HOLD R/W <When inputting “L” level to HOLD pin during term using bus; when data access is completed with 1-bus cycle> 8, 16 16 (Access from even address) l State when inputting “L” level to HOLD pin External data bus Data length External data bus width Using External address bus / External data bus ALE Clock 1 1 5 1 1 5 1 Address B Address A À Data Floating Floating Address A Floating Hold state Term using busTerm using bus À When accepting a Hold request, not a new address but an address output just before is output again. Notes 1: This figure shows the case of no Wait. 2: Clock 1 has the same polarity and the same frequency as . Signals timing to be input or output externally is ordained by clock 1 as a basis.

CONNECTION WITH EXTERNAL DEVICES 7702/7703 Group User’s Manual12–20 Fig. 12.4.4 Timing of acceptance of Hold request and termination of Hold state (3) Address B E ALE HLDA HOLD R/W External address bus BHE <When inputting “L” level to HOLD pin during term using bus; when data access is completed with continuous 2-bus cycle> 16 (Access from odd address) Using l State when inputting “L” level to HOLD pin External data bus Data length External data bus width Judgment timing of input level to HOLD pin Clock 1 External address bus / External data bus Address A+1 À 1 5 1 1 5 1 Not accepted Address A Data Data Floating Floating Floating Hold state Term using busTerm using bus À When accepting a Hold request, not a new address but an address output just before is output again. \` Hold request cannot be accepted before input/output of 16-bit data is completed. Notes 1: This figure shows the case of no Wait. 2: Clock 1 has the same polarity and the same frequency as . Signals timing to be input or output externally is ordained by clock 1 as a basis.

13.1 Hardware reset

13.2 Software reset

7702/7703 Group User’s Manual13–2 This chapter describes the method to reset the microcomputer. There are two methods to do that: Hardware reset and Software reset. When the power source voltage satisfies the microcomputer’s recommended operating conditions, the microcomputer is reset by supplying “L” level to the RESET pin. This is called a hardware reset. Figure 13.1.1 shows an example of hardware reset timing. Fig. 13.1.1 Example of hardware reset timing The following explains how the microcomputer operates for terms À to ˆ above. À After supplying “L” level to the RESET pin, the microcomputer initializes pins within a term of several ten ns. (Refer to Table 13.1.1.) While the RESET pin is “L” level and within the term of 4 to 5 cycles of the internal clock φ after the RESET pin goes from “L” to “H,” the microcomputer initializes the central processing unit (CPU) and SFR area. At this time, the contents of the internal RAM area become undefined (except when Stop or Wait ´ After \` , the microcomputer performs “Internal processing sequence after reset.” (Refer to Figure 13.1.7.) ˆ The microcomputer executes a program beginning with the address set into the reset vector addresses which are FFFE 16 and FFFF 16. RESET Program is executed. “H” 2 s or more Internal processing sequence after a resetNote: When the clock is stably supplied. (Refer to “13.1.4 Time supplying “L” level to RESET pin.”) À 4 to 5 cycles of “L”

7702/7703 Group User’s Manual RESET 13–3 Table 13.1.1 lists the microcomputer’s pin state while the RESET pin is “L” level. Table 13.1.1 Pin state while RESET pin is “L” level Mask ROM version Pin state Floating. Outputs “H” level. Floating. Outputs “H” level. Floating. Outputs “H” level. Outputs “H” or “L” level. Outputs “H” level. Outputs “L” level. Outputs φ1. Floating. Outputs “H” or “L” level. Outputs “H” level. Outputs “L” level. Outputs φ1. Floating. Floating. Outputs “H” level. Floating. Floating while supplying “H” level to two pins of P5 1 and P52, or one of them. Outputs “H” or “L” level while sup- plying “L” level to two pins of P5 and P52. Outputs “H” level. Pin (Port) name P0 to P8 E P0 to P8 E P0 to P8 E P0, P1, P2, P3 P3 0, P33, E P32 P42 P4 0, P41, P43–P4 7, P5 to P8 A 0–A 7, A8/D8–A15/ D 15, A16/D0–A 23/D7, ____ BHE R/W, HLDA, E ALE HOLD, RDY, P4 3– P4 7, P5 to P8 P0 to P8 E P0, P1, P3 to P8 CNV SS pin level Vss or Vcc Vss Vss Vcc Identification] MD External ROM version S1 Vcc PROM version (Including One time PROM and EPROM versions) Vss Vcc (Note) E Identification] : This expresses the internal memory type and its size identification. Refer to “Chapter 1. DESCRIPTION .” Note: Each pin becomes the above state. It is because the microcomputer enters the EPROM mode. Refer to “Chapter 19. PROM VERSION .”

7702/7703 Group User’s Manual13–4

13.1.2 State of CPU, SFR area, and internal RAM area

the state of the SFR area and internal RAM area immediately after reset. 0 : “0” immediately after a reset. 1 : “1” immediately after a reset. ? : Undefined immediately after a reset. : Always “0” at reading. Data bank register (DT) 0016 b7 b0 Program bank register (PG) 0016 b7 b0 Program counter (PC) Contents at address FFFE16Contents at address FFFF16 b7 b0b15 b8 Direct page register (DPR) 0016 b7 b0 0016 b15 b8 Processor status register (PS) 0 00 00 0 1 b7 b0b15 b8 N V mxD IZCIPL Stack pointer (S) ? b7 b0 b15 b8 Index register Y (Y) ? b7 b0 b15 b8 Index register X (X) ? b7 b0 b15 b8 Accumulator B (B) ? b7 b0 b15 b8 Accumulator A (A) ? b7 b0 b15 b8 Register name State immediately after a reset ?? ? Fig. 13.1.2 State of CPU registers immediately after reset

7702/7703 Group User’s Manual RESET 13–5 Fig. 13.1.3 State of SFR and internal RAM areas immediately after reset (1) 0 : “0” immediately after a reset. 1 : “1” immediately after a reset. ? : Undefined immediately after a reset. : Always “0” at reading. 0 : Always undefined at reading. : “0” immediately after a reset. Fix to “0.” 1016 1116 1216 1316 Port P8 direction register1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 016 116 216 316 416 516 616 716 816 916 B16 C 16 D 16 E16 F16 A16 Address Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register A-D sweep pin select register Port P0 register Port P1 register Port P2 register Port P3 register Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Register name Access characteristics State immediately after a reset RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0016 0016 0016 0016 00 00 00000000 0016 0 0 000 ? b7 b0 b7 b0 : It is possible to read the bit state at reading. The written value becomes valid data. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid data. It is not possible to read the bit state. : Nothing is assigned. It is not possible to read the bit state. The written value becomes invalid. RW RO WO l SFR area (016 to 7F16) RW RW RW ? 0016 (Note) Note : In the 7703 Group, after a reset, set “1” to the bits which do not have corresponding pins. (Refer to section “20.4.1 I/O pin.”) 0016 (Note) (Note) (Note) (Note)

7702/7703 Group User’s Manual13–6 UART0 transmit/receive control register 0 UART0 transmit/receive mode register UART0 baud rate register UART0 transmit buffer register UART1 receive buffer register Register name UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 2816 2916 2B16 2C 16 2D 16 2E16 2F16 2A16 2016 2116 2216 2316 2416 2516 2616 2716 3F16 Address Access characteristics RW WO WO RO RO b7 b0 WO RWRO RO RORW RW RO RO RW WO WO WO RW RORW RW State immediately after a reset 1 000 0016 0 000 00 0 ? b7 b0 0016 00000010 0000 0 0 0 1 000 0000 0 0 1 0 A-D register 5 A-D register 1 A-D register 3 A-D register 2 A-D register 4 A-D register 0 A-D register 6 A-D register 7 RO RO RO RO RO RO RO RO RO RO ??? ? ??? Fig. 13.1.4 State of SFR and internal RAM areas immediately after reset (2)

7702/7703 Group User’s Manual RESET 13–7 Fig. 13.1.5 State of SFR and internal RAM areas immediately after reset (3) RW RW RW Timer B2 register 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 4B16 4C 16 4D 16 4E16 4F16 4A16 Address Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Processor mode register One-shot start register Timer A0 register Up-down register Timer A1 register Register name Count start register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Access characteristics WO (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) (Note 2) b7 b0 RW (Note 2) (Note 2) RW RW RW RW RW RW WO State immediately after a reset 0016 0016 0016 0016 0016 b7 b0 0016 WO RW (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) RW Timer A0 mode register Timer A4 mode register (Note 3) 0 00 0 0 0 0 0 0 0 0 0 0 00 0 000 00 0 0 0 0 0RWRW (Note4) Notes 1: The access characteristics at addresses 4616 to 4F16 vary according to Timer A’s operating mode. (Refer to “Chapter 5. TIMER A.”) 2: The access characteristics at addresses 5016 to 5516 vary according to Timer B’s operating mode. (Refer to “Chapter 6. TIMER B.”) 3: The access characteristics for bit 5 at addresses 5B16 to 5D16 vary according to Timer B’s operating mode. (Refer to “Chapter 6. TIMER B.”) 4: The access characteristics for bit 1 at address 5E16 and its state immediately after a reset vary according to the voltage level supplied to the CNVss pin. (Refer to section “2.5 Processor modes.”) (Note 4) RW(Note 3) RW(Note 3) 00 0 000?? 00 0 000??

7702/7703 Group User’s Manual13–8 Fig. 13.1.6 State of SFR and internal RAM areas immediately after reset (4) UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address A-D conversion interrupt control register UART0 transmit interrupt control register UART1 transmit interrupt control register INT2 interrupt control register Watchdog timer frequency select register Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW b7 b0 RW State immediately after a reset ?(Note 2) b7 b0 UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register 0 00 0 By writing dummy data to address 6016, the value “FFF16” is set to the watchdog timer. The dummy data is not retained anywhere. The value “FFF16” is set to the watchdog timer. (Refer to “Chapter 9. WATCHDOG TIMER .”) l Internal RAM area; addresses 8016 to 27F16 in M37702M2BXXXFP)

• At hardware reset
• At terminating Stop or Wait mode WIT instruction is executed RW Notes 1: (Note 1) (Note 3) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 000

7702/7703 Group User’s Manual RESET 13–9

13.1.3 Internal processing sequence after reset

Figure 13.1.7 shows the internal processing sequence after reset. Fig. 13.1.7 Internal processing sequence after reset “H” CPU (1) Single-chip and Memory expansion modes AP AH AL DATA E 000016 0016 FFFE 16 AD H , ADL R/W AD H , ADL Next op-code IPL, reset vector address Not used Not used Not used CPU AP AH AL DATA

000016 FFFE 16 AD H , ADL

AD H , ADL 0016 E R/W CPU : CPU standard clock AP : High-order 8 bits address bus of CPU AH AL : Low-order 16 bits address bus of CPU DATA AD H , ADL : Contents of reset vector address (FFFE16, FFFF16) (2) Microprocessor mode “H” Next op-code IPL, reset vector address Not used Not usedNot used : CPU data bus

7702/7703 Group User’s Manual13–10

13.1.4 Time supplying “L” level to RESET pin______

Time supplying “L” level to the RESET pin varies according to the state of the clock oscillation circuit. l When the oscillator is stably oscillating or a stable clock is input from the XIN pin, supply “L” level for 2 µs or more. l If the oscillator is not stably oscillating (including a power-on reset and In Stop mode), supply “L” level until the oscillation is stabilized. The time to stabilize oscillation varies according to the oscillator. For details, contact the oscillator manufacturer. circuit. ] For details about Stop mode, refer to “Chapter 10. STOP MODE.” For details about clocks, refer to “Chapter 14. CLOCK GENERATING CIRCUIT.” 4.5V 0.9V Note : Refer to “Figure 18.3.1 Power-on reset conditions” for the low supply voltage version. Fig. 13.1.8 Power-on reset condition

7702/7703 Group User’s Manual RESET 13–11 ] The delay time is about 11 ms when Cd = 0.033 µF. td ≈ 0.34 5 C d [ µs], Cd: [ pF ] Note : Refer to “Figure 18.3.2 Example of power-on reset circuit” for the low supply voltage version. Vcc Fig. 13.1.9 Example of power-on reset circuit

7702/7703 Group User’s Manual13–12 When the power source voltage satisfies the microcomputer’s recommended operating conditions, the microcomputer is reset by writing “1” to the software reset bit (bit 3 at address 5E16). This is called a software reset. In this case, the microcomputer initializes pins, CPU, and SFR area just as in the case of a hardware reset. However, the microcomputer retains the contents of the internal RAM area. (Refer to After completing initialization, the microcomputer performs the internal processing sequence after a reset. (Refer to Figure 13.1.7.) After that, it executes a program beginning from the address set into the reset vector addresses which are FFFE 16 and FFFF 16. i Bit Bit name Functions At reset RW Processor mode bits Software reset bit Interrupt priority detection time select bits Clock 1 output select bit (Note 2) 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not selected The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Not selected 0 : Clock 1 output disabled (P42 functions as a programmable I/O port.) 1 : Clock 1 output enabled (P42 functions as a clock 1 out- put pin.) b1 b0 b5 b4 Processor mode register (Address 5E16) (Note 1) Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1” after a reset. (Fixed to “1.”) 2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”) b1 b0b2b3b4b5b6b7 RW RW Wait bit RW WO 0 RW 0 RW Fix this bit to “0.” RW RW 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. : Bits 0 to 2 and 4 to 7 are not used at software reset. Fig. 13.2.1 Structure of processor mode register

14.1 Oscillation circuit example

14.2 Clock

7702/7703 Group User’s Manual14–2 This chapter describes a clock generating circuit which supplies the operating clock of the central processing unit (CPU), bus interface unit (BIU), or internal peripheral devices. The clock generating circuit contains the oscillation circuit. To the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock which is externally generated can be input. The example of the oscillation circuit is described below.

14.1.1 Connection example using resonator/oscillator

Figure 14.1.1 shows an example when connecting a ceramic resonator/quartz-crystal oscillator between pins X IN and XOUT . The circuit constants such as Rf, Rd, CIN, and COUT (shown in Figure 14.1.1) depend on the resonator/ oscillator. These values shall be set to the resonator/ oscillator manufacturer’s recommended values. Fig. 14.1.1 Connection example using resonator/oscillator Fig. 14.1.2 Externally generated clock input example

14.1.2 Input example of externally generated clock

Figure 14.1.2 shows an input example of the clock which is externally generated. The external clock must be input from the X IN pin, and the XOUT pin must be left open. M37702 XIN XOUT R f C IN C OUT R d M37702 XIN XOUT Vcc Vss Externally generated clock Open

14–37702/7703 Group User’s Manual Figure 14.2.1 shows the clock generating circuit block diagram. Fig. 14.2.1 Clock generating circuit block diagram Q XIN XOUT R S Q R S Q R S CPU 1/8 1/2 1/2 1/8 f16 f64 f512 f32 f512 Interrupt request STP instruction Reset WIT instruction Ready request Request of CPU wait from BIU (acceptance of Hold request included) Operation clock for internal peripheral devices Hold request Watchdog timer CPU: Central Processing Unit BIU: Bus Interface Unit Watchdog timer frequency select bit: Bit 0 at address 6116 Note: This is the signal generated when the watchdog timer’s most significant bit becomes “0.” (Note) Watchdog timer frequency select bit “0” “1”

7702/7703 Group User’s Manual14–4

14.2.1 Clock generated in clock generating circuit

(1) φ It is the operation clock of BIU. It is also the clock source of φCPU . The φ stops by Ready request or execution of the STP or WIT instruction. It is not stopped by acceptance of Hold request. (2) φCPU It is the operation clock of CPU. The φCPU stops by the following:

• Execution of the STP or WIT instruction,____
• Ready request; “L” level input to RDY pin
• Wait request from BIU; Hold request acceptance included (3) Clock φ 1 It has the same period as φ and is output to the external from the φ1 pin. The clock φ1 stops by execution of the STP instruction. It is not stopped by Ready request or acceptance of Hold request, or execution of the WIT instruction. (4) f2 to f512 Each of them is the internal peripheral devices’ operating clock. Note: Refer to each functional description for details:

15.1 Absolute maximum ratings

15.2 Recommended operating conditions

15.3 Electrical characteristics

15.4 A-D converter characteristics

15.5 Internal peripheral devices

15.6 Ready and Hold

15.7 Single-chip mode

15.8 Memory expansion mode and

microprocessor mode : with no Wait

15.9 Memory expansion mode and

microprocessor mode : with Wait

15.10 Testing circuit for ports P0 to P8,

φ1, and E

ELECTRICAL CHARACTERISTICS

7702/7703 Group User’s Manual15–2 This chapter describes electrical characteristics of the M37702M2BXXXFP and M37702M2AXXXFP. For the low voltage version, refer to section “18.4 Electrical characteristics.” The 7703 Group’s available pins varies from that of the 7702 Group. Refer to “Chapter 20. 7703 GROUP.” For the latest data, inquire of addresses described last (+ “CONTACT ADDRESSES FOR FURTHER INFORMATION”) . In a part of the standard indicated in this chapter, there are the limits depending on each microcomputer product or used external clock input frequency. Distinguish it described below.

• Limits depending on each microcomputer (Example) M37702M2BXXXFP When this sign is ‘A,’ refer to the column of ”16 MHz.” When this sign is ‘B,’ refer to the column of ”25 MHz.”
• Limits depending on used external clock input frequency The calculation formula is described in the table. When the microcomputer is 16 MHz version, the limits is the value in the case of f(XIN) = 16 MHz. When the microcomputer is 25 MHz version, the limits is the value in the case of f(XIN) = 25 MHz.

15.1 Absolute maxim um ratings

Analog power source voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ta = 25 °C Unit V V V V V mW Ratings –0.3 to 7 –0.3 to 7 –0.3 to 12 –0.3 to VCC +0.3 –0.3 to VCC +0.3 300 (Note) –20 to 85 –40 to 150 RESET , CNV SS , BYTE P0 0–P0 7, P10–P1 7, P20–P2 7, P3 0–P3 3, P40–P4 7, P50–P5 7, P6 0–P6 7, P70–P7 7, P80–P8 7, VREF , X IN P0 0–P0 7, P10–P1 7, P20–P2 7, P3 0–P3 3, P40–P4 7, P50–P5 7, P6 0–P6 7, P70–P7 7, P80–P8 7, XOUT , E Symbol V CC AV CC V I V I V O P d Topr Tstg Note: In the 7703 Group, this value is 1000 mW.

7702/7703 Group User’s Manual 15–3 V V V V V V V V V V mA mA mA mA MHz Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage High-level input voltage High-level input voltage Low-level input voltage Low-level input voltage Low-level input voltage High-level peak output current High-level average output current Low-level peak output current Low-level average output current External clock input frequency Recommended operating conditions (VCC = 5 V±10%, Ta = –20 to 85 °C, unless otherwise noted) IOH (peak) IOH (avg) IOL (peak) IOL (avg) f(XIN) ParameterSymbol Limits Min. Max. 5.54.5 5.0 V CC Typ. Unit VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC –10 0.5VCC M37702M2BXXXFP M37702M2AXXXFP P00–P07, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVSS , BYTE P10–P17, P20–P27 (in single-chip mode) 0–P17, P20–P27 (in memory expansion mode and microprocessor mode) 0–P07, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVSS , BYTE 0–P17, P20–P27 (in single-chip mode) 0–P17, P20–P27 (in memory expansion mode and microprocessor mode) 0–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P43, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P43, P54–P57, P60–P67, P70–P77, P80–P87 0.8VCC 0.8VCC Notes 1: Average output current is the average value of a 100 ms interval. 2: The sum of IOL (peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH (peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL (peak) for ports P4, P5, P6, and P7 must be 80 mA or less, and the sum of IOH (peak) for ports P4, P5, P6, and P7 must be 80 mA or less.

7702/7703 Group User’s Manual15–4 HOLD , RDY , TA0 IN–TA4 IN, TB0 IN–TB2 IN, INT0–INT2, ADTRG , CTS 0, CTS 1, CLK0, CLK1 Electrical characteristics (VCC = 5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) VT+–VT– VT+–VT– VT+–VT– IIH IIL VRAM ICC Symbol Parameter Test conditions Min. Max. V V V V V V V V V V V µA µA V mA µA µA Unit 4.7 3.1 4.8 3.4 4.8 0.4 0.2 0.1 0.45 1.9 0.43 1.6 0.4 0.5 0.3 Typ. P00–P07, P10–P17, P20–P27, P30, P31, P33, P40–P4 7, P5 0–P5 7, P60–P6 7, P70–P7 7, P80–P87 P00–P07, P10–P17, P20–P27, P30, P31, P33 P32 E P00–P07, P10–P17, P20–P27, P30, P31, P33, P40–P4 7, P5 0–P5 7, P60–P6 7, P70–P7 7, P80–P87 P00–P07, P10–P17, P20–P27, P30, P31, P33 P32 E RESET XIN P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVSS , BYTE P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVSS , BYTE High-level output voltage High-level output voltage High-level output voltage High-level output voltage Low-level output voltage Low-level output voltage Low-level output voltage Low-level output voltage Hysteresis Hysteresis Hysteresis High-level input current Low-level input current RAM hold voltage Power source current IOH = –10 mA IOH = –400 µA IOH = –10 mA IOH = –400 µA IOH = –10 mA IOH = –400 µA IOL = 10 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA VI = 5 V VI = 0 V When clock is stopped. In single-chip mode, output pins are open, and the other pins are connected to VSS . Ta = 25 °C ,when clock is stopped f(XIN) = 16 MHz f(XIN) = 25 MHz Limits Ta = 85 °C,when clock is stopped

7702/7703 Group User’s Manual 15–5 A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V± 10%, V SS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) UnitSymbol R LADDER tCONV V REF V IA Parameter Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage Test conditions V REF = VCC V REF = VCC V REF = VCC f(XIN) = 25 MHz f(XIN) = 16 MHz Limits Min. 9.12 14.25 Typ. Max. ± 3 V CC VREF Bits LSB k s V V

7702/7703 Group User’s Manual15–6 Timing requirements (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Timer A input (count input in event counter mode) Limits TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width tc(TA) tw(TAH) tw(TAL) ns ns ns Min. Max. UnitParameterSymbol

16 MHz 25 MHz

Min. 125 Max. ns ns ns tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width 8 5 109 f(XIN) 4 5 109 f(XIN) 4 5 109 f(XIN) Timer A input (gating input in timer mode)

25 MHz16 MHz Unit

Max.Min. 500 250 250 Max. Min. 320 160 160 Symbol Parameter Data formula Note: TAi IN input cycle time must be 4 cycles or more of count source, TAiIN input high-level pulse width must be 2 cycles or more of count source, TAiIN input low-level pulse width must be 2 cycles or more of count source. Timer A input (external trigger input in one-shot pulse mode) Max.Max. Symbol Parameter Data formula Min. ns ns ns TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width tc(TA) tw(TAH) tw(TAL) 160 Min. 4 5 109 f(XIN) 250 150 150 Timer A input (external trigger input in pulse width modulation mode) Max.Max. Symbol Parameter Min. Min. 125 125 TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns tw(TAH) tw(TAL) Timer A input (up-down input in event counter mode) Max.Max. Symbol Parameter Min. tc(UP) tw(UPH) tw(UPL) tsu(UP–TIN) th(TIN–UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time ns ns ns ns ns 2000 1000 1000 400 400 2500 1250 1250 500 500 Min.

7702/7703 Group User’s Manual 15–7 Timer A input (Two-phase pulse input in event counter mode) Limits TAjIN input cycle time TAjIN input setup time TAjOUT input setup time ns ns ns UnitParameterSymbol Min. 1000 250 250 Max. tc(TA) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) Min. 800 200 200 Max.

7702/7703 Group User’s Manual15–8 Internal peripheral devices Test conditions

• VCC = 5 V ± 10%
• Input timing voltage: VIL = 1.0 V, VIH = 4.0 V TAiIN input tc(TA) tw(TAH) tw(TAL) TAiOUT input (Up-down input) tc(UP) tw(UPH) tw(UPL) TAiIN input (When count by falling) TAiIN input (When count by rising) TAiOUT input (Up-down input) th(TIN–UP) tsu(UP–TIN) tsu(TAjIN–TAjOUT ) TAjIN input TAjOUT input tsu(TAjOUT –TAjIN) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) l Two-phase pulse input in event counter mode l Up-down input, count input in event counter mode l Count input in event counter mode l Gating input in timer mode l External trigger input in one-shot pulse mode l External trigger input in pulse width modulation mode tc(TA)

7702/7703 Group User’s Manual 15–9 Timer B input (count input in event counter mode)

25 MHz16 MHz UnitSymbol Parameter

Min. Max.Max.Min. tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) ns ns ns ns ns ns TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edges count) TBiIN input high-level pulse width (both edges count) TBiIN input low-level pulse width (both edges count) 160 Limits 125 250 125 125 TBi IN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width tc(TB) tw(TBH) tw(TBL) Timer B input (pulse period measurement mode) 8 5 109 f(XIN) 4 5 109 f(XIN) 4 5 109 f(XIN) Note: TBiIN input cycle time must be 4 cycles or more of count source, TBiIN input high-level pulse width must be 2 cycles or more of count source, TBiIN input low-level pulse width must be 2 cycles or more of count source. Max.Max. Min. 320 160 160 ns ns ns Max. Symbol Data formulaParameter Min. 500 250 250 t c(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width 8 5 109 f(XIN) 4 5 109 f(XIN) 4 5 109 f(XIN) Note: TBiIN input cycle time must be 4 cycles or more of count source, TBiIN input high-level pulse width must be 2 cycles or more of count source, TBiIN input low-level pulse width must be 2 cycles or more of count source. A-D trigger input Timer B input (pulse width measurement mode) Max.Max. Symbol Data formulaParameter Min. 320 160 160 ns ns ns Min. 500 250 250 Max.Max. tc(AD) tw(ADL) AD TRG input cycle time (minimum allowable trigger) AD TRG input low-level pulse width ns ns Min.Min. 1000 125 1000 125

7702/7703 Group User’s Manual15–10

25 MHz16 MHz

Min. Max. ns ns ns ns ns ns ns CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TxDi output delay time TxDi hold time RxD i input setup time RxD i input hold time tc(CK) tw(CKH) tw(CKL) td(C–Q) th(C–Q) tsu(D–C) th(C–D) Unit Max. 200 100 100 External interrupt INTi input Serial I/O ParameterSymbol Min. 250 250 Max. Min. 250 125 125 Min. 250 250 Max. INTi input high-level pulse width INTi input low-level pulse width tw(INH) tw(INL)

7702/7703 Group User’s Manual 15–11 Internal peripheral devices Test conditions

• VCC = 5 V ± 10%
• Input timing voltage
• Output timing voltage : V IL = 1.0 V, VIH = 4.0 V : VOL = 0.8 V, VOH = 2.0 V TBiIN input tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) AD TRG input tw(INL) tw(INH) INTi input tc(CK) tw(CKH) tw(CKL) th(C–Q) tsu(D–C) CLK i input TxD i output RxD i input td(C–Q) th(C–D)

7702/7703 Group User’s Manual15–12 Timing requirements (VCC = 5 V±10%, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Max.Max. Limits Min. tsu(RDY– φ1) tsu(HOLD– φ1) th(φ1–RDY) th(φ1–HOLD) RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time ns ns ns ns Min. Switching characteristics (V CC = 5 V±10%, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Max.Max. Limits Min. ns Min. 50 50HLDA output delay time Note: For test conditions, refer to Figure 15.10.1. td(φ1–HLDA)

7702/7703 Group User’s Manual 15–13

• VCC = 5 V±10%
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V With no Wait With Wait RDY input E output E output RDY input tsu(RDY– 1) th( 1–RDY) tsu(RDY– 1) th( 1–RDY) l Ready function

7702/7703 Group User’s Manual15–14

• VCC = 5 V±10%
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V HOLD input HLDA output th( 1–HOLD) td( 1–HLDA) td( 1–HLDA) l Hold function 1)tsu(HOLD–

7702/7703 Group User’s Manual 15–15 Timing requirements (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Switching characteristics (V CC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits

25 MHz16 MHz UnitParameterSymbol

Max.Min. Min.Max. ns ns ns ns ns ns ns ns ns t d(E–P0Q) td(E–P1Q) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) 100 100 100 100 100 100 100 100 100 Note: For test conditions, refer to Figure 15.10.1. Min. Max.Max.Min. Port P0 data output delay time Port P1 data output delay time Port P2 data output delay time Port P3 data output delay time Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time t c tw(H) tw(L) tr tf tsu(P0D–E) tsu(P1D–E) tsu(P2D–E) tsu(P3D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P0D) th(E–P1D) th(E–P2D) th(E–P3D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) External clock input cycle time External clock input high-level pulse width External clock input low-level pulse width External clock rise time External clock fall time Port P0 input setup time Port P1 input setup time Port P2 input setup time Port P3 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P0 input hold time Port P1 input hold time Port P2 input hold time Port P3 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time

7702/7703 Group User’s Manual15–16 td(E–P0Q) tsu(P0D–E) th(E–P0D) td(E–P1Q) tsu(P1D–E) th(E–P1D) td(E–P2Q) tsu(P2D–E) th(E–P2D) td(E–P3Q) tsu(P3D–E) th(E–P3D) tW(H)tctrtf E Port P0 output f(XIN) td(E–P4Q) tsu(P4D–E) th(E–P4D) td(E–P5Q) tsu(P5D–E) th(E–P5D) td(E–P6Q) tsu(P6D–E) th(E–P6D) td(E–P7Q) tsu(P7D–E) th(E–P7D) td(E–P8Q) tsu(P8D–E) th(E–P8D) tW(L) Single-chip mode Test conditions

• VCC = 5 V ± 10%
• Input timing voltage
• Output timing voltage : V IL = 1.0 V, VIH = 4.0 V : VOL = 0.8 V, VOH = 2.0 V Port P0 input Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input

7702/7703 Group User’s Manual 15–17

15.8 Memory expansion mode and microprocessor mode : with no Wait

Timing requirements (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) tw(H) tw(L) tr tf tsu(P1D–E) tsu(P2D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P1D) th(E–P2D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) External clock input cycle time External clock input high-level pulse width External clock input low-level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P1 input hold time Port P2 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Max.Max. Min.Min. 100 100 100 100 100 Switching characteristics (V CC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Max.Max. Min.Min. Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time φ1 output delay time_ E low-level pulse width Port P0 address output delay time Port P1 data output delay time (BYTE = “L”) Port P1 floating start delay time (BYTE = “L”) Port P1 address output delay time Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time ALE output delay time ALE pulse width BHE output delay time R/W output delay time td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) td(E–φ1) tw(EL) td(P0A–E) td(E–P1Q) tpxz(E–P1Z) td(P1A–E) td(P1A–ALE) th(E–P2Q) tpxz(E–P2Z) td(P2A–E) th(P2A–ALE) td(ALE–E) tw(ALE) td(BHE–E) td(R/W–E) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: For test conditions, refer to Figure 15.10.1. ] This is the value depending on f(X IN). For data formula, refer to Table 15.8.1. 100 100 100 100 100

7702/7703 Group User’s Manual15–18 Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits

25 MHz16 MHz UnitParameter

Max.Max. Min.Min. th(E–P0A) th(ALE–P1A) th(E–P1Q) tpzx(E–P1Z) th(E–P1A) th(ALE–P2A) th(E–P2Q) tpzx(E–P2Z) th(E–BHE) th(E–RW) Symbol Port P0 address hold time Port P1 address hold time (BYTE = “L”) Port P1 data hold time (BYTE = “L”) Port P1 floating release delay time (BYTE = “L”) Port P1 address hold time (BYTE = “H”) Port P2 address hold time Port P2 data hold time Port P2 floating release delay time ___ BHE hold time__ R/W hold time ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) Notes 1: For the M37702E2AXXXFP, M37702E2AFS, M37702E4AXXXFP, and M37702E4AFS, refer to section “19.5.4 Bus timing and EPROM mode.” For the M37703E2AXXXSP and M37703E4AXXXSP, refer to section “20.6.2 Bus timing and EPROM mode.” 2: For test conditions, refer to Figure 15.10.1. ] : This is the value depending on f(XIN). For data formula, refer to Table 15.8.1. Table 15.8.1 Bus timing data formula tw(EL) td(P0A–E) td(P1A–E) td(P2A–E) td(P1A–ALE) td(P2A–ALE) tw(ALE) td(BHE-E) td(R/W-E) th(E–P0A) th(E–P1A) th(E–P1Q) th(E–P2Q) tpzx(E–P1Z) tpzx(E–P2Z) 2 5 109 f(XIN) – 30 f(XIN) ≤ 8 MHz 8 MHz < f(XIN) ≤ 16 MHz 16 MHz < f(X IN) ≤ 25 MHz 1 5 109 f(XIN)100 + – 125 1 5 109 f(XIN) – 45 1 5 109 f(XIN) – 35 1 5 109 f(XIN)100 + – 125 1 5 109 f(XIN) – 30 1 5 109 f(XIN) – 38.5 1 5 109 f(XIN) – 27.5 1.2 5 109 f(XIN) – 7530 + 1 5 109 f(XIN) – 26 1 5 109 2 5 f(XIN) – 6.251 5 109 2 5 f(XIN) – 12.5 1 5 109 f(XIN) – 35 1 5 109 f(XIN) – 18 1 5 109 f(XIN) – 22 1 5 109 2 5 f(XIN) – 2 1.2 5 109 f(XIN)30 + – 75 1 5 109 f(XIN)12 + – 40 1 5 109 f(XIN) – 4020 + Note: For the M37702E2AXXXFP, M37702E2AFS, M37702E4AXXXFP, and M37702E4AFS, refer to section “19.5.4 Bus timing and EPROM mode.” For the M37703E2AXXXSP and M37703E4AXXXSP, refer to section “20.6.2 Bus timing and EPROM mode.” (Note) f(XIN) Sign

7702/7703 Group User’s Manual 15–19 td(P1A –E) td(P1A – E) tw(L)tw(H) tr tf tc tw(EL) td(E – 1)td(E – 1) th(E –P0A) th(E –P1A) td(P0A – E) th(E –P1Q)td(E –P1Q) Address Address th(E– P2Q)td(E– P2Q)td(P2A –E) DataAddress th(ALE – P1A)td(P1A –ALE) th(E– BHE)td(BHE – E) td(ALE –E) tw(ALE) td(R/W – E) th(E– R/W) td(E– PiQ) <Write> f(XIN) Address output A0–A7 BHE output Port Pi output (i = 4–8) Test conditions (P4–P8)

• VCC = 5 V± 10%
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0V E Address output A8–A15 (BYTE = “ H”) Data input D 8–D 15 (BYTE = “ L”) Address/Data output A16/D0–A23/D7 ALE output R/W output Data input D 0–D 7 Address/Data output A8/D8–A15/D15 (BYTE = “ L”) Test conditions (1, E, P0–P3)
• VCC = 5 V ±10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : VIL = 0.8 V, VIH = 2.5 V th(ALE – P2A)td(P2A – ALE) Memory expansion mode and microprocessor mode ; With no Wait DataAddress

7702/7703 Group User’s Manual15–20 tsu(P1D – E) td(P0A – E) td(P1A – E) td(P1A – E) tw(L)tw(H) tr tf tc tw(EL) td(E – 1)td(E– 1) th(E – P0A) th(E – P1A) tpzx(E – P1Z)tpxz(E – P1Z) Address td(P1A – ALE) th(E – BHE)td(BHE – E) td(ALE – E) tw(ALE) td(R/W – E) th(E – R/W) Memory epxansion mode and microprocessor mode ; With no Wait <Read> th(E – P1D) th(ALE – P1A) Data td(P2A – E) tpzx(E – P2Z) th(E – P2D) Address th(E – PiD) tsu(PiD – E) f(XIN) Address output A0–A7 BHE output Test conditions (1, E, P0–P3)

• VCC = 5 V ± 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : VIL = 0.8 V, VIH = 2.5 V Port Pi input (i = 4–8) Test conditions (P4–P8)
• VCC = 5 V± 10%
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V E Address output A8–A15 (BYTE = “ H”) Data input D 8–D 15 (BYTE = “ L”) Address/Data output A16/D0–A23/D7 ALE output R/W output Data input D 0–D 7 Address/Data output A8/D8–A15/D15 (BYTE = “ L”) tpxz(E – P2Z) th(ALE – P2A)td(P2A – ALE) tsu(P2D – E) Data Address Address

7702/7703 Group User’s Manual 15–21

15.9 Memory expansion mode and microprocessor mode : with Wait

Timing requirements (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits tw(H) tw(L) tr tf tsu(P1D–E) tsu(P2D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P1D) th(E–P2D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns External clock input cycle time External clock input high-level pulse width External clock input low-level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P1 input hold time Port P2 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Min.Max.Min. Max. 100 100 100 100 100 Limits Min.Max.Min. Max. Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time φ1 output delay time_ E low-pulse width Port P0 address output delay time Port P1 data output delay time (BYTE = “L”) Port P1 floating start delay time (BYTE = “L”) Port P1 address output delay time Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time ALE output delay time ALE pulse width ____ BHE output delay time__ R/W output delay time td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) td(E–φ1) tw(EL) td(P0A–E) td(E–P1Q) tpxz(E–P1Z) td(P1A–E) td(P1A–ALE) td(E–P2Q) tpxz(E–P2Z) td(P2A–E) td(P2A–ALE) td(ALE–E) tw(ALE) td(BHE–E) td(R/W–E) Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 100 100 100 100 220 130 Note: For test conditions, refer to Figure 15.10.1. ] : This is the value depending on f(XIN). For data formula, refer to Table 15.9.1.

7702/7703 Group User’s Manual15–22 Switching characteristics (VCC = 5 V±10%, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Min.Max.Min. Max. ns ns ns ns ns ns ns ns ns ns Port P0 address hold time Port P1 address hold time (BYTE = “L”) Port P1 data hold time (BYTE = “L”) Port P1 floating release delay time (BYTE = “L”) Port P1 address hold time (BYTE = “H”) Port P2 address hold time Port P2 data hold time Port P2 floating release delay time ____ BHE hold time__ R/W hold time th(E–P0A) th(ALE–P1A) th(E–P1Q) tpzx(E–P1Z) th(E–P1A) th(ALE–P2A) th(E–P2Q) tpzx(E–P2Z) th(E–BHE) th(E–R/W) (Note 1) (Note 1) Notes 1: For the M37702E2AXXXFP, M37702E2AFS, M37702E4AXXXFP, and M37702E4AFS, refer to section “19.5.4 Bus timing and EPROM mode.” For the M37703E2AXXXSP and M37703E4AXXXSP, refer to section “20.6.2 Bus timing and EPROM mode.” 2: For test conditions, refer to Figure 15.10.1. ] : This is the value depending on f(XIN). For data formula, refer to Table 15.9.1. Table 15.9.1 Bus timing data formula tw(EL) td(P0A–E) td(P1A–E) td(P2A–E) td(P1A–ALE) td(P2A–ALE) tw(ALE) td(BHE-E) td(R/W-E) th(E–P0A) th(E–P1A) th(E–P1Q) th(E–P2Q) tpzx(E–P1Z) tpzx(E–P2Z) 4 5 109 f(XIN) – 30 f(XIN) ≤ 8 MHz 8 MHz < f(X IN) ≤ 16 MHz 16 MHz < f(X IN) ≤ 25 MHz 1 5 109 f(XIN)100 + – 125 1 5 109 f(XIN) – 45 1 5 109 f(XIN) – 35 1 5 109 f(XIN)100 + – 125 1 5 109 f(XIN) – 30 1 5 109 f(XIN) – 38.5 1 5 109 f(XIN) – 27.5 1.2 5 109 f(XIN) – 7530 + 1 5 109 f(XIN) – 26 1 5 109 2 5 f(XIN) – 6.251 5 109 2 5 f(XIN) – 12.5 1 5 109 f(XIN) – 35 1 5 109 f(XIN) – 18 1 5 109 f(XIN) – 22 1 5 109 2 5 f(XIN) – 2 1.2 5 109 f(XIN)30 + – 75 1 5 109 f(XIN)12 + – 40 1 5 109 f(XIN) – 4020 + Note: For the M37702E2AXXXFP, M37702E2AFS, M37702E4AXXXFP, and M37702E4AFS, refer to section “19.5.4 Bus timing and EPROM mode.” For the M37703E2AXXXSP and M37703E4AXXXSP, refer to section “20.6.2 Bus timing and EPROM mode.” (Note) f(XIN)Sign

7702/7703 Group User’s Manual 15–23 td(P1A – E) td(P1A – E) tw(L)tw(H) tr tf tc tw(EL) td(E – 1)td(E – 1) th(E – P0A) th(E – P1A) td(P0A –E) th(E – P1Q)td(E – P1Q) Address Data th(E – P2Q)td(E – P2Q)td(P2A – E) Address th(ALE – P1A)td(P1A – ALE) th(ALE – P2A)td(P2A – ALE) th(E – BHE)td(BHE – E) td(ALE – E) tw(ALE) td(R/W – E) th(E – R/W) td(E – PiQ) <Write> f(XIN) Address output A0–A7 BHE output Port Pi output (i = 4–8) Test conditions (P4–P8)

• VCC = 5V ± 10%
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V E Address output A8–A15 (BYTE = “H” ) Data input D 8–D 15 (BYTE = “L” ) Address/Data output A16/D0–A23/D7 ALE output R/W output Data input D 0–D 7 Address/Data output A8/D8–A15/D15 (BYTE = “L” ) Test conditions (1, E, P0–P3)
• VCC = 5 V± 10%
• Output timing voltage :VOL = 0.8 V, VOH = 2.0V
• Data input : VIL = 0.8 V, VIH = 2.5 V Memory expansion mode and microprocessor mode ; With Wait Address DataAddress

7702/7703 Group User’s Manual15–24 tsu(P1D – E) Data tw(L)tw(H) tr tf tc tw(EL) td(E – 1)td(E – 1) th(E – P0A) th(E – P1A) tpzx(E – P1Z)tpxz(E – P1Z) Address Address th(E – BHE)td(BHE – E) td(ALE – E) tw(ALE) td(R/W – E) th(E – R/W) Memory expansion mode and microprocessor mode ; With Wait <Read> th(E – P1D)th(ALE – P1A) tpzx(E – P2Z)tpxz(E – P2Z) th(E – P2D)th(ALE – P2A) th(E – PiD) tsu(PiD – E) f(XIN) Address output A0–A7 BHE output Port Pi input (i = 4–8) Test conditions (P4–P8)

• VCC = 5 V ± 10%
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V E Address output A8–A15 (BYTE = “H”) Data input D 8–D 15 (BYTE = “L”) Address/Data output A16/D0–A23/D7 ALE output R/W output Data input D 0–D 7 Address/Data output A8/D8–A15/D15 (BYTE = “L”) Test conditions (1, E, P0–P3)
• VCC = 5 V± 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : VIL = 0.8 V, VIH = 2.5 V tsu(P2D – E) Address Data Address td(P1A – E) td(P1A – ALE) td(P1A – E) td(P0A – E) td(P2A – E) td(P2A – ALE)

7702/7703 Group User’s Manual 15–25

15.10 Testing circuit for ports P0 to P8, φ 1, and E

Fig. 15.10.1 Testing circuit for ports P0 to P8, φ 1, and E 100pF E

7702/7703 Group User’s Manual15–26 MEMORANDUM

16.1 Standard characteristics

7702/7703 Group User’s Manual16–2 The data described below are characteristic examples for M37702M2BXXXFP. The data is not guaranteed value. Refer to “Chapter 15. ELECTRICAL CHARACTERISTICS ” for rated value.

16.1.1 Port standard characteristics

(1) Programmable I/O port (CMOS output) P channel IOH –VOH characteristics (2) Programmable I/O port (CMOS output) N channel IOL –V OL characteristics 50.0 40.0 30.0 20.0 10.0 VOH [V] IOH [mA] P channel Ta = 25 °C Ta = 85 °C Power source voltage Vcc = 5 V 50.0 40.0 30.0 20.0 10.0 VOL [V] IOL [mA] N channel Ta = 25 °C Ta = 85 °C Power source voltage Vc c = 5 V

7702/7703 Group User’s Manual 16–3

16.1.2 ICC –f(XIN) standard characteristics

(1) ICC –f(XIN) characteristics on operating and at reset (2) ICC –f(XIN) characteristics during wait 4.0 0 5 1 01 52 02 53 0 Icc [mA] f(XIN) [MHz] Measurement condition (Vcc = 5 V, Ta = 25 °C, f(XIN) : square waveform input, single-chip mode) 3.0 2.0 1.0 0 5 1 01 52 02 53 0 Icc [mA] f(XIN) [MHz] On operating At reset Measurement condition (VCC = 5 V, Ta = 25 °C, f(XIN) : square waveform input, single-chip mode)

7702/7703 Group User’s Manual16–4

16.1.3 A–D converter standard characteristics

The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in output code from 0016 to 0116 should occur at 10 mV, but the measured value is 5 mV. Therefore, the measured point of change is 10 + 5 = 15 mV. The upper lines of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is 0F16 is 22 mV. Therefore, the differential non-linear error is 22 – 20 = 2 mV (0.1LSB). Measurement condition (VCC = 5.12 V, XIN = 25 MHz, Temp. = 25°C )

17.1 Memory expansion

17.2 Sample program execution rate comparison

7702/7703 Group User’s Manual17–2 This chapter describes application. Application shown here is just an example. The user shall modify them according to the actual application and test them. This section shows examples for memory and I/O expansion. Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” for details about the functions and operation of used pins when expanding a memory or I/O. Refer to “Chapter 15. ELECTRICAL CHARACTERISTICS” for timing requirements of the microcomputer. Refer to “Chapter 18. LOW VOLTAGE VERSION” for timing requirements and application of the low voltage version.

17.1.1 Memory expansion model

Memory expansion to the external is possible in the memory expansion mode or the microprocessor mode. The level of the external data bus width select signal makes it possible to select the four memory expansion models shown in Table 17.1.1. (1) Minimum model This is an expansion model of which external data bus width is 8 bits and accessible area is expanded up to 64 Kbytes. It is unnecessary to connect the address latch externally. This is an expansion model having the cost priority which is suited for connecting the memory of which external data bus width is 8 bits. (2) Medium model A This is an expansion model of which external data bus width is 8 bits and accessible area is expanded up to 16 Mbytes. In this expansion model, the high-order 8 bits of the external address bus 23 to A16) are multiplexed with the external data bus. Accordingly, an n-bit (n ≤ 8) address latch is required for latching addresses (n bits of A23 to A16). (3) Medium model B This is an expansion model of which external data bus width is 16 bits and accessible area is expanded up to 64 Kbytes. This expansion model is used when having the speed performance priority. In this expansion model, the middle-order 8 bits of the external address bus (A 15 to A8) are multiplexed with the external data bus. Accordingly, an 8-bit address latch is required for latching address (A 15 to A8). (4) Maximum model This is an expansion model of which external data bus width is 16 bits and accessible area is expanded up to 16 Mbytes. In this expansion model, the high- and middle-order 16 bits of the external address bus (A 23 to A8) are multiplexed with the external data bus. Accordingly, an 8-bit address latch for latching A15 to A8 and an n-bit (n ≤ 8) address latch for latching n bits of A23 to A16 are required.

7702/7703 Group User’s Manual 17–3 Table 17.1.1 Memory expansion model BYTE BYTE M37702 BYTE M37702 BYTE M37702 A0–A15 D 0–D 7 A0–A15 E D 0–D 15 DQ A0–A15+n D 0–D 7 16+n E n DQ Latch E A0–A15+n D 0–D 15 n 16+n DQ E DQ ALE BHE M37702 ALE ALE BHE 8-bit width; BYTE = “H” Notes 1: Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” about the functions and operation of used pins when expanding a memory. Refer to “Chapter 15. ELECTRICAL CHARACTERISTICS” for timing requirements. 2: Because the address bus width is used as maximum 24 bits when expanding a memory, strengthen the M37702’s Vss line. (Refer to “Appendix 5. Countermeasures against noise.”) External data bus width 16-bit width; BYTE = “L” Access area Maximum 64 Kbytes Maximum 16 Mbytes Memory expansion model Minimum model Latch Memory expansion model Medium model B Memory expansion model Medium model A Latch Latch Memory expansion model Maximum model

7702/7703 Group User’s Manual17–4 f(XIN) 1 5 109 f(XIN)100 + – 125 1.2 5 109 f(XIN) – 7530 + f(XIN) ≤ 8 MHz No Wait Wait

8 MHz < f(XIN) ≤ 16 MHz

16 MHz < f(XIN) ≤ 25 MHz

– 30 4 5 109 f(XIN) – 30 4 5 109 f(XIN) – 30– 302 5 109 f(XIN) WaitNo Wait 1 5 109 f(XIN)12 + – 40 – 302 5 109 f(XIN) 4 5 109 f(XIN) – 30 Table 17.1.3 Data of each parameter (unit: ns)

17.1.2 How to calculate timing

When expanding a memory, use a memory of which standard specifications satisfy the address access time and the data setup time for write. The following describes how to calculate each timing. À External memory’s address access time; t a(AD) ta(AD) = td(P0A/P1A/P2A-E) + tw(EL) – tsu(P2D/P1D–E) – (address decode time]1 + address latch delay time] 2) td(P0A/P1A/P2A–E) : td(P0A–E) , td(P1A–E), or td(P2A–E) tsu(P2D/P1D–E) : tsu(P2D–E) or tsu(P1D–E) Address decode time] 1: Time required for the chip select signal to be enabled after decoding address Address latch delay time]2: Delay time required when latching address (Unnecessary in minimum model) \` External memory’s data setup time for write; tsu(D) tsu(D) = tw(EL) – td(E–P2Q/P1Q) td(E–P2Q/P1Q) : td(E–P2Q) or td(E–P1Q) Table 17.1.2 lists the calculation formulas for each parameter; Table 17.1.3 lists the data of each parameter; Figure 17.1.1 shows the bus timing diagrams. Figures 17.1.2 and 17.1.4 show the relationship between t a(A-D) and f(XIN); Figures 17.1.3 and 17.1.5 show the relationship between tsu(D) and f(XIN). Table 17.1.2 Calculation formulas for each parameter (unit: ns) 2 5 109 f(XIN) Parameter Type td(P0A—E) td(P1A—E) td(P2A—E) tw(EL) tsu(P1D—E) tsu(P2D—E) td(E—P1Q) td(E–P2Q)

25 MHz version16 MHz version

7702/7703 Group User’s Manual 17–5 tsu(P1D-E) E ALE td(P0A-E) td(P2A-E) tsu(P2D-E) tw(EL) td(E-P2Q) td(P1A-E) td(E-P1Q) R/W E ALE Address low-order td(P0A- E) td(P1A-E) td(P2A-E) tsu(P2D-E) tw(EL) A0–A7 A8–A15 A16/D0– A23/D7 td(E-P2Q) R/W Data Data ta(AD) tsu(D) tw(EL) ta(AD) tsu(D) tw(EL) A0–A7 A8/D8– A15/D15 A16/D0– A23/D7 : M37702’s standard characteristics (The others are the external memory’s.) External data bus width = 8 bits (BYTE = “H”) External data bus width = 16 bits (BYTE = “L”) Data Data Address low-order Address middle-orderAddress middle-order Address high-order Address high-order When writing dataWhen reading data When writing dataWhen reading data Data low-order Address middle-order Data high-order Address middle-order Address high-order Address high-order Address low-orderAddress low-order Fig. 17.1.1 Bus timing diagrams

7702/7703 Group User’s Manual17–6 Fig. 17.1.2 Relationship between ta(AD) and f(XIN) (16 MHz version) Fig. 17.1.3 Relationship between tsu(D) and f(XIN) (16 MHz version) 7 8 9 10 11 12 13 14 15 16 100 150 200 250 300 350 400 450 500 550 600 650 457 400 352 313 280 251 226 205 614 525 280 235 200 170 146 126 108 93 80 328 275 530 Memory access time t a(AD) External clock input frequency f(XIN) No wait Wait [ns] [MHz] ] Address decode time and address latch delay time are not considered. Data setup time t su(D) 7 8 9 10 11 12 13 14 15 16 100 150 200 250 300 350 400 450 500 400 344 300 263 233 207 185 166 150 150 122 100 81 66 53 42 33 25 471 185 [MHz] [ns] External clock input frequency f(XIN) No wait Wait

7702/7703 Group User’s Manual 17–7 Fig. 17.1.4 Relationship between ta(AD) and f(XIN) (25 MHz version) Fig. 17.1.5 Relationship between tsu(D) and f(XIN) (25 MHz version) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 200 300 400 500 600 700 224 206 189 175 162 150 139 129 120 112 545 472 415 367 328 295 266 241 220 629 540 99 88 78 69 62 54 48 42 37 32 295 250 215 185 161 141 123 108 343 290 [ns] [MHz] Memory access time t a(AD) External clock input frequency f(XIN) No wait Wait ] Address decode time and address latch delay time are not considered. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 150 200 250 300 350 400 450 500 496 425 369 325 288 258 232 210 191 175 160 147 135 125 115 106 98 91 85 210 175 147 125 106 91 78 67 58 50 42 36 30 25 20 15 11 8 5 [MHz] [ns] Data setup time t su(D) External clock input frequency f(XIN) No wait Wait

7702/7703 Group User’s Manual17–8

17.1.3 Points in memory expansion

(1) Reading data Figure 17.1.6 shows the timing at which data is read from an external memory. When reading data, the external data bus is placed in a floating state, and data is read from the_ external memory. This floating state is maintained from tpxz(E–P1Z/P2) after the falling edge of the E_ signal till tpzx(E–P1Z/P2Z) after the rising edge of the E signal. Table 17.1.4 lists the values of tpxz(E–P1Z/P2Z) and the formulas to calculate tpzx(E–P1Z/P2Z). Consider timing during data read to avoid collision between the data being read–in and the preceding or following address output because the external data bus is multiplexed with the external address bus. (Refer to “(3) Precautions on memory expansion.”) Fig. 17.1.6 Timing at which data is read from an external memory External memory data output ]1 This applies when the external data bus has a width of 16 bits (BYTE = “L”). External memory output enable signal (Read signal) OE E External memory chip select signal CE, S ]2 If one of the external memory’s specifications is smaller than tpxz(E-P1Z/P2Z) , there is a possibility of the tail of address colliding with the head of data. → Refer to “(3) Precautions on memory expansion.” ]3 If one of the external memory’s specifications is greater than tpzx(E-P1Z/P2Z) , there is a possibility of the tail of data colliding with the head of address. → Refer to “(3) Precautions on memory expansion.” Address output and data input A8/D 8–A15/D15 A16/D0–A23/D7 ten(OE) Address tpzx(E-P1Z/P2Z) tsu(P1D/P2D-E) : Specifications of the M37702 (The others are specifications of external memory.) ta(OE) ta(CE), ta(S) tDF , tdis(OE) tw(EL) Data tpxz(E-P1Z/P2Z) ten(CE), ten(S) Address

7702/7703 Group User’s Manual 17–9 Table 17.1.4 Values of tpxz(E–P1Z/P2Z) and formulas to calculate tpzx(E–P1Z/P2Z) (unit : ns) Parameter f(XIN) tpxz(E—P1Z) tpxz(E—P2Z) tpzx(E—P1Z) tpzx(E–P2Z) f(XIN) ≤ 8 MHz 8 MHz < f(XIN) ≤ 16 MHz 16 MHz < f(XIN) ≤ 25 MHz 5 5 5 1 5 109 f(XIN) – 30 – 261 5 109 f(XIN) 1 5 109 f(XIN) – 22 Note: In the M37702E2AXXXFP, the M37702E2AFS, the M37702E4AXXXFP, the M37702E4AFS, the M37703E2AXXXSP, and the M37703E4AXXXSP, refer to section “19.5.4 Bus timing and EPROM mode.” (Note)

7702/7703 Group User’s Manual17–10 (2) Writing data Figure 17.1.7 shows the timing at which data is written to an external memory._ When writing data, the output data starts after td(E-P1Q/P2Q) passes from falling of the E signal. Its_ validated data is output continuously until th(E-P1Q/P2Q) passes from rising of the E signal. Data output at writing data must satisfy the data set up time, tsu(D), and the data hold time, th(D), for write to an external memory. Fig. 17.1.7 Timing at which data is written to an external memory Table 17.1.5 Calculation formulas of th(E-P1Q/P2Q) (unit: ns) Parameter 1 5 109 2 5 f(XIN) – 12.5 f(XIN) ≤ 8 MHz 1 5 109 2 5 f(XIN)– 6.25

8 MHz < f(XIN) ≤ 16 MHz 16 MHz < f(X IN) ≤ 25 MHz

2 5 f(XIN)– 2 f(XIN) th(E—P1Q) th(E—P2Q) Table 17.1.6 Constants of td(E-P1Q/P2Q) (unit: ns) Parameter td(E—P1Q) td(E—P2Q) 70 45 tsu(D) th(D) AddressData E W, WE External memory chip select signalsCE, S tw(EL) th(E-P1Q/P2Q) (The others are specifications of external memory.) : Specifications of the M37702 ] This applies when the external data bus has a width of 16 bits (BYTE = “L”). td(E-P1Q/P2Q) A8/D8–A15/D15 A16/D0–A23/D7 Address and data output External memory write signals Address Microcomputer type 25 MHz version16 MHz version

7702/7703 Group User’s Manual 17–11 (3) Precautions on memory expansion As described in À to ´ below, if specifications of the external memory do not match those of the M37702, some considerations must be incorporated into circuit design as in the following cases: À When using an external memory that requires a long access time, ta(AD) \` When using an external memory that outputs data within tpxz(E-P1Z/P2Z) after the falling edge of the_ E signal ´ When using an external memory that outputs data for more than tpzx(E-P1Z/P2Z) after the rising edge_ of the E signal À When using external memory that requires long access time, ta(AD) If the M37702’s tsu(P1D/P2D-E) cannot be satisfied because the external memory requires a long access time, ta(AD), examine the method described below. l Lower f(XIN). l Select software Wait. (Refer to section “12.2 Software Wait.”) l Use Ready function. (Refer to section “12.3 Ready function.”) shows an example of a Ready signal generating circuit (with Wait). Ready function is valid for the internal areas, so that the circuits in Figures 17.1.8 and 17.1.9 use___ the chip select signal (CS2) to specify the area where Ready function is valid.

7702/7703 Group User’s Manual17–12 A8–A23 (D0–D 15) A0–A7 AC74 D T Q RDY E AC32 AC32 AC04 Address bus Data bus CS 2 E CS 2 Q RDY tc td(E- 1) tsu(RDY- 1)] Address latch circuit Address decode circuit Circuit condition: f(XIN) ≤ 14.5 MHz, no Wait Insert Wait by Ready function only for areas accessed by CS : Wait by Ready function. :The condition satisfying tsu(RDY- 1) ≥ 60 ns is tc ≥ 68.5 ns. Accordingly, when f(XIN) ≤ 14.5 MHz, this circuit example satisfies tsu(RDY- 1) ≥ 60 ns. AC32 propagation delay time (max. : 8.5 ns) ] This applies when using the 16 MHz version. Fig. 17.1.8 Example of Ready signal generating circuit (no Wait)

7702/7703 Group User’s Manual 17–13 A8–A23 (D0–D 15) A0–A7 RDY E F32 F32 Address bus Data bus Address latch circuit Address decode circuit CS 2 RD F04 F04 F74 E CS 2 RDY th( 1-RDY) : Software Waittsu(RDY- 1) ]1–]3 (f(XIN) = 25 MHz, 25 ns). 2 5 10 f(XIN) –tsu(RDY– 1) Circuit condition: f(XIN) ≤ 25 MHz, Wait Insert Wait by Ready function only for areas accessed by CS : Wait by Ready function. ] This applies when using the 25 MHz version. Use the elements of which sum of propagation delay time is within Fig. 17.1.9 Example of Ready signal generating circuit (Wait)

7702/7703 Group User’s Manual17–14 \` When using external memory that outputs data within tpxz(E-P1Z/P2Z) after falling edge of E signal_ Because the external memory outputs data within tpxz(E-P1Z/P2Z) after the falling edge of the E signal, there will be a possibility of the tail of address colliding with the head of data. In this case,__ _ generate the memory read signal (OE) by delaying only the leading edge of the fall of the E. (Refer to Figure 17.1.10.) Fig. 17.1.10 Example of causing to delay data output timing Note: Satisfy tpxz(E-P1Z/P2Z) ≤ ten(OE)+d. If ten(OE) ≤ tpxz(E-P1Z/P2Z) (= 5 ns), ensure a certain time (i.e., ‘d’ in this diagram) by delaying the falling edge of OE after the falling edge of E . Address output External memory data output tpxz(E-P1Z/P2Z) E OE d Address Address Data ta(OE) ten(OE) External memory output enable signal (Read signal) (The others are specifications of external memory.) : Specifications of the M37702

7702/7703 Group User’s Manual 17–15 ´ When using external memory that outputs data for more than tpzx(E-P1Z/P2Z) after rising edge of_ E signal Because the external memory outputs data for more than tpzx(E-P1Z/P2Z) after the rising edge of the_ E signal, there will be a possibility of the tail of data colliding with the head of address. In this case, examine the method described below. l Cut the tail of data output from the external memory by using a bus buffer and others. l Use the Mitsubishi’s memories that can be connected without a bus buffer. Table 17.1.7 lists the memories that can be connected without a bus buffer. These memories do not require a bus buffer because timing parameters t DF and tdis(OE) listed below are guaranteed._ (However, the read signal must go high within 10 ns after the rising edge of E signal.) Table 17.1.7 Memories that can be connected without bus buffer Type description M5M27C256AK-85, -10, -12, -15 M5M27C512AK-10, -12, -15 M5M27C100K-12. -15 M5M27C101K-12, -15 M5M27C102K-12, -15 M5M27C201K, JK-10, -12, -15 M5M27C202K, JK-10, -12, -15 M5M27C256AP, FP, VP, RV-12, -15 M5M27C512AP, FP-15 M5M27C100P-15 M5M27C101P, FP, J, VP, RV-15 M5M27C102P, FP, J, VP, RV-15 M5M27C201P, FP, J, VP, RV-12, -15 M5M27C202P, FP, J, VP, RV-12, -15 M5M28F101P, FP, J, VP, RV-10, -12, -15 M5M28F102FP, J, VP, RV-10, -12, -15 M5M5256CP, FP, KP, VP, RV-55LL, -55XL, -70LL, -70XL, -85LL, -85XL, -10LL, -10XL M5M5278CP, FP, J-20, -20L M5M5278CP, FP, J-25, -25L M5M5278DP, J-12 M5M5278DP, FP, J-15, -15L M5M5278DP, FP, J-20, -20L Memory EPROM One-time PROM Frash memory SRAM Conditions f(X IN) ≤ 20 MHz f(XIN) ≤ 25 MHz tDF /tdis(OE) (Maximum) 15 ns (Guaranteed by kit) (Note) 8 ns 10 ns 6 ns 7 ns 8 ns Note: When the user needs a specification of the memories listed above, add the comment “tDF /tdis(OE) 15 ns product, microcomputer and kit.”

7702/7703 Group User’s Manual17–16 Fig. 17.1.11 Example for using bus buffer (1) F245 BYTE A8/D8– A15/D15

25 MHz

Data bus (odd) LE DQ OE AC573 DIR AB LE DQ OE AC573 ALE A1–A7 Address bus M37702 DIR AB E R/W BHE BC32 AC04 RD WO WE AC32XIN XOUT Circuit condition: Wait F245 A16/D0– A23/D7 CNV SS OC OC Data bus (even) ]1: Use the elements of which propagation delay time is within 20 ns. ]2, ]3 : Use the elements of which sum of output disable time in ]2 and propagation delay time in ]3 is within 18 ns and the sum of output enable time in ]2 and propagation delay time in ]3 is 5 ns or more. ]4: Use the elements of which propagation delay time is within 12 ns.

7702/7703 Group User’s Manual 17–17 A A E OC (F245), RD 5 (max.) 130 (min.) 18 (min.) BC32 (t PHL ) BC32 (t PLH D A A <When reading> F245 PHZ PLZ F245 PZH PZL A A E 130 (min.) BC32 (t PLH D A <When writing> D F245 PHL PLH (Unit : ns) F245 PHZ PLZ OC (F245), WO, WE 45 (max.) BC32 (t PHL External memory data output A (F245) External memory data output B (F245) Fig. 17.1.12 Timing chart for sample circuit using bus buffers (1) A

7702/7703 Group User’s Manual17–18 Fig. 17.1.13 Example for using bus buffer (connecting with memory requiring a long hold time for write) ALS245A BYTE E

16 MHz

Data bus (even) Data bus (odd) LE DQ OE AC573 OCDIR AB LE DQ OE AC573 ALE A1–A7 Address bus DIR AB R/W BHE AC32 AC04 RD WE WO 1D1Q 2Q2T

1 AC74

A8/D8– A15/D15 M37702 A16/D0– A23/D7 CNV SS OC This is the circuit that extends the write hold time by making the rising of the write signal 1/2 1 clock earlier. Circuit condition : Wait ]1: Use the elements of which propagation delay time is within 30 ns. ]2: Use the elements of which output enable time is 5 ns or more and output disable time is within 36 ns.

7702/7703 Group User’s Manual 17–19 Fig. 17.1.14 Timing chart for sample circuit using bus buffers (2) A8/D8–A15/D15 A16/D0–A23/D7 RD 5 (max.) 220 (min.) 36 (min.) AC32 (tPHL ) AC32 (t PLH ) D A ALS245A (tPHZ /tPLZ ) E, OC (ALS245A) ALS245A PZH /tPZL ) (Unit : ns) D A D AC32 5 2 (tPLH ) ALS245A PHZ /tPLZ ) A8/D8–A15/D15 A16/D0–A23/D7 WO, WE 2Q(AC74) 1Q (AC74) E, OC (ALS245A) AC04 (tPLH )+AC74 (tPLH ) 70 (max.) ALS245A PHL /tPLH ) 220 (min.) <When reading> <When writing> External memory data output A (ALS245A) Write hold time External memory data output B (ALS245A) A

7702/7703 Group User’s Manual17–20

17.1.4 Example of memory expansion

(1) Example of SRAM expansion (minimum model) Figure 17.1.15 shows a memory expansion example (minimum model) using a 32-Kbyte SRAM in the memory expansion mode. Figure 17.1.16 shows the timing chart for this example. Fig. 17.1.15 Example of SRAM expansion (minimum model) D 0–D 7 AC32 E OpenBHE A0–A14 OE S M5M5256CP-70LL A15 CNV SS WE 088016 SFR area Internal RAM area External RAM area (M5M5256CP) Memory map 000016 008016 AC32 A0–A14 D 0–D 7 ]1, ]2: Use the elements of which propagation delay time is within 18 ns. FFFF 16 800016 Circuit condition : Wait Internal ROM area

7702/7703 Group User’s Manual 17–21 Fig. 17.1.16 Timing chart for SRAM expansion example (minimum model) D 0–D 7 External RAM data output (A) (A) D S ta(AD) 130 (min.) 12 (min.) 5 (max.) 18 (min.) ta(OE) tsu(P2D-E) ≥ 30 15 (max.) (Kit guaranteed) E, OE AC32 (tPLH )AC32 (tPHL ) ta(S) E, OE A0–A14 AA D 0–D 7 S (A) (A) WE D 130 (min.) tsu(D) ≥ 30AC32 (tPHL ) AC32 (tPLH ) 45 (max.) 18 (min.) AC32 (tPLH )AC32 (tPHL ) A0–A14 A <When reading> (Unit : ns) <When writing>

7702/7703 Group User’s Manual17–22 (2) Example of ROM expansion (maximum model) Figure 17.1.17 shows a memory expansion example (maximum model) using a 2-Mbits ROM in the microprocessor mode. Figure 17.1.18 shows the timing chart for this example. Fig. 17.1.17 Example of ROM expansion (maximum model) A0–A16 M5M27C202K-10 OE A1–A7 AC04 A1–A17Address bus A16/D0, A17/D1 ALE D 1–D 7 E R/W A8/D8– A15/D15 AC573 CE D 0–D 15 D 0–D 15 A8–A15 000016 008016 SFR area Internal RAM area External ROM area (M5M27C202K) Memory map Q LE D CNV SS [ 2 [ 1 AC573 Q LE D A16, A17 3FFFF 16 028016 Circuit condition : Wait ]1: Use the elements of which propagation delay time is within 12 ns. ]2: Use the elements of which propagation delay time is within 20 ns.

7702/7703 Group User’s Manual 17–23 A8/D8–A15/D15 A16/D0 A 130 (min.) 12 (min.) ta(AD)+AC573 (tPHL /tPLH ) CE ta(OE) R/W 20 (min.) ta(CE) AC04 (tPHL ) 18 (min.) A 5 (max.) D (Kit guaranteed) tsu(P1D/P2D-E) ≥ 30 18 (max.) E, OE AC04 (tPLH ) 15 (max.) <When reading> (Unit : ns) External ROM data output Fig. 17.1.18 Timing chart for ROM expansion example (maximum model)

7702/7703 Group User’s Manual17–24 (3) Example of ROM and SRAM expansion (maximum model) Figure 17.1.19 shows a memory expansion example (maximum model) using two 32-Kbyte ROM and two 32-Kbyte SRAM in the microprocessor mode. Figure 17.1.20 shows the timing diagram for this example. Fig. 17.1.19 Example of ROM and SRAM expansion (maximum model) 000016 008016 External ROM area (M5M27C256AK 5 2) SFR area Internal RAM area External RAM area (M5M5256CP 5 2) Memory map AC32AC04

20 MHz

A8–A15 Data bus (odd) AC573 DQ LE AC32 AC04 RD D0 –D7D8 –D15 Address bus WO A0–A14 D 0–D 7 M5M27C256AK-15 A1–A15 D 0–D 7 OE A0–A14 CE A1–A15 S S A0–A14 A0–A14 DQ 1–DQ 8 DQ 1–DQ 8 OE W OE W A1–A15 A1 –A15 D0 –D7 M5M5256CP-70LL OE D8 –D15 CE WE A1–A7 A8/D8– A15/D15 ALE A16/D0 D 1–D 7 R/W E BHE CNV SS [ 2 [ 1 AC573 DQ LE [ 2 1FFFF 16 1000016 028016 Data bus (even) Circuit condition : Wait ]1, ]2 : Use the elements of which sum of propagation delay time is within 92 ns. ]2: Use the elements of which propagation delay time is within 12 ns. ]3: Use the elements of which propagation delay time is within 13 ns.

7702/7703 Group User’s Manual 17–25 A1–A7 AA E A8/D 8–A15/D 15 A16/D 0, D1–D 7 S AA D 170 (min.) 45 (max.) 22 (min.) AC32 (tPHL ) tsu(D) ≥ 30 (Unit: ns) WE, WO AC573 (tPHL )+AC04 (tPHL ) AC32 (tPLH ) A8/D 8–A15/D 15 A16/D 0 External memory data output AA D <When reading> E 170 (min.) 22 (min.) 5 (max.) 28 (min.) (Kit guaranteed) ta(AD), ta(CE) tsu(P1D/P2D-E) ≥ 30 ta(S) OE AC32 (tPLH ) A1–A7 AA CE, S ta(OE) AC04 (tPHL ) AC573 (tPHL ) CE S AC32 (tPHL ) 15 (max.) 23 (min.) <When writing> Fig. 17.1.20 Timing diagram for ROM and SRAM expansion example (maximum model)

7702/7703 Group User’s Manual17–26

17.1.5 Example of I/O expansion

(1) Example of port expansion circuit using M66010FP Figure 17.1.21 shows an example of a port expansion circuit using the M60010FP. Use 1.923 MHz or less frequency for Serial I/O transfer clock. Serial I/O control in this expansion example is described below. In this example, 8-bit data transmission/reception is performed 3 times by using UART0 and 24-bit port expansion is realized. Setting of UART0 is described below. l Clock synchronous serial I/O mode; Transmission/Reception enable state l Selected internal clock. Transfer clock frequency of 1.5625 MHz. l LSB first The control procedure is described below. À Output “L” level from port P4 5. (Expansion I/O ports of M66010FP become floating state by this signal.) \` Output “H” level from port P45. ´ Output “L” level from port P44. ˆ Transmit/Receive 24-bit data by using UART0. ˜ Output “H” level from port P44. Figure 17.1.22 shows serial transfer timing between M37702 and M66010FP.

7702/7703 Group User’s Manual 17–27 Fig. 17.1.21 Example of port expansion circuit using M60010FP S V CC GND CNV SS BYTE M66010FP D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 A0–A7 A8/D8– A15/D15 A16/D0– A23/D7 ALE E f 1 R/W BHE Open Expanded I/O port 2 (3 + 1) Circuit condition: •UART0 used in clock synchronous serial I/O mode

• Internal clock selected
• Frequency of transfer clock = = 1.5625 MHz

7702/7703 Group User’s Manual17–28 Fig. 17.1.22 Serial transfer timing between M37702 and M66010FP DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO20 DO21 DO22 DO23 DO24 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI20 DI21 DI22 DI23 DI24 DI1 DI2 DI24 S CS CLK DI DO Expanded I/O port DO24 DO2 DO1 D24 P45 P44 CLK 0 TXD 0 R X D 0 Expanded I/O port Expanded I/O port Terminating floating of expanded I/O ports Inputting data of expanded I/O ports to shift register 1 Inputting serial data to shift register 2 Serial outputting data of shift register 1 ] Expanded I/O ports are N-channel open-drain output type. : M37702’s pin name (The others are M66010FP’s pin name and operation.) Outputting data of shift register 2 to expanded I/O ports

7702/7703 Group User’s Manual 17–29 Sample program execution rates are compared in this paragraph. The execution time ratio depends on the program or the usage conditions.

17.2.1 Difference depending on data bus width and software Wait

Internal areas are always accessed at 16-bit data bus width and without software Wait. In the external areas, the external data bus width and software Wait are selectable. Table 17.2.1 lists the sample program (refer to Figure 17.2.1) execution time ratio depending on these selection and used memory areas. Table 17.2.1 Sample program execution time ratio (external data bus width and software Wait) Memory area RAM Internal Internal External ROM Internal External External External data bus width (bit) Software Wait Sample program execution time ratio Sample B 1.00 1.00 1.10 1.08 1.46 1.00 1.17 1.13 1.65 0.90 Sample A 1.00 1.00 1.17 1.19 1.67 1.00 1.25 1.19 1.78 0.92 (16) (Nothing) Nothing Inserted Nothing Inserted Nothing Inserted Nothing Inserted Calculation value] Calculation value] : The value is calculated from the shortest execution cycle number of each instruction described in the software manual.

7702/7703 Group User’s Manual17–30 Fig. 17.2.1 Sample program list SEP M,X LDA.B A,#0 STA A,DEST+64 STA A,DEST+65 STA A,DEST+66 LDX.B #63 LDA A,SOUR,X TAY AND.B A,#00000011B STA A,DEST,X TYA AND.B A,#00001100B ORA A,DEST+1,X STA A,DEST+1,X TYA AND.B A,#00110000B ORA A,DEST+2,X STA A,DEST+2,X TYA AND.B A,#11000000B ORA A,DEST+3,X STA A,DEST+3,X DEX BPL ITALIC ITALIC: SEP X CLM .DATA 16 .INDEX 8 LDY #69 LDX #69 ASL SOUR,X SEM .DATA 8 ROL SOUR+2,X ROL B CLM .DATA 16 ROR A DEX DEX DEX BNE LOOP1 STA A,DEST,Y SEM .DATA 8 STA B,DEST+2,Y CLM .DATA 16 DEY DEY DEY BNE LOOP0 LOOP0: LOOP1: Sample A Sample B ] SOUR, DEST : Work area (Direct page area : Access this area at the following mode.)

• Direct addressing mode
• Direct Indexed X addressing mode
• Absolute Indexed Y addressing mode

7702/7703 Group User’s Manual 17–31

17.2.2 Comparison software Wait (f(XIN) = 20 MHz) with software Wait + Ready (f(XIN) = 25 MHz)

The following condiitons À and \ are compared. Refer to Figure 17.2.1 about executed sample program. The execution time ratio depends on the program or the usage conditions. Condition À : When selecting software Wait and f(XIN) = 20 MHz Condition \ : When selecting software Wait and f(XIN) = 25 MHz and inserting a Wait which is 1 cycle of φ (inserting total Wait of 2 cycles of φ). Table 17.2.2 Comparison condition Item Processor mode f(XIN) External data bus width Software Wait Ready Program area Work area Condition À Microprocessor mode Condition \` Microprocessor mode Valid only to external EPROM areas External EPROM Internal or External SRAM Fig. 17.2.2 Memory allocation at execution rate comparison External SRAM SFR area Condition \` Ready valid area Insert Wait of 5 2 cycles at access (including software Wait) M37702 memory map Internal SRAM Program area External EPROM Software Wait valid area Specify either area as the work area

7702/7703 Group User’s Manual17–32 Figure 17.2.3 shows that there is almost no difference between conditions À and \ about the execution time. The bus buffers become unnecessary by using the specific memory. (See Table 17.1.7.) Consequently, the case selecting f(X IN) = 20 MHz and inserting software Wait is superior in the cost performance. 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.04 1.01 1.00 1.00 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 : Condition À : Condition \ Execution time ratio in sample BExecution time ratio in sample A Work area = Internal RAM Work area = External RAMWork area = Internal RAM Work area = External RAM Fig. 17.2.3 Execution time ratio

18.1 Performance overview

18.2 Pin configuration

18.3 Functional description

18.4 Electrical characteristics

18.5 Standard characteristics

18.6 Application

7702/7703 Group User’s Manual18–2 The low voltage version has the following characteristics:

• Low power source voltage (2.7 to 5.5 V)
• Wide operating temperature range (–40 to 85 °C) The low voltage version is suitable to control equipment which is required to process a large amount of data with a low power dissipation, for example portable equipment which is driven by a battery and OA equipment. Differences between the M37702M2LXXXGP and the M37702M2BXXXFP are mainly described below. For the EPROM mode of the PROM version, refer to “Chapter 19. PROM VERSION.”

7702/7703 Group User’s Manual 18–3 Input/Output withstand voltage Output current Table 18.1.1 shows the performance overview of the M37702M2LXXXGP. Table 18.1.1 M37702M2LXXXGP performance overview Functions 103 500 ns (the minimum instruction at f(XIN) = 8 MHz)

8 MHz (maximum)

(UART or clock synchronous serial I/O) 5 2 8-bit successive approximation method 5 1 (8 channels) 12 bits 5 1 3 external, 16 internal (priority levels 0 to 7 can be set for each interrupt with software) Built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 2.7 – 5.5 V 12 mW (at supply voltage = 3 V, f(XIN) = 8 MHz frequency) 30 mW (at supply voltage = 5 V, f(XIN) = 8 MHz frequency) 5 V 5 mA Maximum 16 Mbytes –40°C to 85°C CMOS high-performance silicon gate process 80-pin plastic molded QFP Parameters Number of basic instructions Instruction execution time External clock input frequency f(X IN) Memory size Programmable Input/Output ports Multifunction timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation Port Input/Output characteristics Memory expansion Operating temperature range Device structure Package ROM RAM P0–P2, P4–P8 TA0–TA4 TB0–TB2 UART0, UART1 Note: Low voltage versions except the M37702M2LXXXGP are the same except for the package type, memory type, and memory size.

7702/7703 Group User’s Manual18–4 shows the M37702M4LXXXFP pin configuration. E CNV SS RESET 0/HOLD Outline M37702M2LXXXGP • • • • • • 80P6S-A P86/RxD 1 P87/TxD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 75 74 73 72 71 69 68 67 66 657080 79 78 77 76 64 63 62 61 3026 27 28 29 31 32 33 34 35 3621 2322 24 25 37 38 39 40 1/RDY BYTE X IN V SS 0/R/W 7/A 6/A 5/A 4/A 3/A 2/A P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 5/CLK 4/CTS 1/RTS 3/T XD 2/R XD 1/CLK 0/CTS 0/RTS V CC AV CC V REF AV SS V SS 7/AN 7/AD TRG 6/AN 5/AN 4/AN 3/AN 2/AN 1/AN 0/AN 7/TB2 IN M37702M2LXXXGP or M37702M2LXXXHP P43 P44 P45 P46 ] ] Outline M37702M2LXXXHP • • • • • • 80P6D-A ] : The M37702M2LXXXGP and the M37702M2LXXXHP have the pin configuration shifted to 2 pins assignment from the M37702M2BXXXFP. Fig. 18.2.1 M37702M2LXXXGP and M37702M2LXXXHP pin configuration (top view)

7702/7703 Group User’s Manual 18–5 Fig. 18.2.2 M37702M4LXXXFP pin configuration (top view) 25 2726 28 34 29 30 31 32 33 35 36 37 38 39 40 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 0/HOLDBYTECNV SS RESET X IN X OUT E V ss 3/HLDA 2/ALE 1/BHE 0/R/W 7/A 6/A 5/A 4/A 4/AN 5/AN 6/AN 7/AN 7/AD TRG V SS AV SS V REF AV CC V CC 0/CTS 0/RTS 1/CLK 2/R XD 3/T XD P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 80 79 78 77 76 75 74 73 72 71 69 68 67 66 6570 Outline: 80P6N-A P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 P22/A18/D2 P23/A19/D3 M37702M4LXXXFP P41/RDY P47 P46 P45 P44 P43 P42/ 1 1/AN 2/AN 3/AN

7702/7703 Group User’s Manual18–6 The M37702M2LXXXGP has the same functions as the M37702M2BXXXFP except for the power-on reset conditions. Power-on reset conditions are described below. For the other functions, refer to chapters “2. CENTRAL PROCESSING UNIT” to “14. CLOCK GENERATING CIRCUIT.”

7702/7703 Group User’s Manual 18–7

18.3.1 Power-on reset conditions

Figure 18.3.1 shows the power-on reset conditions and Figure 18.3.2 shows an example of power-on reset circuit. For details of reset, refer to “Chapter 13. RESET.” Fig. 18.3.1 Power-on reset conditions Fig. 18.3.2 Example of power-on reset circuit 0 V 0 V VCC RESET Power-on 2.7 V 0.55 V ] In the case of Cd = 0.07 µF, delay time td is about 10 ms. VCC C d INT GND RESET RESET VCC C d 5 V M62003L M37702M2LXXXGP td ≈ 0.152 5 Cd [ µs], Cd: [ µF ] INTi (i = 0–2) (Interrupt signal) (Reset signal)

7702/7703 Group User’s Manual18–8 The electrical characteristics of M37702M2LXXXGP and M37702M2LXXXHP is described below. For the latest data, inquire of addresses described last (“CONTACT ADDRESSES FOR FURTHER INFORMATION”) .

18.4.1 Absolute maximum ratings

Analog power source voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ta = 25 °C Ta = 25 °C Unit V V V V V mW Ratings –0.3 to 7 –0.3 to 7 –0.3 to 12 –0.3 to Vcc+0.3 –0.3 to Vcc+0.3 300 200 –40 to 85 –65 to 150 RESET , CNV SS , BYTE P0 0–P0 7, P10–P1 7, P20–P2 7, P3 0–P3 3, P40–P4 7, P50–P5 7, P6 0–P6 7, P70–P7 7, P80–P8 7, VREF , X IN P0 0–P0 7, P10–P1 7, P20–P2 7, P3 0–P3 3, P40–P4 7, P50–P5 7, P6 0–P6 7, P70–P7 7, P80–P8 7, XOUT , E Symbol V CC AV CC V I V I V O P d Topr Tstg M37702M2LXXXGP M37702M2LXXXHP

7702/7703 Group User’s Manual 18–9

18.4.2 Recommended operating conditions

Recommended operating conditions (VCC = 2.7 – 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) V V V V V V V V V V mA mA mA mA MHz Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage High-level input voltage High-level input voltage Low-level input voltage Low-level input voltage Low-level input voltage High-level peak output current High-level average output current Low-level peak output current Low-level average output current External clock input frequency VCC AV CC VSS AV SS VIH VIH VIH VIL VIL VIL IOH (peak) IOH (avg) IOL (peak) IOL (avg) f(XIN) ParameterSymbol Limits Min. Max. 5.52.7 VCC Typ. Unit VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC –10 0.5VCC P00–P07, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVSS , BYTE P10–P17, P20–P27 (in single-chip mode) P10–P17, P20–P27 (in memory expansion mode and microprocessor mode) P00–P07, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVSS , BYTE P10–P17, P20–P27 (in single-chip mode) P10–P17, P20–P27 (in memory expansion mode and microprocessor mode) P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P43, P50–P57, P60–P67, P70–P77, P80–P87 P00–P07, P10–P17, P20–P27, P30–P33, P40–P43, P54–P57, P60–P67, P70–P77, P80–P87 0.8VCC 0.8VCC Notes 1: Average output current is the average value of a 100 ms interval. 2: The sum of IOL (peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH (peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL (peak) for ports P4, P5, P6, and P7 must be 80 mA or less, and the sum of IOH (peak) for ports P4, P5, P6, and P7 must be 80 mA or less.

7702/7703 Group User’s Manual18–10 High-level output voltage High-level output voltage High-level output voltage High-level output voltage Low-level output voltage Low-level output voltage Low-level output voltage Low-level output voltage Hysteresis Hysteresis Hysteresis High-level input current Low-level input current RAM hold voltage Power source current

18.4.3 Electrical characteristics

Electrical characteristics (VCC = 5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol Parameter Test conditions Min. Max. V V V V V V V V V V V V µA µA V mA µA µA Unit 0.5 0.45 1.9 0.43 0.4 1.6 0.4 0.4 0.7 0.5 0.4 0.3 0.2 Typ. Limits P00–P07, P10–P17, P20–P27, P30, P31, P33, P40–P4 7, P50–P5 7, P60–P6 7, P70–P7 7, P80–P87 P00–P07, P10–P17, P20–P27, P30, P31, P33 P32 E P00–P07, P10–P17, P20–P27, P30, P31, P33, P40–P4 7, P50–P5 7, P60–P6 7, P70–P7 7, P80–P87 P00–P07, P10–P17, P20–P27, P30, P31, P33 P32 E RESET XIN P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVSS , BYTE P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, XIN, RESET , CNVSS , BYTE HOLD , RDY , TA0 IN–TA4 IN, TB0 IN–TB2 IN, INT0–INT2, ADTRG , CTS 0, CTS 1, CLK0, CLK1 VOH VOH VOH VOH VOL VOL VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIL VRAM ICC VCC = 5 V, IOH = –10 mA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOH = –400 µA VCC = 5 V, IOH = –10 mA VCC = 5 V, IOH = –400 µA VCC = 3 V, IOH = –1mA VCC = 5 V, IOH = –10 mA VCC = 5 V, IOH = –400 µA VCC = 3 V, IOH = –1mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 2 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V, VI = 5 V VCC = 3 V, VI = 3 V VCC = 5 V, VI = 0 V VCC = 3 V, VI = 0 V When clock is stopped. In single-chip mode, output pins are open, and the other pins are connected to V SS . f(XIN) = 8 MHz Ta = 25 °c, when clock is stopped Ta = 85 °c, when clock is stopped VCC = 3 V VCC = 5 V 2.5 4.7 3.1 4.8 2.6 3.4 4.8 2.6 0.4 0.1 0.2 0.1 0.1 0.06

7702/7703 Group User’s Manual 18–11

18.4.4 A-D converter characteristics

A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 2.7 – 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) UnitParameter Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage Test conditions V REF = VCC V REF = VCC V REF = VCC Limits Min. 28.5 2.7 Typ. Max. VCC V REF Bits LSB k s V V R LADDER tCONV V REF V IA

7702/7703 Group User’s Manual18–12

18.4.5 Internal peripheral devices

Timing requirements (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Timer A input (count input in event counter mode) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width tc(TA) tw(TAH) tw(TAL) ns ns ns Min. 250 125 125 Max. Limits UnitParameterSymbol Timer A input (gating input in timer mode) ns ns ns tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Max.Min. Note: TAiIN input cycle time must be 4 cycles or more of count source, TAiIN input high-level pulse width must be 2 cycles or more of count source, TAiIN input low-level pulse width must be 2 cycles or more of count source. 1000 500 500 Limits UnitSymbol Parameter Timer A input (external trigger input in one-shot pulse mode) Max.Min. ns ns ns TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width tc(TA) tw(TAH) tw(TAL) 500 250 250 Limits UnitData formula (minimum)Symbol Parameter 4 5 109 f(XIN) Timer A input (external trigger input in pulse width modulation mode) Max.Min. 250 250 TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns tw(TAH) tw(TAL) Limits UnitSymbol Parameter Timer A input (up-down input in event counter mode) Max.Min. tc(UP) tw(UPH) tw(UPL) tsu(UP–TIN) th(TIN–UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time ns ns ns ns ns 5000 2500 2500 1000 1000 Limits UnitParameterSymbol Data formula (minimum) 8 5 109 f(XIN) 4 5 109 f(XIN) 4 5 109 f(XIN)

7702/7703 Group User’s Manual 18–13 Timer A input (Two-phase pulse input in event counter mode) Min. 2000 500 500 Max. Limits UnitParameterSymbol ns ns ns tc(TA) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) TAjIN input cycle time TAjIN input setup time TAjOUT input setup time

7702/7703 Group User’s Manual18–14 l Count input in event counter mode l Gating input in timer mode l External trigger input in one-shot pulse mode l External trigger input in pulse width modulation mode Test conditions

• VCC = 2.7–5.5 V
• Input timing voltage: VIL = 0.2 V, VIH = 0.8 V TAiIN input tc(TA) tw(TAH) tw(TAL) TAiOUT input (Up-down input) tc(UP) tw(UPH) tw(UPL) TAiIN input (Selecting falling count) TAiIN input (Selecting rising count) TAiOUT input (Up-down input) th(TIN–UP) tsu(UP–TIN) tsu(TAjIN–TAjOUT ) TAjIN input TAjOUT input tsu(TAjOUT –TAjIN) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) Internal peripheral devices l Up-down input, count input in event counter mode l Two-phase pulse input in event counter mode tc(TA)

7702/7703 Group User’s Manual 18–15 Timer B input (count input in event counter mode) Min. Max. tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) ns ns ns ns ns ns TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edges count) TBiIN input high-level pulse width (both edges count) TBiIN input low-level pulse width (both edges count) 250 125 125 500 250 250 UnitLimitsSymbol Parameter Timer B input (pulse period measurement mode) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width tc(TB) tw(TBH) tw(TBL) Note: TBiIN input cycle time must be 4 cycles or more of count source, TBiIN input high-level pulse width must be 2 cycles or more of count source, TBiIN input low-level pulse width must be 2 cycles or more of count source. Max.Min. 1000 500 500 ns ns ns Max. Limits UnitData formulaSymbol Parameter 8 5 109 f(XIN) 4 5 109 f(XIN) 4 5 109 f(XIN) Timer B input (pulse width measurement mode) Min. tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Note: TBiIN input cycle time must be 4 cycles or more of count source, TBiIN input high-level pulse width must be 2 cycles or more of count source, TBiIN input low-level pulse width must be 2 cycles or more of count source. Max.Min. 1000 500 500 ns ns ns A-D trigger input Max. tc(AD) tw(ADL) ns ns 2000 250 Limits UnitParameter AD TRG input cycle time (minimum allowable trigger) AD TRG input low-level pulse width Symbol Limits UnitData formula 8 5 109 f(XIN) 4 5 109 f(XIN) 4 5 109 f(XIN) ParameterSymbol

7702/7703 Group User’s Manual18–16 Min. Max. 170 ns ns ns ns ns ns ns CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TxDi output delay time TxDi hold time RxD i input setup time RxD i input hold time tc(CK) tw(CKH) tw(CKL) td(C–Q) th(C–Q) tsu(D–C) th(C–D) 500 250 250 100 Limits UnitParameterSymbol External interrupt INTi input ns ns Min. 250 250 Max. INTi input high-level pulse width INTi input low-level pulse width tw(INH) tw(INL) UnitParameterSymbol Limits

7702/7703 Group User’s Manual 18–17 Internal peripheral devices TBiIN input tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) AD TRG input tw(INL) tw(INH) INTi input tc(CK) tw(CKH) tw(CKL) th(C–Q) tsu(D–C) CLK i input TxD i input RxD i input td(C–Q) th(C–D) Test conditions

• VCC = 2.7–5.5 V
• Input timing voltage
• Output timing voltage : V IL = 0.2 V, VIH = 0.8 V : VOL = 0.8 V, VOH = 2.0 V

7702/7703 Group User’s Manual18–18

18.4.6 Ready and Hold

Timing requirements (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Max.Min. tsu(RDY– φ1) tsu(HOLD– φ1) th(φ1–RDY) th(φ1–HOLD) RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time ns ns ns ns UnitSymbol Parameter Limits Switching characteristics (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Max.Min. ns120HLDA output delay time Note: For test conditions, refer to Figure 18.4.1. td(φ1–HLDA) Limits UnitSymbol Parameter

7702/7703 Group User’s Manual 18–19

• VCC = 2.7–5.5 V
• Input timing voltage: VIL = 0.2 V, VIH = 0.8 V
• Output timing voltage: VOL = 0.8 V, VOH = 2.0 V With no Wait With Wait RDY input l Ready E output E output RDY input tsu(RDY– 1) th( 1–RDY) tsu(RDY– 1) th( 1–RDY)

7702/7703 Group User’s Manual18–20

• VCC = 2.7–5.5 V
• Input timing voltage : VIL = 0.2 V, VIH = 0.8 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V HOLD input HLDA output th( 1–HOLD) td( 1–HLDA) l Hold td( 1–HLDA) tsu(HOLD– 1)

7702/7703 Group User’s Manual 18–21

18.4.7 Single-chip mode

Timing requirements (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tc tw(H) tw(L) tr tf tsu(P0D–E) tsu(P1D–E) tsu(P2D–E) tsu(P3D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P0D) th(E–P1D) th(E–P2D) th(E–P3D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) External clock input cycle time External clock input high-level pulse width External clock input low-level pulse width External clock rise time External clock fall time Port P0 input setup time Port P1 input setup time Port P2 input setup time Port P3 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P0 input hold time Port P1 input hold time Port P2 input hold time Port P3 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time 125 300 300 300 300 300 300 300 300 300 Min. Max. Limits UnitParameterSymbol Switching characteristics (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Max.Min. 300 300 300 300 300 300 300 300 300 ns ns ns ns ns ns ns ns ns t d(E–P0Q) td(E–P1Q) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) Port P0 data output delay time Port P1 data output delay time Port P2 data output delay time Port P3 data output delay time Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time Limits ParameterSymbol Unit Note: For test conditions, refer to Figure 18.4.1.

7702/7703 Group User’s Manual18–22 td(E–P0Q) tsu(P0D–E) th(E–P0D) td(E–P1Q) tsu(P1D–E) th(E–P1D) td(E–P2Q) tsu(P2D–E) th(E–P2D) td(E–P3Q) tsu(P3D–E) th(E–P3D) tW(H)tctrtf E Port P0 output Port P0 input Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input f(XIN) td(E–P4Q) tsu(P4D–E) th(E–P4D) td(E–P5Q) tsu(P5D–E) th(E–P5D) td(E–P6Q) tsu(P6D–E) th(E–P6D) td(E–P7Q) tsu(P7D–E) th(E–P7D) td(E–P8Q) tsu(P8D–E) th(E–P8D) Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input tW(L) Single-chip mode Test conditions

• VCC = 2.7–5.5 V
• Input timing voltage
• Output timing voltage : VIL = 0.2 V, VIH = 0.8 V : VOL = 0.8 V, VOH = 2.0 V

7702/7703 Group User’s Manual 18–23

18.4.8 Memory expansion mode and microprocessor mode : with no Wait

Timing requirements (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) tc tw(H) tw(L) tr tf tsu(P1D–E) tsu(P2D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P1D) th(E–P2D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) External clock input cycle time External clock input high-level pulse width External clock input low-level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P1 input hold time Port P2 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Max.Min. 125 300 300 300 300 300 Limits UnitParameterSymbol ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Switching characteristics (VCC = 2.7–5.5 V, VSS = 0 V, Ta = –40 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) Max.Min. Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time φ1 output delay time_ E low-level pulse width Port P0 address output delay time Port P1 data output delay time (BYTE = “L”) Port P1 floating start delay time (BYTE = “L”) Port P1 address output delay time Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time ALE output delay time ALE pulse width BHE output delay time R/W output delay time td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) td(E–φ1) tw(EL) td(P0A–E) td(E–P1Q) tpxz(E–P1Z) td(P1A–E) td(P1A–ALE) th(E–P2Q) tpxz(E–P2Z) td(P2A–E) th(P2A–ALE) td(ALE–E) tw(ALE) td(BHE–E) td(R/W–E) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: For test conditions, refer to Figure 18.4.1. ] This is the value depending on f(X IN). For data formula, refer to Table 18.4.1. 210 300 300 300 300 300 130 130 Limits Unit ParameterSymbol

7702/7703 Group User’s Manual18–24 Switching characteristics (VCC = 2.7–5.5 V, VSS = 0 V, Ta = –40 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) Max.Min. th(E–P0A) th(ALE–P1A) th(E–P1Q) tpzx(E–P1Z) th(E–P1A) th(ALE–P2A) th(E–P2Q) tpzx(E–P2Z) th(E–BHE) th(E–RW) Port P0 address hold time Port P1 address hold time (BYTE = “L”) Port P1 data hold time (BYTE = “L”) Port P1 floating release delay time (BYTE = “L”) Port P1 address hold time (BYTE = “H”) Port P2 address hold time Port P2 data hold time Port P2 floating release delay time ___ BHE hold time_ R/W hold time ns ns ns ns ns ns ns ns ns ns Notes 1: For test conditions, refer to Figure 18.4.1. ] : This is depending on f(X IN). For data formula, refer to Table 18.4.1. Limits UnitParameterSymbol f(XIN) ≤ 8 MHz 1 5 109 2 5 f(XIN) – 12.5 Symbol Table 18.4.1 Bus timing data formula (Note) (Note) (Note) (Note) (Note) (Note) (Note) E pulse width Port P0 address output delay time Port P1 address output delay time Port P2 address output delay time Port P1 address output delay time Port P2 address output delay time ALE pulse width BHE output delay time R/W output delay time Port P0 address hold time Port P1 address hold time Port P1 data hold time Port P2 data hold time Port P1 floating start delay time Port P2 floating start delay time tw(EL) td(P0A–E) td(P1A–E) td(P2A–E) td(P1A–ALE) td(P2A–ALE) tw(ALE) td(BHE-E) td(R/W-E) th(E–P0A) th(E–P1A) th(E–P1Q) th(E–P2Q) tpzx(E–P1Z) tpzx(E–P2Z) Parameter 2 5 109 f(XIN) – 40 1 5 109 f(XIN) – 12550 + 1 5 109 f(XIN) – 12550 + 1 5 109 f(XIN) – 85 1 5 109 f(XIN) – 65 1 5 109 f(XIN) – 30 1 5 109 2 5 f(XIN) – 12.5 Note: For the M37702E2LXXXGP and the M37702E4LXXXFP, refer to section “19.5.4 Bus timing and EPROM mode.” Unit : ns

7702/7703 Group User’s Manual 18–25 td(P1A – E) tw(L)tw(H) tr tf tc tw(EL) td(E – 1)td(E – 1) th(E – P0A) th(E – P1A) th(E – P1Q)td(E – P1Q) Address Address Data th(E – P2Q)td(E – P2Q) Data Address th(ALE – P1A) th(ALE – P2A) th(E – BHE)td(BHE – E) td(ALE – E) tw(ALE) td(R/W – E) th(E – R/W) td(E – PiQ) f(XIN) Address output A0–A7 BHE output Port Pi output (i = 4–8) Test conditons (P4–P8)

• VCC = 2.7–5.5 V
• Input timing voltage: VIL = 0.2 V, VIH = 0.8 V
• Output timing voltage: VOL = 0.8 V, VOH = 2.0 V E Address output A8–A15 (BYTE = “ H”) Data input D 8–D 15 (BYTE = “ L”) Address/Data output A16/D0–A23/D7 ALE output R/W output Data input D 0–D 7 Address/Data output A8/D8–A15/D15 (BYTE = “ L”) Test conditions (1, E, P0–P3)
• VCC = 2.7–5.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : VIL = 0.16 V, VIH = 0.5 V <Write> Memory expansion mode and microprocessor mode ; With no Wait Address td(P1A – E) td(P0A – E) td(P2A– E) td(P1A – ALE) td(P2A – ALE)

7702/7703 Group User’s Manual18–26 tsu(P1D–E) td(P0A–E) Data td(P1A–E) td(P1A–E) tw(L)tw(H) tr tf tc tw(EL) td(E– 1)td(E– 1) th(E–P0A) th(E–P1A) tpzx(E–P1Z)tpxz(E–P1Z) Address Address Address td(P1A–ALE) th(E–BHE)td(BHE–E) td(ALE–E) tw(ALE) td(R/W–E) th(E–R/W) th(E–P1D) th(ALE–P1A) Data td(P2A–E) tpzx(E–P2Z) th(E–P2D) Address th(E–PiD) tsu(PiD–E) f(XIN) Address output A0–A7 BHE output Test conditions (1, E, P0–P3)

• VCC = 2.7–5.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : VIL = 0.16 V, VIH = 0.5 V Port Pi input (i = 4–8) Test conditions (P4–P8)
• VCC = 2.7–5.5 V
• Input timing voltage : VIL = 0.2 V, VIH = 0.8 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V E Address output A8–A15 (BYTE = “H”) Data input D 8–D 15 (BYTE = “L”) Address/Data Input A16/D0–A23/D7 ALE output R/W output Data input D 0–D 7 Address/Data output A8/D8–A15/D15 (BYTE = “L”) tsu(P2D–E) tpxz(E–P2Z) th(ALE–P2A)td(P2A–ALE) Memory epxansion mode and microprocessor mode ; With no Wait <Read>

7702/7703 Group User’s Manual 18–27

18.4.9 Memory expansion mode and microprocessor mode : with Wait

= 2.7–5.5 V, V SS = 0 V, Ta = –40 to 85 °C, f(X IN ) = 8 MHz, unless otherwise noted) 300 300 300 300 300 t c t w(H) t w(L) t r t f t su(P1D–E) t su(P2D–E) t su(P4D–E) t su(P5D–E) t su(P6D–E) t su(P7D–E) t su(P8D–E) t h(E–P1D) t h(E–P2D) t h(E–P4D) t h(E–P5D) t h(E–P6D) t h(E–P7D) t h(E–P8D) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns External clock input cycle time External clock input high-level pulse width External clock input low-level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P1 input hold time Port P2 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Min. Max. Limits Unit ParameterSymbol Switching characteristics CC = 2.7–5.5 V, V SS = 0 V, Ta = –40 to 85 °C, f(X IN ) = 8 MHz, unless otherwise noted) Min. Max. Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time φ output delay time E low-pulse width Port P0 address output delay time Port P1 data output delay time (BYTE = “L”) Port P1 floating start delay time (BYTE = “L”) Port P1 address output delay time Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time ALE output delay time ALE pulse width ____ BHE output delay time R/W output delay time t d(E–P4Q) t d(E–P5Q) t d(E–P6Q) t d(E–P7Q) t d(E–P8Q) t d(E– φ t w(EL) t d(P0A–E) t d(E–P1Q) t pxz(E–P1Z) t d(P1A–E) t d(P1A–ALE) t d(E–P2Q) t pxz(E–P2Z) t d(P2A–E) t d(P2A–ALE) t d(ALE–E) t w(ALE) t d(BHE–E) t d(R/W–E) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 300 300 300 300 300 130 130 460 Note: For test conditions, refer to Figure 18.4.1. : This is depending on f(X IN ). For data formula, refer to Table 18.4.2. Unit Limits ParameterSymbol

7702/7703 Group User’s Manual18–28 Switching characteristics (VCC = 2.7–5.5 V, VSS = 0 V, Ta = –40 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) Min. Max. ns ns ns ns ns ns ns ns ns ns Port P0 address hold time Port P1 address hold time (BYTE = “L”) Port P1 data hold time (BYTE = “L”) Port P1 floating release delay time (BYTE = “L”) Port P1 address hold time (BYTE = “H”) Port P2 address hold time Port P2 data hold time Port P2 floating release delay time ____ BHE hold time__ R/W hold time th(E–P0A) th(ALE–P1A) th(E–P1Q) tpzx(E–P1Z) th(E–P1A) th(ALE–P2A) th(E–P2Q) tpzx(E–P2Z) th(E–BHE) th(E–R/W) Note: For test conditions, refer to Figure 18.4.1. ] : This is depending on f(XIN). For data formula, refer to Table 18.4.2. LimitsParameterSymbol Unit f(XIN) ≤ 8 MHz 1 5 109 2 5 f(XIN) – 12.5 Symbol Table 18.4.2 Bus timing data formula (Note) (Note) (Note) (Note) (Note) (Note) (Note) E pulse width Port P0 address output delay time Port P1 address output delay time Port P2 address output delay time Port P1 address output delay time Port P2 address output delay time ALE pulse width BHE output delay time R/W output delay time Port P0 address hold time Port P1 address hold time Port P1 data hold time Port P2 data hold time Port P1 floating start delay time Port P2 floating start delay time tw(EL) td(P0A–E) td(P1A–E) td(P2A–E) td(P1A–ALE) td(P2A–ALE) tw(ALE) td(BHE-E) td(R/W-E) th(E–P0A) th(E–P1A) th(E–P1Q) th(E–P2Q) tpzx(E–P1Z) tpzx(E–P2Z) Parameter 4 5 109 f(XIN) – 40 1 5 109 f(XIN) – 12550 + 1 5 109 f(XIN) – 12550 + 1 5 109 f(XIN) – 85 1 5 109 f(XIN) – 65 1 5 109 f(XIN) – 30 1 5 109 2 5 f(XIN) – 12.5 Note: For the M37702E2LXXXGP and the M37702E4LXXXFP, refer to section “19.5.4 Bus timing and EPROM mode.” Unit : ns

7702/7703 Group User’s Manual 18–29 <Write> Memory expansion mode and microprocessor mode ; With Wai t t d(P1A–E) t d(P1A–E) t w(L) t w(H) t r t f t c t w(EL) t d(E– t d(E– t h(E–P0A) t h(E–P1A) t d(P0A–E) t h(E–P1Q) t d(E–P1Q) Address Address Data t h(E–P2Q) t d(E–P2Q) t d(P2A–E) Data Address t h(ALE–P1A) t d(P1A–ALE) t h(ALE–P2A) t d(P2A–ALE) t h(E–BHE) t d(BHE–E) t d(ALE–E) t w(ALE) t d(R/W–E) t h(E–R/W) t d(E–PiQ) Address f(X IN Address output A BHE output Test conditions (P4–P8) CC = 2.7–5.5 V

• Input timing voltage : V IL = 0.2 V, V IH = 0.8 V
• Output timing voltage : V OL = 0.8 V, V OH = 2.0 V E Address output A (BYTE = “H”) Data input D (BYTE = “L”) Address/Data output A ALE output Port Pi output (i = 4–8) R/W output Data input D Address/Data output A (BYTE = “L”) Test conditions ( , E, P0–P3) CC = 2.7 – 5.5 V
• Output timing voltage : V OL = 0.8 V, V OH = 2.0 V
• Data input :V IL = 0.16 V, V IH =0.5 V

7702/7703 Group User’s Manual18–30 <Read> Memory expansion mode and microprocessor mode ; With Wait tsu(P1D–E) td(P0A–E) Data td(P1A–E) td(P1A–E) tw(L)tw(H) tr tf tc tw(EL) td(E– 1)td(E– 1) th(E–P0A) th(E–P1A) tpzx(E–P1Z)tpxz(E–P1Z) Address Address Address td(P1A–ALE) th(E–BHE)td(BHE –E) td(ALE–E) tw(ALE) td(R/W–E) th(E–R/W) th(E–P1D)th(ALE–P1A) td(P2A–E) tpzx(E–P2Z)tpxz(E–P2Z) th(E–P2D)th(ALE–P2A) th(E–PiD) tsu(PiD–E) f(XIN) Address output A0–A7 BHE output Port Pi input (i = 4–8) Test conditons (P4–P8)

• VCC = 2.7–5.5 V
• Input timing voltage : VIL = 0.2 V, VIH = 0.8 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V E Address output A8–A15 (BYTE = “H” ) Data input D 8–D 15 (BYTE = “L” ) Address/Data output A16/D0–A23/D7 ALE output R/W output Data input D 0–D 7 Address/Data output A8/D8–A15/D15 (BYTE = “L” ) Test conditions (1, E, P0–P3)
• VCC = 2.7 – 5.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input : VIL = 0.16 V, VIH = 0.5 V tsu(P2D–E)td(P2A–ALE) Data Address

7702/7703 Group User’s Manual 18–31

18.4.10 Testing circuit for ports P0 to P8, φ 1, and E

Fig. 18.4.1 Testing circuit for ports P0 to P8, φ 1, and E 100 pF E

7702/7703 Group User’s Manual18–32 The data described below are characteristic examples for M37702M2LXXXGP. The data is not guaranteed value. Refer to section “18.4 Electrical characteristics” for rated value.

18.5.1 Port standard characteristics

(1) Programmable I/O port (CMOS output) P channel IOH –VOH characteristics (2) Programmable I/O port (CMOS output) N channel IOL –V OL characteristics 25.0 20.0 15.0 10.0 5.0 VOH [V] IOH [mA] Ta=25°C Ta=85°C 3.0 Ta=–40°C P channel Power source voltage Vcc = 3 V 25.0 20.0 15.0 10.0 5.0 VOL [V] IOL [mA] 3.0 Ta=25°C Ta=85°C Ta=–40°C Power source voltage Vcc = 3 V N channel

7702/7703 Group User’s Manual 18–33 4.0 0 51 0 1 5 Icc [mA] f(XIN) [MHz] 2.0 6.0 At reset Measurement condition (VCC = 3 V, Ta = 25 °C, f(XIN) : square waveform input, microprocessor mode) On operating

18.5.2 ICC –f(XIN) standard characteristics

(1) ICC –f(XIN) characteristics on operating and at reset (2) ICC –f(XIN) characteristics during Wait Icc [mA] 0 51 0 1 5 f(XIN) [MHz] 2.0 1.0 Measurement condition (VCC = 3 V, Ta = 25 °C, f(XIN) : square waveform input, microprocessor mode)

7702/7703 Group User’s Manual18–34

18.5.3 A–D converter standard characteristics

The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in output code from 04 16 to 0516 should occur at 52.7 mV, but the measured value is 2.9 mV. Therefore, the measured point of change is 52.7 + 2.9 = 55.6 mV. The upper lines of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is 0F 16 is 12.4 mV. Therefore, the Measurement condition (VCC = 3 V, f(XIN) = 8 MHz, Temp. = 25 °C )

7702/7703 Group User’s Manual 18–35 Some application examples of connecting external memorys for the low voltage version are described bellow. Applications shown here are just examples. Modify the desired application to suit the user’s need and make sufficient evaluation before actually using it.

18.6.1 Memory expansion

The following items of the low voltage version are the same as those of section “17.1 Memory expansion.” However, a part of the formulas and constants for parameters is different.

• Memory expansion model
• Formulas for address access time of external memory
• Bus timing
• Memory expansion method À Address access time of external memory t a(AD) ta(AD) = td(P0A/P1A/P2A–E) + tw(EL) – tsu(P2D/P1D-E) – (address decode time]1 + address latch delay time] 2) td(P0A/P1A/P2A–E) : td(P0A–E), td(P1A–E), or td(P2A–E) tsu(P2D/P1D–E) : tsu(P2D–E), or tsu(P1D–E) address decode time]1 : time necessary for validating a chip select signal after an address is decoded address latch delay time]2 : delay time necessary for latching an address (This is not necessary on the minimum model.) \` Data setup time of external memory for writing data tsu(D) tsu(D) = tw(EL) – td(E–P2Q/P1Q) td(E–P2Q/P1Q) : td(E–P2Q) , or td(E–P1Q) Table 18.6.1 lists the calculation formulas and constants for each parameter of the low voltage version. Figure 18.6.1 shows the relationship between t a(AD) and f(XIN). Figure 18.6.2 shows the relationship between tsu(D) and f(XIN). Table 18.6.1 Calculation formulas and constants for each parameter (Unit : ns) Parameter td(P0A-E) td(P1A-E) td(P2A-E) tw(EL) tsu(P1D-E) tsu(P2D-E) td(E-P1Q) td(E-P2Q) tpxz(E-P1Z) tpxz(E-P2Z) tpzx(E-P1Z) tpzx(E-P2Z) No wait Wait f(XIN) ≤ 8 MHzf(XIN) 1 5 109 f(XIN)50 + – 125 2 5 109 f(XIN) – 40 4 5 109 f(XIN) – 40 130 1 5 109 f(XIN) – 30 Note: For M37702E2LXXXGP and M37702E4LXXXFP, refer to section “19.5.4 Bus timing and EPROM mode.” (Note) (Note)

7702/7703 Group User’s Manual18–36 Fig. 18.6.1 Relationship between ta(AD) and f(XIN) Fig. 18.6.2 Relationship between tsu(D) and f(XIN) 500 1000 2000 2305 1805 1471 1233 1055 916 805 714 638 574 519 471 430 1305 1005 805 662 555 471 405 350 305 266 233 205 180 [ns] [MHz] Memory access time t a(AD) External clock input frequency f(XIN) No wait Wait ] Address decode time and address latch delay time are not considered. 1500 2500 [MHz] [ns] 200 400 600 800 1200 1400 1600 1800 1830 1430 1163 972 830 718 630 557 496 445 401 363 330 830 630 496 401 330 274 230 193 163 137 115 96 80 2000 Data setup time t su(D) External clock input frequency f(XIN) No wait Wait 1000

7702/7703 Group User’s Manual 18–37 Fig. 18.6.3 Memory expansion example on minimum model

18.6.2 Memory expansion example on minimum model

Figure 18.6.3 shows a memory expansion example on the minimum model (with external RAM) and Figure 18.6.4 shows the corresponding timing diagram. In this example, an Atmel company’s EPROM (AT27LV256R) is used as the external ROM. In Figure 18.6.3, the circuit condition is “No Wait.” 000016 008016 A15 A0–A14 D 0–D 7 AC04 AC32

8 MHz

E BHE Open A0–A14 D 0–D 7 OE M5M5256CFP-10VLL OE RD WR CE S AT27LV256R-15DIAC04 AC32 A0–A14 DQ 1–DQ 8 Vcc = 3.0–3.3 V 800016 FFFF 16 028016 W SFR area Internal RAM area External ROM area (AT27LV256R) Memory map Circuit condition : no Wait Use the elements of which propagation delay time is within 30 ns. Use the elements of which propagation delay time is within 50 ns. External RAM area (M5M5256CFP) ]1, ]2: ]3:

7702/7703 Group User’s Manual18–38 D 0–D 7 A A D S, OE 210 (min.) 50 (min.) 10 (max.) 95 (min.) tsu(P2D-E) ≥ 80 ROM : 25 (max.) RAM : 30 (max.) E AC32 (tPLH )AC32 (tPHL ) E A1–A14 AA D 0–D 7 AA S, W D 210 (min.) tsu(D) ≥ 40AC32 (tPHL ) AC32 (tPLH ) 130 (max.) 50 (min.) A1–A14 A ta(AD) ta(CE)AC04 (tPHL ) CE 50 (min.) A External memory data output <When reading> (Unit : ns) <When writing> ta(S), ta(OE) Fig. 18.6.4 Timing diagram on minimum model

7702/7703 Group User’s Manual 18–39

18.6.3 Memory expansion example on medium model A

Figure 18.6.5 shows a memory expansion example on the medium model A of mask ROM version and PROM version. Figure 18.6.6 shows the corresponding timing diagram. Fig. 18.6.5 Memory expansion example on medium model A A16/D0 –A23/D7 E OpenBHE A0–A16 OE M5M51008AFP-10VLL A0–A15 CNV SS W 00000016 00008016 DQ 1–DQ 8 03FFFF 16 00C000 16 00027F16 Not used Not used00FFFF 16 02000016 D Q LE ALE A16 A17 AC573 D 0–D 7 VCC = 2.7–3.3 V SFR area Internal RAM area Memory map Circuit condition : no Wait ]: Use the elements of which propagation delay time is within 50 ns. External RAM area (M5M51008AFP) Internal ROM area

7702/7703 Group User’s Manual18–40 Fig. 18.6.6 Memory expansion example on medium model A A0–A15 A E, OE, S1 A16/D 0–A23/D 7 A16, A17, S2 AA D 210 (min.) 130 (max.) 50 (min.) tsu(D) ≥ 40 R/W, WE AC573 (tPHL ) A16/D 0–A23/D 7 A D E, OE, S1 210 (min.) 50 (min.) 10 (max.) 95 (min.) ta(OE), ta(S1) tsu(P1D/P2D-E) ≥ 80 ta(S2) AC573 (tPLH ) A0–A15 A A16, A17, S2 AC573 (tPHL ) 35 (max.) 50 (min.) ta(A)+AC573 External memory data output <When reading> (Unit : ns) <When writing> A A A

7702/7703 Group User’s Manual 18–41

18.6.4 Memory expansion example on maximum model

corresponding timing diagram. In this example, Atmel company’s EPROMs (AT27LV256R) are used as the external ROMs. In Figure 18.6.7, the circuit condition is “No Wait.” Fig. 18.6.7 Memory expansion example on maximum model RAM area R/W E BHE AC04 A8–A16 AC573 AC32 RD D0–D7D 8–D 15 WO A1–A15 D 0–D 7 OE A0–A14 CE A1–A15 A0–A14 D0 –D7 OE CE WE AT27LV256R-15DI AC32 DQ LE DQ LE A16/D0 –A17/D1 A1–A16 D0–D7 M5M51008AFP-10VLL A0–A15 DQ 1–DQ 8 OE W A1–A16 D 8–D 15 A0–A15 DQ 1–DQ 8 OE W AC32 03FFFF 16 00000016 00008016 00028016 00FFFF 16 02000016 Not used AC04 S1 S1 A1–A7 A8/D8 –A15/D15 ALE D 2–D 7 A16 A16 A16 Vcc = 3.0–3.3 V S2 S2 ]3 ]2 External ROM area (AT27LV256R 5 2) SFR area Internal External RAM area (M5M51008AFP 5 2) Memory map Data bus (odd) Address bus Data bus (even) Circuit condition : no Wait Use the elements of which propagation delay time is within 30 ns. Use the elements of which propagation delay time is within 50 ns. ]1, ]2 : ]3:

7702/7703 Group User’s Manual18–42 Fig. 18.6.8 Timing diagram on maximum model A1–A7 A E A8/D 8–A15/D 15 A16/D 0, D1–D 7 A D 210 (min.) 130 (max.) 50 (min.) AC32 (tPHL ) tsu(D) 40 (Unit : ns) W AC32 (tPLH ) A8/D 8–A15/D 15 A16/D 0 A D E 210 (min.) 50 (min.) 10 (max.) 95 (min.) ta(AD), ta(CE) tsu(P1D/P2D-E) 80 OE AC 32 (tPLH ) A1–A7 A CE, S1 ta(OE) AC 573 (tPHL ) CE AC32 (tPHL ) ROM : 25 (max.) RAM : 35 (max.) 50 (min.) ta(S1) AC 04 (tPHL ) AC573 (tPHL )+AC04 (tPHL ) External memory data output <When reading> <When writing> A A A A

7702/7703 Group User’s Manual 18–43

18.6.5 Ready generating circuit example

When validating “Wait” only for a certain area (for example, ROM area) in Figures 18.6.3 to 18.6.8, use Ready function. Figure 18.6.9 shows a Ready generating circuit example. Fig. 18.6.9 Ready generating circuit example M37702 A8–A23 (D0–D 15) A0–A7 AC74 D T Q RDY E AC32 AC32 AC04 Address bus E ALE RDY CE CE CS 1Address latch circuit Address decode circuit Data bus RDY signal falling timing Term expanded by RDY input Wait by ready is inserted in only area accessed by CE.

7702/7703 Group User’s Manual18–44

19.1 Overview

19.2 EPROM mode

19.3 1M mode 19.4 256K mode

19.5 Usage precaution

7702/7703 Group User’s Manual19–2 This chapter describes the PROM version including the PROM. The PROM version can be used with the program written into the built-in PROM. Refer to “Chapter 20. 7703 GROUP ” about the pin connections and others. In the PROM version, programming to the built-in PROM can be performed by using a general-purpose PROM programmer and a programming adapter, which is suitable for the used microcomputer. The PROM version has the following two types : l One time PROM version Programming to the PROM can be performed once. This version is suitable for a small quantity of and various productions. l EPROM version Programming to the PROM can be performed repeatedly because a program can be erased by exposing the erase window on the top of the package to an ultraviolet light source. This version can be used only for program development, evaluation only. The built-in PROM version has the same functions as the mask ROM version except that the former has a built-in PROM.

7702/7703 Group User’s Manual 19–3 Table 19.1.1 Write address of PROM version Type name M37702E2BXXXFP M37702E2BXXXHP M37702E2AXXXFP ( Note 1) M37702E2LXXXGP ( Note 1) M37702E2LXXXHP M37702E4BXXXFP M37702E4AXXXFP ( Note 1) M37702E4LXXXFP ( Note 1) M37702E4LXXXGP M37702E6BXXXFP M37702E6LXXXFP M37702E8BXXXFP M37702E8BXXXHP M37702E8LXXXFP M37702E8LXXXHP M37702E2BFS M37702E2AFS ( Note 1) M37702E4BFS M37702E4AFS ( Note 1) M37702E6BFS M37702E8BFS PROM size (Byte) 16K RAM size (Byte) 512 Write address 1M mode 256K mode 1C000 16 to 1FFFF16 400016 to 7FFF16 1C000 16 to 1FFFF16 18000 16 to 1FFFF16 000016 to 7FFF1632K 2048 48K 60K 2048 2048 18000 16 to 1FFFF16 14000 16 to 1FFFF16 11000 16 to 1FFFF16 1C000 16 to 1FFFF16 400016 to 7FFF16 18000 16 to 1FFFF16 000016 to 7FFF16 14000 16 to 1FFFF16 11000 16 to 1FFFF16 16K 32K 48K 60K 512 2048 2048 2048 EPROM version One time PROM version Notes 1: Refer also to section “19.5.4 Bus timing and EPROM mode .” 2: A blank product of the one time PROM version does not have the ROM number, which is printed on the XXX position. For example, M37702E2BFP.

7702/7703 Group User’s Manual PROM VERSION 19–4 The built-in PROM version has the following two modes : l Normal operating mode This mode has the same function as the mask ROM version. l EPROM mode The built-in PROM can be programmed and read in this mode. The PROM version enters this mode when______ “L” level is input to the RESET pin

19.2.1 Write method

There are 2 types of the EPROM mode: 1M mode and 256K mode. 256K mode is recommended to write data deeply for the one time PROM version of which internal PROM size is 32 Kbytes or less. 1M mode is recommended for the EPROM version owing to its write velocity faster than 256K mode. It is because to write and erase is repeated for the EPROM version. However, the M37702E2AFS and M37702E4AFS cannot use 1M mode. Additionally, use 1M mode to write and read in the built-in PROM version of which PROM size is 32 Kbytes or more.

7702/7703 Group User’s Manual 19–5

19.2.2 Pin description

Table 19.2.1 lists the pin description in the EPROM mode. In the normal operating mode, each pin has the same function as the mask ROM version. Functions Apply 5 V ± 10% to pin Vcc, and 0 V to pin Vss. Apply VPP level when programming or verifying. Connect to pin Vss. Connect a ceramic resonator or a quartz-crystal oscillator between pins X IN and XOUT . When an external generated clock is input, the clock must be input to pin X IN, and pin XOUT must be left open. Open. Connect pin AVcc to Vcc and pin AVss to Vss. Connect to pin Vss. Input pins for A 0–A 7 of address. Input pins for A8–A15 of address. Connect P17 to Vcc in 256K mode. I/O pins for data D 0–D 7. Connect to Vss. Connect to Vss. P5 0 functions as PGM input pin in 1M mode. Connect to Vcc in 256K mode. P5 1 functions as OE input pin and P52 does as CE input pin. Connect to Vcc. Connect to Vcc in 1M mode or to Vss in 256K mode. Connect to Vss. Connect to Vss. Connect to Vss. Connect to Vss. Pin Vcc, Vss CNVss BYTE RESET X IN X OUT E AVcc, AVss V REF P0 0–P0 7 P1 0–P1 7 P2 0–P2 7 P3 0–P3 3 P4 0–P4 7 P5 0 P5 1, P5 2 P5 3–P5 5 P5 6 P5 7 P6 0–P6 7 P7 0–P7 7 P8 0–P8 7 Input/Output Input Input Input Output Output Input Input Input I/O Input Input Input Input Input Input Input Name Power source input V PP input Reset input Clock input Clock output Enable output Analog power source input Reference voltage input Address input (A 0–A 7) Address input (A8–A 15) Data input/output (D0–D 7) Input port P3 Input port P4 Control input Input port P5 Input port P6 Input port P7 Input port P8 Table 19.2.1 Pin description in EPROM mode

7702/7703 Group User’s Manual PROM VERSION 19–6 19.3 1M mode 19.3 1M mode 1M mode can perform reading/programming from and to the built-in PROM with the same manner as M5M27C101K. However, there is no device identification code. Accordingly, programming conditions must be set carefully. connections in 1M mode. M5M27C101K Vcc VPP Vss A 0–A 15 D 0–D 7 CE OE PGM Vcc V PP input Vss Address input Data I/O CE input OE input ____ PGM input Table 19.3.1 Pin correspondence with M5M27C101K Vcc CNVss, BYTE Vss P0, P1 P52 P51 P50 M37702E2BXXXFP (M37702E2BFP) M37702E2BFS

7702/7703 Group User’s Manual 19–7 19.3 1M mode 2/RxD 1/CLK P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P41/RDY

64 P84/CTS1/RTS1

63 P85/CLK1

62 P86/RxD1

61 P87/TxD1

60 P00/A0

59 P01/A1

58 P02/A2

57 P03/A3

56 P04/A4

55 P05/A5

54 P06/A6

53 P07/A7

52 P10/A8/D8

51 P11/A9/D9

50 P12/A10/D10

49 P13/A11/D11

48 P14/A12/D12

47 P15/A13/D13

46 P16/A14/D14

45 P17/A15/D15

44 P20/A16/D0

43 P21/A17/D1

42 P22/A18/D2

41 P23/A19/D3

V SS AV SS V REF AV CC V CC 0/CTS 0/RTS 3/TxD 5/A 6/A 0/HOLD BYTE CNV SS RESET X IN X OUT 31 32 V SS 3/HLDA 2/ALE 1/BHE 0/R/W 7/A 4/A M37702E2BXXXFP or M37702E2BFS Outline 80P6N-A ] : Connect an oscillating circuit. A10 A11 A12 A13 A14 D 0 D 1 D 2 D 3 OE CE V PP D D D D VSS : EPROM pins A15 PGM VCC E P70/AN0 P67/TB2IN l 1M mode (top view) Outline 80D0 Fig. 19.3.1 Pin connections in 1M mode (1)

7702/7703 Group User’s Manual PROM VERSION 19–8 19.3 1M mode D 2 A14 Outline 80P6S-A Outline 80P6D-A P86/RXD 1 P87/TXD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 75 74 73 72 71 69 68 67 66 657080 79 78 77 76 64 63 62 61 3026 27 28 29 31 32 33 34 35 3621 2322 24 25 37 38 39 40 1/RDY 0/HOLDBYTECNV SS RESET X IN X OUT E V SS 3/HLDAP3 2/ALE 1/BHE 0/R/W 7/A 6/A 5/A 4/A P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 5/CLK 4/CTS 1/RTS 3/T XD 2/R XD 1/CLK 0/CTS 0/RTS V CC AV CC V REF AV SS V SS 7/AN 7/AD TRG 6/AN 5/AN 4/AN 3/AN 2/AN 1/AN 0/AN 7/TB2 IN M37702E2LXXXGP or M37702E2LXXXHP P43 P44 P45 P46 3/A 2/A VCC A15 A13 A12 A10 A11 D 0 D 1 D 7 D 6 D 5 D 4 D 3 VPP VSS CE PGM OE l 1M mode (top view) ] : Connect an oscillating circuit. : EPROM pins Fig. 19.3.2 Pin connections in 1M mode (2)

7702/7703 Group User’s Manual 19–9

19.3.1 Read/Program/Erase

Table 19.3.2 lists the built-in PROM state in 1M mode and each mode is described bellow. When pins CE and OE are set to “L” level and an address is input to address input pins, the contents of the built-in PROM can be output from data I/O pins and read.___ ___ When pins CE and OE are set to “H” level, data I/O pins enter the floating state. When pin CE is set to “L” level and pin OE is set to “H” level and VPP level is applied to pin VPP , programming to the built-in PROM becomes possible. Input an address to address input pins and supply data to be programmed to data I/O pins in 8-bit ____ parallel. In this condition, when pin PGM is set to “L” level, the data is programmed at the specified address, input address, into the built-in PROM. (3) Erase (Possible only in EPROM version) The contents of the built-in PROM is erased by exposing the glass window on top of the package to an ultraviolet light which has a wave length of 2537 Angstrom. The light must be 15 J/cm 2 or more. 19.3 1M mode Table 19.3.2 Built-in PROM state in 1M mode Pin name Data I/O Output Floating Floating Input Output Floating V IL V IL V IH V IL V IL V IH VIL V IH V IH VIL V IH V IL VIH VIH 5 V 5 V 5 V 12.5 V 12.5 V 12.5 V VccV PPPGMCE 5 V 5 V 5 V 6 V 6 V 6 V OE Mode Read-out Output disable Program Program verify Program disable 5 : It may be VIL or VIH.

7702/7703 Group User’s Manual PROM VERSION 19–10

19.3.2 Programming algorithm of 1M mode

Figure 19.3.3 shows the programming algorithm flow chart of 1M mode. À Set Vcc = 6 V, VPP = 12.5 V, and address to 1C00016]. \` After applying a programming pulse of 0.2 ms, check whether data can be read or not. ´ If the data cannot be read, apply a programming pulse of 0.2 ms again. ˆ Repeat the procedure, which consists of applying a programming pulse of 0.2 ms and read check, until the data can be read. Additionally, record the number of applied pulses ( χ) before the data has been read. ˜ Apply χ pulses (0.2 5 χ ms) (described in ˆ ) as additional programming pulses. ¯ When this procedure ( À to ˜ ) is completed, increment the address and repeat the above procedure until the last address is reached. ˘ After programming to the last address, read data when Vcc = VPP = 5 V (or Vcc = VPP = 5.5 V). ] : This applies to the M37702E2BFS. Refer to Table 19.1.1 about each write address of other products. 19.3 1M mode Fig. 19.3.3 Programming algorithm flow chart of 1M mode VERIFY ALL BYTE START ADDR = FIRST LOCATION = 0 VCC = VPP = 5.0 V] DEVICE FAILED DEVICE PASSED VCC = 6.0 V VPP = 12.5 V = + 1 = 25? VERIFY BYTE INCREMENT ADDR VERIFY BYTE DEVICE FAILED LAST ADDR? FAIL YES NO PASS PASS YES FAIL PASS NO FAIL PROGRAM ONE PULSE OF 0.2 ms PROGRAM PULSE OF 0.2 5 ms DURATION ] : 4.5 V ≤ VCC = VPP ≤ 5.5 V

7702/7703 Group User’s Manual 19–11 AC electrical characteristics (Ta = 25 ± 5 °C, Vcc = 6 V ± 0.25 V, VPP = 12.5 ± 0.3 V, unless otherwise noted)

19.3.3 Electrical characteristics of programming algorithm in 1M mode

Max. 130 0.21 5.25 150 Typ. 0.2 Min. Limits UnitParameter µs µs µs µs µs ns µs µs ms ms µs ns Address setup time OE setup time Data setup time Address hold time Data hold time ___ Output floating delay time after OE Vcc setup time V PP setup time ____ PGM pulse width ____ Additional PGM pulse width ___ CE setup time ___ Data delay time after OE tAS tOES tDS tAH tDH tDFP tVCS tVPS tPW tOPW tCES tOE Symbol 0.19 0.19 19.3 1M mode Switching characteristics measuring conditions l Input voltage : VIL = 0.45 V, VIH = 2.4 V l Input signal rise/fall time (10%–90%) : ≤ 20 ns l Reference voltage in timing measurement : Input/output “L” = 0.8 V, “H” = 2 V tVCS tVPS tDS tDH tDFP tAS tAH VerifyProgram Data set Data output valid VIH VIL VIH/VOH VIL/VOL VPP VCC VCC + 1 VCC Address Data VPP VCC tOES tOE tOPW tPW VIH VIL VIH VIL PGM OE VIH VIL tCES CE Programming timing diagram

7702/7703 Group User’s Manual PROM VERSION 19–12 19.4 256K mode 19.4 256K mode 256K mode can perform reading/programming from and to the built-in PROM with the same manner as M5M27C256K. However, there is no device identification code. Accordingly, programming conditions must be set carefully. connections in 256K mode. M5M27C256K Vcc VPP Vss A 0–A 14 D 0–D 7 CE OE Vcc V PP input Vss Address input Data I/O CE OE Table 19.4.1 Pin correspondence with M5M27C256K Vcc CNVss, BYTE Vss P0, P1 P52 P51 M37702E2BXXXFP (M37702E2BFP) M37702EHBFS

7702/7703 Group User’s Manual 19–13 19.4 256K mode 25 2726 28 34 29 30 31 32 33 35 36 37 38 39 40 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT 0/HOLDBYTECNV SS RESET X IN X OUT E V SS 3/HLDA 2/ALE 1/BHE 0/R/W 7/A 6/A 5/A 4/A 1/AN 2/AN 3/AN 4/AN 5/AN 6/AN 7/AN 7/AD TRG V SS AV SS V REF AV CC V CC 0/CTS 0/RTS 1/CLK 2/R XD 3/T XD P84/CTS1/RTS1 P85/CLK1 P86/RXD 1 P87/TXD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 80 79 78 77 76 75 74 73 72 71 69 68 67 66 6570 Outline 80P6N-A P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 P22/A18/D2 P23/A19/D3 M37702E2BXXXFP P41/RDY P47 P46 P45 P44 P43 P42/ 1 A10 A11 A12 A13 A14 D 0 D 1 D 2 D 3 V PP D D D D V SS Vcc CE OE l 256K mode (top view) ] : Connect an oscillating circuit. : EPROM pins Fig. 19.4.1 Pin connections in 256K mode (1)

7702/7703 Group User’s Manual PROM VERSION 19–14 19.4 256K mode D 2 A14 Outline 80P6S-A Outline 80P6D-A P86/RXD 1 P87/TXD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 75 74 73 72 71 69 68 67 66 657080 79 78 77 76 64 63 62 61 3026 27 28 29 31 32 33 34 35 3621 2322 24 25 37 38 39 40 1/RDY 0/HOLDBYTECNV SS RESET X IN X OUT E V SS 3/HLDAP3 2/ALE 1/BHE 0/R/W 7/A 6/A 5/A 4/A P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 5/CLK 4/CTS 1/RTS 3/T XD 2/R XD 1/CLK 0/CTS 0/RTS V CC AV CC V REF AV SS V SS 7/AN 7/AD TRG 6/AN 5/AN 4/AN 3/AN 2/AN 1/AN 0/AN 7/TB2 IN M37702E2LXXXGP or M37702E2LXXXHP P43 P44 P45 P46 3/A 2/A VCC A13 A12 A10 A11 D 0 D 1 D 7 D 6 D 5 D 4 D 3 VPP VSS CE OE ] : Connect an oscillating circuit. : EPROM pins l 256K mode (top view) Fig. 19.4.2 Pin connections in 256K mode (2)

7702/7703 Group User’s Manual 19–15

19.4.1 Read/Program/Erase

Table 19.4.2 lists the built-in PROM state in 256K mode and each mode is described bellow. When pins CE and OE are set to “L” level and an address is input to address input pins, the contents of the built-in PROM can be output from data I/O pins and read.___ ___ When pins CE and OE are set to “H” level, data I/O pins enter the floating state. (2) Program (Write) ___ When pin OE is set to “H” level and VPP level is applied to pin VPP , programming to the built-in PROM becomes possible. Input an address to address input pins and supply data to be programmed to data I/O pins in 8-bit___ parallel. In this condition, when pin CE is set to “L” level, the data is programmed at the specified address, input address, into the built-in PROM. (3) Erase (Possible only in EPROM version) The contents of the built-in PROM is erased by exposing the glass window on top of the package to an ultraviolet light which has a wave length of 2537 Angstrom. The light must be 15 J/cm 2 or more. 19.4 256K mode Table 19.4.2 Built-in PROM state in 256K mode Pin name Data I/O CE 5 V 5 V 5 V 6 V 6 V 6 V Mode Read-out Output disable Program Program verify Program disable 5 : It may be V IL or VIH. V IL V IL V IH V IL V IH V IH OE VPP 5 V 5 V 5 V 12.5 V 12.5 V 12.5 V V IL VIH VIH V IL VIH Vcc Output Floating Floating Input Output Floating

7702/7703 Group User’s Manual PROM VERSION 19–16

19.4.2 Programming algorithm of 256K mode

Figure 19.4.3 shows the programming algorithm flow chart of 256K mode. À Set Vcc = 6 V, VPP = 12.5 V, and address to 400016]. \` After applying a programming pulse of 1 ms, check whether data can be read or not. ´ If the data cannot be read, apply a programming pulse of 1 ms again. ˆ Repeat the procedure, which consists of applying a programming pulse of 1 ms and read check, until the data can be read. Additionally, record the number of pulses applied ( χ) before the data has been read. ˜ Apply three times as many numbers as χ pulses (described in ˆ ), that is, 3 5 χ ms as additional programming pulses. ¯ When this procedure ( À to ˜ ) is completed, increment the address and repeat the above procedure until the last address is reached. ˘ After programming to the last address, read data when Vcc = VPP = 5 V (or Vcc = VPP = 5.5 V). ] : This applies to the M37702E2BXXXFP. Refer to Table 19.1.1 about each write address of other products. 19.4 256K mode VERIFY ALL BYTE START ADDR = FIRST LOCATION = 0 VCC = VPP = 5.0 V] DEVICE FAILED DEVICE PASSED VCC = 6.0 V VPP = 12.5 V = + 1 = 25? VERIFY BYTE INCREMENT ADDR VERIFY BYTE DEVICE FAILED LAST ADDR? FAIL YES NO PASS PASS YES FAIL PASS NO FAIL PROGRAM ONE PULSE OF 1 ms PROGRAM PULSE OF 3 5 ms DURATION ] : 4.5 V ≤ VCC = VPP ≤ 5.5 V Fig. 19.4.3 Programming algorithm flow chart of 256K mode

7702/7703 Group User’s Manual 19–17 AC electrical characteristics (Ta = 25 ± 5 °C, Vcc = 6 V ± 0.25 V, VPP = 12.5 ± 0.3 V, unless otherwise noted)

19.4.3 Electrical characteristics of programming algorithm in 256K mode

Max. 130 1.05 78.75 150 Typ. Min. Limits UnitParameter µs µs µs µs µs ns µs µs ms ms ns Address setup time OE setup time Data setup time Address hold time Data hold time ___ Output floating delay time after OE Vcc setup time V PP setup time CE initial program pulse width Additional CE pulse width ___ Data delay time after OE Symbol 0.95 2.85 19.4 256K mode tAS tOES tDS tAH tDH tDFP tVCS tVPS tFPW tOPW tOE tVCS tVPS tDS tDH tOES tOE tDFP tAS tOPW tFPW tAH VIH VIL VIH/VOH VIL/VOL VPP VCC VCC +1 VCC VIH VIL VIH VIL CE OE VPP VCC VerifyProgram Data set Data output valid Address Data Programming timing diagram

7702/7703 Group User’s Manual PROM VERSION 19–18 The usage precaution of PROM version is described bellow.

19.5.1 Precautions on all PROM versions

When programming to the built-in PROM, high voltage is required. Accordingly, be careful not to apply excessive voltage to the microcomputer. Furthermore, be especially careful during power-on.

19.5.2 Precautions on One time PROM version

One time PROM versions shipped in a blank, of which built-in PROMs are programmed by users, are also provided. For these microcomputers, a programming test and screening are not performed in the assembly process and the following processes. To improve their reliability after programming, we recommend to program and test as the flow shown in Figure 19.5.1 before use. Fig. 19.5.1 Programming and test flow for One Time PROM version Programming with PROM programmer Screening (Note) (Leave at 150 °C for 40 hours) Verify test with PROM programmer Function check in target device Note: Never expose to 150 °C exceeding 100 hours.

19.5.3 Precautions on EPROM version

(1) Cover transparent glass window Cover the transparent glass window with a shield or others during the read mode because exposing to sun light or fluorescent lamp can cause erasing the programmed data. A shield to cover the transparent window is available from Mitsubishi Electric Corporation. Be careful that the shield does not touch the EPROM lead pins. (2) Erase Clean the transparent glass before erasing. There is a possibility that fingers’ fat and paste disturb the passage of ultraviolet rays and affect badly the erasure capability. (3) Usage The EPROM version is a tool only for program development, evaluation only, and do not use it for the mass product run.

7702/7703 Group User’s Manual 19–19

19.5.4 Bus timing and EPROM mode

The PROM versions shown in Tables 19.5.1 and 19.5.2 have the different bus timing from other PROM versions, mask ROM, external ROM versions. Additionally, they can use 256K mode as EPROM mode though its PROM size is 32 Kbytes or less. Table 19.5.1 PROM versions having peculiar bus timing (16MHz version) Bus timing Type name M37702E2AXXXFP M37702E2AFS M37702E4AXXXFP M37702E4AFS t pzx(E – P1Z), tpzx(E – P2Z) f(XIN) ≤ 8 MHz 8MHz < f(X IN) ≤ 16 MHz Limits: 50 ns Limits: 25 ns Formulas: Formulas: – 6.25 1 5 109 2 5 f(XIN) – 12.5 1 5 109 2 5 f(XIN) Table 19.5.2 PROM versions having peculiar bus timing (Low voltage version) (1) Bus timing The limits and formulas of the PROM versions having the peculiar bus timing which is different from When the user is planning to use the product shown in Tables 19.5.1 and 19.5.2 for evaluation or in early production and replace it later with the mask ROM version, we recommend to use the substitute shown in Table 19.5.3 for evaluation or in early production. However, the substitute for the low voltage version has the larger ROM and RAM size. Make sure of its memory usage. The substitute for the 16 MHz version has the higher frequency of external clock input. There are no precaution about its operation. Type name M37702E2LXXXGP M37702E4LXXXFP 1 5 109 2 5 f(XIN) – 12.5 1 5 109 2 5 f(XIN)50 + – 62.5 tpzx(E – P1Z), tpzx(E – P2Z) td(P0A – E), td(P1A – E), td(P2A – E), td(BHE – E), td(R/W – E) Limits: 50 ns Limits: 50 ns Formulas: Formulas: Bus timing Table 19.5.3 Substitutes Type name to be used Substitute Remark M37702E2AXXXFP M37702E2BXXXFP The substitute has the higher frequency of external clock input. M37702E2AFS M37702E2BFS M37702E4AXXXFP M37702E4BXXXFP M37702E4AFS M37702E4BFS M37702E2LXXXGP M37702E4LXXXGP The substitute has the larger ROM and RAM size. M37702E4LXXXFP M37702E6LXXXFP (2) EPROM mode The products shown in Table 19.5.1 can use only 256K mode as the EPROM mode. Do not use 1M mode.

7702/7703 Group User’s Manual PROM VERSION 19–20

20.1 Description

20.2 Performance overview

20.3 Pin configuration

20.4 Functional description

20.5 Electrical characteristics

20.6 PROM version

7702/7703 Group User’s Manual20–2 This chapter describes the 7703 Group. The 7703 Group has the same functions as the 7702 Group except for some functions. This chapter mainly describes the differences between the 7703 and 7702 Groups. Refer to the relevant descriptions of the 7702 Group about the common functions. The 16-bit single-chip microcomputers 7703 Group is suitable for office, business, and industrial equipment controllers that require high-speed processing. These microcomputers develop with the M37703M2BXXXSP as the base chip. This manual describes the functions about the M37703M2BXXXSP unless there is a specific difference and the M37703M2BXXXXSP is referred to as “M37703.”

7702/7703 Group User’s Manual 20–3 Functions 103 160 ns (the minimum instruction at f(XIN) = 25 MHz) 250 ns (the minimum instruction at f(XIN) = 16 MHz) 16 bits 5 5; With I/O function5 4 16 bits 5 3; With Input function5 1 UART 5 2 (UART0 also as clock synchronous serial I/O) 8-bit successive approximation method 5 1 (4 channels) 12 bits 5 1 3 external, 16 internal (priority levels 0 to 7 can be set for each interrupt with software) Built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 95 mW (at f(XIN) = 25 MHz frequency, typ.) 5 V 5 mA Maximum 16 Mbytes –20°C to 85°C CMOS high-performance silicon gate process 80-pin plastic molded SDIP Table 20.2.1 lists the performance overview of the M37703. Table 20.2.1 M37703 performance overview Parameters Number of basic instructions Instruction execution time External clock input frequency f(XIN) Memory size Programmable Input/Output ports Multifunction timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation Port Input/Output characteristics Memory expansion Operating temperature range Device structure Package M37703M2BXXXSP M37703M2AXXXSP M37703M2BXXXSP M37703M2AXXXSP ROM RAM P0, P1, P2, P5 P4, P6, P7 TA0–TA4 TB0–TB2 UART0, UART1 Input/Output withstand voltage Output current

7702/7703 Group User’s Manual20–4 Figure 20.3.1 shows the M37703M2BXXXSP pin configuration. E VCC P10/A8/D8 P81/CLK0 P80/CTS0/RTS0 P00/A0 P82/RXD 0 P83/TXD 0 P86/RXD 1 P87/TXD 1 P02/A2 P01/A1 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P20/A16/D0 P12/A10/D10 P11/A9/D9 P13/A11/D11 P14/A12D 12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P30/R/W P22/A18/D2 P21/A17/D1 P23/A19/D3 P24/A20/D4 P25/A21/D5 P26/A22/D6 P27/A23/D7 Outline 64P4B M37703M2BXXXSP 22Fig. 20.3.1 M37703M2BXXXSP pin configuration (top view)

7702/7703 Group User’s Manual 20–5 The M37703 has the same internal circuit as the M37702. The control registers in the SFR area and the memory assignment are also the same. However, part of the M37703 functions varies from the M37702’s, because the number of M37703’s pins is 64 pins. Table 20.4.1 lists the differences between the M37703 and M37702. This paragraph describes the differences from the M37702. Refer to the relevant functional descriptions of the M37702 about others. Table 20.4.1 Differences between the M37703 and M37702 Parameters Programmable I/O port Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Port P8 Timer TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 Serial I/O UART0 UART1 A-D converter Package 53 (In single-chip mode) 8 bits 8 bits 8 bits 3 bits; Without P33/HLDA pin 4 bits; Without P43 to P46 pins 8 bits 4 bits; Without P6 0, P61, P66, and P67 pins 4 bits; Without P73 to P76 pins 6 bits; Without P84 and P85 pins 16 bits 5 8 With timer I/O pins: Input pin (TAiIN); Output pin (TAiOUT ) (i = 0 to 3) Internal timer; Without I/O pins With timer input pin (TB0 IN) Internal timer; Without I/O pins Clock synchronous or Clock asynchronous Clock asynchronous Resolution 8 bits 5 1 Analog input pin 4 channels: AN 0, AN1, AN2, AN 7 pins; Without AN3 to AN6 pins) 64-pin plastic molded SDIP; 64P4B M37702M2BXXXFP 68 (In single-chip mode) 8 bits 8 bits 8 bits 4 bits 8 bits 8 bits 8 bits 8 bits 8 bits 16 bits 5 8 With timer I/O pins: Input pin (TAj IN); Output pin (TAjOUT ) (j = 0 to 4) With timer input pins: Input pin (TBkIN) (k = 0 to 2) Clock synchronous or Clock asynchronous Clock synchronous or Clock asynchronous Resolution 8 bits 5 1 Analog input pin 8 channels: AN 0 to AN7 pins 80-pin plastic molded QFP; 80P6N-A

7702/7703 Group User’s Manual20–6

20.4.1 I/O pin

The M37703 does not have the following pins of the M37702:

• Port P33
• Ports P43 to P46
• Ports P60, P61, P66, P67
• Ports P73 to P76
• Ports P84, P85 (1) Port direction register Fix the bits of port Pi (i = 3, 4, 6, 7, 8) direction register which do not have the corresponding pins to “1.” All products of the M37703 need this procedure. Do it regardless of the product type and the used mode. All bits of port Pi direction register are cleared to “0” after reset. Accordingly, follow the procedure shown by Figure 20.4.1 in the initial setting program after reset. Do not write “0” after that to the bits to be fixed to “1.” Paragraph “1.3.1 Example for processing unused pins” explains the examples when there are pins, however, those pins are not used. The above explanation is independent of that example explanation. (2) Memory expansion and Microprocessor modes The M37703 does not have the HLDA pin, so that the HLDA signal cannot be used in those modes. b1 b0b2b3b4b5b6b7 1111 11 11 1111 l Be sure to set “1” to the bit indicated by using “1”. Though these bits do not have the corresponding pins, follow the above procedure. The above procedure is necessary whether or not other programmable I/O ports are used. Port P3 direction register (address 916) Port P4 direction register (address C16) Port P6 direction register (address 1016) Port P7 direction register (address 1116) Port P8 direction register (address 1416) Notes 1: When executing the instruction to write to bits 4 to 7 of Port P3 direction register, the value cannot be written into them. When reading to those bits, “0” is read. 2: The bits which are not indicated by using “1” and bits 4 to 7 of Port P3 direction register function as a programmable I/O port. Just as in ports P0–P2 and P5, set “0” when using as an input port, and set “1” when using as an output port. Fig. 20.4.1 Procedure of port Pi (i = 3, 4, 6, 7, 8) direction register

7702/7703 Group User’s Manual 20–7

20.4.2 Timer A

The M37703 does not have the I/O functions of Timer A4. It can be used only in the timer mode. Fix bits 5 to 0 of the timer A4 mode register to “000000 Figure 20.4.2 shows the structure of the timer A4 mode register. Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer A4 mode register (Addresses 5A 0 0 : f 0 1 : f 1 0 : f 1 1 : f 512 Count source select bits Bit At reset RW 5 to 0 RW RW RW Fix these bits to “0”. In timer mode, without pulse output and gate functions. 0 000 Fig. 20.4.2 Structure of timer A4 mode register

20.4.3 Timer B

The M37703 does not have the input functions of Timers B1 and B2. They can be used only in the timer mode. Fix bits 1 and 0 of the timer B1 and B2 mode registers to “00 Figure 20.4.3 shows the structure of the timer B1 and B2 mode registers. b7 b6 b5 b4 b3 b2 b1 b0 Bit This bit is ignored in timer mode. Nothing is assigned. Bit name Count source select bits Functions At reset RW These bits are ignored in timer mode. RW RW RW RW Timer B1 mode register (Addresses 5C Timer B2 mode register (Addresses 5D Undefined Undefined 0 0 : f 0 1 : f 1 0 : f 1 1 : f 512 b7 b6 RW RW Fix these bits to “0”. In timer mode. Fig. 20.4.3 Structure of timer B1 and B2 mode registers

7702/7703 Group User’s Manual20–8

20.4.4 Serial I/O

The M37703’s UART1 can be used only in the clock asynchronous serial I/O mode, UART mode. It cannot be used in the clock synchronous serial I/O mode. Do not set the serial I/O mode select bits (bits 2 to 0 at address 38 16) to “0012” to select the clock synchronous serial I/O mode. Figure 20.4.4 shows the structure of the UART1 transmit/receive mode register. (1) CLK1 pin The M37703 does not have the CLK1 pin. Set the internal/external clock select bit (bit 3 at address 3816) to “0” to select the internal clock. Fig. 20.4.4 Structure of UART1 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Bit Bit name At reset RWFunctions b2 b1 b0 RW RW RW RW RW RW RW RW Serial I/O mode select bits 0 0 0: Serial I/O disabled (P8 functions as a programmable I/O port.) 0 0 1: Not selected 0 1 0: Not selected 0 1 1: Not selected 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Not selected Sleep select bit (Valid in UART mode) (Note) Parity enable bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit is “1”) (Note) Stop bit length select bit (Valid in UART mode) (Note) UART1 transmit/receive mode register (Address 3816) Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode cleared (ignored) 1 : Sleep mode selected 0 : One stop bit 1 : Two stop bits Fix these bits to “0”. (To select internal clock.)

7702/7703 Group User’s Manual 20–9 The M37703 does not have the CTS1/RTS 1 pin. Fix the CTS/RTS select bit (bit 2 at address 3C16) to “1”. Figure 20.4.5 shows the structure of the UART1 transmit/receive control register 0 and Figure 20.4.6 shows the structure of the port P8 direction register when using UART1. Fix this bit to “1.” Bit BRG count source select bits Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 UART1 transmit/receive control register 0 (Address 3C16) b1 b0 Transmit register empty flag0 : Data present in transmit register. (During transmitting) 1 : No data present in transmit register. (Transmitting completed) 7 to 4 RW RW RO3 RW Nothing is assigned. Undefined – Fig. 20.4.5 Structure of UART1 transmit/receive control register 0 Fig. 20.4.6 Structure of port P8 direction register when using UART1 Bit Corresponding pin Functions CTS 0/RTS 0 pin RxD 0 pin TxD 0 pin RxD 1 pin 0 : Input mode 1 : Output mode When using pin P82 as serial data input pin (RxD0),set bit 2 to “0.” Port P8 direction register (Address 1416) b1 b0b2b3b4b5b6b7 CLK 0 pin TxD 1 pin At reset RW RW RW RW RW RW RW RW RW When using pin P86 as serial data input pin (RxD1),set bit 6 to “0.” Fix these bits to “1.” : Bits 0 to 3 are not used in UART1.

7702/7703 Group User’s Manual20–10

20.4.5 A-D converter

The M37703’s analog inputs are 4 channels: AN0 to AN2 and AN 7. (1) One-shot and Repeat modes Set the analog input select bits (bits 2 to 0 at address 1E16) to one of “0002”, “0012”, “0102” and “1112.” Set the bits of the port P7 direction register which do not have pins corresponding to analog inputs AN 3 to AN6 to “1” to make them output mode. Figure 20.4.7 shows the structure of the A-D control register and Figure 20.4.8 shows the structure of the port P7 direction register when using A-D converter. (2) Single sweep and Repeat sweep modes Set the bits of the port P7 direction register corresponding to AN0 to AN2 and AN7 pins to “0” to make them input mode. Set the bits of the port P7 direction register which do not have pins corresponding to analog inputs AN 3 to AN6 to “1” to make them output mode. The A-D register contents corresponding to analog inputs AN3 to AN6, which do not have their pins, become undefined. Fig. 20.4.7 Structure of A-D control register b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (Address 1E16) Bit A-D conversion frequency ( AD ) select bit A-D conversion start bit Trigger select bit A-D operation mode select bits Bit name At reset Undefined RWFunctions 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : Not selected 1 0 0 : Not selected 1 0 1 : Not selected 1 1 0 : Not selected 1 1 1 : AN 7 selected (Note 2) b2 b1 b0 0 : Internal trigger 1 : External trigger 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 : Stop A-D conversion 1 : Start A-D conversion b4 b3 Notes 1: These bits are ignored in the single sweep and repeat sweep modes. (They may be either “0” or “1.”) 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit except bit 6 of the A-D control register must be performed while the A-D converter halts. Analog input select bits (Valid in one-shot and repeat modes) (Note 1) Undefined Undefined RW RW RW RW RW RW RW RW 0 : f2 divided by 4 1 : f2 divided by 2

7702/7703 Group User’s Manual 20–11 Fig. 20.4.8 Structure of the port P7 direction register when using A-D converter Bit Corresponding bit name Functions AN 0 pin AN 2 pin 0: Input mode 1: Output mode Port P7 direction register (Address 1116) b1 b0b2b3b4b5b6b7 AN 1 pin At reset When using these pins as A-D converter’s input pins, set the corresponding bits to “0.”

7 AN 7 pin/ADTRG pin

When using this pin as A-D converter’s input pin or external trigger input pin, set this bit to “0.” 0: Input mode 1: Output mode 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 111 1 Fix these bits to “1.”

7702/7703 Group User’s Manual20–12 The M37703 electrical characteristics is the same as the M37702’s except for the absolute maximum ratings shown in Table 20.5.1 and the parameters of not existing pins of the M37703. Refer to “Chapter 15. ELECTRICAL CHARACTERISTICS .” Additionally, the M37703 standard characteristics is the same as the M37702’s and refer to “Chapter 16. STANDARD CHARACTERISTICS .” Table 20.5.1 Absolute maximum ratings Symbol Parameter Conditions Ratings Unit P d Power dissipation Ta = 25 °C 1000 mW Note: The electrical characteristics except above is the same as the M37702’s.

7702/7703 Group User’s Manual 20–13 Type name M37703E2BXXXSP M37703E2AXXXSP ( Note 1) M37703E4BXXXSP M37703E4AXXXSP ( Note 1) In the PROM version, programming to the built-in PROM can be performed by using a general-purpose PROM programmer and a programming adapter, which is suitable for the used microcomputer. The PROM version of M37703 is the one time PROM version. Programming to the PROM can be performed once in this version. The one time PROM version has the same functions as the mask ROM version except that the former has a built-in PROM. Table 20.6.1 lists the write address of PROM version. The M37703 does not have the EPROM version. Use the EPROM version of M37702 with a pitch converter for the M37703 evaluation. Table 20.6.1 Write address of PROM version PROM size (Byte) 16K RAM size (Byte) 512 Write address 1M mode 256K mode 1C000 16 to 1FFFF16 400016 to 7FFF16 32K 2048 18000 16 to 1FFFF16 000016 to 7FFF16 Notes 1: Refer also to section “20.6.2 Bus timing and EPROM mode .” 2: A blank product of the one time PROM version does not have the ROM number, which is printed on the XXX position. For example, M37703E2BSP.

20.6.1 EPROM mode

The EPROM mode of M37703 is the same as the M37702’s. Refer to section “19.2 EPROM mode .” The pin connections vary from the M37702’s. Figure 20.6.1 shows the pin connections in EPROM mode.

7702/7703 Group User’s Manual20–14 Fig. 20.6.1 Pin connections in EPROM mode AV CC VREF P71/AN1 AV SS P72/AN2 P77/AN7/ADTRG P70/AN0 P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P57/TA3IN P56/TA3OUT P55/TA2IN P52/TA1OUT P54/TA2OUT P53/TA1IN P51/TA0IN P50/TA0OUT P47 P42/ 1 P41/RDY P40/HOLD BYTE CNV SS RESET XIN XOUT P32/ALE VSS P31/BHE E VCC P10/A8/D8 P81/CLK0 P80/CTS0/RTS0 P00/A0 P82/RXD 0 P83/TXD 0 P86/RXD 1 P87/TXD 1 P02/A2 P01/A1 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P20/A16/D0 P12/A10/D10 P11/A9/D9 P13/A11/D11 P14/A12D 12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P30/R/W P22/A18/D2 P21/A17/D1 P23/A19/D3 P24/A20/D4 P25/A21/D5 P26/A22/D6 P27/A23/D7 Outline 64P4B M37703E2BXXXSP A10 A11 A12 A13 A14 A15 D 0 D 1 D 2 D 4 D 5 D 6 D 7 D 3 CE OE VPP PGM Vss Vcc Equivalent to M5M27C256K Equivalent to M5M27C101K Equivalent to M5M27C256K Equivalent to M5M27C101K Equivalent to M5M27C256K Equivalent to M5M27C101K ] : Connect an oscillating circuit. : EPROM pins

7702/7703 Group User’s Manual 20–15

20.6.2 Bus timing and EPROM mode

The PROM versions shown in Table 20.6.2 have the different bus timing from other PROM versions, mask ROM, external ROM versions. Additionally, they can use only 256K mode as the EPROM mode though its PROM size is 32 Kbytes or less. Table 20.6.2 PROM versions having peculiar bus timing Bus timing Type name M37703E2AXXXSP M37703E4AXXXSP t pzx(E – P1Z), tpzx(E – P2Z) f(XIN) ≤ 8 MHz 8MHz < f(X IN) ≤ 16 MHz Limits: 50 ns Limits: 25 ns Formulas: Formulas: – 6.25 1 5 109 2 5 f(XIN) – 12.5 1 5 109 2 5 f(XIN) (1) Bus timing The limits and formulas of the PROM versions having the peculiar bus timing which is different from other PROM versions are shown in Table 20.6.2. When the user is planning to use the product shown in Table 20.6.2 for evaluation or in early production and replace it later with the mask ROM version, we recommend to use the substitute shown in Table 20.6.3 for evaluation or in early production. However, the substitute version has the higher frequency of external clock input. There are no precaution about its operation. Table 20.6.3 Substitutes Type name to be used Substitute Remark M37703E2AXXXSP M37703E2BXXXSP The substitute has the higher frequency of external clock input. M37703E4AXXXSP M37703E4BXXXSP (2) EPROM mode The products shown in Table 20.6.2 can use only 256K mode as the EPROM mode. Do not use 1M mode.

7702/7703 Group User’s Manual20–16

Appendix 1. Memory assignment Appendix 2.Memory assignment in SFR area Appendix 3. Control registers Appendix 4. Package outlines Appendix 5. Countermeasures against noise Appendix 6. Q&A Appendix 7.Hexadecimal instruction code table Appendix 8. Machine instructions

Appendix 1. Memory assignment 7702/7703 Group User’s Manual21–2 Appendix 1. Memory assignment Figure 1 to Figure 5 show the memory assignment of the M37702 and the M37703 in each processor mode. Refer to the memory assignment whose type name show suitable memory type and memory size. M37702M2BXXXFP Memory type and memory size 00000016 00007F16 00008016 00027F16 00C000 16 00FFFF 16 00047F16 00A00016 00800016 l Single-chip mode SFR area Internal RAM 512 bytes Not used Not used Not used Internal ROM

24 Kbytes

32 Kbytes

Note: These can be used only in the single-chip mode. Fig. 1 Memory assignment during single-chip mode (1)

Appendix 1. Memory assignment APPENDIX 7702/7703 Group User’s Manual 21–3 Fig. 2 Memory assignment during single-chip mode (2) 00000016 00007F16 00008016 00087F16 00800016 00FFFF 16 00400016 00100016 l Single-chip mode SFR area Internal RAM 2048 bytes Not used Internal ROM

48 Kbytes

60 Kbytes

Appendix 1. Memory assignment 7702/7703 Group User’s Manual21–4 01FFFF 16 FF000016 00000016 00007F16 00008016 00027F16 00C000 16 00FFFF 16 00087F16 00800016 01000016 FFFFFF 16 00000016 00000216 00000916 00007F16 l Memory expansion mode SFR area Internal RAM 512 bytes Bank 016 Bank 116 Bank FF16 SFR area Internal RAM 2048 bytes External area External area External area Internal ROM External areaExternal area Fig. 3 Memory assignment during memory expansion mode (1)

Appendix 1. Memory assignment APPENDIX 7702/7703 Group User’s Manual 21–5 00000016 00007F16 00008016 00400016 00FFFF 16 00087F16 00100016 01000016 01FFFF 16 FF000016 FFFFFF 16 00000016 00000216 00000916 00007F16 l Memory expansion mode SFR area Internal RAM 2048 bytes Bank 016 External area Internal ROM External area External area Fig. 4 Memory assignment during memory expansion mode (2)

Appendix 1. Memory assignment 7702/7703 Group User’s Manual21–6 Fig. 5 Memory assignment during microprocessor mode 00000016 00007F16 00008016 00FFFF 16 01000016 01FFFF 16 FF000016 FFFFFF 16 00000016 00000216 00000916 00007F16 00027F16 00087F16 (Note 2) External area l Microprocessor mode SFR area Internal RAM 512 bytes S4 ( Note 1) Bank 016 External area Bank 116 Bank FF16 SFR area Internal RAM 2048 bytes External area (Note 2) Notes 1: These can be used only in the microprocessor mode . 2: Interrupt vector table is assigned to addresses 00FFD616 to 00FFFF16. Set a ROM to this area.

7702/7703 Group User’s Manual 21–7 Appendix 2. Memory assignment in SFR area Appendix 2. Memory assignment in SFR area Figures 6 to 9 show the memory assignment in SFR area. The significations which are used in Figures 6 to 9 is described below. Fig. 6 Memory assignment in SFR area (1) 1016 1116 1216 1316 Port P8 direction register1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 016 116 216 316 416 516 616 716 816 916 B16 C 16 D 16 E16 F16 A16 Address Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register A-D sweep pin select register Port P0 register Port P1 register Port P2 register Port P3 register Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Register name Access characteristics State immediately after a reset RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0016 0016 0016 0016 00000000 0016 00000 ? b7 b0 b7 b0 0016 ] : In the 7703 Group, set “1” to the bit of which corresponding pin is nothing. (Refer to section “20.4.1 Input/Output pins.” ) RW ? 0016RW 0000 ? : It is possible to read the bit state at reading. The written value becomes valid data. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid data. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value is ignored. RW RO WO Access characteristics : “0” immediately after a reset. : “1” immediately after a reset. : Undefined immediately after a reset. : Always “0” at reading 0 : Always undefined at reading : “0” immediately after a reset. Fix this bit to “0.” State immediately after a reset

Appendix 2. Memory assignment in SFR area 7702/7703 Group User’s Manual21–8 UART0 transmit/receive control register 0 UART0 transmit/receive mode register UART0 baud rate register UART0 transmit buffer register UART1 receive buffer register Register name UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 2816 2916 2B16 2C 16 2D 16 2E16 2F16 2A16 2016 2116 2216 2316 2416 2516 2616 2716 3F16 Address Access characteristics RW WO WO b7 b0 WO RW RO State immediately after a reset b7 b0 0016 A-D register 5 A-D register 1 A-D register 3 A-D register 2 A-D register 4 A-D register 0 A-D register 6 A-D register 7 RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RO RW RO RO RW WO WO WO RW RO RO RW RO RO RW RO ?? ?? 10 0 0 00 00 00 1 0 0 000 00 0 ? 0016 ?? ?? 10 0 0 00 00 00 1 0 0 000 00 0 ? Fig. 7 Memory assignment in SFR area (2)

7702/7703 Group User’s Manual 21–9 Appendix 2. Memory assignment in SFR area RW RW Timer B2 register 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 4B16 4C 16 4D 16 4E16 4F16 4A16 Address Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Processor mode register One-shot start register Timer A0 register Up-down register Timer A1 register Register name Count start register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Access characteristics RW b7 b0 RW RW WO State immediately after a reset 0016 0016 0016 0016 0016 b7 b0 0016 RW RW Timer A0 mode register Timer A4 mode register (Note 3) 0 00 0 0 0 0 0 0 0 0 0 0 00 0 000 00 0 0 0 0 0 RW RW ]1: The access characteristics at addresses 46 16 to 4F16 varies according to Timer A’s operating mode. (Refer to “Chapter 5. TIMER A.”) ]2: The access characteristics at addresses 5016 to 5516 varies according to Timer B’s operating mode. (Refer to “Chapter 6. TIMER B.”) ]3: The access characteristics of bit 5 at addresses 5B16 to 5D16 varies according to Timer B’s operating mode. (Refer to “Chapter 6. TIMER B.”) ]4: The access characteristics of bit 1 at address 5E16 and its state immediately after a reset vary according to the voltage level supplied to the CNVSS pin. (Refer to section “2.5 Processor modes.”) RW RW 00 0 000?? 00 0 000?? WO WO RW RW RW RW RW RW Fig. 8 Memory assignment in SFR area (3)

Appendix 2. Memory assignment in SFR area 7702/7703 Group User’s Manual21–10 UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 6B16 6C 16 6D 16 6E16 6F16 6A16 Address A-D conversion interrupt control register UART0 transmit interrupt control register UART1 transmit interrupt control register INT2 interrupt control register Watchdog timer frequency select register Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW b7 b0 RW State immediately after a reset ? (Note) b7 b0 UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register 0 0 0 0 00 0 ]5 : By writing dummy data to address 6016, a value “FFF16” is set to the watchdog timer. The dummy data is not retained anywhere. RW ? ?RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0? 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 Note: A value “FFF16” is set to the watchdog timer. (Refer to “Chapter 9. WATCHDOG TIMER .”) Fig. 9 Memory assignment in SFR area (4)

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–11 Appendix 3. Control registers The register structure of each control register assignment in the SFR area are shown on the following pages. The view of the register structure is described below. XXX register (Address XX b1 b0 ... select bit 1 : ... The value is “0” at reading. 0 : ... 1 : ... Fix this bit to “0.” t o Nothing is assigned. RW WO RO RW RW Bit Bit name This bit is ignored in ... mode. Functions At reset RW ... flag Undefined Undefined Blank : This bit is not used in the specific mode or state. It may be either “0” or “1.” : Nothing is assigned. Undefined RW RO value may be either “0” or “1.” WO reading. However, the bit with the commentaries of “The value is “0” at reading” in the functions column or the notes is always “0” at reading.(See 4 above.) commentaries of “The value is “0” at reading” in the functions column or the notes is always “0” at reading.(See 4 above.) The written value becomes invalid. Accordingly, the written value may be “0” or “1.” : Set to “1” at writing. : Set to “0” at writing. : Set to “0” or “1” to meet the purpose. : “0” immediately after a reset. : “1” immediately after a reset. : Undefined immediately after a reset. : It is possible to read the bit state at reading. The written value becomes valid data. : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written : The written value becomes valid data. It is impossible to read the bit state. The value is undefined at It is impossible to read the bit state. The value is undefined at reading. However, the bit with the

Appendix 3. Control registers 7702/7703 Group User’s Manual21–12 Port Pi register Bit Bit name Functions Port Pi0 Port Pi2 Port Pi3 Port Pi4 Port Pi6 Data is input/output to/from a pin by reading/writing from/to the corres- ponding bit. Port Pi Port Pi register (i = 0 to 8) (Addresses 216, 316, 616, 716, A16, B16, E16, F16, 1216) b1 b0b2b3b4b5b6b7 Port Pi1 Port Pi7 At reset RW Undefined Note: Bits 7 to 4 of the port P3 register cannot be written (they may be either “0” or “1”) and are fixed to “0” at reading. Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 : “L” level 1 : “H” level RW RW RW RW RW RW RW RW Port Pi direction register Bit Bit name Functions Port Pi 0 direction bit Port Pi2 direction bit Port Pi3 direction bit Port Pi4 direction bit Port Pi6 direction bit 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Port Pi5 direction bit Port Pi direction register (i = 0 to 8) (Addresses 416, 516, 816, 916, C16, D16, 1016, 1116, 1416) b1 b0b2b3b4b5b6b7 Port Pi1 direction bit Port Pi7 direction bit At reset RW RW RW RW RW RW RW RW RW Notes 1: Bits 7 to 4 of the port P3 direction register cannot be written (they may be either “0” or “1”) and are fixed to “0” at reading. 2: In the memory expansion mode or the microprocessor mode, fix bits 0 and 1 of the port P4 direction register to “0.” Fix the following bits which do not have the corresponding pin to “1.”

• Bit 3 of port P3 direction register
• Bits 3 to 6 of port P4 direction register
• Bits 0, 1, 6, and 7 of port P6 direction register
• Bits 3 to 6 of port P7 direction register
• Bits 4 and 5 of port P8 direction register Bit Corresponding pin b7 b6 b5 b4 b3 b2 b1 b0 Pi7 Pi6 Pi5 Pi4 Pi3 Pi2 Pi1 Pi0

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–13 A-D control register b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (Address 1E16) Bit A-D conversion frequency ( AD ) select bit A-D conversion start bit Trigger select bit A-D operation mode select bits Bit name At reset Undefined RWFunctions 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected (Note 2) b2 b1 b0 0 : Internal trigger 1 : External trigger 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 : Stop A-D conversion 1 : Start A-D conversion b4 b3 Notes 1: These bits are ignored in the single sweep and repeat sweep mode. (They may be either “0” or “1.”) 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit (except bit 6) of the A-D control register must be performed while the A-D converter halts. Analog input select bits (Valid in one-shot and repeat modes) (Note 1) Undefined Undefined RW RW RW RW RW RW RW RW 0 : f2 divided by 4 1 : f2 divided by 2

Appendix 3. Control registers 7702/7703 Group User’s Manual21–14 A-D sweep pin select register b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select register (Address 1F16) Bit Bit name At reset Undefined RWFunctions Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”) 2: When selecting an external trigger, the AN7 pin cannot be used as an analog input pin. 3: Writing to each bit of the A-D sweep pin select register must be performed while the A-D converter halts. 7 to 2 RW0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) (Note 2) A-D sweep pin select bits (Valid in single sweep and repeat sweep mode ) (Note 1) b1 b0 1 RW Nothing is assigned. – A-D register i A-D register 0 (Addresses 2016) A-D register 1 (Addresses 2216) A-D register 2 (Addresses 2416) A-D register 3 (Addresses 2616) A-D register 4 (Addresses 2816) A-D register 5 (Addresses 2A16) A-D register 6 (Addresses 2C16) A-D register 7 (Addresses 2E16) Bit 7 to 0 At reset Undefined RWFunctions ROReads an A-D conversion result. b7 b6 b5 b4 b3 b2 b1 b0

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–15 UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Bit Bit name At reset RWFunctions b2 b1 b0 RW RW RW RW RW RW RW RW Serial I/O mode select bits 0 0 0 : Serial I/O disabled (P8 functions as a programmable I/O port.) 0 0 1 : Clock synchronous serial I/O mode 0 1 0 : Not selected 0 1 1 : Not selected 1 0 0 : UART mode (Transfer data length = 7 bits) 1 0 1 : UART mode (Transfer data length = 8 bits) 1 1 0 : UART mode (Transfer data length = 9 bits) 1 1 1 : Not selected Sleep select bit (Valid in UART mode) (Note) Parity enable bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit is “1”) (Note) Stop bit length select bit (Valid in UART mode) (Note) Internal/External clock select bit UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode cleared (ignored) 1 : Sleep mode selected 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits b7 b0 UART0 baud rate register (Address 3116) UART1 baud rate register (Address 3916) FunctionsBit At reset RW 7 to 0 Can be set to “0016” to “FF16.” Assuming that the set value = n, BRGi divides the count source frequency by n + 1. Undefined WO UARTi baud rate register (BRGi)

Appendix 3. Control registers 7702/7703 Group User’s Manual21–16 UARTi transmit buffer register b7 b0 Bit 8 to 0 At reset Undefined RWFunctions WO b7 b0 (b15) (b8) 15 to 9 –Undefined UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) Nothing is assigned. Transmit data is set. UARTi transmit/receive control register 0 CTS/RTS select bit Bit BRG count source select bits Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b1 b0 0 : CTS function selected. 1 : RTS function selected. Transmit register empty flag0 : Data present in transmit register. (During transmitting) 1 : No data present in transmit register. (Transmitting completed) 7 to 4 RW RW RO3 RW Nothing is assigned. Undefined –

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–17 UARTi transmit/receive control register 1 Bit Bit name At reset (Valid in UART mode) 00 : No framing error 1 : Framing error detected RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) Notes 1: Bits 7 to 4 are cleared to “0” when clearing the receive enable bit to “0” or when reading the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16) out. 2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode. 1 : Transmission enabled 0 : Data present in transmit buffer register. 1 : No data present in transmit buffer register. 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register. 1 : Data present in receive buffer register. 0 : No overrun error 1 : Overrun error detected (Valid in UART mode) 00 : No parity error 1 : Parity error detected (Valid in UART mode) 0 : No error 1 : Error detected (Notes 1, 2) (Notes 1, 2) (Notes 1, 2) (Note 1) RW RO RW RO RO RO RO RO UARTi receive buffer register b7 b0 Bit 8 to 0 At reset Undefined RWFunctions RO b7 b0 (b15) (b8) 15 to 9 – UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) Nothing is assigned. The value is “0” at reading. Receive data is read out from here.

Appendix 3. Control registers 7702/7703 Group User’s Manual21–18 Count start register Bit Timer B2 count start bit Timer B1 count start bit Timer B0 count start bit Timer A4 count start bit Timer A3 count start bit Timer A2 count start bit Timer A1 count start bit Timer A0 count start bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) 0 : Stop counting 1 : Start counting RW RW RW RW RW RW RW RW One-shot start register Bit 7 to 5Nothing is assigned. Timer A4 one-shot start bit Timer A3 one-shot start bit Timer A2 one-shot start bit Timer A1 one-shot start bit Timer A0 one-shot start bit Bit name At reset Undefined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register (Address 4216) 1 : Start outputting one-shot pulse (valid when selecting internal trigger.) The value is “0” at reading. WO WO WO WO WO

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–19 Up-down register Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Up-down register (Address 4416) Timer A4 up-down bit Timer A3 up-down bit Timer A2 up-down bit Timer A1 up-down bit Timer A0 up-down bit Timer A2 two-phase pulse signal processing select bit (Note) Timer A3 two-phase pulse signal processing select bit (Note) Timer A4 two-phase pulse signal processing select bit (Note) 0 : Down-count 1 : Up-count This function is valid when the contents of the up-down register is selected as the up-down switching factor. 0 : Two-phase pulse signal processing function disabled 1 : Two-phase pulse signal processing function enabled When not using the two-phase pulse signal processing function, make sure to set the bit to “0.” The value is “0” at reading. Note: Use the LDM or STA instruction when writing to bits 5 to 7. RW RW RW RW RW WO WO WO

Appendix 3. Control registers 7702/7703 Group User’s Manual21–20 Timer Ai register Timer Ai mode register b7 b0 b7 b0 (b15) (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 These bits have different functions according to the operating mode. Undefined RW Bit Bit name At reset RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot pulse mode 1 1 : Pulse width modulation (PWM) mode b1 b0 These bits have different functions according to the operating mode. Operating mode select bits 0 RW RW RW RW RW RW RW RW

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–21 Timer Mode b7 b0 b7 b0 (b15) (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 These bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by n + 1. When reading, the register indicates the counter value. Undefined RW Gate function select bits Pulse output function select bit Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 0 0 : Timer mode 0 : No pulse output (TAiOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b4 b3 0 0 : No gate function 0 1 : (TAiIN pin functions as a prog- rammable I/O port.) 1 0 : Gate function (Counter counts only while TAiIN pin’s input signal is “L” level.) 1 1 : Gate function (Counter counts only while TAiIN pin’s input signal is “H” level.) Bit At reset RW 0 RW 0 RW 0 RW 3 0 RW 0 RW 5 0 RW 0 RW 0 RW Fix this bit to “0” in the timer mode.

Appendix 3. Control registers 7702/7703 Group User’s Manual21–22 Event counter mode b7 b6 b5 b4 b3 b2 b1 b0 00 1 Bit Up-down switching factor select bit Count polarity select bit Bit name These bits are ignored in event counter mode. Fix this bit to “0” in event counter mode. 5 : It may be either “0” or “1.” Functions 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 : Contents of up-down register 1 : Input signal to TAi OUT pin At reset RW Pulse output function select bit Operating mode select bits 0 : No pulse output (TAiOUT pin functions as a programmable I/O port.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) 0 1 : Event counter mode b1 b0 RW RW RW RW RW RW RW RW Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) b7 b0 b7 b0 (b15) (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) RW 15 to 0 Bit Functions At reset RWThese bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by n + 1 when down-counting, or by FFFF 16 – n + 1 when up-counting. When reading, the register indicates the counter value. Undefined

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–23 One-shot pulse mode b7 b0 b7 b0 (b15) (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0 These bits can be set to “000116” to “FFFF16.” Assuming that the set value = n, the “H” level width of the one-shot pulse output from the TAi OUT pin is expressed as follows : n / fi. Undefined fi: Frequency of count source (f2, f16, f64, or f512) WO Trigger select bits Fix this bit to “1” in one-shot pulse mode. 1 @ Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 1 0 : One-shot pulse mode 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6 Count source select bits b1 b0 b4 b3 Fix this bit to “0” in one-shot pulse mode. 10 1 0 0 : Writing “1” to one-shot start register 0 1 (TAiIN pin functions as a prog- rammable I/O port.) 1 0 : Falling edge of TAiIN pin’s input signal 1 1 : Rising edge of TAiIN pin’s input signal Bit At reset RW RW RW RW RW RW RW RW RW Operating mode select bits

Appendix 3. Control registers 7702/7703 Group User’s Manual21–24 Pulse width modulation (PWM) mode b7 b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 15 to 0These bits can be set to “000016” to “FFFE16.” Assuming that the set value = n, the “H” level width of the PWM pulse output from the TAiOUT pin is expressed as follows: Undefined <When operating as a 16-bit pulse width modulator> (b15) (b8) WO n fi fi: Frequency of count source (f2, f16, f64, or f512) <When operating as an 8-bit pulse width modulator> (b15) b7 b0 b7 b0 (b8) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) FunctionsBit At reset RW 7 to 0 15 to 8 Undefined Undefined These bits can be set to “0016” to “FF16.” Assuming that the set value = m, PWM pulse’s period output from the TAiOUT pin is expressed as follows:(m + 1)(28 – 1) fi WO These bits can be set to “0016” to “FE16.” Assuming that the set value = n, the “H” level width of the PWM pulse output from the TAi OUT pin is expressed as follows: n(m + 1) fi WO fi: Frequency of count source (f2, f16, f64, or f512) b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits 11 1 At reset RW Trigger select bits Fix this bit to “1” in PWM mode. Operating mode select bits Bit name Functions 1 1 : PWM mode b1 b0 b4 b3 16/8-bit PWM mode select bit 0 0 : Writing “1” to count start register 0 1 : IN pin functions as a pro- grammable I/O port.) 1 0 : Falling edge of TAiIN pin’s input signal 1 1 : Rising edge of TAiIN pin’s input signal Bit 0 : As a 16-bit pulse width modulator 1 : As an 8-bit pulse width modulator RW RW RW RW RW RW RW RW

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–25 Timer Bi register b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) FunctionsBit At reset RW 15 to 0 These bits have different functions according to the operating mode. Undefined RW Timer Bi mode register Nothing is assigned. These bits have different functions according to the operating mode. Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Not selected b1 b0 Bit At reset RW 0 RW RW RW Note: Bit 5 is ignored in the timer mode and event counter mode; its value is undefined at reading. RW0 –Undefined4 RO (Note) Undefined RW0 RW0 These bits have different functions according to the operating mode.

Appendix 3. Control registers 7702/7703 Group User’s Manual21–26 Timer mode b7 b6 b5 b4 b3 b2 b1 b0 Bit This bit is ignored in timer mode. Nothing is assigned. Bit name Count source select bits 5 : It may be either “0” or “1.” Functions At reset RW These bits are ignored in timer mode. Operating mode select bits 0 0 : Timer mode b1 b0 RW RW RW RW Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)5 –Undefined4 Undefined5 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6 RW0 RW0 b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) RW 15 to 0 Bit Functions At reset These bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by n + 1. When reading, the register indicates the counter value. Undefined RW

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–27 Event counter mode b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) RW 15 to 0 Bit Functions At reset RWThese bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by n + 1. When reading, the register indicates the counter value. Undefined 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Counts at both falling and rising edges of external signal 1 1 : Not selected b7 b6 b5 b4 b3 b2 b1 b0 Bit Count polarity select bits Bit name These bits are ignored in event counter mode. This bit is ignored in event counter mode. 5 : It may be either “0” or “1.” Functions At reset Undefined RW Operating mode select bits 0 1 : Event counter mode b1 b0 RW RW RW RW RW RW Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) b3 b2 Nothing is assigned. Undefined

Appendix 3. Control registers 7702/7703 Group User’s Manual21–28 Pulse period/pulse width measurement mode b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) FunctionsBit At reset RW 15 to 0 The measurement result of pulse period or pulse width is read out. Undefined RO Measurement mode select bits Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) 1 0 : Pulse period/Pulse width measurement mode 0 0 : f 0 1 : f16 1 0 : f64 1 1 : f512 b7 b6Count source select bits b1 b0 b3 b2 Nothing is assigned. 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : Not selected Bit At reset Undefined RW RW RW RW RW RW RW Timer Bi overflow flag (Note) 0 : No overflow 1 : Overflowed Undefined RO Note: The timer Bi overflow flag is cleared to “0” by writing to the timer Bi mode register with the count start bit = “1”.

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–29 Bit Bit name Functions At reset RW Processor mode bits Software reset bit Interrupt priority detection time select bits Clock 1 output select bit (Note 2) 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not selected The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Not selected 0 : Clock 1 output disabled (P42 functions as a programmable I/O port.) 1 : Clock 1 output enabled (P42 functions as a clock 1 out- put pin.) b1 b0 b5 b4 Processor mode register (Address 5E16) (Note 1) Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1” after a reset. (Fixed to “1.”) 2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”) b1 b0b2b3b4b5b6b7 RW RW Wait bit RW WO 0 RW 0 RW Fix this bit to “0.” RW RW 0 : Software Wait is inserted when accessing external area. 1 : No software Wait is inserted when accessing external area. Processor mode register

Appendix 3. Control registers 7702/7703 Group User’s Manual21–30 Watchdog timer register Watchdog timer register (Address 6016) Bit Initializes the watchdog timer. When a dummy data is written to this register, the watchdog timer’s value is initialized to “FFF 16.” (Dummy data: 0016 to FF16) At reset Undefined RWFunctions 7 to 0 – b7 b0 Watchdog timer frequency select register 0 : f512 1 : f32 At reset Undefined RWFunctions b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit Nothing is assigned. Watchdog timer frequency select bit Bit name 7 to 1 RW

Appendix 3. Control registers 7702/7703 Group User’s Manual 21–31 Interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 7016 to 7C16) Bit 7 to 4 Interrupt request bit Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request Interrupt priority level select bits RW RW RW RW –Undefined Nothing is assigned. Note: Use the SEB or CLB instruction to set each interrupt control register. b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit Interrupt request bit (Note 1) Bit name At reset RWFunctions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request 0 : Edge sense 1 : Level sense Notes 1: The INT 0 to INT2 interrupt request bits are invalid when selecting the level sense. Interrupt priority level select bits 7, 6 RW RW RW RW RW RW Undefined Polarity select bit 0 : Set the interrupt request bit at “H” level for level sense and at falling edge for edge sense. 1 : Set the interrupt request bit at “L” level for level sense and at rising edge for edge sense. Level sense/Edge sense select bit Nothing is assigned. 2: Use the SEB or CLB instruction to set the INT0 to INT2 interrupt interrupt control registers.

7702/7703 Group User’s Manual21–32 Appendix 4. Package outlines Appendix 4. Package outlines

7702/7703 Group User’s Manual 21–33 Appendix 4. Package outlines

7702/7703 Group User’s Manual21–34 Appendix 4. Package outlines

7702/7703 Group User’s Manual 21–35 APPENDIX Appendix 5. Countermeasures against noise Appendix 5. Countermeasures against noise The following describes some examples of countermeasures against noise. Although the effect depends on the system, refer to the following if the problem being relevant to noise occurs. 1. Reduction in wiring length Wiring on a circuit board can serve as an antenna that pulls in noise into the microcomputer. Shorter the total length of wiring (in mm), the smaller the possibility of pulling in noise into the microcomputer. (1) Reduce the length of wiring connected to the RESET pin.______ Especially, a capacitor that is inserted between the RESET and Vss pins must be connected to these pins in the shortest possible distance (within 20 mm). Reasons: If noise gets into the RESET pin, the microcomputer will restart op- erating before its internal state is completely initialized, which can cause a program runaway. Fig. 10 Wiring of RESET pin RESETReset circuit Noise VssVss M37702 Reset circuit Vss RESET Vss M37702 O .K . N .G .

7702/7703 Group User’s Manual21–36 APPENDIX Appendix 5. Countermeasures against noise (2) Wiring of clock input/output pins Reduce the length of wiring connected to the clock input/output pins. Connect the lead wire on the ground side of a capacitor connected to the oscillator and the microcomputer’s Vss pin in the shortest possible distance (within 20 mm). Separate the Vss pattern for oscillation purpose from the other Vss patterns. (Refer to Figure 19.) Reasons: The microcomputer operates synchronously with the clock generated by the oscillation circuit. If noise gets into the clock input/ output pins, the clock waveform is disturbed, which can cause the microcomputer to malfunction or a program runaway. Furthermore, if noise causes a potential difference between the microcomputer’s Vss level and the oscillator’s Vss level, the oscillator cannot generate an exact clock. (3) Wiring of CNVss pin When connecting the CNVss and Vss pins, connect them in the shortest possible distance. Reasons: The voltage level on the CNVss pin affects the selection of microcomputer’s processor modes. If noise causes a potential difference between the voltage levels of the CNVss and Vss pins when these pins are connected, the microcomputer’s processor mode will become unstable, causing the microcomputer to malfunction or a program runaway. Fig. 11 Wiring of clock input/output pins Fig. 12 Wiring of CNVss pin Noise XIN XOUT Vss XIN XOUT Vss M37702 M37702 N .G . O .K . Noise CNVss Vss M37702 CNVss Vss M37702 O .K .N .G .

7702/7703 Group User’s Manual 21–37 APPENDIX Appendix 5. Countermeasures against noise (4) Wiring of CNVss (VPP ) pin of built-in PROM version < In single-chip or memory expansion mode> l Connect the CNVss (VPP ) pin to the microcomputer’s Vss pin in the shortest possible distance. l If the wiring cannot be shortened, insert a resistor of about 5 kohms as close to the CNVss (VPP ) pin as possible. By way of this resistor, connect the CNVss (VPP ) pin to the Vss pin. < In microprocessor mode> l Connect the CNVss (VPP ) and Vcc pins in the shortest possible distance. Reasons: The CNVss (VPP ) pin serves as a power source input pin for the built-in PROM, and this pin has a reduced impedance to allow a programming current to flow in when programming to the built-in PROM. (This means that noise gets in easily.) If noise gets into the CNVss (VPP ) pin, abnormal instruction codes or data will be read out from the built-in PROM, causing a program runaway. In microprocessor mode Shortest possible distance Connect the CNVss pin to the Vcc pin in the shortest possible distance. CNV SS (VPP ) VCC M37702 Shortest possible distance Approx. 5 kohms Connect the CNVss pin to the Vss pin in the shortest possible distance. CNV SS (VPP ) VSS In single-chip and memory expansion modes M37702 ] The above processing is unnecessary for the BYTE (VPP ) pin. Fig. 13 Wiring of CNVss (VPP ) pin of built-in PROM version

7702/7703 Group User’s Manual21–38 APPENDIX Appendix 5. Countermeasures against noise 2. Inserting bypass capacitor between Vss and Vcc lines Insert a bypass capacitor of about 0.1 µF between the Vss and Vcc lines. When inserting this bypass capacitor, make sure that the following conditions are satisfied. l Wiring length between the Vss pin and the bypass capacitor equals that between the Vcc pin and the bypass capacitor. l Wiring between the Vss pin and the bypass capacitor and that between the Vcc pin and the bypass capacitor have the shortest possible length. l The Vss and Vcc lines both have broader wiring width than the other signal wires. Bypass capacitor /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VccVss M37702 Wiring pattern Wiring pattern Fig. 14 Bypass capacitor between Vss and Vcc lines

7702/7703 Group User’s Manual 21–39 APPENDIX Appendix 5. Countermeasures against noise 3. Wiring processing of analog input pin, analog power source pin and others (1) Processing of analog input pin l Connect a resistor in series to the analog signal wire connecting to an analog input pin at the position closest possible to the microcomputer. l Insert a capacitor between the analog input pin and AVss pin at a position closest possible to the AVss pin. Reasons: Normally, the signal which is input to the analog input pin is an output signal from a sensor. A sensor used to detect changes in event is in many cases located away from the board on which the microcomputer is mounted. Accordingly, wiring from the sensor to the analog input pin inevitably becomes long. This long wiring can serve as an antenna that pulls in noise into the microcomputer, letting noise get into the analog input pin easily. Additionally, if the capacitor between the analog input pin and AVss pin is grounded away from the AVss pin, noise on that ground can get into the microcomputer via the capacitor. AN i AVss Thermistor Noise M37702 RI CI Reference value RI :Approximately 100 to 1000 CI :Approximately 100 to 1000 pF Notes 1 : Make sure that the external circuit of the ANi pin is designed so that the ANi pin can be charged/discharged within 1 cycle of AD . 2 : This resistor is used to divide resistance from the thermistor. (Note 2) N .G . O .K O .K Fig. 15 Example for protecting analog input pin against noise by using thermistor

7702/7703 Group User’s Manual21–40 APPENDIX Appendix 5. Countermeasures against noise (2) Processing of analog power source pins and others l For each of the Vcc, AVcc, and VREF pins, use separated power sources. l Insert capacitors between the AVcc and AVss pin, and between the VREF and AVss pin, respectively. Reasons: Avoids affecting the A-D converter due to noise on Vcc. AVcc AVss M37702 Reference value C1 0.47 F C2 0.47 F Note : Connect capacitors with the thickest possible wiring in the shortest possible distance. VREF AN i C1 C2 (sensor, and others) Fig. 16 Processing of analog power source pin and others

7702/7703 Group User’s Manual 21–41 APPENDIX Appendix 5. Countermeasures against noise 4. Consideration to oscillator The oscillator that generates the fundamental clock of the microcomputer’s operation requires careful consideration not to be affected by the other signals. (1) Isolation from signal wires where a large current flows The signal wires where a large current exceeding the microcomputer’s current limits accepted flows must be located as far away from the microcomputer (especially the oscillator) as possible. Reasons: A system using a microcomputer contains signal wires to control, for example, motors, LEDs, and thermal heads. When a large current flows in these signal wires, noise due to mutual inductance is generated. (2) Isolation from signal wires whose levels change rapidly l The signal wires whose levels change rapidly must be located as far away from the oscillator as possible. l Make sure that signal wires whose levels change rapidly do not cross any other clock-related or noise-susceptible signal wires. Reasons: The signal wires whose voltage levels change rapidly tend to affect other signal wires as the signal level changes from high to low or from low to high. Especially if these signal wires cross a clock-related signal wire, they can disturb the clock waveform, causing the microcomputer to malfunction or a program runaway. Fig. 17 Connection of signal wires where a large current flows XIN XOUT Vss M M37702 Mutual inductance Large current XIN XOUT Vss Must not cross other signal wires. M37702 ] I/O pin for a signal whose level changes rapidly Fig. 18 Wiring of rapidly level changing signal wire

7702/7703 Group User’s Manual21–42 APPENDIX Appendix 5. Countermeasures against noise (3) Protection with Vss pattern For double-sided boards in which the oscillator is mounted on one side (mount side), make sure that there is a Vss pattern at the same position as the oscillator on the reverse side (solder side) of the board. This Vss pattern must be connected to the microcomputer’s Vss pin in the shortest possible distance and must be located away from the other Vss patterns. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines XIN XOUT Vss Example of Vss pattern on reverse side of oscillator Example of mount pattern for oscillator unit Separate the Vss pattern for oscillator from the Vss supply line. M37702 Fig. 19 Vss pattern on reverse side of oscillator

7702/7703 Group User’s Manual 21–43 APPENDIX Appendix 5. Countermeasures against noise 5. Processing of ports Take protective measures for ports in both hardware and software. <Hardware protection> l Insert a resistor of 100 ohms or more in series. <Software protection> l For ports in the input mode, try reading in several times to detect whether their levels are matched or not. l For ports in the output mode, since the output data can reverse owing to noise, periodically set the port Pi register. l Set the port Pi direction register again at stated periods. Noise Direction register Port latch Data bus Port Fig. 20 Processing of ports

7702/7703 Group User’s Manual21–44 APPENDIX Appendix 5. Countermeasures against noise 6. Reinforcement of the power supply line l Use the broader wiring width than that of the other signal wire for the Vss and Vcc lines. l When using the multilayer boards, make sure that one of the middle layer is Vss side, and the other one of middle layer is Vcc side. l When using the double-sided boards, one side must be located with looped or mesh form to the Vss line centering the microcomputer. The vacant space must be filled with the Vss line. The other side must be located with the Vcc line just as in the above-mentioned Vss line. Connect the power supply line of external devices connected to the microcomputer with the bus and the power supply line of the microcomputer in the shortest possible distance. Reasons: The level of many wiring among 24 pieces of external address bus will change at the same time when connecting external devices. That may causes noise of the power supply line.

7702/7703 Group User’s Manual 21–45 Appendix 6. Q & A Appendix 6. Q & A Information which may be helpful in fully utilizing the 7702 Group and the 7703 Group are provided in Q & A format. In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each page is a question, and a box below the question is its answer. (If a question or an answer extends to two or more pages, there is a page number at the lower right corner.) At the upper right corner of each page, the main function related to the contents of description in that page is listed.

Appendix 6. Q & A 7702/7703 Group User’s Manual21–46 Interrupt Q If an interrupt request (b) occurs while executing an interrupt routine (a), is the main routine is not executed before the INTACK sequence for the next interrupt (b) is executed after the interrupt routine (a) under execution is completed? (2) If the next interrupt request (b) occurs immediately after generating of the sampling pulse À , the microcomputer executes one instruction of the main routine before executing the INTACK se- quence for (b) because the interrupt request is sampled by the next sampling pulse \` . Sampling for interrupt requests are performed by sampling pulses generated synchronously with the CPU’s op-code fetch cycles. (1) If the next interrupt request (b) occurs before the sampling pulse (À ) for the RTI instruction is generated, the microcomputer executes the INTACK sequence for (b) without executing the main routine (not even one instruction) because sampling is completed while executing the RTI instruction. A Condition l I is cleared to “0” with the RTI instruction. l The interrupt priority level of the interrupt (b) is higher than the main routine IPL. l The interrupt priority detection time is 2 cycles of Interrupt routine (a) Main routine INTACK sequence for interrupt (b) Sequence of execution RTI instruction ? INTACK sequence for interrupt (b) Interrupt request (b) Interrupt routine (a) Sampling pulse RTI instruction À Main routine Interrupt request (b) Sampling pulse À INTACK sequence for interrupt (b) One instruction executed Interrupt routine (a) RTI instruction

7702/7703 Group User’s Manual 21–47 Appendix 6. Q & A Interrupt There is a routine where a certain interrupt request should not be accepted (with enabled acceptance of all other interrupt requests). Accordingly, the program set the interrupt priority level select bits of the interrupt to be not accepted to “000 2” in order to disable it before executing the routine. However, the interrupt request of that interrupt has been accepted immediately after the priority level had been changed. Why did this occur and what can I do about it? CLB #07H, XXXIC ; Writes “000 2” to interrupt priority level select bits. ; Clears interrupt request bit to “0.” LDA A,DATA ; Instruction at the beginning of the routine that should not accept one certain interrupt. When changing the interrupt priority level, the microcomputer can behave “as if the interrupt request is accepted immediately after it is disabled ” if the next instruction (the LDA instruction in the above case) is already stored in the BIU’s instruction queue buffer and conditions to accept the interrupt request which should not be accepted are met immediately before executing the instruction which is in that buffer. When writing to a memory or an I/O, the CPU passes the address and data to the BIU. Then, the CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into the actual address. Detection of interrupt priority level is performed at the beginning of each instruc- tion. In the above case, in the interrupt priority detection which is performed simultaneously with the execution of the next instruction, the interrupt priority level before changing it is detected and the interrupt request is accepted. It is because the CPU executes the next instruction before the BIU finishes changing the interrupt priority levels. Q A (1/2) Previous instruction executed (Instruction prefetch) CPU operation BIU operation Interrupt priority detection time Sequence of execution Interrupt priority level select bits set Change of interrupt priority levels completed Interrupt request accepted Interrupt request generated CLB instruction executed LDA instruction executed Interrupt request is accepted in this interval

Appendix 6. Q & A 7702/7703 Group User’s Manual21–48 Interrupt To prevent this problem, use software to execute the routine that should not accept a certain interrupt request after change of interrupt priority level is completed. The following shows a sample program. [Sample program ] After an instruction which writes “0002” to the interrupt priority level select bits, fill the instruc- tion queue buffer with the NOP instruction to make the next instruction not be executed before the writing is completed. CLB #07H, XXXIC ; Sets the interrupt priority level select bits to “0002.” NOP ; NOP ; NOP ; LDA A,DATA ; Instruction at the beginning of the routine that should not accept a certain interrupt request (2/2) A

7702/7703 Group User’s Manual 21–49 Appendix 6. Q & A Interrupt Q (1) In both the edge sense and level sense, external interrupt requests occur when the input ____ signal to the INT i pin changes its level regardless of clock φ In the edge sense, the interrupt request bit is set to “1” at this time. (2) There are two methods: one uses external interrupt’s level sense, and the other uses the timer’s event counter mode. À Using external interrupt’s level sense ____ In hardware, input a logical sum of multiple interrupt signals (e.g., ‘a’, ‘b’, and ‘c’) to the INT i pin, and input each signal to each corresponding port. ___ In software, check the ports’ input levels in the INT i interrupt routine to determine that which of the signals ‘a’, ‘b’, and ‘c’ is input. A (1) ____ Which timing of clock φ is the external interrupts (input signals to the INT i pin) detected? (2) ____ How can four or more external interrupt input pins (INT i ) be used? a M37702 Port Port Port INT i b c Using timer’s event counter mode In hardware, input interrupt signals to the TAiIN pins or TBi IN pins. In software, set the timer’s operating mode to the event counter mode and a value “0000 into the timer register to the effective edge. The timer’s interrupt request occurs when an interrupt signal (selected effective edge) is input.

Appendix 6. Q & A 7702/7703 Group User’s Manual21–50 ____ In the case selecting the CTS function in UART (clock asynchronous serial I/O) mode, when the____ transmitting side check the CTS input level ? It is check near the middle of the stop bit (when two stop bits are selected, the second stop bit). A Q Serial I/O (UART mode) D 6 n: 1-bit length nnn n/2 n/2 nn n/2 n/2 Input level to CTSi pin is checked near here. Input level to CTSi pin is checked near here. Transmit data

7702/7703 Group User’s Manual 21–51 Appendix 6. Q & A When “L” level is input to the HOLD pin, how long is the bus actually opened ? A The bus is opened after 50 ns at maximum has passed from the rising edge of next clock φ1 when____ the HLDA pin output becomes “L” level. Q Hold function Term where bus is open Clock 1 HOLD HLDA tpxz(HOLD-PZ) : Maximum 50 ns Note: The 7703 Group does not have the HLDA pin.

Appendix 6. Q & A 7702/7703 Group User’s Manual21–52 Processor mode If the processor mode is switched as described below by using the processor mode bits (bits 1 and 0 at address 5E16) during program execution, is there any precaution in software? l Single-chip mode → Microprocessor mode l Memory expansion mode → Microprocessor mode Q A If the processor mode is switched as described above by using the processor mode bits, the mode is switched simultaneously when the cycle to write to the processor mode bits is completed. Then, the program counter indicates the address next to the address (address XXXX16) that contains the write instruction for the processor mode bits. Additionally, access to the internal ROM area is disabled. However, since the instruction queue buffer can prefetch up to three instructions, the address in the external ROM area and is accessed first after the mode is switched is one of XXXX16 + 1 to XXXX 16 + 4. The instructions at addresses XXXX16 + 1 to XXXX 16 + 3 in the internal ROM area can be executed. To prevent this problem, process the following by software. À Write the write instruction for the processor mode bits and next instructions (at least three bytes) at the same addresses both in the internal ROM and external ROM areas. (See below.) \` Transfer the write instruction for the processor mode bits to an internal RAM area and make a branch to there in order to execute the write instruction. After that, make a branch to the program address in the external ROM area. (Contents of the instruction queue buffer is initialized by a branch instruction.) LDM . B #00000010B, PMR NOP NOP NOP LDM . B #00000010B, PMR NOP NOP NOP XXXX External ROM areaInternal ROM area XXXX 16 At least three bytes

7702/7703 Group User’s Manual 21–53 Appendix 6. Q & A SFR Q Is there any SFR for which instructions that can be used to set registers or bits are limited? (1) Use the STA or LDM instruction to set the registers or the bits listed below. Do not use read-modify-write instructions (i.e., CLB, SEB, INC, DEC, ASL, ASR, LSR, ROL, and ROR ). UART0 baud rate register (address 3116) UART1 baud rate register (address 3916) UART0 transmit buffer register (addresses 3316, 3216) UART1 transmit buffer register (addresses 3B16, 3A16) Timer A4 two-phase pulse signal processing select bit (bit 7 at address 4416) Timer A3 two-phase pulse signal processing select bit (bit 6 at address 4416) Timer A2 two-phase pulse signal processing select bit (bit 5 at address 4416) (2) Use the SEB and CLB instructions to set interrupt control registers (addresses 7F16 to 7016). A

Appendix 6. Q & A 7702/7703 Group User’s Manual21–54 Watchdog timer When detecting the software runaway by the watchdog timer, if not software reset but setting the same value as the contents of the reset bector address to the watchdog timer interrupt bector address is processed , how does it result in? When branching the reset branch address within the watchdog timer interrupt routine, how does it result in? A The CPU registers and the SFR are not initialized in the above-mentioned way. Accordingly, it is necessary that you must perform the initial setting for these all by software. The processor interrupt priority level (IPL) retains “7” of the watchdog timer interrupt priority level, and that is not initialized. Consequently, all interrupt requests are not accepted. When rewriting the IPL by software, store once the 16-bit immediate value to the stack area and next return that 16-bit immediate value to all bits of the processor status register (PS). We recommend software reset in order to initialize the microcomputer for software runaway. Q

7702/7703 Group User’s Manual 21–55 Appendix 7. Hexadecimal instruction code table Appendix 7. Hexadecimal instruction code table

7702/7703 Group User’s Manual21–56 Appendix 7. Hexadecimal instruction code table

7702/7703 Group User’s Manual 21–57 Appendix 7. Hexadecimal instruction code table

7702/7703 Group User’s Manual21–58 Appendix 8. Machine instructions Appendix 8. Machine instructions

7702/7703 Group User’s Manual 21–59 Appendix 8. Machine instructions

7702/7703 Group User’s Manual21–60 Appendix 8. Machine instructions

7702/7703 Group User’s Manual 21–61 Appendix 8. Machine instructions

7702/7703 Group User’s Manual21–62 Appendix 8. Machine instructions

7702/7703 Group User’s Manual 21–63 Appendix 8. Machine instructions

7702/7703 Group User’s Manual21–64 Appendix 8. Machine instructions

7702/7703 Group User’s Manual 21–65 Appendix 8. Machine instructions

7702/7703 Group User’s Manual21–66 Appendix 8. Machine instructions

7702/7703 Group User’s Manual 21–67 Appendix 8. Machine instructions

7702/7703 Group User’s Manual21–68 Appendix 8. Machine instructions

7702/7703 Group User’s Manual 21–69 Appendix 8. Machine instructions

7702/7703 Group User’s Manual21–70 Appendix 8. Machine instructions

7702/7703 Group User’s Manual 21–71 Appendix 8. Machine instructions

7702/7703 Group User’s Manual21–72 Appendix 8. Machine instructions MEMORANDUM

7702/7703 Group User’s Manual2 This section briefly explains the terms used in this user’s manual. The terms defined here apply to this manual only. Term Access Access area Access characteristics Baud rate Branch Bus control signal Count source Counter contents (values) Down-count Event counter mode External area External bus External device Gate function of Timer Internal area Interrupt routine LSB first Overflow Power saving Read-modify-write instruction Signal required for access to external device Stop mode Synchronizing clock Meaning Means performing read, write, or read and write. An accessible memory space of up to 16 Mbytes. Means whether accessible or not. Means a transfer rate of Serial I/O Means moving the program’s execution point (= address) to another location. A generic name for ALE, E, BHE, R/W, RDY, HOLD, HLDA and BYTE signals. A signal that is counted by Timers A and B, the UARTi baud rate register (BRGi) and Watchdog timer. That is f 2, f16, f64, f512 selected by the count source select bits and others. Means a value read when reading the timer Ai and Bi registers. Means decreasing by 1 and counting. Means the mode of Timers which can count the number of external pulses exactly without a divider. An accessible area for external devices connected in the memory expansion or microprocessor mode. It is up to 16-Mbyte external area. A generic name for the external address bus and the data bus. Devices connected externally to the microcomputer. A generic name for a memory, an I/O device and a peripheral IC. Means the function that the user can control input of the timer count source. An accessible internal area. A generic name for areas of the internal RAM, internal ROM and the SFR. A routine that is automatically executed when an interrupt request is accepted. Set the start address of this routine into the interrupt vector table. Means a transfer data format of Serial I/O;LSB is transferred first. A state where the up-count resultant is greater than the counter resolution. Means reducing a power dissipation by Stop mode, Wait mode or others An instruction that reads the memory contents, modifies them and writes back to the same address. Relevant instructions are the ASL , CLB , DEC , INC , LSR , ROL , ROR , SEB instructions. A generic name for bus control, address bus, and data bus signals. A state where the oscillation circuit halts and the program execution is stopped. By executing the STP instruction, the microcomputer enters Stop mode. Means a transfer clock of the clock synchronous serial I/O. Relevant term Access Access Up-count Internal area External area Under flow Up-count Stop mode Wait mode Bus control signal Wait mode

7702/7703 Group User’s Manual 3 Meaning Clock asynchronous serial I/O. When used to designate the name of a functional block, this term also means the serial I/O which can be switched to the cock synchronous serial I/O. A state where the down-count resultant is greater than the counter resolution. Means increasing by 1 and counting. A state where the oscillation circuit is operating, however, the program execution is stopped. By executing the WIT instruction, the microcomputer enters Wait mode. Relevant term Clock synchronous serial I/O. Overflow Down-count Down-count Stop mode Term UART Under flow Up-count Wait mode

7702/7703 Group User’s Manual4 MEMORANDUM

USER’S MANUAL 7702/7703 Group Mar. First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1997 MITSUBISHI ELECTRIC CORPORATION

User’s Manual 7702/7703 Group H-EF493-A KI-9703 Printed in Japan (ROD) © 1997 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Mar. 1997. Specifications subject to change without notice.