7700601EA

SN54165 TI | Alldatasheet

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SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Complementary Outputs /C0068 Direct Overriding Load (Data) Inputs /C0068 Gated Clock Inputs /C0068 Parallel-to-Serial Data Conversion TYPE TYPICAL MAXIMUM CLOCK FREQUENCY TYPICAL POWER DISSIPATION ’165 26 MHz 210 mW ’LS165A 35 MHz 90 mW

description

The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD ) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD high enables the other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD is high. Data at the parallel inputs are loaded directly into the register while SH/LD is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs. The SN54165 and SN74165 devices are obsolete and are no longer supplied Copyright  2002, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SN54165, SN54LS165A ...J O R W PACKAGE SN74165 ...N PACKAGE SN74LS165A . . . D, N, OR NS PACKAGE (TOP VIEW) 3212 0 1 9 91 0 1 1 1 2 1 3 D C NC B A E F NC G H SN54LS165A . . . FK PACKAGE (TOP VIEW)CLK SH/LD NC SER CLK INH H GND NC VCC SH/LD CLK E F G H Q H GND VCC CLK INH D C B A SER Q H Q HQ NC – No internal connection PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

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ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube SN74LS165AN SN74LS165AN 0°Ct o7 0°C SOIC D Tube SN74LS165AD LS165A0°C to 70°C SOIC – D Tape and reel SN74LS165ADR LS165A SOP – NS Tape and reel SN74LS165ANSR 74LS165A CDIP J Tube SN54LS165AJ SN54LS165AJ 55°Ct o1 2 5°C CDIP – J Tube SNJ54LS165AJ SNJ54LS165AJ –55°C to 125°C CFP – W Tube SNJ54LS165AW SNJ54LS165AW LCCC – FK Tube SNJ54LS165AFK SNJ54LS165AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS INTERNAL OUTPUTS OUTPUT SH/LD CLK INH CLK SER PARALLEL A...H Q A Q B Q H L X X X a...h a b h H LL X X Q A0 Q B0 Q H0 H L ↑ HX H Q An Q Gn H L ↑ LX L Q An Q Gn H H X X X Q A0 Q B0 Q H0 The SN54165 and SN74165 devices are obsolete and are no longer supplied.

SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematics of inputs and outputs EQUIVALENT OF EACH INPUT VCC Input R eq SH/LD : Req = 3 kΩ NOM Other Inputs: Req = 6 kΩ NOM TYPICAL OF BOTH OUTPUTS VCC Output ’165 100 Ω NOM EQUIVALENT OF PARALLEL INPUTS AND SERIAL INPUT VCC Input EQUIVALENT OF ALL OTHER INPUTS ’LS165A CLK, CLK INH: Req = 10 kΩ NOM SH/LD : Req = 13 kΩ NOM TYPICAL OF BOTH OUTPUTS Output VCC 120 Ω NOM 24 kΩ NOM R eq Input The SN54165 and SN74165 devices are obsolete and are no longer supplied.

SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

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logic diagram (positive logic) S R S R S R S R S R S R S R S R SH/LD CLK INH CLK SER Q H Q H 11 12 13 14 3 4 5 6 AB CDEF G H Pin numbers shown are for D, J, N, NS, and W packages. Q A Q B Q C Q D Q E Q F Q G typical shift, load, and inhibit sequences Serial ShiftInhibit Load E Output QH H G C F Data Inputs D SH/LD SER CLK INH CLK B A Output QH L L H L H L H H H H L H L H L H L H L L H L H L H The SN54165 and SN74165 devices are obsolete and are no longer supplied.

SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the ’165 to the SH/LD input in conjunction with the CLK INH input. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions SN54165 SN74165 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V IOH High-level output current –800 –800 /C0109 A IOL Low-level output current 16 16 mA fclock Clock frequency 0 20 0 20 MHz tw(clock) Width of clock input pulse 25 25 ns tw(load) Width of load input pulse 15 15 ns tsu Clock-enable setup time (see Figure 1) 30 30 ns tsu Parallel input setup time (see Figure 1) 10 10 ns tsu Serial input setup time (see Figure 1) 20 20 ns tsu Shift setup time (see Figure 1) 45 45 ns th Hold time at any input 0 0 ns TA Operating free-air temperature –55 125 0 70 °C The SN54165 and SN74165 devices are obsolete and are no longer supplied.

SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † SN54165 SN74165 UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VIK Input clamp voltage VCC = MIN, II = –12 mA –1.5 –1.5 V VOH High-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOH = –800 /C0109 A 2.4 3.4 2.4 3.4 V VOL Low-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V II Input current at maximum input voltageVCC = MAX, VI = 5.5 V 1 1 mA IIH High level input current SH/LD VCC = MAX VI=24V 80 80 µAIIH High-level input current Other inputs VCC = MAX , VI = 2.4 V 40 40 µA IIL Low level input current SH/LD VCC = MAX VI=04V –3.2 –3.2 mAIIL Low -level input current Other inputs VCC = MAX , VI = 0.4 V –1.6 –1.6 mA IOS Short-circuit output current§ VCC = MAX –20 –55 –18 –55 mA ICC Supply current VCC = MAX, See Note 4 42 63 42 63 mA NOTE 4: With the outputs open, CLK INH and CLK at 4.5 V, and a clock pulse applied to SH/LD, ICC is measured first with the parallel inputs at 4.5 V, then with the parallel inputs grounded. † For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. SN54165 and SN74165 switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER ¶ FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT fmax 20 26 MHz tPLH LD Any C L =1 5pFR L = 400/C0087 21 31 ns tPHL LD Any C L = 15 pF, R L = 400 /C0087 27 40 ns tPLH CLK Any C L =1 5pFR L = 400/C0087 16 24 ns tPHL CLK Any C L = 15 pF, R L = 400 /C0087 21 31 ns tPLH H Q H C L =1 5pFR L = 400/C0087 11 17 ns tPHL H Q H C L = 15 pF, R L = 400 /C0087 24 36 ns tPLH H Q H C L =1 5pFR L = 400/C0087 18 27 ns tPHL H Q H C L = 15 pF, R L = 400 /C0087 18 27 ns ¶ fmax = maximum clock frequency, tPLH = propagation delay time, low-to-high-level output, tPHL = propagation delay time, high-to-low-level output The SN54165 and SN74165 devices are obsolete and are no longer supplied.

SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions SN54LS165A SN74LS165A UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –0.4 –0.4 mA IOL Low-level output current 4 8 mA fclock Clock frequency 0 25 0 25 MHz t (l k ) Width of clock inputpulse (see Figure 2) Clock high 15 15 nstw(clock) Width of clock input pulse (see Figure 2) Clock low 25 25 ns t (l d) Width of load inputpulse Clock high 25 25 nstw(load) Width of load input pulse Clock low 17 17 ns tsu Clock-enable setup time (see Figure 2) 30 30 ns tsu Parallel input setup time (see Figure 2) 10 10 ns tsu Serial input setup time (see Figure 2) 20 20 ns tsu Shift setup time (see Figure 2) 45 45 ns th Hold time at any input 0 0 ns TA Operating free-air temperature –55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS † SN54LS165A SN74LS165A UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VIK VCC = MIN, II = –18 mA –1.5 –1.5 V VOL VCC = MIN VIH =2V VIL= MAX IOL = 4 mA 0.25 0.4 0.25 0.4 VVOL VCC = MIN , VIH = 2 V, VIL = MAX IOL = 8 mA 0.35 0.5 V II VCC = MAX, VI = 7 V 0.1 0.1 mA IIH VCC = MAX, VI = 2.7 V 20 20 µA IIL VCC = MAX, VI = 0.4 V –0.4 –0.4 mA IOS § VCC = MAX –20 –100 –20 –100 mA ICC VCC = MAX, See Note 4 18 30 18 30 mA NOTE 4. With the outputs open, CLK INH and CLK at 4.5 V, and a clock pulse applied to SH/LD, ICC is measured first with the parallel inputs at 4.5 V, then with the parallel inputs grounded. † For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. The SN54165 and SN74165 devices are obsolete and are no longer supplied.

SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002

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SN54LS165A and SN74LS165A switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2) PARAMETER † FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT fmax 25 35 MHz tPLH LD Any R L =2k /C0087 C L =1 5pF 21 35 ns tPHL LD Any R L = 2 k/C0087 , C L = 15 pF 26 35 ns tPLH CLK Any R L =2k /C0087 C L =1 5pF 14 25 ns tPHL CLK Any R L = 2 k/C0087 , C L = 15 pF 16 25 ns tPLH H Q H R L =2k /C0087 C L =1 5pF 13 25 ns tPHL H Q H R L = 2 k/C0087 , C L = 15 pF 24 30 ns tPLH H Q H R L =2k /C0087 C L =1 5pF 19 30 ns tPHL H Q H R L = 2 k/C0087 , C L = 15 pF 17 25 ns † fmax = maximum clock frequency, tPLH = propagation delay time, low-to-high-level output, tPHL = propagation delay time, high-to-low-level output The SN54165 and SN74165 devices are obsolete and are no longer supplied.

NOTES: A. C L includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH , tPHL , tPHZ , and tPLZ ; S1 is open and S2 is closed for tPZH ; S1 is closed and S2 is open for tPZL . 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms are obsolete and are no longer supplied.

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NOTES: A. C L includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH , tPHL , tPHZ , and tPLZ ; S1 is open and S2 is closed for tPZH ; S1 is closed and S2 is open for tPZL . E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω , tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms are obsolete and are no longer supplied.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-7700601VEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC 5962-7700601VFA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC 7700601EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC 7700601FA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC JM38510/30608B2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC JM38510/30608BEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC JM38510/30608BFA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC SN54LS165AJ ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC SN74165N OBSOLETE PDIP N 16 TBD Call TI Call TI SN74LS165AD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS165ADE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS165ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS165ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS165AJ OBSOLETE CDIP J 16 TBD Call TI Call TI SN74LS165AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74LS165AN3 OBSOLETE PDIP N 16 TBD Call TI Call TI SN74LS165ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LS165ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54LS165AFK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC SNJ54LS165AJ ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC SNJ54LS165AW ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Addendum-Page 1

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 Addendum-Page 2

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