7700 BITECH | Alldatasheet

Document overview

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Technical content

Specifications subject to change without notice.

  • Module contains all power components necessary to provide power factor correction in a switching power supply. - Rectifier bridge with SCRs for inrush current limiting - Ultrafast platinum output diode - 500V .1Ω Max. FET (7700B) - Low gate charge, 500V, .0675Ω max. FET (7700-2A)
  • Provides optimum use of available line current
  • Allows power supply to meet harmonic requirement
  • Module design reduces cost of heat sink
  • Saves significant space and assembly time
  • Low cost
  • Internal temperature sensing
  • Replaces up to 10 each TO-220 or TO-247 discrete power semiconductors
  • Custom module versions available to meet specific requirements such as: - Motor drives - Power servo amplifiers - Solenoid drivers - Solid state relays - 3 phase rectifier bridges Designed to optimally facilitate a boost type power factor correction (PFC) system for designs with up to 36A rms input current. FEATURES AND BENEFITS 7700B 1,500 Watts / 3,000 Watts 7700-2A 2,000 Watts / 4,000 Watts MODELS/RANGE

APPLICATIONS

Standard applications include switching power supplies from 1,000 watts to 4,000 watts with line voltages up to 300 V rms.

Parameter Symbol Conditions 1 Model Min. Typ. Max. Units MOS FET Continuous Drain Current I D TC = 25°C B 56 A -2A 80 A TC = 100°C B 34.8 A -2A 48 A Pulsed Drain Current I DM B 224 A -2A 320 A Single Pulse Avalanche Energy E AS B 760 mJ -2A 960 mJ Repetitive Avalanche Energy E AR B1 9 m J -2A 28 mJ Avalanche Current I AR B 8.7 A -2A 20 A Gate to Source Voltage V GS B, -2A ±30 V Leakage Current I DSS VGS = 0V, VDS = 500V B, -2A 100 µA Drain to Source ON Voltage V DS(ON) IC = 28A, VGS= 10V B 1.5 2.8 V -2A 1.0 2.7 V Gate Threshold Voltage V GS(TH) VDS = VGS, ID = 1mA B, -2A 2.0 4.0 V Gate Leakage Current I GSS VGS ±20V B, -2A ±400 nA Total Gate Charge Qg I D = 56A, VDS = 400V B 600 nC Gate Source Charge Qgs V GS = 10V B 80 nC Gate Drain (Miller) Charge Qgd B 320 nC Total Gate Charge Qg I D = 80A, VDS = 400V -2A 480 nC Gate Source Charge Qgs V GS = 10V -2A 128 nC Gate Drain (Miller) Charge Qgd -2A 196 nC Continous Source Current I S B5 6 A (Body Diode) -2A 80 A Pulsed Source Current I SM B 224 A (Body Diode) -2A 320 A Body Diode Forward Voltage V SD IS = 56A, VGS = 0V B 0.4 1.4 V IS = 80A, VGS = 0V -2A 0.5 1.8 V Reverse Recovery Time trr I F = 56A, di/dt = 400Aµs B 810 ns (Body Diode) I F = 80A, di/dt = 400Aµs -2A 860 ns Reverse Recovery Charge Qrr I F = 56A, di/dt = 400Aµs B 28.8 ns (Body Diode) I F = 80A, di/dt = 400Aµs -2A 39.6 ns Internal Gate Resistor R G B 1.25 Ω -2A 0.25 Ω Junction Temperature T J B, -2A 150 °C Thermal Resistance R THJC B 0.20 .025 °C/W -2A .15 .20 °C/W

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions 1 Model Min. Typ. Max. Units SCRS Average On Current I T(AV) TC = 75°C, 180° half B 20 A sine wave -2A 35 A RMS On Current I RMS B3 0 A (As AC switch) -2A 55 A Peak Repetitive Off Voltage V RRM/ B 600 V VDRM -2A 800 V Peak One Cycle Non-Repetitive ITSM TJ = TJMax., t = 10ms B 300 A Surge Current (50 Hz), sine -2A 400 A Reverse and Direct Leakage I R/ID VR = VRRM, VD = VDRM B2 5 µ A Current -2A 300 µA On Voltage V T IT = 25A B 0.5 1.6 V IT = 45A -2A 0.5 1.6 V Gate Trigger Voltage V GT VD= 6V, 22Ω B, -2A 0.2 3.5 V (Includes drop across RG)V D= 6V, 22Ω . TJ = -40°C B, -2A 0.3 1.5 V VD= 6V, 22Ω . TJ = 125°C B, -2A 0.1 1.5 V Gate Trigger Current V GT VD= 6V, 22Ω B, -2A 5 60 mA (Each SCR Individually) V D= 6V, 22Ω . TJ = -40°C B, -2A 10 120 mA VD= 6V, 22Ω . TJ = 125°C B, -2A 2 35 mA Holding Current I H (Each SCR Individually) B 100 mA -2A 100 mA Internal Gate Resistor R G Connected to each SCR B 10 Ω -2A 10 Ω Junction Temperature T j B, -2A 150 °C Thermal Resistance R thjc B 1.4 2.0 °C/W -2A 0.7 1.0 °C/W Bridge Diodes Average Forward Current I F(AV) TC= 105°C, 180°, half B 20 A sine wave -2A 40 A Peak Repetitive Reverse V RRM B 600 V Voltage -2A 800 V Peak One Cycle Non-Repetitive IFSM TJ = TJ Max., t = 10ms B 300 A Surge Current (50 Hz), sine -2A 400 A Reverse Leakage Current I R/ VR = VRRM B 100 µA -2A 300 µA Forward Voltage V F IF = 25A B 0.5 1.2 V IF = 40A -2A 0.5 1.2 V Junction Temperature T J B, -2A 150 °C Thermal Resistance R THJC B 1.5 1.8 °C/W -2A 1.0 1.2 °C/W

Parameter Symbol Conditions 1 Model Min. Typ. Max. Units Output Diode Average Forward Current I F(AV) TC= 120°C B 24 A -2A 60 A Peak Repetitive Reverse V RRM B, -2A 600 V Voltage Peak One Cycle Non-Repetitive IFSM TJ = TJMax., t = 10ms B 500 A Surge Current (50 Hz), sine -2A 500 A Reverse Leakage Current I R/ VR = VRRM B6 0 µ A -2A 1 mA Forward Voltage V F IF = 24A B 1.0 2.8 V IF = 50A -2A 0.5 2.8 V Reverse Recovery Time trr I F = 6A, di/dt = 300Aµs B 35 ns IF = 2A, di/dt = 200Aµs -2A 40 ns Junction Temperature T J B, -2A 175 °C Thermal Resistance R THJC B 0.9 1.0 °C/W -2A 0.75 0.9 °C/W TH1 NTC Thermistor Resistance R 25 I = 1mA B, -2A 22.5 25 27.5 K Ω Resistance Ratio R T/R25 T = 80°C B, -2A .126 T = 90°C B, -2A .0916 T = 100°C B, -2A .0679 T = 110°C B, -2A .0511 Dissipation Constant P D B, -2A 1.0 mW/°C Thermal Time Constant t B, -2A 10 sec 1 - TCase = 25°C unless otherwise specified.

associated pins. Pin 1: AC 1 Pin 2: AC 2 Pin 3: Bridge Output Pin 4: SCR Gates Pin 5: Ground Pin 6: Ground Pin 7: FET Drain Pin 8: Ultrafast Anode Pin 9: Ultrafast Cathode Pin 10: Gate Ground Pin 11: Gate Drive Pin 12: N.C. Pin 13: TH 1 Pin 14: TH 2 EMI Filter Gate Driver 14 1213 11 10 PFC PWM Thermal Shutdown Circuitry 3 L1 CT CT Vo Co Load SYSTEM DIAGRAM

3.050 Max. 2.560 Pin .050 x .020

14 Places

.505 ±.010 .950 1.440 Max. .075 Ref. Date CodeLot NumberPart Number .160 Ref. 1.100±.015 R .235 ∅ .280 ∅ .150 .150 .286 Pin 14 Pin 1 .515 Ref. .361 .154±.015 .3306X .175 6X .275 OUTLINE DIMENSIONS (Inch) 77 0 0 B Model Package Range, Watts: B = 1,500 to 3,000 Watts -2A = 2,000 to 4,000 Watts Circuit Function: 0 = Power Factor Correction

ORDERING INFORMATION

V x (1- )IN 2.828 x Lx f 1.414 x VIN VO I =RMS 100K (1.414 x V ) L x f O P – P 100KV = x + ESR1 2x π xfxC O ( ) V x (1- ) IN IN VO OUTPUT VOLTAGE The dc output voltage must be greater than the highest peak line voltage expected: DISCONTINUOUS CONDUCTION When the line voltage approaches zero volts the PFC PWM will be forced towards its maximum duty cycle. This will cause the current to become discontinuous, which will result in some distortion. The line voltage at which the current will become discontinuous will be: The line voltage at which the PWM will be duty cycle limited will be: INDUCTOR L1 The inductor value controls the amplitude of the 100KHz current ripple. This can greatly effect the amount of distortion and thus the amount of EMI filtering required on the input. Ripple current can be calculated for any point along the input sine wave: Where: DC(t)=1-V IN(t)/VO , L is the inductance of L1, and f is the switching frequency. A good starting point would be to set Ip-p equal to 20% of the 120 Hz peakcurrent, solving for L: MODEL 7700 APPLICATION NOTES OUTPUT CAPACITOR The output capacitor size is often limited by the line dropout requirements of the power supply: Where: P OUT is the output power, td is the dropout time, and VO MIN is the minimum allowed output voltage. The 120Hz output voltage ripple can be calculated to insure it meets the system requirements: The maximum rms 120Hz ripple current will be: The 100KHz output voltage ripple will be: The maximum rms 100KHz ripple current will be: GATE DRIVE REQUIREMENTS FET switching times must be fast enough to insure that the FET turns off when the PWM is at maximum duty cycle. Snubbing circuits across the FET will slow the turn off time and should not be used. A discrete gate driver circuit will allow the fastest possible switching times. The Unitrode UC3710 or Telcom TC4422 drivers offer a single chip approach IN discontinuousV =V x (1 - DC )O MAX MAXDC C = 2 x P x tOUT d O V - VO MIN 2O MIN L ≥ IN 5 x V x (1- )IN P x f 1.414 x VIN VO I (t) =V (t) x DC (t)IN L x f P – P 2xPO VO O P – P 120 ()V = x + ESR1 2x π xfxC O 1.414 x PO VO I =RMS 120 V = V x (1-DC )O MAXIN duty cycle limited V > V x 1 .414IN MAXO 7-25 Model 7700 Series

with only slightly slower switching times. The gate driver must be located as close to the module as possible. Ground sense pin 10 should be used to insure the fastest possible switching times. HEAT RADIATOR The heat radiator requirements can be determined by the maximum power dissipated (at low line) and the maximum ambient temperature. The back side of the module should be limited to about 100°C by utilizing the internal thermistor. Care should be used when attaching the module to the heat radiator. The screws must be tightened incrementally in a crisscross pattern. A torque limiting screwdriver should be used. The high current levels require currrent sense transformers to maintain a reasonable efficiency. We recommend BI Technologies HM31-20200. PFC PWM VENDORS Popular sources are: Unitrode UC3854 Micro Linear ML4812 Linear Technology LT1248 MODEL 7700 APPLICATION NOTES R = O LOWLINE 100 - TMAX AMB P Θ 7-26